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author | Alexey Neyman <stilor@att.net> | 2022-02-14 08:11:42 (GMT) |
---|---|---|
committer | GitHub <noreply@github.com> | 2022-02-14 08:11:42 (GMT) |
commit | 681aaef1f1ff39c341fdc529e0db2c14639a58d8 (patch) | |
tree | ce98c2b3d9648db065d27add325370392a35d584 /packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch | |
parent | ba680a3e5b8c62a7c1554e71f6d09903dac95a2f (diff) | |
parent | 86c2982568de1ad4d4cc12a65b19231331484405 (diff) |
Merge pull request #1674 from stilor/master
Updates to make `ct-ng build-all` pass
Diffstat (limited to 'packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch')
-rw-r--r-- | packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch b/packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch index 5213378..a660266 100644 --- a/packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch +++ b/packages/glibc/2.19/0017-Fix-cmpli-usage-in-power6-memset.patch @@ -24,9 +24,14 @@ the powerpc32 change. sysdeps/powerpc/powerpc32/power6/memset.S (memset): Use cmplwi instead of cmpli. sysdeps/powerpc/powerpc64/power6/memset.S (memset): Use cmpldi instead of cmpli. +--- + sysdeps/powerpc/powerpc32/power6/memset.S | 2 +- + sysdeps/powerpc/powerpc64/power6/memset.S | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + --- a/sysdeps/powerpc/powerpc32/power6/memset.S +++ b/sysdeps/powerpc/powerpc32/power6/memset.S -@@ -394,7 +394,7 @@ L(cacheAlignedx): +@@ -394,7 +394,7 @@ /* A simple loop for the longer (>640 bytes) lengths. This form limits the branch miss-predicted to exactly 1 at loop exit.*/ L(cacheAligned512): @@ -35,10 +40,9 @@ the powerpc32 change. blt cr1,L(cacheAligned1) dcbz 0,rMEMP addi rLEN,rLEN,-128 - --- a/sysdeps/powerpc/powerpc64/power6/memset.S +++ b/sysdeps/powerpc/powerpc64/power6/memset.S -@@ -251,7 +251,7 @@ L(cacheAlignedx): +@@ -251,7 +251,7 @@ /* A simple loop for the longer (>640 bytes) lengths. This form limits the branch miss-predicted to exactly 1 at loop exit.*/ L(cacheAligned512): |