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Diffstat (limited to 'patches/gcc/3.4.6/601-gcc34-arm-ldm-peephole2.patch')
-rw-r--r--patches/gcc/3.4.6/601-gcc34-arm-ldm-peephole2.patch32
1 files changed, 32 insertions, 0 deletions
diff --git a/patches/gcc/3.4.6/601-gcc34-arm-ldm-peephole2.patch b/patches/gcc/3.4.6/601-gcc34-arm-ldm-peephole2.patch
new file mode 100644
index 0000000..395c516
--- /dev/null
+++ b/patches/gcc/3.4.6/601-gcc34-arm-ldm-peephole2.patch
@@ -0,0 +1,32 @@
+diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
+--- gcc-3.4.6.orig/gcc/config/arm/arm.c 2007-08-15 22:57:51.000000000 +0200
++++ gcc-3.4.6/gcc/config/arm/arm.c 2007-08-15 22:57:51.000000000 +0200
+@@ -4572,6 +4572,10 @@
+ int
+ adjacent_mem_locations (rtx a, rtx b)
+ {
++ /* We don't guarantee to preserve the order of these memory refs. */
++ if (volatile_refs_p (a) || volatile_refs_p (b))
++ return 0;
++
+ if ((GET_CODE (XEXP (a, 0)) == REG
+ || (GET_CODE (XEXP (a, 0)) == PLUS
+ && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
+@@ -4611,6 +4615,17 @@
+ return 0;
+
+ val_diff = val1 - val0;
++
++ if (arm_ld_sched)
++ {
++ /* If the target has load delay slots, then there's no benefit
++ to using an ldm instruction unless the offset is zero and
++ we are optimizing for size. */
++ return (optimize_size && (REGNO (reg0) == REGNO (reg1))
++ && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
++ && (val_diff == 4 || val_diff == -4));
++ }
++
+ return ((REGNO (reg0) == REGNO (reg1))
+ && (val_diff == 4 || val_diff == -4));
+ }