From 04459efaac7ee39cc96ffaa1a30967b6841a0e4d Mon Sep 17 00:00:00 2001 From: "Yann E. MORIN\"" Date: Thu, 23 Oct 2008 21:12:29 +0000 Subject: Fix memset on PowerPC 8xx, by Nye Liu: http://sourceware.org/ml/crossgcc/2008-10/msg00067.html /trunk/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch | 40 40 0 0 +++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch b/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch new file mode 100644 index 0000000..03cd441 --- /dev/null +++ b/patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch @@ -0,0 +1,40 @@ +Fix memset on PowerPC 8xx, by Nye Liu: +http://sourceware.org/ml/crossgcc/2008-10/msg00067.html + +Quote: + I am working on a powerpc 860 toolchain, but I am having problems + convincing glibc to not emit code that uses the dcbz instruction (CPU15 + dcbX bug). The source of the problem is sysdeps/powerpc/power3/memset.S + +--- glibc-2.7/sysdeps/powerpc/powerpc32/memset.S 2007-03-26 13:09:07.000000000 -0700 ++++ glibc-2.7/sysdeps/powerpc/powerpc32/memset.S.new 2008-10-23 12:20:04.000000000 -0700 +@@ -112,11 +112,13 @@ + clrrwi. rALIGN, rLEN, 5 + mtcrf 0x01, rLEN /* 40th instruction from .align */ + ++#ifndef BROKEN_PPC_8xx_CPU15 + /* Check if we can use the special case for clearing memory using dcbz. + This requires that we know the correct cache line size for this + processor. Getting the __cache_line_size may require establishing GOT + addressability, so branch out of line to set this up. */ + beq cr1, L(checklinesize) ++#endif + + /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary. + Can't assume that rCHR is zero or that the cache line size is either +@@ -248,6 +250,7 @@ + stw rCHR, -8(rMEMP) + blr + ++#ifndef BROKEN_PPC_8xx_CPU15 + L(checklinesize): + #ifdef SHARED + mflr rTMP +@@ -329,6 +332,7 @@ + L(handletail32): + clrrwi. rALIGN, rLEN, 5 + b L(nondcbz) ++#endif /* ! BROKEN_PPC_8xx_CPU15 */ + + END (BP_SYM (memset)) + libc_hidden_builtin_def (memset) -- cgit v0.10.2-6-g49f6