patches/eglibc/2_9/100-powerpc-8xx-CPU15-errata.patch
author "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
Mon Apr 16 15:25:36 2012 +0200 (2012-04-16)
changeset 2941 13e40098fffc
permissions -rw-r--r--
cc/gcc: update Linaro GCC revisions to 2012.04

Update Linaro GCC with the latest available revisions.

The 4.7 revision is also released, but the infrastructure is not yet ready for
it in CT-NG.

Signed-off-by: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
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diff -ru eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S
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--- eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S	2007-04-13 08:35:45.000000000 -0700
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+++ eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S	2009-05-06 16:52:04.000000000 -0700
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@@ -112,11 +112,13 @@
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 	clrrwi.	rALIGN, rLEN, 5
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 	mtcrf	0x01, rLEN	/* 40th instruction from .align */
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+#ifndef BROKEN_PPC_8xx_CPU15
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 /* Check if we can use the special case for clearing memory using dcbz.
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    This requires that we know the correct cache line size for this
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    processor.  Getting the __cache_line_size may require establishing GOT
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    addressability, so branch out of line to set this up.  */
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 	beq	cr1, L(checklinesize)
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+#endif
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 /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.
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    Can't assume that rCHR is zero or that the cache line size is either
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@@ -158,6 +160,7 @@
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 	add	rMEMP, rMEMP, rALIGN
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 	b	L(medium_tail2)	/* 72nd instruction from .align */
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+#ifndef BROKEN_PPC_8xx_CPU15
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 	.align	5
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 	nop
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 /* Clear cache lines of memory in 128-byte chunks.
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@@ -191,6 +194,7 @@
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 	bdnz	L(zloop)
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 	beqlr	cr5
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 	b	L(medium_tail2)
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+#endif /* ! BROKEN_PPC_8xx_CPU15 */
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 	.align	5
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 L(small):
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@@ -248,6 +252,7 @@
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 	stw	rCHR, -8(rMEMP)
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 	blr
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+#ifndef BROKEN_PPC_8xx_CPU15
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 L(checklinesize):
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 #ifdef SHARED
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 	mflr	rTMP
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@@ -329,6 +334,7 @@
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 L(handletail32):
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 	clrrwi.	rALIGN, rLEN, 5
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 	b	L(nondcbz)
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+#endif /* ! BROKEN_PPC_8xx_CPU15 */
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 END (BP_SYM (memset))
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 libc_hidden_builtin_def (memset)