patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
author "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
Mon Apr 16 15:25:36 2012 +0200 (2012-04-16)
changeset 2941 13e40098fffc
parent 746 b150d6f590fc
permissions -rw-r--r--
cc/gcc: update Linaro GCC revisions to 2012.04

Update Linaro GCC with the latest available revisions.

The 4.7 revision is also released, but the infrastructure is not yet ready for
it in CT-NG.

Signed-off-by: "Benoît Thébaudeau" <benoit.thebaudeau@advansee.com>
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diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
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--- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
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+++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
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@@ -4572,6 +4572,10 @@
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 int
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 adjacent_mem_locations (rtx a, rtx b)
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 {
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+  /* We don't guarantee to preserve the order of these memory refs.  */
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+  if (volatile_refs_p (a) || volatile_refs_p (b))
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+    return 0;
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+
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   if ((GET_CODE (XEXP (a, 0)) == REG
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        || (GET_CODE (XEXP (a, 0)) == PLUS
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 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
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@@ -4611,6 +4615,17 @@
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 	return 0;
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       val_diff = val1 - val0;
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+
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+      if (arm_ld_sched)
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+	{
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+	  /* If the target has load delay slots, then there's no benefit
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+	     to using an ldm instruction unless the offset is zero and
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+	     we are optimizing for size.  */
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+	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
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+		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
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+		  && (val_diff == 4 || val_diff == -4));
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+	}
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+
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       return ((REGNO (reg0) == REGNO (reg1))
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 	      && (val_diff == 4 || val_diff == -4));
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     }