patches/glibc/2.7/290-powerpc-8xx-CPU15-errata.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Wed May 18 23:00:46 2011 +0200 (2011-05-18)
changeset 2467 200836977ce6
parent 966 b6eec1274efb
permissions -rw-r--r--
config: rename variables that are arrays

Make it explicit that a variable is an array bu the name of the variable.
It will be used later when .config gets munged to allow both multiple
arguments and arguments with spaces at the same time to be passed from the
configuration down to the build scripts.

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
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Fix memset on PowerPC 8xx, by Nye Liu:
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http://sourceware.org/ml/crossgcc/2008-10/msg00067.html
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Quote:
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 I am working on a powerpc 860 toolchain, but I am having problems  
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 convincing glibc to not emit code that uses the dcbz instruction (CPU15  
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 dcbX bug). The source of the problem is sysdeps/powerpc/power3/memset.S
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--- glibc-2.7/sysdeps/powerpc/powerpc32/memset.S	2007-03-26 13:09:07.000000000 -0700
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+++ glibc-2.7/sysdeps/powerpc/powerpc32/memset.S.new	2008-10-23 20:28:52.000000000 -0700
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@@ -112,11 +112,13 @@
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 	clrrwi.	rALIGN, rLEN, 5
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 	mtcrf	0x01, rLEN	/* 40th instruction from .align */
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+#ifndef BROKEN_PPC_8xx_CPU15
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 /* Check if we can use the special case for clearing memory using dcbz.
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    This requires that we know the correct cache line size for this
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    processor.  Getting the __cache_line_size may require establishing GOT
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    addressability, so branch out of line to set this up.  */
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 	beq	cr1, L(checklinesize)
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+#endif
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 /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.
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    Can't assume that rCHR is zero or that the cache line size is either
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@@ -158,6 +160,7 @@
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 	add	rMEMP, rMEMP, rALIGN
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 	b	L(medium_tail2)	/* 72nd instruction from .align */
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+#ifndef BROKEN_PPC_8xx_CPU15
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 	.align	5
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 	nop
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 /* Clear cache lines of memory in 128-byte chunks.
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@@ -191,6 +194,7 @@
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 	bdnz	L(zloop)
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 	beqlr	cr5
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 	b	L(medium_tail2)
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+#endif /* ! BROKEN_PPC_8xx_CPU15 */
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 	.align	5
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 L(small):
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@@ -248,6 +252,7 @@
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 	stw	rCHR, -8(rMEMP)
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 	blr
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+#ifndef BROKEN_PPC_8xx_CPU15
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 L(checklinesize):
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 #ifdef SHARED
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 	mflr	rTMP
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@@ -329,6 +334,7 @@
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 L(handletail32):
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 	clrrwi.	rALIGN, rLEN, 5
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 	b	L(nondcbz)
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+#endif /* ! BROKEN_PPC_8xx_CPU15 */
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 END (BP_SYM (memset))
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 libc_hidden_builtin_def (memset)