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yann@1
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http://sources.redhat.com/cgi-bin/cvsweb.cgi/libc/sysdeps/unix/sysv/linux/sh/sysdep.h.diff?r1=1.9&r2=1.10&cvsroot=glibc
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yann@1
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yann@1
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Ankur Sheth said:
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yann@1
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yann@1
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"This is actually a workaround for a bug in the sh4. The actual bug is
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yann@1
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documented here :
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yann@1
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http://documentation.renesas.com/eng/products/mpumcu/tu/tnsh7456ae.pdf
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yann@1
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Basically the cache & TLB should not be accessed for 4 (or was it 5?) cycles
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yann@1
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after isssuing a TRAPA instruction. I didn't run into any specific problem
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yann@1
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because of this bug, but it seems useful to have and the patch itself seems
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yann@1
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pretty harmless."
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yann@1
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yann@1
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yann@1
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===================================================================
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yann@1
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RCS file: /cvs/glibc/libc/sysdeps/unix/sysv/linux/sh/sysdep.h,v
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yann@1
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retrieving revision 1.9
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yann@1
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retrieving revision 1.10
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yann@1
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diff -u -r1.9 -r1.10
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yann@1
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--- libc/sysdeps/unix/sysv/linux/sh/sysdep.h 2003/09/01 04:05:21 1.9
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yann@1
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+++ libc/sysdeps/unix/sysv/linux/sh/sysdep.h 2003/10/15 04:36:32 1.10
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yann@1
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@@ -183,6 +183,13 @@
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yann@1
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# endif /* _LIBC_REENTRANT */
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yann@1
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#endif /* PIC */
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yann@1
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yann@1
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+# ifdef NEED_SYSCALL_INST_PAD
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yann@1
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+# define SYSCALL_INST_PAD \
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yann@1
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+ or r0,r0; or r0,r0; or r0,r0; or r0,r0; or r0,r0
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yann@1
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+# else
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yann@1
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+# define SYSCALL_INST_PAD
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yann@1
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+# endif
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yann@1
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+
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yann@1
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#define SYSCALL_INST0 trapa #0x10
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yann@1
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#define SYSCALL_INST1 trapa #0x11
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yann@1
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#define SYSCALL_INST2 trapa #0x12
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yann@1
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@@ -195,19 +202,13 @@
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yann@1
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#define DO_CALL(syscall_name, args) \
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yann@1
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mov.l 1f,r3; \
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yann@1
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SYSCALL_INST##args; \
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yann@1
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+ SYSCALL_INST_PAD; \
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yann@1
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bra 2f; \
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yann@1
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nop; \
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yann@1
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.align 2; \
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yann@1
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1: .long SYS_ify (syscall_name); \
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yann@1
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2:
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yann@1
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yann@1
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-# ifdef NEED_SYSCALL_INST_PAD
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yann@1
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-# define SYSCALL_INST_PAD \
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yann@1
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- or r0,r0; or r0,r0; or r0,r0; or r0,r0; or r0,r0
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yann@1
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-# else
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yann@1
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-# define SYSCALL_INST_PAD
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yann@1
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-# endif
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yann@1
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-
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yann@1
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#else /* not __ASSEMBLER__ */
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yann@1
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yann@1
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#define SYSCALL_INST_STR0 "trapa #0x10\n\t"
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