patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
author Daniel Price <daniel.price@gmail.com>
Tue Nov 20 16:59:17 2012 -0800 (2012-11-20)
changeset 3126 333d3e40cbd1
parent 746 b150d6f590fc
permissions -rw-r--r--
scripts: refine static linking check to better guide the user

The current mechanism to check if static linking is possible, and the mesage
displayed on failure, can be puzzling to the unsuspecting user.

Also, the current implementation is not using the existing infrastructure,
and is thus difficult to enhance with new tests.

So, switch to using the standard CT_DoExecLog infra, and use four tests to
check for the host compiler:
- check we can run it
- check it can build a trivial program
- check it can statically link that program
- check if it statically link with libstdc++

That should cover most of the problems. Hopefully.

(At the same time, fix a typo in a comment)

Signed-off-by: Daniel Price <daniel.price@gmail.com>
[yann.morin.1998@free.fr: split original patch for self-contained changes]
[yann.morin.1998@free.fr: use steps to better see gcc's output]
[yann.morin.1998@free.fr: commit log]
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Message-Id: <163f86b5216fc08c672a.1353459722@nipigon.dssd.com>
Patchwork-Id: 200536
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diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
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--- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
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+++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
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@@ -4572,6 +4572,10 @@
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 int
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 adjacent_mem_locations (rtx a, rtx b)
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 {
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+  /* We don't guarantee to preserve the order of these memory refs.  */
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+  if (volatile_refs_p (a) || volatile_refs_p (b))
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+    return 0;
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+
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   if ((GET_CODE (XEXP (a, 0)) == REG
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        || (GET_CODE (XEXP (a, 0)) == PLUS
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 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
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@@ -4611,6 +4615,17 @@
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 	return 0;
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       val_diff = val1 - val0;
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+
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+      if (arm_ld_sched)
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+	{
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+	  /* If the target has load delay slots, then there's no benefit
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+	     to using an ldm instruction unless the offset is zero and
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+	     we are optimizing for size.  */
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+	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
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+		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
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+		  && (val_diff == 4 || val_diff == -4));
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+	}
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+
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       return ((REGNO (reg0) == REGNO (reg1))
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 	      && (val_diff == 4 || val_diff == -4));
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     }