patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Mon Jul 28 21:32:33 2008 +0000 (2008-07-28)
changeset 747 d3e603e7c17c
parent 746 patches/gcc/3.4.6/602-arm-ldm-peephole2.patch@b150d6f590fc
permissions -rw-r--r--
Fourth step at renaming patches: renumber all patches with a 10-step.
yann@339
     1
diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
yann@339
     2
--- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
yann@339
     3
+++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
yann@339
     4
@@ -4572,6 +4572,10 @@
yann@339
     5
 int
yann@339
     6
 adjacent_mem_locations (rtx a, rtx b)
yann@339
     7
 {
yann@339
     8
+  /* We don't guarantee to preserve the order of these memory refs.  */
yann@339
     9
+  if (volatile_refs_p (a) || volatile_refs_p (b))
yann@339
    10
+    return 0;
yann@339
    11
+
yann@339
    12
   if ((GET_CODE (XEXP (a, 0)) == REG
yann@339
    13
        || (GET_CODE (XEXP (a, 0)) == PLUS
yann@339
    14
 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
yann@339
    15
@@ -4611,6 +4615,17 @@
yann@339
    16
 	return 0;
yann@339
    17
 
yann@339
    18
       val_diff = val1 - val0;
yann@339
    19
+
yann@339
    20
+      if (arm_ld_sched)
yann@339
    21
+	{
yann@339
    22
+	  /* If the target has load delay slots, then there's no benefit
yann@339
    23
+	     to using an ldm instruction unless the offset is zero and
yann@339
    24
+	     we are optimizing for size.  */
yann@339
    25
+	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
yann@339
    26
+		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
yann@339
    27
+		  && (val_diff == 4 || val_diff == -4));
yann@339
    28
+	}
yann@339
    29
+
yann@339
    30
       return ((REGNO (reg0) == REGNO (reg1))
yann@339
    31
 	      && (val_diff == 4 || val_diff == -4));
yann@339
    32
     }