patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Tue Aug 31 23:24:40 2010 +0200 (2010-08-31)
changeset 2107 f5ab0a80e466
parent 746 b150d6f590fc
permissions -rw-r--r--
binutils/binutils: remove faulty patch

The added code should be conditinal to the target system
being !MIPS, but is based on the host system being !MIPS.

This is plain wrong, and had not been noticed until now
as I never used those binutils versions on MIPS.

See:
http://sourceware.org/ml/crossgcc/2010-08/msg00192.html

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
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diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
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--- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
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+++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
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@@ -4572,6 +4572,10 @@
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 int
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 adjacent_mem_locations (rtx a, rtx b)
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 {
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+  /* We don't guarantee to preserve the order of these memory refs.  */
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+  if (volatile_refs_p (a) || volatile_refs_p (b))
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+    return 0;
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+
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   if ((GET_CODE (XEXP (a, 0)) == REG
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        || (GET_CODE (XEXP (a, 0)) == PLUS
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 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
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@@ -4611,6 +4615,17 @@
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 	return 0;
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       val_diff = val1 - val0;
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+
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+      if (arm_ld_sched)
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+	{
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+	  /* If the target has load delay slots, then there's no benefit
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+	     to using an ldm instruction unless the offset is zero and
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+	     we are optimizing for size.  */
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+	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
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+		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
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+		  && (val_diff == 4 || val_diff == -4));
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+	}
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+
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       return ((REGNO (reg0) == REGNO (reg1))
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 	      && (val_diff == 4 || val_diff == -4));
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     }