1.1 --- a/patches/glibc/2.1.3/glibc-2.1.3-allow-gcc3-longlong.patch Tue Aug 14 19:32:22 2007 +0000
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,774 +0,0 @@
1.4 ---- glibc-2.1.3/stdlib/longlong.h.old 2004-03-05 14:49:14.000000000 -0800
1.5 -+++ glibc-2.1.3/stdlib/longlong.h 2004-03-05 15:19:26.000000000 -0800
1.6 -@@ -106,8 +106,8 @@
1.7 -
1.8 - #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
1.9 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.10 -- __asm__ ("add %1,%4,%5
1.11 -- addc %0,%2,%3" \
1.12 -+ __asm__ ("add %1,%4,%5\n" \
1.13 -+ "addc %0,%2,%3" \
1.14 - : "=r" ((USItype)(sh)), \
1.15 - "=&r" ((USItype)(sl)) \
1.16 - : "%r" ((USItype)(ah)), \
1.17 -@@ -115,8 +115,8 @@
1.18 - "%r" ((USItype)(al)), \
1.19 - "rI" ((USItype)(bl)))
1.20 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.21 -- __asm__ ("sub %1,%4,%5
1.22 -- subc %0,%2,%3" \
1.23 -+ __asm__ ("sub %1,%4,%5\n" \
1.24 -+ "subc %0,%2,%3" \
1.25 - : "=r" ((USItype)(sh)), \
1.26 - "=&r" ((USItype)(sl)) \
1.27 - : "r" ((USItype)(ah)), \
1.28 -@@ -173,8 +173,8 @@
1.29 -
1.30 - #if defined (__arm__) && W_TYPE_SIZE == 32
1.31 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.32 -- __asm__ ("adds %1, %4, %5
1.33 -- adc %0, %2, %3" \
1.34 -+ __asm__ ("adds %1, %4, %5\n" \
1.35 -+ "adc %0, %2, %3" \
1.36 - : "=r" ((USItype)(sh)), \
1.37 - "=&r" ((USItype)(sl)) \
1.38 - : "%r" ((USItype)(ah)), \
1.39 -@@ -182,8 +182,8 @@
1.40 - "%r" ((USItype)(al)), \
1.41 - "rI" ((USItype)(bl)))
1.42 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.43 -- __asm__ ("subs %1, %4, %5
1.44 -- sbc %0, %2, %3" \
1.45 -+ __asm__ ("subs %1, %4, %5\n" \
1.46 -+ "sbc %0, %2, %3" \
1.47 - : "=r" ((USItype)(sh)), \
1.48 - "=&r" ((USItype)(sl)) \
1.49 - : "r" ((USItype)(ah)), \
1.50 -@@ -192,19 +192,19 @@
1.51 - "rI" ((USItype)(bl)))
1.52 - #if 0
1.53 - #define umul_ppmm(xh, xl, a, b) \
1.54 -- __asm__ ("%@ Inlined umul_ppmm
1.55 -- mov %|r0, %2, lsr #16
1.56 -- mov %|r2, %3, lsr #16
1.57 -- bic %|r1, %2, %|r0, lsl #16
1.58 -- bic %|r2, %3, %|r2, lsl #16
1.59 -- mul %1, %|r1, %|r2
1.60 -- mul %|r2, %|r0, %|r2
1.61 -- mul %|r1, %0, %|r1
1.62 -- mul %0, %|r0, %0
1.63 -- adds %|r1, %|r2, %|r1
1.64 -- addcs %0, %0, #65536
1.65 -- adds %1, %1, %|r1, lsl #16
1.66 -- adc %0, %0, %|r1, lsr #16" \
1.67 -+ __asm__ ("%@ Inlined umul_ppmm\n" \
1.68 -+ "mov %|r0, %2, lsr #16\n" \
1.69 -+ "mov %|r2, %3, lsr #16\n" \
1.70 -+ "bic %|r1, %2, %|r0, lsl #16\n" \
1.71 -+ "bic %|r2, %3, %|r2, lsl #16\n" \
1.72 -+ "mul %1, %|r1, %|r2\n" \
1.73 -+ "mul %|r2, %|r0, %|r2\n" \
1.74 -+ "mul %|r1, %0, %|r1\n" \
1.75 -+ "mul %0, %|r0, %0\n" \
1.76 -+ "adds %|r1, %|r2, %|r1\n" \
1.77 -+ "addcs %0, %0, #65536\n" \
1.78 -+ "adds %1, %1, %|r1, lsl #16\n" \
1.79 -+ "adc %0, %0, %|r1, lsr #16" \
1.80 - : "=&r" ((USItype)(xh)), \
1.81 - "=r" ((USItype)(xl)) \
1.82 - : "r" ((USItype)(a)), \
1.83 -@@ -245,8 +245,8 @@
1.84 -
1.85 - #if defined (__gmicro__) && W_TYPE_SIZE == 32
1.86 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.87 -- __asm__ ("add.w %5,%1
1.88 -- addx %3,%0" \
1.89 -+ __asm__ ("add.w %5,%1\n" \
1.90 -+ "addx %3,%0" \
1.91 - : "=g" ((USItype)(sh)), \
1.92 - "=&g" ((USItype)(sl)) \
1.93 - : "%0" ((USItype)(ah)), \
1.94 -@@ -254,8 +254,8 @@
1.95 - "%1" ((USItype)(al)), \
1.96 - "g" ((USItype)(bl)))
1.97 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.98 -- __asm__ ("sub.w %5,%1
1.99 -- subx %3,%0" \
1.100 -+ __asm__ ("sub.w %5,%1\n" \
1.101 -+ "subx %3,%0" \
1.102 - : "=g" ((USItype)(sh)), \
1.103 - "=&g" ((USItype)(sl)) \
1.104 - : "0" ((USItype)(ah)), \
1.105 -@@ -284,8 +284,8 @@
1.106 -
1.107 - #if defined (__hppa) && W_TYPE_SIZE == 32
1.108 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.109 -- __asm__ ("add %4,%5,%1
1.110 -- addc %2,%3,%0" \
1.111 -+ __asm__ ("add %4,%5,%1\n" \
1.112 -+ "addc %2,%3,%0" \
1.113 - : "=r" ((USItype)(sh)), \
1.114 - "=&r" ((USItype)(sl)) \
1.115 - : "%rM" ((USItype)(ah)), \
1.116 -@@ -293,8 +293,8 @@
1.117 - "%rM" ((USItype)(al)), \
1.118 - "rM" ((USItype)(bl)))
1.119 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.120 -- __asm__ ("sub %4,%5,%1
1.121 -- subb %2,%3,%0" \
1.122 -+ __asm__ ("sub %4,%5,%1\n" \
1.123 -+ "subb %2,%3,%0" \
1.124 - : "=r" ((USItype)(sh)), \
1.125 - "=&r" ((USItype)(sl)) \
1.126 - : "rM" ((USItype)(ah)), \
1.127 -@@ -332,22 +332,22 @@
1.128 - do { \
1.129 - USItype __tmp; \
1.130 - __asm__ ( \
1.131 -- "ldi 1,%0
1.132 -- extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
1.133 -- extru,tr %1,15,16,%1 ; No. Shift down, skip add.
1.134 -- ldo 16(%0),%0 ; Yes. Perform add.
1.135 -- extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
1.136 -- extru,tr %1,23,8,%1 ; No. Shift down, skip add.
1.137 -- ldo 8(%0),%0 ; Yes. Perform add.
1.138 -- extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
1.139 -- extru,tr %1,27,4,%1 ; No. Shift down, skip add.
1.140 -- ldo 4(%0),%0 ; Yes. Perform add.
1.141 -- extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
1.142 -- extru,tr %1,29,2,%1 ; No. Shift down, skip add.
1.143 -- ldo 2(%0),%0 ; Yes. Perform add.
1.144 -- extru %1,30,1,%1 ; Extract bit 1.
1.145 -- sub %0,%1,%0 ; Subtract it.
1.146 -- " : "=r" (count), "=r" (__tmp) : "1" (x)); \
1.147 -+ "ldi 1,%0\n" \
1.148 -+ "extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
1.149 -+ "extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
1.150 -+ "ldo 16(%0),%0 ; Yes. Perform add.\n" \
1.151 -+ "extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
1.152 -+ "extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
1.153 -+ "ldo 8(%0),%0 ; Yes. Perform add.\n" \
1.154 -+ "extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
1.155 -+ "extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
1.156 -+ "ldo 4(%0),%0 ; Yes. Perform add.\n" \
1.157 -+ "extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
1.158 -+ "extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
1.159 -+ "ldo 2(%0),%0 ; Yes. Perform add.\n" \
1.160 -+ "extru %1,30,1,%1 ; Extract bit 1.\n" \
1.161 -+ "sub %0,%1,%0 ; Subtract it.\n" \
1.162 -+ : "=r" (count), "=r" (__tmp) : "1" (x)); \
1.163 - } while (0)
1.164 - #endif /* hppa */
1.165 -
1.166 -@@ -394,8 +394,8 @@
1.167 -
1.168 - #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
1.169 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.170 -- __asm__ ("addl %5,%1
1.171 -- adcl %3,%0" \
1.172 -+ __asm__ ("addl %5,%1\n" \
1.173 -+ "adcl %3,%0" \
1.174 - : "=r" ((USItype)(sh)), \
1.175 - "=&r" ((USItype)(sl)) \
1.176 - : "%0" ((USItype)(ah)), \
1.177 -@@ -403,8 +403,8 @@
1.178 - "%1" ((USItype)(al)), \
1.179 - "g" ((USItype)(bl)))
1.180 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.181 -- __asm__ ("subl %5,%1
1.182 -- sbbl %3,%0" \
1.183 -+ __asm__ ("subl %5,%1\n" \
1.184 -+ "sbbl %3,%0" \
1.185 - : "=r" ((USItype)(sh)), \
1.186 - "=&r" ((USItype)(sl)) \
1.187 - : "0" ((USItype)(ah)), \
1.188 -@@ -516,8 +516,8 @@
1.189 -
1.190 - #if (defined (__mc68000__) || defined (__mc68020__) || defined (__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
1.191 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.192 -- __asm__ ("add%.l %5,%1
1.193 -- addx%.l %3,%0" \
1.194 -+ __asm__ ("add%.l %5,%1\n" \
1.195 -+ "addx%.l %3,%0" \
1.196 - : "=d" ((USItype)(sh)), \
1.197 - "=&d" ((USItype)(sl)) \
1.198 - : "%0" ((USItype)(ah)), \
1.199 -@@ -525,8 +525,8 @@
1.200 - "%1" ((USItype)(al)), \
1.201 - "g" ((USItype)(bl)))
1.202 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.203 -- __asm__ ("sub%.l %5,%1
1.204 -- subx%.l %3,%0" \
1.205 -+ __asm__ ("sub%.l %5,%1\n" \
1.206 -+ "subx%.l %3,%0" \
1.207 - : "=d" ((USItype)(sh)), \
1.208 - "=&d" ((USItype)(sl)) \
1.209 - : "0" ((USItype)(ah)), \
1.210 -@@ -564,28 +564,28 @@
1.211 - #else /* not mc68020 */
1.212 - #define umul_ppmm(xh, xl, a, b) \
1.213 - do { USItype __umul_tmp1, __umul_tmp2; \
1.214 -- __asm__ ("| Inlined umul_ppmm
1.215 -- move%.l %5,%3
1.216 -- move%.l %2,%0
1.217 -- move%.w %3,%1
1.218 -- swap %3
1.219 -- swap %0
1.220 -- mulu %2,%1
1.221 -- mulu %3,%0
1.222 -- mulu %2,%3
1.223 -- swap %2
1.224 -- mulu %5,%2
1.225 -- add%.l %3,%2
1.226 -- jcc 1f
1.227 -- add%.l %#0x10000,%0
1.228 --1: move%.l %2,%3
1.229 -- clr%.w %2
1.230 -- swap %2
1.231 -- swap %3
1.232 -- clr%.w %3
1.233 -- add%.l %3,%1
1.234 -- addx%.l %2,%0
1.235 -- | End inlined umul_ppmm" \
1.236 -+ __asm__ ("| Inlined umul_ppmm\n" \
1.237 -+ "move%.l %5,%3\n" \
1.238 -+ "move%.l %2,%0\n" \
1.239 -+ "move%.w %3,%1\n" \
1.240 -+ "swap %3\n" \
1.241 -+ "swap %0\n" \
1.242 -+ "mulu %2,%1\n" \
1.243 -+ "mulu %3,%0\n" \
1.244 -+ "mulu %2,%3\n" \
1.245 -+ "swap %2\n" \
1.246 -+ "mulu %5,%2\n" \
1.247 -+ "add%.l %3,%2\n" \
1.248 -+ "jcc 1f\n" \
1.249 -+ "add%.l %#0x10000,%0\n" \
1.250 -+"1: move%.l %2,%3\n" \
1.251 -+ "clr%.w %2\n" \
1.252 -+ "swap %2\n" \
1.253 -+ "swap %3\n" \
1.254 -+ "clr%.w %3\n" \
1.255 -+ "add%.l %3,%1\n" \
1.256 -+ "addx%.l %2,%0\n" \
1.257 -+ "| End inlined umul_ppmm" \
1.258 - : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
1.259 - "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
1.260 - : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
1.261 -@@ -597,8 +597,8 @@
1.262 -
1.263 - #if defined (__m88000__) && W_TYPE_SIZE == 32
1.264 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.265 -- __asm__ ("addu.co %1,%r4,%r5
1.266 -- addu.ci %0,%r2,%r3" \
1.267 -+ __asm__ ("addu.co %1,%r4,%r5\n" \
1.268 -+ "addu.ci %0,%r2,%r3" \
1.269 - : "=r" ((USItype)(sh)), \
1.270 - "=&r" ((USItype)(sl)) \
1.271 - : "%rJ" ((USItype)(ah)), \
1.272 -@@ -606,8 +606,8 @@
1.273 - "%rJ" ((USItype)(al)), \
1.274 - "rJ" ((USItype)(bl)))
1.275 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.276 -- __asm__ ("subu.co %1,%r4,%r5
1.277 -- subu.ci %0,%r2,%r3" \
1.278 -+ __asm__ ("subu.co %1,%r4,%r5\n" \
1.279 -+ "subu.ci %0,%r2,%r3" \
1.280 - : "=r" ((USItype)(sh)), \
1.281 - "=&r" ((USItype)(sl)) \
1.282 - : "rJ" ((USItype)(ah)), \
1.283 -@@ -665,9 +665,9 @@
1.284 - "d" ((USItype)(v)))
1.285 - #else
1.286 - #define umul_ppmm(w1, w0, u, v) \
1.287 -- __asm__ ("multu %2,%3
1.288 -- mflo %0
1.289 -- mfhi %1" \
1.290 -+ __asm__ ("multu %2,%3\n" \
1.291 -+ "mflo %0\n" \
1.292 -+ "mfhi %1" \
1.293 - : "=d" ((USItype)(w0)), \
1.294 - "=d" ((USItype)(w1)) \
1.295 - : "d" ((USItype)(u)), \
1.296 -@@ -687,9 +687,9 @@
1.297 - "d" ((UDItype)(v)))
1.298 - #else
1.299 - #define umul_ppmm(w1, w0, u, v) \
1.300 -- __asm__ ("dmultu %2,%3
1.301 -- mflo %0
1.302 -- mfhi %1" \
1.303 -+ __asm__ ("dmultu %2,%3\n" \
1.304 -+ "mflo %0\n" \
1.305 -+ "mfhi %1" \
1.306 - : "=d" ((UDItype)(w0)), \
1.307 - "=d" ((UDItype)(w1)) \
1.308 - : "d" ((UDItype)(u)), \
1.309 -@@ -857,8 +857,8 @@
1.310 -
1.311 - #if defined (__pyr__) && W_TYPE_SIZE == 32
1.312 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.313 -- __asm__ ("addw %5,%1
1.314 -- addwc %3,%0" \
1.315 -+ __asm__ ("addw %5,%1\n" \
1.316 -+ "addwc %3,%0" \
1.317 - : "=r" ((USItype)(sh)), \
1.318 - "=&r" ((USItype)(sl)) \
1.319 - : "%0" ((USItype)(ah)), \
1.320 -@@ -866,8 +866,8 @@
1.321 - "%1" ((USItype)(al)), \
1.322 - "g" ((USItype)(bl)))
1.323 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.324 -- __asm__ ("subw %5,%1
1.325 -- subwb %3,%0" \
1.326 -+ __asm__ ("subw %5,%1\n" \
1.327 -+ "subwb %3,%0" \
1.328 - : "=r" ((USItype)(sh)), \
1.329 - "=&r" ((USItype)(sl)) \
1.330 - : "0" ((USItype)(ah)), \
1.331 -@@ -879,8 +879,8 @@
1.332 - ({union {UDItype __ll; \
1.333 - struct {USItype __h, __l;} __i; \
1.334 - } __xx; \
1.335 -- __asm__ ("movw %1,%R0
1.336 -- uemul %2,%0" \
1.337 -+ __asm__ ("movw %1,%R0\n" \
1.338 -+ "uemul %2,%0" \
1.339 - : "=&r" (__xx.__ll) \
1.340 - : "g" ((USItype) (u)), \
1.341 - "g" ((USItype)(v))); \
1.342 -@@ -889,8 +889,8 @@
1.343 -
1.344 - #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
1.345 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.346 -- __asm__ ("a %1,%5
1.347 -- ae %0,%3" \
1.348 -+ __asm__ ("a %1,%5\n" \
1.349 -+ "ae %0,%3" \
1.350 - : "=r" ((USItype)(sh)), \
1.351 - "=&r" ((USItype)(sl)) \
1.352 - : "%0" ((USItype)(ah)), \
1.353 -@@ -898,8 +898,8 @@
1.354 - "%1" ((USItype)(al)), \
1.355 - "r" ((USItype)(bl)))
1.356 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.357 -- __asm__ ("s %1,%5
1.358 -- se %0,%3" \
1.359 -+ __asm__ ("s %1,%5\n" \
1.360 -+ "se %0,%3" \
1.361 - : "=r" ((USItype)(sh)), \
1.362 - "=&r" ((USItype)(sl)) \
1.363 - : "0" ((USItype)(ah)), \
1.364 -@@ -910,26 +910,26 @@
1.365 - do { \
1.366 - USItype __m0 = (m0), __m1 = (m1); \
1.367 - __asm__ ( \
1.368 -- "s r2,r2
1.369 -- mts r10,%2
1.370 -- m r2,%3
1.371 -- m r2,%3
1.372 -- m r2,%3
1.373 -- m r2,%3
1.374 -- m r2,%3
1.375 -- m r2,%3
1.376 -- m r2,%3
1.377 -- m r2,%3
1.378 -- m r2,%3
1.379 -- m r2,%3
1.380 -- m r2,%3
1.381 -- m r2,%3
1.382 -- m r2,%3
1.383 -- m r2,%3
1.384 -- m r2,%3
1.385 -- m r2,%3
1.386 -- cas %0,r2,r0
1.387 -- mfs r10,%1" \
1.388 -+ "s r2,r2\n" \
1.389 -+ "mts r10,%2\n" \
1.390 -+ "m r2,%3\n" \
1.391 -+ "m r2,%3\n" \
1.392 -+ "m r2,%3\n" \
1.393 -+ "m r2,%3\n" \
1.394 -+ "m r2,%3\n" \
1.395 -+ "m r2,%3\n" \
1.396 -+ "m r2,%3\n" \
1.397 -+ "m r2,%3\n" \
1.398 -+ "m r2,%3\n" \
1.399 -+ "m r2,%3\n" \
1.400 -+ "m r2,%3\n" \
1.401 -+ "m r2,%3\n" \
1.402 -+ "m r2,%3\n" \
1.403 -+ "m r2,%3\n" \
1.404 -+ "m r2,%3\n" \
1.405 -+ "m r2,%3\n" \
1.406 -+ "cas %0,r2,r0\n" \
1.407 -+ "mfs r10,%1" \
1.408 - : "=r" ((USItype)(ph)), \
1.409 - "=r" ((USItype)(pl)) \
1.410 - : "%r" (__m0), \
1.411 -@@ -959,9 +959,9 @@
1.412 - #if defined (__sh2__) && W_TYPE_SIZE == 32
1.413 - #define umul_ppmm(w1, w0, u, v) \
1.414 - __asm__ ( \
1.415 -- "dmulu.l %2,%3
1.416 -- sts macl,%1
1.417 -- sts mach,%0" \
1.418 -+ "dmulu.l %2,%3\n" \
1.419 -+ "sts macl,%1\n" \
1.420 -+ "sts mach,%0" \
1.421 - : "=r" ((USItype)(w1)), \
1.422 - "=r" ((USItype)(w0)) \
1.423 - : "r" ((USItype)(u)), \
1.424 -@@ -972,8 +972,8 @@
1.425 -
1.426 - #if defined (__sparc__) && W_TYPE_SIZE == 32
1.427 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.428 -- __asm__ ("addcc %r4,%5,%1
1.429 -- addx %r2,%3,%0" \
1.430 -+ __asm__ ("addcc %r4,%5,%1\n" \
1.431 -+ "addx %r2,%3,%0" \
1.432 - : "=r" ((USItype)(sh)), \
1.433 - "=&r" ((USItype)(sl)) \
1.434 - : "%rJ" ((USItype)(ah)), \
1.435 -@@ -982,8 +982,8 @@
1.436 - "rI" ((USItype)(bl)) \
1.437 - __CLOBBER_CC)
1.438 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.439 -- __asm__ ("subcc %r4,%5,%1
1.440 -- subx %r2,%3,%0" \
1.441 -+ __asm__ ("subcc %r4,%5,%1\n" \
1.442 -+ "subx %r2,%3,%0" \
1.443 - : "=r" ((USItype)(sh)), \
1.444 - "=&r" ((USItype)(sl)) \
1.445 - : "rJ" ((USItype)(ah)), \
1.446 -@@ -1029,45 +1029,45 @@
1.447 - "r" ((USItype)(v)))
1.448 - #define UMUL_TIME 5
1.449 - #define udiv_qrnnd(q, r, n1, n0, d) \
1.450 -- __asm__ ("! Inlined udiv_qrnnd
1.451 -- wr %%g0,%2,%%y ! Not a delayed write for sparclite
1.452 -- tst %%g0
1.453 -- divscc %3,%4,%%g1
1.454 -- divscc %%g1,%4,%%g1
1.455 -- divscc %%g1,%4,%%g1
1.456 -- divscc %%g1,%4,%%g1
1.457 -- divscc %%g1,%4,%%g1
1.458 -- divscc %%g1,%4,%%g1
1.459 -- divscc %%g1,%4,%%g1
1.460 -- divscc %%g1,%4,%%g1
1.461 -- divscc %%g1,%4,%%g1
1.462 -- divscc %%g1,%4,%%g1
1.463 -- divscc %%g1,%4,%%g1
1.464 -- divscc %%g1,%4,%%g1
1.465 -- divscc %%g1,%4,%%g1
1.466 -- divscc %%g1,%4,%%g1
1.467 -- divscc %%g1,%4,%%g1
1.468 -- divscc %%g1,%4,%%g1
1.469 -- divscc %%g1,%4,%%g1
1.470 -- divscc %%g1,%4,%%g1
1.471 -- divscc %%g1,%4,%%g1
1.472 -- divscc %%g1,%4,%%g1
1.473 -- divscc %%g1,%4,%%g1
1.474 -- divscc %%g1,%4,%%g1
1.475 -- divscc %%g1,%4,%%g1
1.476 -- divscc %%g1,%4,%%g1
1.477 -- divscc %%g1,%4,%%g1
1.478 -- divscc %%g1,%4,%%g1
1.479 -- divscc %%g1,%4,%%g1
1.480 -- divscc %%g1,%4,%%g1
1.481 -- divscc %%g1,%4,%%g1
1.482 -- divscc %%g1,%4,%%g1
1.483 -- divscc %%g1,%4,%%g1
1.484 -- divscc %%g1,%4,%0
1.485 -- rd %%y,%1
1.486 -- bl,a 1f
1.487 -- add %1,%4,%1
1.488 --1: ! End of inline udiv_qrnnd" \
1.489 -+ __asm__ ("! Inlined udiv_qrnnd\n" \
1.490 -+ "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1.491 -+ "tst %%g0\n" \
1.492 -+ "divscc %3,%4,%%g1\n" \
1.493 -+ "divscc %%g1,%4,%%g1\n" \
1.494 -+ "divscc %%g1,%4,%%g1\n" \
1.495 -+ "divscc %%g1,%4,%%g1\n" \
1.496 -+ "divscc %%g1,%4,%%g1\n" \
1.497 -+ "divscc %%g1,%4,%%g1\n" \
1.498 -+ "divscc %%g1,%4,%%g1\n" \
1.499 -+ "divscc %%g1,%4,%%g1\n" \
1.500 -+ "divscc %%g1,%4,%%g1\n" \
1.501 -+ "divscc %%g1,%4,%%g1\n" \
1.502 -+ "divscc %%g1,%4,%%g1\n" \
1.503 -+ "divscc %%g1,%4,%%g1\n" \
1.504 -+ "divscc %%g1,%4,%%g1\n" \
1.505 -+ "divscc %%g1,%4,%%g1\n" \
1.506 -+ "divscc %%g1,%4,%%g1\n" \
1.507 -+ "divscc %%g1,%4,%%g1\n" \
1.508 -+ "divscc %%g1,%4,%%g1\n" \
1.509 -+ "divscc %%g1,%4,%%g1\n" \
1.510 -+ "divscc %%g1,%4,%%g1\n" \
1.511 -+ "divscc %%g1,%4,%%g1\n" \
1.512 -+ "divscc %%g1,%4,%%g1\n" \
1.513 -+ "divscc %%g1,%4,%%g1\n" \
1.514 -+ "divscc %%g1,%4,%%g1\n" \
1.515 -+ "divscc %%g1,%4,%%g1\n" \
1.516 -+ "divscc %%g1,%4,%%g1\n" \
1.517 -+ "divscc %%g1,%4,%%g1\n" \
1.518 -+ "divscc %%g1,%4,%%g1\n" \
1.519 -+ "divscc %%g1,%4,%%g1\n" \
1.520 -+ "divscc %%g1,%4,%%g1\n" \
1.521 -+ "divscc %%g1,%4,%%g1\n" \
1.522 -+ "divscc %%g1,%4,%%g1\n" \
1.523 -+ "divscc %%g1,%4,%0\n" \
1.524 -+ "rd %%y,%1\n" \
1.525 -+ "bl,a 1f\n" \
1.526 -+ "add %1,%4,%1\n" \
1.527 -+"1: ! End of inline udiv_qrnnd" \
1.528 - : "=r" ((USItype)(q)), \
1.529 - "=r" ((USItype)(r)) \
1.530 - : "r" ((USItype)(n1)), \
1.531 -@@ -1087,46 +1087,46 @@
1.532 - /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd. */
1.533 - #ifndef umul_ppmm
1.534 - #define umul_ppmm(w1, w0, u, v) \
1.535 -- __asm__ ("! Inlined umul_ppmm
1.536 -- wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
1.537 -- sra %3,31,%%g2 ! Don't move this insn
1.538 -- and %2,%%g2,%%g2 ! Don't move this insn
1.539 -- andcc %%g0,0,%%g1 ! Don't move this insn
1.540 -- mulscc %%g1,%3,%%g1
1.541 -- mulscc %%g1,%3,%%g1
1.542 -- mulscc %%g1,%3,%%g1
1.543 -- mulscc %%g1,%3,%%g1
1.544 -- mulscc %%g1,%3,%%g1
1.545 -- mulscc %%g1,%3,%%g1
1.546 -- mulscc %%g1,%3,%%g1
1.547 -- mulscc %%g1,%3,%%g1
1.548 -- mulscc %%g1,%3,%%g1
1.549 -- mulscc %%g1,%3,%%g1
1.550 -- mulscc %%g1,%3,%%g1
1.551 -- mulscc %%g1,%3,%%g1
1.552 -- mulscc %%g1,%3,%%g1
1.553 -- mulscc %%g1,%3,%%g1
1.554 -- mulscc %%g1,%3,%%g1
1.555 -- mulscc %%g1,%3,%%g1
1.556 -- mulscc %%g1,%3,%%g1
1.557 -- mulscc %%g1,%3,%%g1
1.558 -- mulscc %%g1,%3,%%g1
1.559 -- mulscc %%g1,%3,%%g1
1.560 -- mulscc %%g1,%3,%%g1
1.561 -- mulscc %%g1,%3,%%g1
1.562 -- mulscc %%g1,%3,%%g1
1.563 -- mulscc %%g1,%3,%%g1
1.564 -- mulscc %%g1,%3,%%g1
1.565 -- mulscc %%g1,%3,%%g1
1.566 -- mulscc %%g1,%3,%%g1
1.567 -- mulscc %%g1,%3,%%g1
1.568 -- mulscc %%g1,%3,%%g1
1.569 -- mulscc %%g1,%3,%%g1
1.570 -- mulscc %%g1,%3,%%g1
1.571 -- mulscc %%g1,%3,%%g1
1.572 -- mulscc %%g1,0,%%g1
1.573 -- add %%g1,%%g2,%0
1.574 -- rd %%y,%1" \
1.575 -+ __asm__ ("! Inlined umul_ppmm\n" \
1.576 -+ "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
1.577 -+ "sra %3,31,%%g2 ! Don't move this insn\n" \
1.578 -+ "and %2,%%g2,%%g2 ! Don't move this insn\n" \
1.579 -+ "andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1.580 -+ "mulscc %%g1,%3,%%g1\n" \
1.581 -+ "mulscc %%g1,%3,%%g1\n" \
1.582 -+ "mulscc %%g1,%3,%%g1\n" \
1.583 -+ "mulscc %%g1,%3,%%g1\n" \
1.584 -+ "mulscc %%g1,%3,%%g1\n" \
1.585 -+ "mulscc %%g1,%3,%%g1\n" \
1.586 -+ "mulscc %%g1,%3,%%g1\n" \
1.587 -+ "mulscc %%g1,%3,%%g1\n" \
1.588 -+ "mulscc %%g1,%3,%%g1\n" \
1.589 -+ "mulscc %%g1,%3,%%g1\n" \
1.590 -+ "mulscc %%g1,%3,%%g1\n" \
1.591 -+ "mulscc %%g1,%3,%%g1\n" \
1.592 -+ "mulscc %%g1,%3,%%g1\n" \
1.593 -+ "mulscc %%g1,%3,%%g1\n" \
1.594 -+ "mulscc %%g1,%3,%%g1\n" \
1.595 -+ "mulscc %%g1,%3,%%g1\n" \
1.596 -+ "mulscc %%g1,%3,%%g1\n" \
1.597 -+ "mulscc %%g1,%3,%%g1\n" \
1.598 -+ "mulscc %%g1,%3,%%g1\n" \
1.599 -+ "mulscc %%g1,%3,%%g1\n" \
1.600 -+ "mulscc %%g1,%3,%%g1\n" \
1.601 -+ "mulscc %%g1,%3,%%g1\n" \
1.602 -+ "mulscc %%g1,%3,%%g1\n" \
1.603 -+ "mulscc %%g1,%3,%%g1\n" \
1.604 -+ "mulscc %%g1,%3,%%g1\n" \
1.605 -+ "mulscc %%g1,%3,%%g1\n" \
1.606 -+ "mulscc %%g1,%3,%%g1\n" \
1.607 -+ "mulscc %%g1,%3,%%g1\n" \
1.608 -+ "mulscc %%g1,%3,%%g1\n" \
1.609 -+ "mulscc %%g1,%3,%%g1\n" \
1.610 -+ "mulscc %%g1,%3,%%g1\n" \
1.611 -+ "mulscc %%g1,%3,%%g1\n" \
1.612 -+ "mulscc %%g1,0,%%g1\n" \
1.613 -+ "add %%g1,%%g2,%0\n" \
1.614 -+ "rd %%y,%1" \
1.615 - : "=r" ((USItype)(w1)), \
1.616 - "=r" ((USItype)(w0)) \
1.617 - : "%rI" ((USItype)(u)), \
1.618 -@@ -1138,30 +1138,30 @@
1.619 - /* It's quite necessary to add this much assembler for the sparc.
1.620 - The default udiv_qrnnd (in C) is more than 10 times slower! */
1.621 - #define udiv_qrnnd(q, r, n1, n0, d) \
1.622 -- __asm__ ("! Inlined udiv_qrnnd
1.623 -- mov 32,%%g1
1.624 -- subcc %1,%2,%%g0
1.625 --1: bcs 5f
1.626 -- addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1.627 -- sub %1,%2,%1 ! this kills msb of n
1.628 -- addx %1,%1,%1 ! so this can't give carry
1.629 -- subcc %%g1,1,%%g1
1.630 --2: bne 1b
1.631 -- subcc %1,%2,%%g0
1.632 -- bcs 3f
1.633 -- addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1.634 -- b 3f
1.635 -- sub %1,%2,%1 ! this kills msb of n
1.636 --4: sub %1,%2,%1
1.637 --5: addxcc %1,%1,%1
1.638 -- bcc 2b
1.639 -- subcc %%g1,1,%%g1
1.640 --! Got carry from n. Subtract next step to cancel this carry.
1.641 -- bne 4b
1.642 -- addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
1.643 -- sub %1,%2,%1
1.644 --3: xnor %0,0,%0
1.645 -- ! End of inline udiv_qrnnd" \
1.646 -+ __asm__ ("! Inlined udiv_qrnnd\n" \
1.647 -+ "mov 32,%%g1\n" \
1.648 -+ "subcc %1,%2,%%g0\n" \
1.649 -+"1: bcs 5f\n" \
1.650 -+ "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1.651 -+ "sub %1,%2,%1 ! this kills msb of n\n" \
1.652 -+ "addx %1,%1,%1 ! so this can't give carry\n" \
1.653 -+ "subcc %%g1,1,%%g1\n" \
1.654 -+"2: bne 1b\n" \
1.655 -+ "subcc %1,%2,%%g0\n" \
1.656 -+ "bcs 3f\n" \
1.657 -+ "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1.658 -+ "b 3f\n" \
1.659 -+ "sub %1,%2,%1 ! this kills msb of n\n" \
1.660 -+"4: sub %1,%2,%1\n" \
1.661 -+"5: addxcc %1,%1,%1\n" \
1.662 -+ "bcc 2b\n" \
1.663 -+ "subcc %%g1,1,%%g1\n" \
1.664 -+"! Got carry from n. Subtract next step to cancel this carry.\n" \
1.665 -+ "bne 4b\n" \
1.666 -+ "addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1.667 -+ "sub %1,%2,%1\n" \
1.668 -+"3: xnor %0,0,%0\n" \
1.669 -+ "! End of inline udiv_qrnnd" \
1.670 - : "=&r" ((USItype)(q)), \
1.671 - "=&r" ((USItype)(r)) \
1.672 - : "r" ((USItype)(d)), \
1.673 -@@ -1179,11 +1179,11 @@
1.674 - #if (defined (__sparc_v9__) || (defined (__sparc__) && defined (__arch64__)) \
1.675 - || defined (__sparcv9)) && W_TYPE_SIZE == 64
1.676 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.677 -- __asm__ ("addcc %r4,%5,%1
1.678 -- add %r2,%3,%0
1.679 -- bcs,a,pn %%xcc, 1f
1.680 -- add %0, 1, %0
1.681 -- 1:" \
1.682 -+ __asm__ ("addcc %r4,%5,%1\n" \
1.683 -+ "add %r2,%3,%0\n" \
1.684 -+ "bcs,a,pn %%xcc, 1f\n" \
1.685 -+ "add %0, 1, %0\n" \
1.686 -+ "1:" \
1.687 - : "=r" ((UDItype)(sh)), \
1.688 - "=&r" ((UDItype)(sl)) \
1.689 - : "r" ((UDItype)(ah)), \
1.690 -@@ -1193,11 +1193,11 @@
1.691 - : "cc")
1.692 -
1.693 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.694 -- __asm__ ("subcc %r4,%5,%1
1.695 -- sub %r2,%3,%0
1.696 -- bcs,a,pn %%xcc, 1f
1.697 -- sub %0, 1, %0
1.698 -- 1:" \
1.699 -+ __asm__ ("subcc %r4,%5,%1\n" \
1.700 -+ "sub %r2,%3,%0\n" \
1.701 -+ "bcs,a,pn %%xcc, 1f\n" \
1.702 -+ "sub %0, 1, %0\n" \
1.703 -+ "1:" \
1.704 - : "=r" ((UDItype)(sh)), \
1.705 - "=&r" ((UDItype)(sl)) \
1.706 - : "r" ((UDItype)(ah)), \
1.707 -@@ -1210,27 +1210,27 @@
1.708 - do { \
1.709 - UDItype tmp1, tmp2, tmp3, tmp4; \
1.710 - __asm__ __volatile__ ( \
1.711 -- "srl %7,0,%3
1.712 -- mulx %3,%6,%1
1.713 -- srlx %6,32,%2
1.714 -- mulx %2,%3,%4
1.715 -- sllx %4,32,%5
1.716 -- srl %6,0,%3
1.717 -- sub %1,%5,%5
1.718 -- srlx %5,32,%5
1.719 -- addcc %4,%5,%4
1.720 -- srlx %7,32,%5
1.721 -- mulx %3,%5,%3
1.722 -- mulx %2,%5,%5
1.723 -- sethi %%hi(0x80000000),%2
1.724 -- addcc %4,%3,%4
1.725 -- srlx %4,32,%4
1.726 -- add %2,%2,%2
1.727 -- movcc %%xcc,%%g0,%2
1.728 -- addcc %5,%4,%5
1.729 -- sllx %3,32,%3
1.730 -- add %1,%3,%1
1.731 -- add %5,%2,%0" \
1.732 -+ "srl %7,0,%3\n" \
1.733 -+ "mulx %3,%6,%1\n" \
1.734 -+ "srlx %6,32,%2\n" \
1.735 -+ "mulx %2,%3,%4\n" \
1.736 -+ "sllx %4,32,%5\n" \
1.737 -+ "srl %6,0,%3\n" \
1.738 -+ "sub %1,%5,%5\n" \
1.739 -+ "srlx %5,32,%5\n" \
1.740 -+ "addcc %4,%5,%4\n" \
1.741 -+ "srlx %7,32,%5\n" \
1.742 -+ "mulx %3,%5,%3\n" \
1.743 -+ "mulx %2,%5,%5\n" \
1.744 -+ "sethi %%hi(0x80000000),%2\n" \
1.745 -+ "addcc %4,%3,%4\n" \
1.746 -+ "srlx %4,32,%4\n" \
1.747 -+ "add %2,%2,%2\n" \
1.748 -+ "movcc %%xcc,%%g0,%2\n" \
1.749 -+ "addcc %5,%4,%5\n" \
1.750 -+ "sllx %3,32,%3\n" \
1.751 -+ "add %1,%3,%1\n" \
1.752 -+ "add %5,%2,%0" \
1.753 - : "=r" ((UDItype)(wh)), \
1.754 - "=&r" ((UDItype)(wl)), \
1.755 - "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1.756 -@@ -1244,8 +1244,8 @@
1.757 -
1.758 - #if defined (__vax__) && W_TYPE_SIZE == 32
1.759 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.760 -- __asm__ ("addl2 %5,%1
1.761 -- adwc %3,%0" \
1.762 -+ __asm__ ("addl2 %5,%1\n" \
1.763 -+ "adwc %3,%0" \
1.764 - : "=g" ((USItype)(sh)), \
1.765 - "=&g" ((USItype)(sl)) \
1.766 - : "%0" ((USItype)(ah)), \
1.767 -@@ -1253,8 +1253,8 @@
1.768 - "%1" ((USItype)(al)), \
1.769 - "g" ((USItype)(bl)))
1.770 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.771 -- __asm__ ("subl2 %5,%1
1.772 -- sbwc %3,%0" \
1.773 -+ __asm__ ("subl2 %5,%1\n" \
1.774 -+ "sbwc %3,%0" \
1.775 - : "=g" ((USItype)(sh)), \
1.776 - "=&g" ((USItype)(sl)) \
1.777 - : "0" ((USItype)(ah)), \