1.1 --- a/patches/glibc/2.2.2/glibc-2.2.2-allow-gcc3-longlong.patch Tue Aug 14 19:32:22 2007 +0000
1.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000
1.3 @@ -1,811 +0,0 @@
1.4 -Fixes error
1.5 -./longlong.h:423: error: parse error before '%' token
1.6 -./longlong.h:423: error: missing terminating " character
1.7 -./longlong.h:432: error: missing terminating " character
1.8 -See also patches/glibc-2.1.3/glibc-2.1.3-allow-gcc3-longlong.patch
1.9 -
1.10 -===================================================================
1.11 ---- glibc-2.2.2/stdlib/longlong.h.old 2000-02-11 15:48:58.000000000 -0800
1.12 -+++ glibc-2.2.2/stdlib/longlong.h 2005-04-11 15:36:10.000000000 -0700
1.13 -@@ -108,8 +108,8 @@
1.14 -
1.15 - #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32
1.16 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.17 -- __asm__ ("add %1,%4,%5
1.18 -- addc %0,%2,%3" \
1.19 -+ __asm__ ("add %1,%4,%5\n" \
1.20 -+ "addc %0,%2,%3" \
1.21 - : "=r" ((USItype) (sh)), \
1.22 - "=&r" ((USItype) (sl)) \
1.23 - : "%r" ((USItype) (ah)), \
1.24 -@@ -117,8 +117,8 @@
1.25 - "%r" ((USItype) (al)), \
1.26 - "rI" ((USItype) (bl)))
1.27 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.28 -- __asm__ ("sub %1,%4,%5
1.29 -- subc %0,%2,%3" \
1.30 -+ __asm__ ("sub %1,%4,%5\n" \
1.31 -+ "subc %0,%2,%3" \
1.32 - : "=r" ((USItype) (sh)), \
1.33 - "=&r" ((USItype) (sl)) \
1.34 - : "r" ((USItype) (ah)), \
1.35 -@@ -175,8 +175,8 @@
1.36 -
1.37 - #if defined (__arc__) && W_TYPE_SIZE == 32
1.38 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.39 -- __asm__ ("add.f %1, %4, %5
1.40 -- adc %0, %2, %3" \
1.41 -+ __asm__ ("add.f %1, %4, %5\n" \
1.42 -+ "adc %0, %2, %3" \
1.43 - : "=r" ((USItype) (sh)), \
1.44 - "=&r" ((USItype) (sl)) \
1.45 - : "%r" ((USItype) (ah)), \
1.46 -@@ -184,8 +184,8 @@
1.47 - "%r" ((USItype) (al)), \
1.48 - "rIJ" ((USItype) (bl)))
1.49 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.50 -- __asm__ ("sub.f %1, %4, %5
1.51 -- sbc %0, %2, %3" \
1.52 -+ __asm__ ("sub.f %1, %4, %5\n" \
1.53 -+ "sbc %0, %2, %3" \
1.54 - : "=r" ((USItype) (sh)), \
1.55 - "=&r" ((USItype) (sl)) \
1.56 - : "r" ((USItype) (ah)), \
1.57 -@@ -206,8 +206,8 @@
1.58 -
1.59 - #if defined (__arm__) && W_TYPE_SIZE == 32
1.60 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.61 -- __asm__ ("adds %1, %4, %5
1.62 -- adc %0, %2, %3" \
1.63 -+ __asm__ ("adds %1, %4, %5\n" \
1.64 -+ "adc %0, %2, %3" \
1.65 - : "=r" ((USItype) (sh)), \
1.66 - "=&r" ((USItype) (sl)) \
1.67 - : "%r" ((USItype) (ah)), \
1.68 -@@ -215,8 +215,8 @@
1.69 - "%r" ((USItype) (al)), \
1.70 - "rI" ((USItype) (bl)))
1.71 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.72 -- __asm__ ("subs %1, %4, %5
1.73 -- sbc %0, %2, %3" \
1.74 -+ __asm__ ("subs %1, %4, %5\n" \
1.75 -+ "sbc %0, %2, %3" \
1.76 - : "=r" ((USItype) (sh)), \
1.77 - "=&r" ((USItype) (sl)) \
1.78 - : "r" ((USItype) (ah)), \
1.79 -@@ -225,19 +225,19 @@
1.80 - "rI" ((USItype) (bl)))
1.81 - #define umul_ppmm(xh, xl, a, b) \
1.82 - {register USItype __t0, __t1, __t2; \
1.83 -- __asm__ ("%@ Inlined umul_ppmm
1.84 -- mov %2, %5, lsr #16
1.85 -- mov %0, %6, lsr #16
1.86 -- bic %3, %5, %2, lsl #16
1.87 -- bic %4, %6, %0, lsl #16
1.88 -- mul %1, %3, %4
1.89 -- mul %4, %2, %4
1.90 -- mul %3, %0, %3
1.91 -- mul %0, %2, %0
1.92 -- adds %3, %4, %3
1.93 -- addcs %0, %0, #65536
1.94 -- adds %1, %1, %3, lsl #16
1.95 -- adc %0, %0, %3, lsr #16" \
1.96 -+ __asm__ ("%@ Inlined umul_ppmm\n" \
1.97 -+ "mov %2, %5, lsr #16\n" \
1.98 -+ "mov %0, %6, lsr #16\n" \
1.99 -+ "bic %3, %5, %2, lsl #16\n" \
1.100 -+ "bic %4, %6, %0, lsl #16\n" \
1.101 -+ "mul %1, %3, %4\n" \
1.102 -+ "mul %4, %2, %4\n" \
1.103 -+ "mul %3, %0, %3\n" \
1.104 -+ "mul %0, %2, %0\n" \
1.105 -+ "adds %3, %4, %3\n" \
1.106 -+ "addcs %0, %0, #65536\n" \
1.107 -+ "adds %1, %1, %3, lsl #16\n" \
1.108 -+ "adc %0, %0, %3, lsr #16" \
1.109 - : "=&r" ((USItype) (xh)), \
1.110 - "=r" ((USItype) (xl)), \
1.111 - "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \
1.112 -@@ -277,8 +277,8 @@
1.113 -
1.114 - #if defined (__gmicro__) && W_TYPE_SIZE == 32
1.115 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.116 -- __asm__ ("add.w %5,%1
1.117 -- addx %3,%0" \
1.118 -+ __asm__ ("add.w %5,%1\n" \
1.119 -+ "addx %3,%0" \
1.120 - : "=g" ((USItype) (sh)), \
1.121 - "=&g" ((USItype) (sl)) \
1.122 - : "%0" ((USItype) (ah)), \
1.123 -@@ -286,8 +286,8 @@
1.124 - "%1" ((USItype) (al)), \
1.125 - "g" ((USItype) (bl)))
1.126 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.127 -- __asm__ ("sub.w %5,%1
1.128 -- subx %3,%0" \
1.129 -+ __asm__ ("sub.w %5,%1\n" \
1.130 -+ "subx %3,%0" \
1.131 - : "=g" ((USItype) (sh)), \
1.132 - "=&g" ((USItype) (sl)) \
1.133 - : "0" ((USItype) (ah)), \
1.134 -@@ -316,8 +316,8 @@
1.135 -
1.136 - #if defined (__hppa) && W_TYPE_SIZE == 32
1.137 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.138 -- __asm__ ("add %4,%5,%1
1.139 -- addc %2,%3,%0" \
1.140 -+ __asm__ ("add %4,%5,%1\n" \
1.141 -+ "addc %2,%3,%0" \
1.142 - : "=r" ((USItype) (sh)), \
1.143 - "=&r" ((USItype) (sl)) \
1.144 - : "%rM" ((USItype) (ah)), \
1.145 -@@ -325,8 +325,8 @@
1.146 - "%rM" ((USItype) (al)), \
1.147 - "rM" ((USItype) (bl)))
1.148 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.149 -- __asm__ ("sub %4,%5,%1
1.150 -- subb %2,%3,%0" \
1.151 -+ __asm__ ("sub %4,%5,%1\n" \
1.152 -+ "subb %2,%3,%0" \
1.153 - : "=r" ((USItype) (sh)), \
1.154 - "=&r" ((USItype) (sl)) \
1.155 - : "rM" ((USItype) (ah)), \
1.156 -@@ -357,22 +357,22 @@
1.157 - do { \
1.158 - USItype __tmp; \
1.159 - __asm__ ( \
1.160 -- "ldi 1,%0
1.161 -- extru,= %1,15,16,%%r0 ; Bits 31..16 zero?
1.162 -- extru,tr %1,15,16,%1 ; No. Shift down, skip add.
1.163 -- ldo 16(%0),%0 ; Yes. Perform add.
1.164 -- extru,= %1,23,8,%%r0 ; Bits 15..8 zero?
1.165 -- extru,tr %1,23,8,%1 ; No. Shift down, skip add.
1.166 -- ldo 8(%0),%0 ; Yes. Perform add.
1.167 -- extru,= %1,27,4,%%r0 ; Bits 7..4 zero?
1.168 -- extru,tr %1,27,4,%1 ; No. Shift down, skip add.
1.169 -- ldo 4(%0),%0 ; Yes. Perform add.
1.170 -- extru,= %1,29,2,%%r0 ; Bits 3..2 zero?
1.171 -- extru,tr %1,29,2,%1 ; No. Shift down, skip add.
1.172 -- ldo 2(%0),%0 ; Yes. Perform add.
1.173 -- extru %1,30,1,%1 ; Extract bit 1.
1.174 -- sub %0,%1,%0 ; Subtract it.
1.175 -- " : "=r" (count), "=r" (__tmp) : "1" (x)); \
1.176 -+ "ldi 1,%0\n" \
1.177 -+ "extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \
1.178 -+ "extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \
1.179 -+ "ldo 16(%0),%0 ; Yes. Perform add.\n" \
1.180 -+ "extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \
1.181 -+ "extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \
1.182 -+ "ldo 8(%0),%0 ; Yes. Perform add.\n" \
1.183 -+ "extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \
1.184 -+ "extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \
1.185 -+ "ldo 4(%0),%0 ; Yes. Perform add.\n" \
1.186 -+ "extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \
1.187 -+ "extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \
1.188 -+ "ldo 2(%0),%0 ; Yes. Perform add.\n" \
1.189 -+ "extru %1,30,1,%1 ; Extract bit 1.\n" \
1.190 -+ "sub %0,%1,%0 ; Subtract it.\n" \
1.191 -+ : "=r" (count), "=r" (__tmp) : "1" (x)); \
1.192 - } while (0)
1.193 - #endif
1.194 -
1.195 -@@ -419,8 +419,8 @@
1.196 -
1.197 - #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
1.198 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.199 -- __asm__ ("addl %5,%1
1.200 -- adcl %3,%0" \
1.201 -+ __asm__ ("addl %5,%1\n" \
1.202 -+ "adcl %3,%0" \
1.203 - : "=r" ((USItype) (sh)), \
1.204 - "=&r" ((USItype) (sl)) \
1.205 - : "%0" ((USItype) (ah)), \
1.206 -@@ -428,8 +428,8 @@
1.207 - "%1" ((USItype) (al)), \
1.208 - "g" ((USItype) (bl)))
1.209 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.210 -- __asm__ ("subl %5,%1
1.211 -- sbbl %3,%0" \
1.212 -+ __asm__ ("subl %5,%1\n" \
1.213 -+ "sbbl %3,%0" \
1.214 - : "=r" ((USItype) (sh)), \
1.215 - "=&r" ((USItype) (sl)) \
1.216 - : "0" ((USItype) (ah)), \
1.217 -@@ -525,9 +525,9 @@
1.218 - #if defined (__M32R__) && W_TYPE_SIZE == 32
1.219 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.220 - /* The cmp clears the condition bit. */ \
1.221 -- __asm__ ("cmp %0,%0
1.222 -- addx %%5,%1
1.223 -- addx %%3,%0" \
1.224 -+ __asm__ ("cmp %0,%0\n" \
1.225 -+ "addx %%5,%1\n" \
1.226 -+ "addx %%3,%0" \
1.227 - : "=r" ((USItype) (sh)), \
1.228 - "=&r" ((USItype) (sl)) \
1.229 - : "%0" ((USItype) (ah)), \
1.230 -@@ -537,9 +537,9 @@
1.231 - : "cbit")
1.232 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.233 - /* The cmp clears the condition bit. */ \
1.234 -- __asm__ ("cmp %0,%0
1.235 -- subx %5,%1
1.236 -- subx %3,%0" \
1.237 -+ __asm__ ("cmp %0,%0\n" \
1.238 -+ "subx %5,%1\n" \
1.239 -+ "subx %3,%0" \
1.240 - : "=r" ((USItype) (sh)), \
1.241 - "=&r" ((USItype) (sl)) \
1.242 - : "0" ((USItype) (ah)), \
1.243 -@@ -551,8 +551,8 @@
1.244 -
1.245 - #if defined (__mc68000__) && W_TYPE_SIZE == 32
1.246 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.247 -- __asm__ ("add%.l %5,%1
1.248 -- addx%.l %3,%0" \
1.249 -+ __asm__ ("add%.l %5,%1\n" \
1.250 -+ "addx%.l %3,%0" \
1.251 - : "=d" ((USItype) (sh)), \
1.252 - "=&d" ((USItype) (sl)) \
1.253 - : "%0" ((USItype) (ah)), \
1.254 -@@ -560,8 +560,8 @@
1.255 - "%1" ((USItype) (al)), \
1.256 - "g" ((USItype) (bl)))
1.257 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.258 -- __asm__ ("sub%.l %5,%1
1.259 -- subx%.l %3,%0" \
1.260 -+ __asm__ ("sub%.l %5,%1\n" \
1.261 -+ "subx%.l %3,%0" \
1.262 - : "=d" ((USItype) (sh)), \
1.263 - "=&d" ((USItype) (sl)) \
1.264 - : "0" ((USItype) (ah)), \
1.265 -@@ -602,32 +602,32 @@
1.266 - #if !defined(__mcf5200__)
1.267 - /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */
1.268 - #define umul_ppmm(xh, xl, a, b) \
1.269 -- __asm__ ("| Inlined umul_ppmm
1.270 -- move%.l %2,%/d0
1.271 -- move%.l %3,%/d1
1.272 -- move%.l %/d0,%/d2
1.273 -- swap %/d0
1.274 -- move%.l %/d1,%/d3
1.275 -- swap %/d1
1.276 -- move%.w %/d2,%/d4
1.277 -- mulu %/d3,%/d4
1.278 -- mulu %/d1,%/d2
1.279 -- mulu %/d0,%/d3
1.280 -- mulu %/d0,%/d1
1.281 -- move%.l %/d4,%/d0
1.282 -- eor%.w %/d0,%/d0
1.283 -- swap %/d0
1.284 -- add%.l %/d0,%/d2
1.285 -- add%.l %/d3,%/d2
1.286 -- jcc 1f
1.287 -- add%.l %#65536,%/d1
1.288 --1: swap %/d2
1.289 -- moveq %#0,%/d0
1.290 -- move%.w %/d2,%/d0
1.291 -- move%.w %/d4,%/d2
1.292 -- move%.l %/d2,%1
1.293 -- add%.l %/d1,%/d0
1.294 -- move%.l %/d0,%0" \
1.295 -+ __asm__ ("| Inlined umul_ppmm\n" \
1.296 -+ "move%.l %2,%/d0\n" \
1.297 -+ "move%.l %3,%/d1\n" \
1.298 -+ "move%.l %/d0,%/d2\n" \
1.299 -+ "swap %/d0\n" \
1.300 -+ "move%.l %/d1,%/d3\n" \
1.301 -+ "swap %/d1\n" \
1.302 -+ "move%.w %/d2,%/d4\n" \
1.303 -+ "mulu %/d3,%/d4\n" \
1.304 -+ "mulu %/d1,%/d2\n" \
1.305 -+ "mulu %/d0,%/d3\n" \
1.306 -+ "mulu %/d0,%/d1\n" \
1.307 -+ "move%.l %/d4,%/d0\n" \
1.308 -+ "eor%.w %/d0,%/d0\n" \
1.309 -+ "swap %/d0\n" \
1.310 -+ "add%.l %/d0,%/d2\n" \
1.311 -+ "add%.l %/d3,%/d2\n" \
1.312 -+ "jcc 1f\n" \
1.313 -+ "add%.l %#65536,%/d1\n" \
1.314 -+"1: swap %/d2\n" \
1.315 -+ "moveq %#0,%/d0\n" \
1.316 -+ "move%.w %/d2,%/d0\n" \
1.317 -+ "move%.w %/d4,%/d2\n" \
1.318 -+ "move%.l %/d2,%1\n" \
1.319 -+ "add%.l %/d1,%/d0\n" \
1.320 -+ "move%.l %/d0,%0" \
1.321 - : "=g" ((USItype) (xh)), \
1.322 - "=g" ((USItype) (xl)) \
1.323 - : "g" ((USItype) (a)), \
1.324 -@@ -653,8 +653,8 @@
1.325 -
1.326 - #if defined (__m88000__) && W_TYPE_SIZE == 32
1.327 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.328 -- __asm__ ("addu.co %1,%r4,%r5
1.329 -- addu.ci %0,%r2,%r3" \
1.330 -+ __asm__ ("addu.co %1,%r4,%r5\n" \
1.331 -+ "addu.ci %0,%r2,%r3" \
1.332 - : "=r" ((USItype) (sh)), \
1.333 - "=&r" ((USItype) (sl)) \
1.334 - : "%rJ" ((USItype) (ah)), \
1.335 -@@ -662,8 +662,8 @@
1.336 - "%rJ" ((USItype) (al)), \
1.337 - "rJ" ((USItype) (bl)))
1.338 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.339 -- __asm__ ("subu.co %1,%r4,%r5
1.340 -- subu.ci %0,%r2,%r3" \
1.341 -+ __asm__ ("subu.co %1,%r4,%r5\n" \
1.342 -+ "subu.ci %0,%r2,%r3" \
1.343 - : "=r" ((USItype) (sh)), \
1.344 - "=&r" ((USItype) (sl)) \
1.345 - : "rJ" ((USItype) (ah)), \
1.346 -@@ -880,8 +880,8 @@
1.347 -
1.348 - #if defined (__pyr__) && W_TYPE_SIZE == 32
1.349 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.350 -- __asm__ ("addw %5,%1
1.351 -- addwc %3,%0" \
1.352 -+ __asm__ ("addw %5,%1\n" \
1.353 -+ "addwc %3,%0" \
1.354 - : "=r" ((USItype) (sh)), \
1.355 - "=&r" ((USItype) (sl)) \
1.356 - : "%0" ((USItype) (ah)), \
1.357 -@@ -889,8 +889,8 @@
1.358 - "%1" ((USItype) (al)), \
1.359 - "g" ((USItype) (bl)))
1.360 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.361 -- __asm__ ("subw %5,%1
1.362 -- subwb %3,%0" \
1.363 -+ __asm__ ("subw %5,%1\n" \
1.364 -+ "subwb %3,%0" \
1.365 - : "=r" ((USItype) (sh)), \
1.366 - "=&r" ((USItype) (sl)) \
1.367 - : "0" ((USItype) (ah)), \
1.368 -@@ -902,8 +902,8 @@
1.369 - ({union {UDItype __ll; \
1.370 - struct {USItype __h, __l;} __i; \
1.371 - } __xx; \
1.372 -- __asm__ ("movw %1,%R0
1.373 -- uemul %2,%0" \
1.374 -+ __asm__ ("movw %1,%R0\n" \
1.375 -+ "uemul %2,%0" \
1.376 - : "=&r" (__xx.__ll) \
1.377 - : "g" ((USItype) (u)), \
1.378 - "g" ((USItype) (v))); \
1.379 -@@ -912,8 +912,8 @@
1.380 -
1.381 - #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
1.382 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.383 -- __asm__ ("a %1,%5
1.384 -- ae %0,%3" \
1.385 -+ __asm__ ("a %1,%5\n" \
1.386 -+ "ae %0,%3" \
1.387 - : "=r" ((USItype) (sh)), \
1.388 - "=&r" ((USItype) (sl)) \
1.389 - : "%0" ((USItype) (ah)), \
1.390 -@@ -921,8 +921,8 @@
1.391 - "%1" ((USItype) (al)), \
1.392 - "r" ((USItype) (bl)))
1.393 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.394 -- __asm__ ("s %1,%5
1.395 -- se %0,%3" \
1.396 -+ __asm__ ("s %1,%5\n" \
1.397 -+ "se %0,%3" \
1.398 - : "=r" ((USItype) (sh)), \
1.399 - "=&r" ((USItype) (sl)) \
1.400 - : "0" ((USItype) (ah)), \
1.401 -@@ -933,26 +933,26 @@
1.402 - do { \
1.403 - USItype __m0 = (m0), __m1 = (m1); \
1.404 - __asm__ ( \
1.405 -- "s r2,r2
1.406 -- mts r10,%2
1.407 -- m r2,%3
1.408 -- m r2,%3
1.409 -- m r2,%3
1.410 -- m r2,%3
1.411 -- m r2,%3
1.412 -- m r2,%3
1.413 -- m r2,%3
1.414 -- m r2,%3
1.415 -- m r2,%3
1.416 -- m r2,%3
1.417 -- m r2,%3
1.418 -- m r2,%3
1.419 -- m r2,%3
1.420 -- m r2,%3
1.421 -- m r2,%3
1.422 -- m r2,%3
1.423 -- cas %0,r2,r0
1.424 -- mfs r10,%1" \
1.425 -+ "s r2,r2\n"
1.426 -+ "mts r10,%2\n" \
1.427 -+ "m r2,%3\n" \
1.428 -+ "m r2,%3\n" \
1.429 -+ "m r2,%3\n" \
1.430 -+ "m r2,%3\n" \
1.431 -+ "m r2,%3\n" \
1.432 -+ "m r2,%3\n" \
1.433 -+ "m r2,%3\n" \
1.434 -+ "m r2,%3\n" \
1.435 -+ "m r2,%3\n" \
1.436 -+ "m r2,%3\n" \
1.437 -+ "m r2,%3\n" \
1.438 -+ "m r2,%3\n" \
1.439 -+ "m r2,%3\n" \
1.440 -+ "m r2,%3\n" \
1.441 -+ "m r2,%3\n" \
1.442 -+ "m r2,%3\n" \
1.443 -+ "cas %0,r2,r0\n" \
1.444 -+ "mfs r10,%1" \
1.445 - : "=r" ((USItype) (ph)), \
1.446 - "=r" ((USItype) (pl)) \
1.447 - : "%r" (__m0), \
1.448 -@@ -982,9 +982,9 @@
1.449 - #if defined (__sh2__) && W_TYPE_SIZE == 32
1.450 - #define umul_ppmm(w1, w0, u, v) \
1.451 - __asm__ ( \
1.452 -- "dmulu.l %2,%3
1.453 -- sts macl,%1
1.454 -- sts mach,%0" \
1.455 -+ "dmulu.l %2,%3\n" \
1.456 -+ "sts macl,%1\n" \
1.457 -+ "sts mach,%0" \
1.458 - : "=r" ((USItype)(w1)), \
1.459 - "=r" ((USItype)(w0)) \
1.460 - : "r" ((USItype)(u)), \
1.461 -@@ -996,8 +996,8 @@
1.462 - #if defined (__sparc__) && !defined(__arch64__) \
1.463 - && !defined(__sparcv9) && W_TYPE_SIZE == 32
1.464 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.465 -- __asm__ ("addcc %r4,%5,%1
1.466 -- addx %r2,%3,%0" \
1.467 -+ __asm__ ("addcc %r4,%5,%1\n" \
1.468 -+ "addx %r2,%3,%0" \
1.469 - : "=r" ((USItype) (sh)), \
1.470 - "=&r" ((USItype) (sl)) \
1.471 - : "%rJ" ((USItype) (ah)), \
1.472 -@@ -1006,8 +1006,8 @@
1.473 - "rI" ((USItype) (bl)) \
1.474 - __CLOBBER_CC)
1.475 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.476 -- __asm__ ("subcc %r4,%5,%1
1.477 -- subx %r2,%3,%0" \
1.478 -+ __asm__ ("subcc %r4,%5,%1\n" \
1.479 -+ "subx %r2,%3,%0" \
1.480 - : "=r" ((USItype) (sh)), \
1.481 - "=&r" ((USItype) (sl)) \
1.482 - : "rJ" ((USItype) (ah)), \
1.483 -@@ -1040,45 +1040,45 @@
1.484 - : "r" ((USItype) (u)), \
1.485 - "r" ((USItype) (v)))
1.486 - #define udiv_qrnnd(q, r, n1, n0, d) \
1.487 -- __asm__ ("! Inlined udiv_qrnnd
1.488 -- wr %%g0,%2,%%y ! Not a delayed write for sparclite
1.489 -- tst %%g0
1.490 -- divscc %3,%4,%%g1
1.491 -- divscc %%g1,%4,%%g1
1.492 -- divscc %%g1,%4,%%g1
1.493 -- divscc %%g1,%4,%%g1
1.494 -- divscc %%g1,%4,%%g1
1.495 -- divscc %%g1,%4,%%g1
1.496 -- divscc %%g1,%4,%%g1
1.497 -- divscc %%g1,%4,%%g1
1.498 -- divscc %%g1,%4,%%g1
1.499 -- divscc %%g1,%4,%%g1
1.500 -- divscc %%g1,%4,%%g1
1.501 -- divscc %%g1,%4,%%g1
1.502 -- divscc %%g1,%4,%%g1
1.503 -- divscc %%g1,%4,%%g1
1.504 -- divscc %%g1,%4,%%g1
1.505 -- divscc %%g1,%4,%%g1
1.506 -- divscc %%g1,%4,%%g1
1.507 -- divscc %%g1,%4,%%g1
1.508 -- divscc %%g1,%4,%%g1
1.509 -- divscc %%g1,%4,%%g1
1.510 -- divscc %%g1,%4,%%g1
1.511 -- divscc %%g1,%4,%%g1
1.512 -- divscc %%g1,%4,%%g1
1.513 -- divscc %%g1,%4,%%g1
1.514 -- divscc %%g1,%4,%%g1
1.515 -- divscc %%g1,%4,%%g1
1.516 -- divscc %%g1,%4,%%g1
1.517 -- divscc %%g1,%4,%%g1
1.518 -- divscc %%g1,%4,%%g1
1.519 -- divscc %%g1,%4,%%g1
1.520 -- divscc %%g1,%4,%%g1
1.521 -- divscc %%g1,%4,%0
1.522 -- rd %%y,%1
1.523 -- bl,a 1f
1.524 -- add %1,%4,%1
1.525 --1: ! End of inline udiv_qrnnd" \
1.526 -+ __asm__ ("! Inlined udiv_qrnnd\n" \
1.527 -+ "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1.528 -+ "tst %%g0\n" \
1.529 -+ "divscc %3,%4,%%g1\n" \
1.530 -+ "divscc %%g1,%4,%%g1\n" \
1.531 -+ "divscc %%g1,%4,%%g1\n" \
1.532 -+ "divscc %%g1,%4,%%g1\n" \
1.533 -+ "divscc %%g1,%4,%%g1\n" \
1.534 -+ "divscc %%g1,%4,%%g1\n" \
1.535 -+ "divscc %%g1,%4,%%g1\n" \
1.536 -+ "divscc %%g1,%4,%%g1\n" \
1.537 -+ "divscc %%g1,%4,%%g1\n" \
1.538 -+ "divscc %%g1,%4,%%g1\n" \
1.539 -+ "divscc %%g1,%4,%%g1\n" \
1.540 -+ "divscc %%g1,%4,%%g1\n" \
1.541 -+ "divscc %%g1,%4,%%g1\n" \
1.542 -+ "divscc %%g1,%4,%%g1\n" \
1.543 -+ "divscc %%g1,%4,%%g1\n" \
1.544 -+ "divscc %%g1,%4,%%g1\n" \
1.545 -+ "divscc %%g1,%4,%%g1\n" \
1.546 -+ "divscc %%g1,%4,%%g1\n" \
1.547 -+ "divscc %%g1,%4,%%g1\n" \
1.548 -+ "divscc %%g1,%4,%%g1\n" \
1.549 -+ "divscc %%g1,%4,%%g1\n" \
1.550 -+ "divscc %%g1,%4,%%g1\n" \
1.551 -+ "divscc %%g1,%4,%%g1\n" \
1.552 -+ "divscc %%g1,%4,%%g1\n" \
1.553 -+ "divscc %%g1,%4,%%g1\n" \
1.554 -+ "divscc %%g1,%4,%%g1\n" \
1.555 -+ "divscc %%g1,%4,%%g1\n" \
1.556 -+ "divscc %%g1,%4,%%g1\n" \
1.557 -+ "divscc %%g1,%4,%%g1\n" \
1.558 -+ "divscc %%g1,%4,%%g1\n" \
1.559 -+ "divscc %%g1,%4,%%g1\n" \
1.560 -+ "divscc %%g1,%4,%0\n" \
1.561 -+ "rd %%y,%1\n" \
1.562 -+ "bl,a 1f\n" \
1.563 -+ "add %1,%4,%1\n" \
1.564 -+"1: ! End of inline udiv_qrnnd" \
1.565 - : "=r" ((USItype) (q)), \
1.566 - "=r" ((USItype) (r)) \
1.567 - : "r" ((USItype) (n1)), \
1.568 -@@ -1099,46 +1099,46 @@
1.569 - /* SPARC without integer multiplication and divide instructions.
1.570 - (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
1.571 - #define umul_ppmm(w1, w0, u, v) \
1.572 -- __asm__ ("! Inlined umul_ppmm
1.573 -- wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr
1.574 -- sra %3,31,%%o5 ! Don't move this insn
1.575 -- and %2,%%o5,%%o5 ! Don't move this insn
1.576 -- andcc %%g0,0,%%g1 ! Don't move this insn
1.577 -- mulscc %%g1,%3,%%g1
1.578 -- mulscc %%g1,%3,%%g1
1.579 -- mulscc %%g1,%3,%%g1
1.580 -- mulscc %%g1,%3,%%g1
1.581 -- mulscc %%g1,%3,%%g1
1.582 -- mulscc %%g1,%3,%%g1
1.583 -- mulscc %%g1,%3,%%g1
1.584 -- mulscc %%g1,%3,%%g1
1.585 -- mulscc %%g1,%3,%%g1
1.586 -- mulscc %%g1,%3,%%g1
1.587 -- mulscc %%g1,%3,%%g1
1.588 -- mulscc %%g1,%3,%%g1
1.589 -- mulscc %%g1,%3,%%g1
1.590 -- mulscc %%g1,%3,%%g1
1.591 -- mulscc %%g1,%3,%%g1
1.592 -- mulscc %%g1,%3,%%g1
1.593 -- mulscc %%g1,%3,%%g1
1.594 -- mulscc %%g1,%3,%%g1
1.595 -- mulscc %%g1,%3,%%g1
1.596 -- mulscc %%g1,%3,%%g1
1.597 -- mulscc %%g1,%3,%%g1
1.598 -- mulscc %%g1,%3,%%g1
1.599 -- mulscc %%g1,%3,%%g1
1.600 -- mulscc %%g1,%3,%%g1
1.601 -- mulscc %%g1,%3,%%g1
1.602 -- mulscc %%g1,%3,%%g1
1.603 -- mulscc %%g1,%3,%%g1
1.604 -- mulscc %%g1,%3,%%g1
1.605 -- mulscc %%g1,%3,%%g1
1.606 -- mulscc %%g1,%3,%%g1
1.607 -- mulscc %%g1,%3,%%g1
1.608 -- mulscc %%g1,%3,%%g1
1.609 -- mulscc %%g1,0,%%g1
1.610 -- add %%g1,%%o5,%0
1.611 -- rd %%y,%1" \
1.612 -+ __asm__ ("! Inlined umul_ppmm\n" \
1.613 -+ "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
1.614 -+ "sra %3,31,%%o5 ! Don't move this insn\n" \
1.615 -+ "and %2,%%o5,%%o5 ! Don't move this insn\n" \
1.616 -+ "andcc %%g0,0,%%g1 ! Don't move this insn\n" \
1.617 -+ "mulscc %%g1,%3,%%g1\n" \
1.618 -+ "mulscc %%g1,%3,%%g1\n" \
1.619 -+ "mulscc %%g1,%3,%%g1\n" \
1.620 -+ "mulscc %%g1,%3,%%g1\n" \
1.621 -+ "mulscc %%g1,%3,%%g1\n" \
1.622 -+ "mulscc %%g1,%3,%%g1\n" \
1.623 -+ "mulscc %%g1,%3,%%g1\n" \
1.624 -+ "mulscc %%g1,%3,%%g1\n" \
1.625 -+ "mulscc %%g1,%3,%%g1\n" \
1.626 -+ "mulscc %%g1,%3,%%g1\n" \
1.627 -+ "mulscc %%g1,%3,%%g1\n" \
1.628 -+ "mulscc %%g1,%3,%%g1\n" \
1.629 -+ "mulscc %%g1,%3,%%g1\n" \
1.630 -+ "mulscc %%g1,%3,%%g1\n" \
1.631 -+ "mulscc %%g1,%3,%%g1\n" \
1.632 -+ "mulscc %%g1,%3,%%g1\n" \
1.633 -+ "mulscc %%g1,%3,%%g1\n" \
1.634 -+ "mulscc %%g1,%3,%%g1\n" \
1.635 -+ "mulscc %%g1,%3,%%g1\n" \
1.636 -+ "mulscc %%g1,%3,%%g1\n" \
1.637 -+ "mulscc %%g1,%3,%%g1\n" \
1.638 -+ "mulscc %%g1,%3,%%g1\n" \
1.639 -+ "mulscc %%g1,%3,%%g1\n" \
1.640 -+ "mulscc %%g1,%3,%%g1\n" \
1.641 -+ "mulscc %%g1,%3,%%g1\n" \
1.642 -+ "mulscc %%g1,%3,%%g1\n" \
1.643 -+ "mulscc %%g1,%3,%%g1\n" \
1.644 -+ "mulscc %%g1,%3,%%g1\n" \
1.645 -+ "mulscc %%g1,%3,%%g1\n" \
1.646 -+ "mulscc %%g1,%3,%%g1\n" \
1.647 -+ "mulscc %%g1,%3,%%g1\n" \
1.648 -+ "mulscc %%g1,%3,%%g1\n" \
1.649 -+ "mulscc %%g1,0,%%g1\n" \
1.650 -+ "add %%g1,%%o5,%0\n" \
1.651 -+ "rd %%y,%1" \
1.652 - : "=r" ((USItype) (w1)), \
1.653 - "=r" ((USItype) (w0)) \
1.654 - : "%rI" ((USItype) (u)), \
1.655 -@@ -1148,30 +1148,30 @@
1.656 - /* It's quite necessary to add this much assembler for the sparc.
1.657 - The default udiv_qrnnd (in C) is more than 10 times slower! */
1.658 - #define udiv_qrnnd(q, r, n1, n0, d) \
1.659 -- __asm__ ("! Inlined udiv_qrnnd
1.660 -- mov 32,%%g1
1.661 -- subcc %1,%2,%%g0
1.662 --1: bcs 5f
1.663 -- addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1.664 -- sub %1,%2,%1 ! this kills msb of n
1.665 -- addx %1,%1,%1 ! so this can't give carry
1.666 -- subcc %%g1,1,%%g1
1.667 --2: bne 1b
1.668 -- subcc %1,%2,%%g0
1.669 -- bcs 3f
1.670 -- addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb
1.671 -- b 3f
1.672 -- sub %1,%2,%1 ! this kills msb of n
1.673 --4: sub %1,%2,%1
1.674 --5: addxcc %1,%1,%1
1.675 -- bcc 2b
1.676 -- subcc %%g1,1,%%g1
1.677 --! Got carry from n. Subtract next step to cancel this carry.
1.678 -- bne 4b
1.679 -- addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb
1.680 -- sub %1,%2,%1
1.681 --3: xnor %0,0,%0
1.682 -- ! End of inline udiv_qrnnd" \
1.683 -+ __asm__ ("! Inlined udiv_qrnnd\n" \
1.684 -+ "mov 32,%%g1\n" \
1.685 -+ "subcc %1,%2,%%g0\n" \
1.686 -+"1: bcs 5f\n" \
1.687 -+ "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1.688 -+ "sub %1,%2,%1 ! this kills msb of n\n" \
1.689 -+ "addx %1,%1,%1 ! so this can't give carry\n" \
1.690 -+ "subcc %%g1,1,%%g1\n" \
1.691 -+"2: bne 1b\n" \
1.692 -+ "subcc %1,%2,%%g0\n" \
1.693 -+ "bcs 3f\n" \
1.694 -+ "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \
1.695 -+ "b 3f\n" \
1.696 -+ "sub %1,%2,%1 ! this kills msb of n\n" \
1.697 -+"4: sub %1,%2,%1\n" \
1.698 -+"5: addxcc %1,%1,%1\n" \
1.699 -+ "bcc 2b\n" \
1.700 -+ "subcc %%g1,1,%%g1\n" \
1.701 -+"! Got carry from n. Subtract next step to cancel this carry.\n" \
1.702 -+ "bne 4b\n" \
1.703 -+ "addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \
1.704 -+ "sub %1,%2,%1\n" \
1.705 -+"3: xnor %0,0,%0\n" \
1.706 -+ "! End of inline udiv_qrnnd" \
1.707 - : "=&r" ((USItype) (q)), \
1.708 - "=&r" ((USItype) (r)) \
1.709 - : "r" ((USItype) (d)), \
1.710 -@@ -1185,11 +1185,11 @@
1.711 - #if ((defined (__sparc__) && defined (__arch64__)) \
1.712 - || defined (__sparcv9)) && W_TYPE_SIZE == 64
1.713 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.714 -- __asm__ ("addcc %r4,%5,%1
1.715 -- add %r2,%3,%0
1.716 -- bcs,a,pn %%xcc, 1f
1.717 -- add %0, 1, %0
1.718 -- 1:" \
1.719 -+ __asm__ ("addcc %r4,%5,%1\n" \
1.720 -+ "add %r2,%3,%0\n" \
1.721 -+ "bcs,a,pn %%xcc, 1f\n" \
1.722 -+ "add %0, 1, %0\n" \
1.723 -+ "1:" \
1.724 - : "=r" ((UDItype)(sh)), \
1.725 - "=&r" ((UDItype)(sl)) \
1.726 - : "%rJ" ((UDItype)(ah)), \
1.727 -@@ -1199,11 +1199,11 @@
1.728 - __CLOBBER_CC)
1.729 -
1.730 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.731 -- __asm__ ("subcc %r4,%5,%1
1.732 -- sub %r2,%3,%0
1.733 -- bcs,a,pn %%xcc, 1f
1.734 -- sub %0, 1, %0
1.735 -- 1:" \
1.736 -+ __asm__ ("subcc %r4,%5,%1\n" \
1.737 -+ "sub %r2,%3,%0\n" \
1.738 -+ "bcs,a,pn %%xcc, 1f\n" \
1.739 -+ "sub %0, 1, %0\n" \
1.740 -+ "1:" \
1.741 - : "=r" ((UDItype)(sh)), \
1.742 - "=&r" ((UDItype)(sl)) \
1.743 - : "rJ" ((UDItype)(ah)), \
1.744 -@@ -1216,27 +1216,27 @@
1.745 - do { \
1.746 - UDItype tmp1, tmp2, tmp3, tmp4; \
1.747 - __asm__ __volatile__ ( \
1.748 -- "srl %7,0,%3
1.749 -- mulx %3,%6,%1
1.750 -- srlx %6,32,%2
1.751 -- mulx %2,%3,%4
1.752 -- sllx %4,32,%5
1.753 -- srl %6,0,%3
1.754 -- sub %1,%5,%5
1.755 -- srlx %5,32,%5
1.756 -- addcc %4,%5,%4
1.757 -- srlx %7,32,%5
1.758 -- mulx %3,%5,%3
1.759 -- mulx %2,%5,%5
1.760 -- sethi %%hi(0x80000000),%2
1.761 -- addcc %4,%3,%4
1.762 -- srlx %4,32,%4
1.763 -- add %2,%2,%2
1.764 -- movcc %%xcc,%%g0,%2
1.765 -- addcc %5,%4,%5
1.766 -- sllx %3,32,%3
1.767 -- add %1,%3,%1
1.768 -- add %5,%2,%0" \
1.769 -+ "srl %7,0,%3\n" \
1.770 -+ "mulx %3,%6,%1\n" \
1.771 -+ "srlx %6,32,%2\n" \
1.772 -+ "mulx %2,%3,%4\n" \
1.773 -+ "sllx %4,32,%5\n" \
1.774 -+ "srl %6,0,%3\n" \
1.775 -+ "sub %1,%5,%5\n" \
1.776 -+ "srlx %5,32,%5\n" \
1.777 -+ "addcc %4,%5,%4\n" \
1.778 -+ "srlx %7,32,%5\n" \
1.779 -+ "mulx %3,%5,%3\n" \
1.780 -+ "mulx %2,%5,%5\n" \
1.781 -+ "sethi %%hi(0x80000000),%2\n" \
1.782 -+ "addcc %4,%3,%4\n" \
1.783 -+ "srlx %4,32,%4\n" \
1.784 -+ "add %2,%2,%2\n" \
1.785 -+ "movcc %%xcc,%%g0,%2\n" \
1.786 -+ "addcc %5,%4,%5\n" \
1.787 -+ "sllx %3,32,%3\n" \
1.788 -+ "add %1,%3,%1\n" \
1.789 -+ "add %5,%2,%0" \
1.790 - : "=r" ((UDItype)(wh)), \
1.791 - "=&r" ((UDItype)(wl)), \
1.792 - "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \
1.793 -@@ -1250,8 +1250,8 @@
1.794 -
1.795 - #if defined (__vax__) && W_TYPE_SIZE == 32
1.796 - #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1.797 -- __asm__ ("addl2 %5,%1
1.798 -- adwc %3,%0" \
1.799 -+ __asm__ ("addl2 %5,%1\n" \
1.800 -+ "adwc %3,%0" \
1.801 - : "=g" ((USItype) (sh)), \
1.802 - "=&g" ((USItype) (sl)) \
1.803 - : "%0" ((USItype) (ah)), \
1.804 -@@ -1259,8 +1259,8 @@
1.805 - "%1" ((USItype) (al)), \
1.806 - "g" ((USItype) (bl)))
1.807 - #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1.808 -- __asm__ ("subl2 %5,%1
1.809 -- sbwc %3,%0" \
1.810 -+ __asm__ ("subl2 %5,%1\n" \
1.811 -+ "sbwc %3,%0" \
1.812 - : "=g" ((USItype) (sh)), \
1.813 - "=&g" ((USItype) (sl)) \
1.814 - : "0" ((USItype) (ah)), \