1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/patches/gcc/3.4.6/160-arm-ldm-peephole2.patch	Mon Jul 28 21:32:33 2008 +0000
     1.3 @@ -0,0 +1,32 @@
     1.4 +diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
     1.5 +--- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
     1.6 ++++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
     1.7 +@@ -4572,6 +4572,10 @@
     1.8 + int
     1.9 + adjacent_mem_locations (rtx a, rtx b)
    1.10 + {
    1.11 ++  /* We don't guarantee to preserve the order of these memory refs.  */
    1.12 ++  if (volatile_refs_p (a) || volatile_refs_p (b))
    1.13 ++    return 0;
    1.14 ++
    1.15 +   if ((GET_CODE (XEXP (a, 0)) == REG
    1.16 +        || (GET_CODE (XEXP (a, 0)) == PLUS
    1.17 + 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
    1.18 +@@ -4611,6 +4615,17 @@
    1.19 + 	return 0;
    1.20 + 
    1.21 +       val_diff = val1 - val0;
    1.22 ++
    1.23 ++      if (arm_ld_sched)
    1.24 ++	{
    1.25 ++	  /* If the target has load delay slots, then there's no benefit
    1.26 ++	     to using an ldm instruction unless the offset is zero and
    1.27 ++	     we are optimizing for size.  */
    1.28 ++	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
    1.29 ++		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
    1.30 ++		  && (val_diff == 4 || val_diff == -4));
    1.31 ++	}
    1.32 ++
    1.33 +       return ((REGNO (reg0) == REGNO (reg1))
    1.34 + 	      && (val_diff == 4 || val_diff == -4));
    1.35 +     }