1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
1.2 +++ b/patches/gcc/3.4.3/pr16201-fix.patch Sat Feb 24 11:00:05 2007 +0000
1.3 @@ -0,0 +1,149 @@
1.4 +See http://gcc.gnu.org/PR16201
1.5 +
1.6 +Should fix "bad immediate value for offset" errors for several flavors of arm, e.g.
1.7 +
1.8 +/tmp/ccmdoQyg.s: Assembler messages:
1.9 +/tmp/ccmdoQyg.s:6235: Error: bad immediate value for offset (4096)
1.10 +make[2]: *** [crosstool-0.32/build/arm-xscale-linux-gnu/gcc-3.4.3-glibc-2.3.3/build-glibc/locale/ld-collate.o] Error 1
1.11 +
1.12 +/tmp/cc0c7qop.s: Assembler messages:
1.13 +/tmp/cc0c7qop.s:6234: Error: bad immediate value for offset (4104)
1.14 +make[2]: *** [crosstool-0.32/build/armv5b-softfloat-linux/gcc-3.4.3-glibc-2.3.3/build-glibc/locale/ld-collate.o] Error 1
1.15 +
1.16 +
1.17 +CVSROOT: /cvs/gcc
1.18 +Module name: gcc
1.19 +Branch: gcc-3_4-branch
1.20 +Changes by: rearnsha@gcc.gnu.org 2005-02-01 15:07:05
1.21 +
1.22 +Modified files:
1.23 + gcc : ChangeLog
1.24 + gcc/config/arm : arm-protos.h arm.c
1.25 +
1.26 +Log message:
1.27 + PR target/16201
1.28 + * arm.c (arm_eliminable_register): New function.
1.29 + (adjacent_mem_locations): Don't allow eliminable registers. Use
1.30 + HOST_WIDE_INT for address offsets.
1.31 + * arm-protos.h (arm_eliminable_register): Add prototype.
1.32 +
1.33 +Patches:
1.34 +http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/ChangeLog.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=2.2326.2.790&r2=2.2326.2.791
1.35 +http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm-protos.h.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=1.61&r2=1.61.4.1
1.36 +http://gcc.gnu.org/cgi-bin/cvsweb.cgi/gcc/gcc/config/arm/arm.c.diff?cvsroot=gcc&only_with_tag=gcc-3_4-branch&r1=1.317.4.8&r2=1.317.4.9
1.37 +
1.38 +===================================================================
1.39 +RCS file: /cvs/gcc/gcc/gcc/config/arm/arm-protos.h,v
1.40 +retrieving revision 1.61
1.41 +retrieving revision 1.61.4.1
1.42 +diff -u -r1.61 -r1.61.4.1
1.43 +--- gcc/gcc/config/arm/arm-protos.h 2003/11/20 11:44:18 1.61
1.44 ++++ gcc/gcc/config/arm/arm-protos.h 2005/02/01 15:07:02 1.61.4.1
1.45 +@@ -1,5 +1,6 @@
1.46 + /* Prototypes for exported functions defined in arm.c and pe.c
1.47 +- Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
1.48 ++ Copyright (C) 1999, 2000, 2001, 2002, 2003, 2005
1.49 ++ Free Software Foundation, Inc.
1.50 + Contributed by Richard Earnshaw (rearnsha@arm.com)
1.51 + Minor hacks by Nick Clifton (nickc@cygnus.com)
1.52 +
1.53 +@@ -138,6 +139,7 @@
1.54 + extern int arm_is_longcall_p (rtx, int, int);
1.55 + extern int arm_emit_vector_const (FILE *, rtx);
1.56 + extern const char * arm_output_load_gr (rtx *);
1.57 ++extern int arm_eliminable_register (rtx);
1.58 +
1.59 + #if defined TREE_CODE
1.60 + extern rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int);
1.61 +===================================================================
1.62 +RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.c,v
1.63 +retrieving revision 1.317.4.8
1.64 +retrieving revision 1.317.4.9
1.65 +diff -u -r1.317.4.8 -r1.317.4.9
1.66 +--- gcc/gcc/config/arm/arm.c 2004/04/29 19:52:41 1.317.4.8
1.67 ++++ gcc/gcc/config/arm/arm.c 2005/02/01 15:07:02 1.317.4.9
1.68 +@@ -1,6 +1,6 @@
1.69 + /* Output routines for GCC for ARM.
1.70 + Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
1.71 +- 2002, 2003, 2004 Free Software Foundation, Inc.
1.72 ++ 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
1.73 + Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl)
1.74 + and Martin Simmons (@harleqn.co.uk).
1.75 + More major hacks by Richard Earnshaw (rearnsha@arm.com).
1.76 +@@ -4056,6 +4056,16 @@
1.77 + && INTVAL (op) < 64);
1.78 + }
1.79 +
1.80 ++/* Return true if X is a register that will be eliminated later on. */
1.81 ++int
1.82 ++arm_eliminable_register (rtx x)
1.83 ++{
1.84 ++ return REG_P (x) && (REGNO (x) == FRAME_POINTER_REGNUM
1.85 ++ || REGNO (x) == ARG_POINTER_REGNUM
1.86 ++ || (REGNO (x) >= FIRST_VIRTUAL_REGISTER
1.87 ++ && REGNO (x) <= LAST_VIRTUAL_REGISTER));
1.88 ++}
1.89 ++
1.90 + /* Returns TRUE if INSN is an "LDR REG, ADDR" instruction.
1.91 + Use by the Cirrus Maverick code which has to workaround
1.92 + a hardware bug triggered by such instructions. */
1.93 +@@ -4569,33 +4579,42 @@
1.94 + || (GET_CODE (XEXP (b, 0)) == PLUS
1.95 + && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
1.96 + {
1.97 +- int val0 = 0, val1 = 0;
1.98 +- int reg0, reg1;
1.99 +-
1.100 ++ HOST_WIDE_INT val0 = 0, val1 = 0;
1.101 ++ rtx reg0, reg1;
1.102 ++ int val_diff;
1.103 ++
1.104 + if (GET_CODE (XEXP (a, 0)) == PLUS)
1.105 + {
1.106 +- reg0 = REGNO (XEXP (XEXP (a, 0), 0));
1.107 ++ reg0 = XEXP (XEXP (a, 0), 0);
1.108 + val0 = INTVAL (XEXP (XEXP (a, 0), 1));
1.109 + }
1.110 + else
1.111 +- reg0 = REGNO (XEXP (a, 0));
1.112 ++ reg0 = XEXP (a, 0);
1.113 +
1.114 + if (GET_CODE (XEXP (b, 0)) == PLUS)
1.115 + {
1.116 +- reg1 = REGNO (XEXP (XEXP (b, 0), 0));
1.117 ++ reg1 = XEXP (XEXP (b, 0), 0);
1.118 + val1 = INTVAL (XEXP (XEXP (b, 0), 1));
1.119 + }
1.120 + else
1.121 +- reg1 = REGNO (XEXP (b, 0));
1.122 ++ reg1 = XEXP (b, 0);
1.123 +
1.124 + /* Don't accept any offset that will require multiple
1.125 + instructions to handle, since this would cause the
1.126 + arith_adjacentmem pattern to output an overlong sequence. */
1.127 + if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1))
1.128 + return 0;
1.129 +-
1.130 +- return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4);
1.131 ++
1.132 ++ /* Don't allow an eliminable register: register elimination can make
1.133 ++ the offset too large. */
1.134 ++ if (arm_eliminable_register (reg0))
1.135 ++ return 0;
1.136 ++
1.137 ++ val_diff = val1 - val0;
1.138 ++ return ((REGNO (reg0) == REGNO (reg1))
1.139 ++ && (val_diff == 4 || val_diff == -4));
1.140 + }
1.141 ++
1.142 + return 0;
1.143 + }
1.144 +
1.145 +@@ -7301,7 +7320,6 @@
1.146 + return "";
1.147 + }
1.148 +
1.149 +-
1.150 + /* Output a move from arm registers to an fpa registers.
1.151 + OPERANDS[0] is an fpa register.
1.152 + OPERANDS[1] is the first registers of an arm register pair. */