Update the architecture API: architecture help is mandatory.
Update all architectures (some with pointer to the specs, when available).
/trunk/docs/overview.txt | 8 8 0 0 ++++++++
/trunk/arch/arm/config.in | 3 3 0 0 +++
/trunk/arch/powerpc/config.in | 3 3 0 0 +++
/trunk/arch/ia64/config.in | 3 3 0 0 +++
/trunk/arch/alpha/config.in | 2 2 0 0 ++
/trunk/arch/x86/config.in | 3 3 0 0 +++
/trunk/arch/mips/config.in | 3 3 0 0 +++
/trunk/arch/sh/config.in | 3 3 0 0 +++
/trunk/arch/x86_64/config.in | 3 3 0 0 +++
9 files changed, 31 insertions(+)
1 diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
2 --- gcc-3.4.6.orig/gcc/config/arm/arm.c 2007-08-15 22:57:51.000000000 +0200
3 +++ gcc-3.4.6/gcc/config/arm/arm.c 2007-08-15 22:57:51.000000000 +0200
6 adjacent_mem_locations (rtx a, rtx b)
8 + /* We don't guarantee to preserve the order of these memory refs. */
9 + if (volatile_refs_p (a) || volatile_refs_p (b))
12 if ((GET_CODE (XEXP (a, 0)) == REG
13 || (GET_CODE (XEXP (a, 0)) == PLUS
14 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
15 @@ -4611,6 +4615,17 @@
18 val_diff = val1 - val0;
22 + /* If the target has load delay slots, then there's no benefit
23 + to using an ldm instruction unless the offset is zero and
24 + we are optimizing for size. */
25 + return (optimize_size && (REGNO (reg0) == REGNO (reg1))
26 + && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
27 + && (val_diff == 4 || val_diff == -4));
30 return ((REGNO (reg0) == REGNO (reg1))
31 && (val_diff == 4 || val_diff == -4));