patches/gcc/3.4.4/601-gcc34-arm-ldm-peephole2.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Sat Jul 28 21:34:41 2007 +0000 (2007-07-28)
changeset 301 2be7232a73ac
permissions -rw-r--r--
Bump version to 0.2.2.
     1 The 30_all_gcc34-arm-ldm-peephole.patch from Debian was conflicting 
     2 with the newer 36_all_pr16201-fix.patch, so i cut out the hunk from 
     3 it that was causing problems and grabbed an updated version from 
     4 upstream cvs.
     5 
     6 Index: gcc/config/arm/arm.c
     7 ===================================================================
     8 RCS file: /cvsroot/gcc/gcc/gcc/config/arm/arm.c,v
     9 retrieving revision 1.432
    10 retrieving revision 1.433
    11 diff -u -r1.432 -r1.433
    12 --- gcc-3.4.4/gcc/config/arm/arm.c	29 Mar 2005 03:00:23 -0000	1.432
    13 +++ gcc-3.4.4/gcc/config/arm/arm.c	1 Apr 2005 11:02:22 -0000	1.433
    14 @@ -5139,6 +5139,10 @@
    15  int
    16  adjacent_mem_locations (rtx a, rtx b)
    17  {
    18 +  /* We don't guarantee to preserve the order of these memory refs.  */
    19 +  if (volatile_refs_p (a) || volatile_refs_p (b))
    20 +    return 0;
    21 +
    22    if ((GET_CODE (XEXP (a, 0)) == REG
    23         || (GET_CODE (XEXP (a, 0)) == PLUS
    24  	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
    25 @@ -5178,6 +5182,17 @@
    26  	return 0;
    27  
    28        val_diff = val1 - val0;
    29 +
    30 +      if (arm_ld_sched)
    31 +	{
    32 +	  /* If the target has load delay slots, then there's no benefit
    33 +	     to using an ldm instruction unless the offset is zero and
    34 +	     we are optimizing for size.  */
    35 +	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
    36 +		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
    37 +		  && (val_diff == 4 || val_diff == -4));
    38 +	}
    39 +
    40        return ((REGNO (reg0) == REGNO (reg1))
    41  	      && (val_diff == 4 || val_diff == -4));
    42      }