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patches/gcc/4.6.0/000-gcc-bug-54369.patch
author Cody Schafer <dev@codyps.com>
Fri May 09 19:13:49 2014 -0700 (2014-05-09)
changeset 3312 4876ff97e039
parent 3049 f0ae157444dc
permissions -rw-r--r--
cc/gcc: allow CC_EXTRA_CONFIG_ARRAY on baremetal

The final bare-metal compiler is built using the core backend.
Currently the core uses the CC_CORE_EXTRA_CONFIG_ARRAY variable.

While this works as supposed to, this can leave the user puzzled
in the menuconfig, since all he can see is the core options, not
the final options.

Only show the core options if any of the core passes are needed,
and use the final options in the core-backend if we're issuing
the bare-metal compiler.

Signed-off-by: Cody P Schafer <dev@codyps.com>
[yann.morin.1998@free.fr: hide core options if no core pass needed;
use final option in core backend if issuing the bare-metal compiler]
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@free.fr>
Message-Id: <22181e546ba746202489.1399688067@localhost>
Patchwork-Id: 347586 
     1 Author: ebotcazou

     2 Date: Sun Sep  2 10:37:49 2012

     3 New Revision: 190860

     4 

     5 URL: http://gcc.gnu.org/viewcvs?root=gcc&view=rev&rev=190860

     6 Log:

     7     PR rtl-optimization/54369

     8     * config/mips/mips.c (mips_reorg): Invoke cleanup_barriers before

     9     calling dbr_schedule.

    10     * config/sparc/sparc.c (sparc_reorg): Likewise.

    11 

    12 Modified:

    13     branches/gcc-4_6-branch/gcc/ChangeLog

    14     branches/gcc-4_6-branch/gcc/config/mips/mips.c

    15     branches/gcc-4_6-branch/gcc/config/sparc/sparc.c

    16 

    17 [yann.morin.1998@free.fr: remove the sparc part, it does not apply]

    18 

    19 ---

    20 --- gcc-4_6-branch/gcc/config/mips/mips.c	2012/09/02 10:36:54	190859

    21 +++ gcc-4_6-branch/gcc/config/mips/mips.c	2012/09/02 10:37:49	190860

    22 @@ -15083,7 +15083,10 @@

    23      }

    24  

    25    if (optimize > 0 && flag_delayed_branch)

    26 -    dbr_schedule (get_insns ());

    27 +    {

    28 +      cleanup_barriers ();

    29 +      dbr_schedule (get_insns ());

    30 +    }

    31    mips_reorg_process_insns ();

    32    if (!TARGET_MIPS16

    33        && TARGET_EXPLICIT_RELOCS
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