patches/eglibc/2_10/100-powerpc-8xx-CPU15-errata.patch
author "Horst Kronstorfer" <horst.kronstorfer@aon.at>
Sat Jan 08 18:07:02 2011 +0100 (2011-01-08)
branch1.9
changeset 2258 587e1dd6d423
parent 1328 f9e0931908f4
permissions -rw-r--r--
debug/ltrace: fix building for mips

ltrace 0.5.3 currently fails to build for target mips because MY_TARGET
(introduced by patches/ltrace/0.5.3/150-allow-configurable-arch.patch)
is set to 'mips' via CT_ARCH, while the mips specific stuff in ltrace
(0.5.3) is stored under sysdeps/linux-gnu/mipsel:

result: *** No rule to make target `mips/arch.h', needed by `sysdep.h'.
Stop.

The following patch fixes this issue

Signed-off-by: "Horst Kronstorfer" <horst.kronstorfer@aon.at>
[yann.morin.1998@anciens.enib.fr: reformat commit log]
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
(transplanted from 2115901c7f07181d92ddbd7dd7ebeaa72e4fb176)
     1 diff -ru eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S
     2 --- eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S	2007-04-13 08:35:45.000000000 -0700
     3 +++ eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S	2009-05-06 16:52:04.000000000 -0700
     4 @@ -112,11 +112,13 @@
     5  	clrrwi.	rALIGN, rLEN, 5
     6  	mtcrf	0x01, rLEN	/* 40th instruction from .align */
     7  
     8 +#ifndef BROKEN_PPC_8xx_CPU15
     9  /* Check if we can use the special case for clearing memory using dcbz.
    10     This requires that we know the correct cache line size for this
    11     processor.  Getting the __cache_line_size may require establishing GOT
    12     addressability, so branch out of line to set this up.  */
    13  	beq	cr1, L(checklinesize)
    14 +#endif
    15  
    16  /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.
    17     Can't assume that rCHR is zero or that the cache line size is either
    18 @@ -158,6 +160,7 @@
    19  	add	rMEMP, rMEMP, rALIGN
    20  	b	L(medium_tail2)	/* 72nd instruction from .align */
    21  
    22 +#ifndef BROKEN_PPC_8xx_CPU15
    23  	.align	5
    24  	nop
    25  /* Clear cache lines of memory in 128-byte chunks.
    26 @@ -191,6 +194,7 @@
    27  	bdnz	L(zloop)
    28  	beqlr	cr5
    29  	b	L(medium_tail2)
    30 +#endif /* ! BROKEN_PPC_8xx_CPU15 */
    31  
    32  	.align	5
    33  L(small):
    34 @@ -248,6 +252,7 @@
    35  	stw	rCHR, -8(rMEMP)
    36  	blr
    37  
    38 +#ifndef BROKEN_PPC_8xx_CPU15
    39  L(checklinesize):
    40  #ifdef SHARED
    41  	mflr	rTMP
    42 @@ -329,6 +334,7 @@
    43  L(handletail32):
    44  	clrrwi.	rALIGN, rLEN, 5
    45  	b	L(nondcbz)
    46 +#endif /* ! BROKEN_PPC_8xx_CPU15 */
    47  
    48  END (BP_SYM (memset))
    49  libc_hidden_builtin_def (memset)