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patches/gcc/3.2.3/110-gcc-20020722-ppc405erratum77.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Sun Feb 17 22:08:06 2008 +0000 (2008-02-17)
changeset 431 8bde4c6ea47a
permissions -rw-r--r--
Robert P. J. DAY says:

apparently, the patchset for gcc 4.2.1 applies properly to the
source for gcc 4.2.2 and gcc 4.2.3. so, if you want, you can simply
add support for those last two just by augmenting menuconfig and
adding a couple symlinks for those two directories. seems like a
cheap way to add a couple new versions. 
     1 # See http://gcc.gnu.org/PR7383, http://www.kegel.com/xgcc3/ppc405erratum77.html

     2 # Fixed in gcc-3.3

     3 

     4 diff -aur gcc-20020722.orig/gcc/config/rs6000/rs6000.h gcc-20020722/gcc/config/rs6000/rs6000.h

     5 --- gcc-20020722.orig/gcc/config/rs6000/rs6000.h	Thu Jul 25 09:32:21 2002

     6 +++ gcc-20020722/gcc/config/rs6000/rs6000.h	Thu Jul 25 09:34:45 2002

     7 @@ -66,7 +66,7 @@

     8  %{mcpu=rsc1: -D_ARCH_PWR} \

     9  %{mcpu=401: -D_ARCH_PPC} \

    10  %{mcpu=403: -D_ARCH_PPC} \

    11 -%{mcpu=405: -D_ARCH_PPC} \

    12 +%{mcpu=405: -D_ARCH_PPC -D__PPC405__} \

    13  %{mcpu=505: -D_ARCH_PPC} \

    14  %{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \

    15  %{mcpu=602: -D_ARCH_PPC} \

    16 diff -aur gcc-20020722.orig/libjava/sysdep/powerpc/locks.h gcc-20020722/libjava/sysdep/powerpc/locks.h

    17 --- gcc-20020722.orig/libjava/sysdep/powerpc/locks.h	Thu Jul 25 09:32:30 2002

    18 +++ gcc-20020722/libjava/sysdep/powerpc/locks.h	Thu Jul 25 11:39:13 2002

    19 @@ -11,6 +11,17 @@

    20  #ifndef __SYSDEP_LOCKS_H__

    21  #define __SYSDEP_LOCKS_H__

    22  

    23 +#ifdef __PPC405__

    24 +// workaround for PPC405 erratum #77 - 07/18/02 JRO, dank, NN.  References:

    25 +// http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/89DED00DEBFF54BF87256A8000491BA2/$file/405CR_C_errata_1_2.pdf

    26 +// http://ppc.bkbits.net:8080/linuxppc_2_4_devel/cset@1.489

    27 +// http://www.kegel.com/xgcc3/ppc405erratum77.html

    28 +// FIXME: using dbct instead of sync would be faster

    29 +#define __LIBGCJ_PPC405_ERR77_SYNC   "sync \n\t"

    30 +#else

    31 +#define __LIBGCJ_PPC405_ERR77_SYNC

    32 +#endif

    33 +

    34  typedef size_t obj_addr_t;	/* Integer type big enough for object	*/

    35  				/* address.				*/

    36  

    37 @@ -25,6 +36,7 @@

    38  	   "0:    lwarx %0,0,%1 ;"

    39  	   "      xor. %0,%3,%0;"

    40  	   "      bne 1f;"

    41 +  	  __LIBGCJ_PPC405_ERR77_SYNC

    42  	   "      stwcx. %2,0,%1;"

    43  	   "      bne- 0b;"

    44  	   "1:    "

    45 @@ -58,6 +70,7 @@

    46  	   "0:    lwarx %0,0,%1 ;"

    47  	   "      xor. %0,%3,%0;"

    48  	   "      bne 1f;"

    49 +	   __LIBGCJ_PPC405_ERR77_SYNC	 

    50  	   "      stwcx. %2,0,%1;"

    51  	   "      bne- 0b;"

    52  	   "1:    "

    53 diff -aur gcc-20020722.orig/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h gcc-20020722/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h

    54 --- gcc-20020722.orig/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h	Thu Jul 25 09:32:31 2002

    55 +++ gcc-20020722/libstdc++-v3/config/cpu/powerpc/bits/atomicity.h	Thu Jul 25 09:34:45 2002

    56 @@ -32,6 +32,17 @@

    57  

    58  typedef int _Atomic_word;

    59  

    60 +#ifdef __PPC405__

    61 +// workaround for PPC405 erratum #77 - 07/18/02 JRO & dank.  References:

    62 +// http://www-3.ibm.com/chips/techlib/techlib.nsf/techdocs/89DED00DEBFF54BF87256A8000491BA2/$file/405CR_C_errata_1_2.pdf

    63 +// http://ppc.bkbits.net:8080/linuxppc_2_4_devel/cset@1.489

    64 +// http://www.kegel.com/xgcc3/ppc405erratum77.html

    65 +// FIXME: using dbct instead of sync would be faster

    66 +#define	__LIBSTDCPP_PPC405_ERR77_SYNC	"sync \n\t"

    67 +#else

    68 +#define __LIBSTDCPP_PPC405_ERR77_SYNC

    69 +#endif

    70 +

    71  static inline _Atomic_word

    72  __attribute__ ((__unused__))

    73  __exchange_and_add (volatile _Atomic_word* __mem, int __val)

    74 @@ -42,6 +53,7 @@

    75  	"0:\t"

    76  	"lwarx    %0,0,%2 \n\t"

    77  	"add%I3   %1,%0,%3 \n\t"

    78 +	__LIBSTDCPP_PPC405_ERR77_SYNC

    79  	"stwcx.   %1,0,%2 \n\t"

    80  	"bne-     0b \n\t"

    81  	"/* End exchange & add */"

    82 @@ -61,6 +73,7 @@

    83  	"0:\t"

    84  	"lwarx    %0,0,%1 \n\t"

    85  	"add%I2   %0,%0,%2 \n\t"

    86 +	__LIBSTDCPP_PPC405_ERR77_SYNC

    87  	"stwcx.   %0,0,%1 \n\t"

    88  	"bne-     0b \n\t"

    89  	"/* End atomic add */"

    90 @@ -78,6 +91,7 @@

    91  	"/* Inline always swap */\n"

    92  	"0:\t"

    93  	"lwarx    %0,0,%1 \n\t"

    94 +	__LIBSTDCPP_PPC405_ERR77_SYNC

    95  	"stwcx.   %2,0,%1 \n\t"

    96  	"bne-     0b \n\t"

    97  	"/* End always swap */"

    98 @@ -98,6 +112,7 @@

    99  	"lwarx    %0,0,%1 \n\t"

   100  	"cmpwi    %0,0 \n\t"

   101  	"bne-     1f \n\t"

   102 +	__LIBSTDCPP_PPC405_ERR77_SYNC

   103  	"stwcx.   %2,0,%1 \n\t"

   104  	"bne-     0b \n"

   105  	"1:\n\t"
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