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patches/linux/2.6.8/110-linux-2.6.8-allow-gcc-4.0-asm-i386.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Sun Feb 17 22:08:06 2008 +0000 (2008-02-17)
changeset 431 8bde4c6ea47a
permissions -rw-r--r--
Robert P. J. DAY says:

apparently, the patchset for gcc 4.2.1 applies properly to the
source for gcc 4.2.2 and gcc 4.2.3. so, if you want, you can simply
add support for those last two just by augmenting menuconfig and
adding a couple symlinks for those two directories. seems like a
cheap way to add a couple new versions. 
     1 Fixes

     2 

     3 In file included from include/asm/thread_info.h:16,

     4                  from include/linux/thread_info.h:21,

     5                  from include/linux/spinlock.h:12,

     6                  from include/linux/capability.h:45,

     7                  from include/linux/sched.h:7,

     8                  from arch/i386/kernel/asm-offsets.c:7:

     9 include/asm/processor.h:87: error: array type has incomplete element type

    10 make[1]: *** [arch/i386/kernel/asm-offsets.asm] Error 1

    11 

    12 --- linux-2.6.8/include/asm-i386/processor.h.old	Tue Mar 15 00:14:42 2005

    13 +++ linux-2.6.8/include/asm-i386/processor.h	Tue Mar 15 00:18:45 2005

    14 @@ -79,6 +79,58 @@

    15  #define X86_VENDOR_UNKNOWN 0xff

    16  

    17  /*

    18 + * Size of io_bitmap.

    19 + */

    20 +#define IO_BITMAP_BITS  65536

    21 +#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)

    22 +#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))

    23 +#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)

    24 +#define INVALID_IO_BITMAP_OFFSET 0x8000

    25 +

    26 +struct tss_struct {

    27 +	unsigned short	back_link,__blh;

    28 +	unsigned long	esp0;

    29 +	unsigned short	ss0,__ss0h;

    30 +	unsigned long	esp1;

    31 +	unsigned short	ss1,__ss1h;	/* ss1 is used to cache MSR_IA32_SYSENTER_CS */

    32 +	unsigned long	esp2;

    33 +	unsigned short	ss2,__ss2h;

    34 +	unsigned long	__cr3;

    35 +	unsigned long	eip;

    36 +	unsigned long	eflags;

    37 +	unsigned long	eax,ecx,edx,ebx;

    38 +	unsigned long	esp;

    39 +	unsigned long	ebp;

    40 +	unsigned long	esi;

    41 +	unsigned long	edi;

    42 +	unsigned short	es, __esh;

    43 +	unsigned short	cs, __csh;

    44 +	unsigned short	ss, __ssh;

    45 +	unsigned short	ds, __dsh;

    46 +	unsigned short	fs, __fsh;

    47 +	unsigned short	gs, __gsh;

    48 +	unsigned short	ldt, __ldth;

    49 +	unsigned short	trace, io_bitmap_base;

    50 +	/*

    51 +	 * The extra 1 is there because the CPU will access an

    52 +	 * additional byte beyond the end of the IO permission

    53 +	 * bitmap. The extra byte must be all 1 bits, and must

    54 +	 * be within the limit.

    55 +	 */

    56 +	unsigned long	io_bitmap[IO_BITMAP_LONGS + 1];

    57 +	/*

    58 +	 * pads the TSS to be cacheline-aligned (size is 0x100)

    59 +	 */

    60 +	unsigned long __cacheline_filler[37];

    61 +	/*

    62 +	 * .. and then another 0x100 bytes for emergency kernel stack

    63 +	 */

    64 +	unsigned long stack[64];

    65 +} __attribute__((packed));

    66 +

    67 +#define ARCH_MIN_TASKALIGN	16

    68 +

    69 +/*

    70   * capabilities of CPUs

    71   */

    72  

    73 @@ -296,15 +348,6 @@

    74   */

    75  #define TASK_UNMAPPED_BASE	(PAGE_ALIGN(TASK_SIZE / 3))

    76  

    77 -/*

    78 - * Size of io_bitmap.

    79 - */

    80 -#define IO_BITMAP_BITS  65536

    81 -#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)

    82 -#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))

    83 -#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)

    84 -#define INVALID_IO_BITMAP_OFFSET 0x8000

    85 -

    86  struct i387_fsave_struct {

    87  	long	cwd;

    88  	long	swd;

    89 @@ -356,49 +399,6 @@

    90  typedef struct {

    91  	unsigned long seg;

    92  } mm_segment_t;

    93 -

    94 -struct tss_struct {

    95 -	unsigned short	back_link,__blh;

    96 -	unsigned long	esp0;

    97 -	unsigned short	ss0,__ss0h;

    98 -	unsigned long	esp1;

    99 -	unsigned short	ss1,__ss1h;	/* ss1 is used to cache MSR_IA32_SYSENTER_CS */

   100 -	unsigned long	esp2;

   101 -	unsigned short	ss2,__ss2h;

   102 -	unsigned long	__cr3;

   103 -	unsigned long	eip;

   104 -	unsigned long	eflags;

   105 -	unsigned long	eax,ecx,edx,ebx;

   106 -	unsigned long	esp;

   107 -	unsigned long	ebp;

   108 -	unsigned long	esi;

   109 -	unsigned long	edi;

   110 -	unsigned short	es, __esh;

   111 -	unsigned short	cs, __csh;

   112 -	unsigned short	ss, __ssh;

   113 -	unsigned short	ds, __dsh;

   114 -	unsigned short	fs, __fsh;

   115 -	unsigned short	gs, __gsh;

   116 -	unsigned short	ldt, __ldth;

   117 -	unsigned short	trace, io_bitmap_base;

   118 -	/*

   119 -	 * The extra 1 is there because the CPU will access an

   120 -	 * additional byte beyond the end of the IO permission

   121 -	 * bitmap. The extra byte must be all 1 bits, and must

   122 -	 * be within the limit.

   123 -	 */

   124 -	unsigned long	io_bitmap[IO_BITMAP_LONGS + 1];

   125 -	/*

   126 -	 * pads the TSS to be cacheline-aligned (size is 0x100)

   127 -	 */

   128 -	unsigned long __cacheline_filler[37];

   129 -	/*

   130 -	 * .. and then another 0x100 bytes for emergency kernel stack

   131 -	 */

   132 -	unsigned long stack[64];

   133 -} __attribute__((packed));

   134 -

   135 -#define ARCH_MIN_TASKALIGN	16

   136  

   137  struct thread_struct {

   138  /* cached TLS descriptors. */
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