3 @@ -503,6 +503,9 @@ case "${target}" in
5 noconfigdirs="$noconfigdirs ld target-libgloss ${libgcj}"
8 + noconfigdirs="$noconfigdirs target-libiberty target-libmudflap target-libffi ${libgcj}"
11 noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}"
15 @@ -9223,7 +9223,7 @@ validate_arglist (tree arglist, ...)
19 - code = va_arg (ap, enum tree_code);
20 + code = va_arg (ap, int);
26 @@ -3447,7 +3447,7 @@ emit_library_call_value_1 (int retval, r
27 for (; count < nargs; count++)
29 rtx val = va_arg (p, rtx);
30 - enum machine_mode mode = va_arg (p, enum machine_mode);
31 + enum machine_mode mode = va_arg (p, int);
33 /* We cannot convert the arg value to the mode the library wants here;
34 must do it earlier where we know the signedness of the arg. */
37 @@ -347,6 +347,18 @@ add_path (char *path, int chain, int cxx
39 for (c = path; *c; c++)
40 if (*c == '\\') *c = '/';
41 + /* Remove unnecessary trailing slashes. On some versions of MS
42 + Windows, trailing _forward_ slashes cause no problems for stat().
43 + On newer versions, stat() does not recognise a directory that ends
44 + in a '\\' or '/', unless it is a drive root dir, such as "c:/",
45 + where it is obligatory. */
46 + int pathlen = strlen (path);
47 + char* end = path + pathlen - 1;
48 + /* Preserve the lead '/' or lead "c:/". */
49 + char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1);
51 + for (; end > start && IS_DIR_SEPARATOR (*end); end--)
57 +++ b/gcc/config/avr32/avr32.c
60 + Target hooks and helper functions for AVR32.
61 + Copyright 2003-2006 Atmel Corporation.
63 + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
64 + Initial porting by Anders �dland.
66 + This file is part of GCC.
68 + This program is free software; you can redistribute it and/or modify
69 + it under the terms of the GNU General Public License as published by
70 + the Free Software Foundation; either version 2 of the License, or
71 + (at your option) any later version.
73 + This program is distributed in the hope that it will be useful,
74 + but WITHOUT ANY WARRANTY; without even the implied warranty of
75 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
76 + GNU General Public License for more details.
78 + You should have received a copy of the GNU General Public License
79 + along with this program; if not, write to the Free Software
80 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
84 +#include "coretypes.h"
90 +#include "hard-reg-set.h"
92 +#include "insn-config.h"
93 +#include "conditions.h"
95 +#include "insn-attr.h"
98 +#include "function.h"
105 +#include "c-pragma.h"
106 +#include "integrate.h"
108 +#include "langhooks.h"
111 +#include "target-def.h"
115 +/* Forward definitions of types. */
116 +typedef struct minipool_node Mnode;
117 +typedef struct minipool_fixup Mfix;
119 +/* Obstack for minipool constant handling. */
120 +static struct obstack minipool_obstack;
121 +static char *minipool_startobj;
122 +static rtx minipool_vector_label;
124 +/* True if we are currently building a constant table. */
125 +int making_const_table;
127 +/* Some forward function declarations */
128 +static unsigned long avr32_isr_value (tree);
129 +static unsigned long avr32_compute_func_type (void);
130 +static tree avr32_handle_isr_attribute (tree *, tree, tree, int, bool *);
131 +static tree avr32_handle_acall_attribute (tree *, tree, tree, int, bool *);
132 +static tree avr32_handle_fndecl_attribute (tree * node, tree name, tree args,
133 + int flags, bool * no_add_attrs);
134 +static void avr32_reorg (void);
135 +bool avr32_return_in_msb (tree type);
136 +bool avr32_vector_mode_supported (enum machine_mode mode);
137 +static void avr32_init_libfuncs (void);
141 +avr32_add_gc_roots (void)
143 + gcc_obstack_init (&minipool_obstack);
144 + minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0);
148 +/* List of all known AVR32 parts */
149 +static const struct part_type_s avr32_part_types[] = {
150 + /* name, part_type, architecture type, macro */
151 + {"none", PART_TYPE_AVR32_NONE, ARCH_TYPE_AVR32_AP, "__AVR32__"},
152 + {"ap7000", PART_TYPE_AVR32_AP7000, ARCH_TYPE_AVR32_AP, "__AVR32_AP7000__"},
153 + {"ap7001", PART_TYPE_AVR32_AP7001, ARCH_TYPE_AVR32_AP, "__AVR32_AP7001__"},
154 + {"ap7002", PART_TYPE_AVR32_AP7002, ARCH_TYPE_AVR32_AP, "__AVR32_AP7002__"},
155 + {"ap7200", PART_TYPE_AVR32_AP7200, ARCH_TYPE_AVR32_AP, "__AVR32_AP7200__"},
156 + {"uc3a0128", PART_TYPE_AVR32_UC3A0128, ARCH_TYPE_AVR32_UCR2,
157 + "__AVR32_UC3A0128__"},
158 + {"uc3a0256", PART_TYPE_AVR32_UC3A0256, ARCH_TYPE_AVR32_UCR2,
159 + "__AVR32_UC3A0256__"},
160 + {"uc3a0512", PART_TYPE_AVR32_UC3A0512, ARCH_TYPE_AVR32_UCR2,
161 + "__AVR32_UC3A0512__"},
162 + {"uc3a0512es", PART_TYPE_AVR32_UC3A0512ES, ARCH_TYPE_AVR32_UCR1,
163 + "__AVR32_UC3A0512ES__"},
164 + {"uc3a1128", PART_TYPE_AVR32_UC3A1128, ARCH_TYPE_AVR32_UCR2,
165 + "__AVR32_UC3A1128__"},
166 + {"uc3a1256", PART_TYPE_AVR32_UC3A1256, ARCH_TYPE_AVR32_UCR2,
167 + "__AVR32_UC3A1256__"},
168 + {"uc3a1512", PART_TYPE_AVR32_UC3A1512, ARCH_TYPE_AVR32_UCR2,
169 + "__AVR32_UC3A1512__"},
170 + {"uc3a1512es", PART_TYPE_AVR32_UC3A1512ES, ARCH_TYPE_AVR32_UCR1,
171 + "__AVR32_UC3A1512ES__"},
172 + {"uc3a3revd", PART_TYPE_AVR32_UC3A3REVD, ARCH_TYPE_AVR32_UCR2NOMUL,
173 + "__AVR32_UC3A3256S__"},
174 + {"uc3a364", PART_TYPE_AVR32_UC3A364, ARCH_TYPE_AVR32_UCR2,
175 + "__AVR32_UC3A364__"},
176 + {"uc3a364s", PART_TYPE_AVR32_UC3A364S, ARCH_TYPE_AVR32_UCR2,
177 + "__AVR32_UC3A364S__"},
178 + {"uc3a3128", PART_TYPE_AVR32_UC3A3128, ARCH_TYPE_AVR32_UCR2,
179 + "__AVR32_UC3A3128__"},
180 + {"uc3a3128s", PART_TYPE_AVR32_UC3A3128S, ARCH_TYPE_AVR32_UCR2,
181 + "__AVR32_UC3A3128S__"},
182 + {"uc3a3256", PART_TYPE_AVR32_UC3A3256, ARCH_TYPE_AVR32_UCR2,
183 + "__AVR32_UC3A3256__"},
184 + {"uc3a3256s", PART_TYPE_AVR32_UC3A3256S, ARCH_TYPE_AVR32_UCR2,
185 + "__AVR32_UC3A3256S__"},
186 + {"uc3b064", PART_TYPE_AVR32_UC3B064, ARCH_TYPE_AVR32_UCR1,
187 + "__AVR32_UC3B064__"},
188 + {"uc3b0128", PART_TYPE_AVR32_UC3B0128, ARCH_TYPE_AVR32_UCR1,
189 + "__AVR32_UC3B0128__"},
190 + {"uc3b0256", PART_TYPE_AVR32_UC3B0256, ARCH_TYPE_AVR32_UCR1,
191 + "__AVR32_UC3B0256__"},
192 + {"uc3b0256es", PART_TYPE_AVR32_UC3B0256ES, ARCH_TYPE_AVR32_UCR1,
193 + "__AVR32_UC3B0256ES__"},
194 + {"uc3b164", PART_TYPE_AVR32_UC3B164, ARCH_TYPE_AVR32_UCR1,
195 + "__AVR32_UC3B164__"},
196 + {"uc3b1128", PART_TYPE_AVR32_UC3B1128, ARCH_TYPE_AVR32_UCR1,
197 + "__AVR32_UC3B1128__"},
198 + {"uc3b1256", PART_TYPE_AVR32_UC3B1256, ARCH_TYPE_AVR32_UCR1,
199 + "__AVR32_UC3B1256__"},
200 + {"uc3b1256es", PART_TYPE_AVR32_UC3B1256ES, ARCH_TYPE_AVR32_UCR1,
201 + "__AVR32_UC3B1256ES__"},
205 +/* List of all known AVR32 architectures */
206 +static const struct arch_type_s avr32_arch_types[] = {
207 + /* name, architecture type, microarchitecture type, feature flags, macro */
208 + {"ap", ARCH_TYPE_AVR32_AP, UARCH_TYPE_AVR32B,
209 + (FLAG_AVR32_HAS_DSP
210 + | FLAG_AVR32_HAS_SIMD
211 + | FLAG_AVR32_HAS_UNALIGNED_WORD
212 + | FLAG_AVR32_HAS_BRANCH_PRED | FLAG_AVR32_HAS_RETURN_STACK
213 + | FLAG_AVR32_HAS_CACHES),
215 + {"ucr1", ARCH_TYPE_AVR32_UCR1, UARCH_TYPE_AVR32A,
216 + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW),
218 + {"ucr2", ARCH_TYPE_AVR32_UCR2, UARCH_TYPE_AVR32A,
219 + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW
220 + | FLAG_AVR32_HAS_V2_INSNS),
222 + {"ucr2nomul", ARCH_TYPE_AVR32_UCR2NOMUL, UARCH_TYPE_AVR32A,
223 + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW
224 + | FLAG_AVR32_HAS_V2_INSNS | FLAG_AVR32_HAS_NO_MUL_INSNS),
226 + {NULL, 0, 0, 0, NULL}
229 +/* Default arch name */
230 +const char *avr32_arch_name = "none";
231 +const char *avr32_part_name = "none";
233 +const struct part_type_s *avr32_part;
234 +const struct arch_type_s *avr32_arch;
237 +/* Set default target_flags. */
238 +#undef TARGET_DEFAULT_TARGET_FLAGS
239 +#define TARGET_DEFAULT_TARGET_FLAGS \
240 + (MASK_HAS_ASM_ADDR_PSEUDOS | MASK_MD_REORG_OPTIMIZATION | MASK_COND_EXEC_BEFORE_RELOAD)
243 +avr32_optimization_options (int level,
245 + if (AVR32_ALWAYS_PIC)
248 + /* Enable section anchors if optimization is enabled. */
249 + if (level > 0 || size)
250 + flag_section_anchors = 1;
253 +/* Override command line options */
255 +avr32_override_options (void)
257 + const struct part_type_s *part;
258 + const struct arch_type_s *arch;
260 + /*Add backward compability*/
261 + if (strcmp ("uc", avr32_arch_name)== 0)
263 + fprintf (stderr, "Warning: Deprecated arch `%s' specified. "
264 + "Please use '-march=ucr1' instead. "
265 + "Converting to arch 'ucr1'\n",
267 + avr32_arch_name="ucr1";
270 + /* Check if arch type is set. */
271 + for (arch = avr32_arch_types; arch->name; arch++)
273 + if (strcmp (arch->name, avr32_arch_name) == 0)
278 + if (!arch->name && strcmp("none", avr32_arch_name) != 0)
280 + fprintf (stderr, "Unknown arch `%s' specified\n"
281 + "Known arch names:\n"
282 + "\tuc (deprecated)\n",
284 + for (arch = avr32_arch_types; arch->name; arch++)
285 + fprintf (stderr, "\t%s\n", arch->name);
286 + avr32_arch = &avr32_arch_types[ARCH_TYPE_AVR32_AP];
289 + /* Check if part type is set. */
290 + for (part = avr32_part_types; part->name; part++)
291 + if (strcmp (part->name, avr32_part_name) == 0)
297 + fprintf (stderr, "Unknown part `%s' specified\nKnown part names:\n",
299 + for (part = avr32_part_types; part->name; part++)
301 + if (strcmp("none", part->name) != 0)
302 + fprintf (stderr, "\t%s\n", part->name);
304 + /* Set default to NONE*/
305 + avr32_part = &avr32_part_types[PART_TYPE_AVR32_NONE];
308 + /* NB! option -march= overrides option -mpart
309 + * if both are used at the same time */
311 + avr32_arch = &avr32_arch_types[avr32_part->arch_type];
313 + /* If optimization level is two or greater, then align start of loops to a
314 + word boundary since this will allow folding the first insn of the loop.
315 + Do this only for targets supporting branch prediction. */
316 + if (optimize >= 2 && TARGET_BRANCH_PRED)
320 + /* Enable fast-float library if unsafe math optimizations
322 + if (flag_unsafe_math_optimizations)
323 + target_flags |= MASK_FAST_FLOAT;
325 + /* Check if we should set avr32_imm_in_const_pool
326 + based on if caches are present or not. */
327 + if ( avr32_imm_in_const_pool == -1 )
329 + if ( TARGET_CACHES )
330 + avr32_imm_in_const_pool = 1;
332 + avr32_imm_in_const_pool = 0;
338 + avr32_add_gc_roots ();
343 +If defined, a function that outputs the assembler code for entry to a
344 +function. The prologue is responsible for setting up the stack frame,
345 +initializing the frame pointer register, saving registers that must be
346 +saved, and allocating size additional bytes of storage for the
347 +local variables. size is an integer. file is a stdio
348 +stream to which the assembler code should be output.
350 +The label for the beginning of the function need not be output by this
351 +macro. That has already been done when the macro is run.
353 +To determine which registers to save, the macro can refer to the array
354 +regs_ever_live: element r is nonzero if hard register
355 +r is used anywhere within the function. This implies the function
356 +prologue should save register r, provided it is not one of the
357 +call-used registers. (TARGET_ASM_FUNCTION_EPILOGUE must likewise use
360 +On machines that have ``register windows'', the function entry code does
361 +not save on the stack the registers that are in the windows, even if
362 +they are supposed to be preserved by function calls; instead it takes
363 +appropriate steps to ``push'' the register stack, if any non-call-used
364 +registers are used in the function.
366 +On machines where functions may or may not have frame-pointers, the
367 +function entry code must vary accordingly; it must set up the frame
368 +pointer if one is wanted, and not otherwise. To determine whether a
369 +frame pointer is in wanted, the macro can refer to the variable
370 +frame_pointer_needed. The variable's value will be 1 at run
371 +time in a function that needs a frame pointer. (see Elimination).
373 +The function entry code is responsible for allocating any stack space
374 +required for the function. This stack space consists of the regions
375 +listed below. In most cases, these regions are allocated in the
376 +order listed, with the last listed region closest to the top of the
377 +stack (the lowest address if STACK_GROWS_DOWNWARD is defined, and
378 +the highest address if it is not defined). You can use a different order
379 +for a machine if doing so is more convenient or required for
380 +compatibility reasons. Except in cases where required by standard
381 +or by a debugger, there is no reason why the stack layout used by GCC
382 +need agree with that used by other compilers for a machine.
385 +#undef TARGET_ASM_FUNCTION_PROLOGUE
386 +#define TARGET_ASM_FUNCTION_PROLOGUE avr32_target_asm_function_prologue
389 +#undef TARGET_DEFAULT_SHORT_ENUMS
390 +#define TARGET_DEFAULT_SHORT_ENUMS hook_bool_void_false
392 +#undef TARGET_PROMOTE_FUNCTION_ARGS
393 +#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
395 +#undef TARGET_PROMOTE_FUNCTION_RETURN
396 +#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
398 +#undef TARGET_PROMOTE_PROTOTYPES
399 +#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
401 +#undef TARGET_MUST_PASS_IN_STACK
402 +#define TARGET_MUST_PASS_IN_STACK avr32_must_pass_in_stack
404 +#undef TARGET_PASS_BY_REFERENCE
405 +#define TARGET_PASS_BY_REFERENCE avr32_pass_by_reference
407 +#undef TARGET_STRICT_ARGUMENT_NAMING
408 +#define TARGET_STRICT_ARGUMENT_NAMING avr32_strict_argument_naming
410 +#undef TARGET_VECTOR_MODE_SUPPORTED_P
411 +#define TARGET_VECTOR_MODE_SUPPORTED_P avr32_vector_mode_supported
413 +#undef TARGET_RETURN_IN_MEMORY
414 +#define TARGET_RETURN_IN_MEMORY avr32_return_in_memory
416 +#undef TARGET_RETURN_IN_MSB
417 +#define TARGET_RETURN_IN_MSB avr32_return_in_msb
419 +#undef TARGET_ENCODE_SECTION_INFO
420 +#define TARGET_ENCODE_SECTION_INFO avr32_encode_section_info
422 +#undef TARGET_ARG_PARTIAL_BYTES
423 +#define TARGET_ARG_PARTIAL_BYTES avr32_arg_partial_bytes
425 +#undef TARGET_STRIP_NAME_ENCODING
426 +#define TARGET_STRIP_NAME_ENCODING avr32_strip_name_encoding
428 +#define streq(string1, string2) (strcmp (string1, string2) == 0)
430 +#undef TARGET_NARROW_VOLATILE_BITFIELD
431 +#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false
433 +#undef TARGET_ATTRIBUTE_TABLE
434 +#define TARGET_ATTRIBUTE_TABLE avr32_attribute_table
436 +#undef TARGET_COMP_TYPE_ATTRIBUTES
437 +#define TARGET_COMP_TYPE_ATTRIBUTES avr32_comp_type_attributes
440 +#undef TARGET_RTX_COSTS
441 +#define TARGET_RTX_COSTS avr32_rtx_costs
443 +#undef TARGET_CANNOT_FORCE_CONST_MEM
444 +#define TARGET_CANNOT_FORCE_CONST_MEM avr32_cannot_force_const_mem
446 +#undef TARGET_ASM_INTEGER
447 +#define TARGET_ASM_INTEGER avr32_assemble_integer
449 +#undef TARGET_FUNCTION_VALUE
450 +#define TARGET_FUNCTION_VALUE avr32_function_value
452 +#undef TARGET_MIN_ANCHOR_OFFSET
453 +#define TARGET_MIN_ANCHOR_OFFSET (0)
455 +#undef TARGET_MAX_ANCHOR_OFFSET
456 +#define TARGET_MAX_ANCHOR_OFFSET ((1 << 15) - 1)
458 +#undef TARGET_SECONDARY_RELOAD
459 +#define TARGET_SECONDARY_RELOAD avr32_secondary_reload
462 +avr32_secondary_reload (bool in_p, rtx x, enum reg_class class ATTRIBUTE_UNUSED,
463 + enum machine_mode mode, secondary_reload_info *sri)
466 + if ( avr32_rmw_memory_operand (x, mode) )
469 + sri->icode = CODE_FOR_reload_out_rmw_memory_operand;
471 + sri->icode = CODE_FOR_reload_in_rmw_memory_operand;
478 + * Switches to the appropriate section for output of constant pool
479 + * entry x in mode. You can assume that x is some kind of constant in
480 + * RTL. The argument mode is redundant except in the case of a
481 + * const_int rtx. Select the section by calling readonly_data_ section
482 + * or one of the alternatives for other sections. align is the
483 + * constant alignment in bits.
485 + * The default version of this function takes care of putting symbolic
486 + * constants in flag_ pic mode in data_section and everything else in
487 + * readonly_data_section.
489 +//#undef TARGET_ASM_SELECT_RTX_SECTION
490 +//#define TARGET_ASM_SELECT_RTX_SECTION avr32_select_rtx_section
494 + * If non-null, this hook performs a target-specific pass over the
495 + * instruction stream. The compiler will run it at all optimization
496 + * levels, just before the point at which it normally does
497 + * delayed-branch scheduling.
499 + * The exact purpose of the hook varies from target to target. Some
500 + * use it to do transformations that are necessary for correctness,
501 + * such as laying out in-function constant pools or avoiding hardware
502 + * hazards. Others use it as an opportunity to do some
503 + * machine-dependent optimizations.
505 + * You need not implement the hook if it has nothing to do. The
506 + * default definition is null.
508 +#undef TARGET_MACHINE_DEPENDENT_REORG
509 +#define TARGET_MACHINE_DEPENDENT_REORG avr32_reorg
511 +/* Target hook for assembling integer objects.
512 + Need to handle integer vectors */
514 +avr32_assemble_integer (rtx x, unsigned int size, int aligned_p)
516 + if (avr32_vector_mode_supported (GET_MODE (x)))
520 + if (GET_CODE (x) != CONST_VECTOR)
523 + units = CONST_VECTOR_NUNITS (x);
525 + switch (GET_MODE (x))
537 + for (i = 0; i < units; i++)
541 + elt = CONST_VECTOR_ELT (x, i);
542 + assemble_integer (elt, size, i == 0 ? 32 : size * BITS_PER_UNIT, 1);
548 + return default_assemble_integer (x, size, aligned_p);
552 + * This target hook describes the relative costs of RTL expressions.
554 + * The cost may depend on the precise form of the expression, which is
555 + * available for examination in x, and the rtx code of the expression
556 + * in which it is contained, found in outer_code. code is the
557 + * expression code--redundant, since it can be obtained with GET_CODE
560 + * In implementing this hook, you can use the construct COSTS_N_INSNS
561 + * (n) to specify a cost equal to n fast instructions.
563 + * On entry to the hook, *total contains a default estimate for the
564 + * cost of the expression. The hook should modify this value as
565 + * necessary. Traditionally, the default costs are COSTS_N_INSNS (5)
566 + * for multiplications, COSTS_N_INSNS (7) for division and modulus
567 + * operations, and COSTS_N_INSNS (1) for all other operations.
569 + * When optimizing for code size, i.e. when optimize_size is non-zero,
570 + * this target hook should be used to estimate the relative size cost
571 + * of an expression, again relative to COSTS_N_INSNS.
573 + * The hook returns true when all subexpressions of x have been
574 + * processed, and false when rtx_cost should recurse.
577 +/* Worker routine for avr32_rtx_costs. */
579 +avr32_rtx_costs_1 (rtx x, enum rtx_code code ATTRIBUTE_UNUSED,
580 + enum rtx_code outer ATTRIBUTE_UNUSED)
582 + enum machine_mode mode = GET_MODE (x);
584 + switch (GET_CODE (x))
587 + /* Using pre decrement / post increment memory operations on the
588 + avr32_uc architecture means that two writebacks must be performed
589 + and hence two cycles are needed. */
591 + && GET_MODE_SIZE (mode) <= 2 * UNITS_PER_WORD
593 + && (GET_CODE (XEXP (x, 0)) == PRE_DEC
594 + || GET_CODE (XEXP (x, 0)) == POST_INC))
595 + return COSTS_N_INSNS (5);
597 + /* Memory costs quite a lot for the first word, but subsequent words
598 + load at the equivalent of a single insn each. */
599 + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
600 + return COSTS_N_INSNS (3 + (GET_MODE_SIZE (mode) / UNITS_PER_WORD));
602 + return COSTS_N_INSNS (4);
605 + /* These are valid for the pseudo insns: lda.w and call which operates
606 + on direct addresses. We assume that the cost of a lda.w is the same
607 + as the cost of a ld.w insn. */
608 + return (outer == SET) ? COSTS_N_INSNS (4) : COSTS_N_INSNS (1);
613 + return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16);
617 + if (mode == TImode)
618 + return COSTS_N_INSNS (100);
620 + if (mode == DImode)
621 + return COSTS_N_INSNS (10);
622 + return COSTS_N_INSNS (4);
627 + if (mode == TImode)
628 + return COSTS_N_INSNS (10);
630 + if (mode == DImode)
631 + return COSTS_N_INSNS (4);
632 + return COSTS_N_INSNS (1);
638 + if (GET_MODE_CLASS (mode) == MODE_FLOAT)
639 + return COSTS_N_INSNS (100);
641 + if (mode == TImode)
642 + return COSTS_N_INSNS (50);
644 + if (mode == DImode)
645 + return COSTS_N_INSNS (2);
646 + return COSTS_N_INSNS (1);
650 + if (GET_MODE_CLASS (mode) == MODE_FLOAT)
651 + return COSTS_N_INSNS (300);
653 + if (mode == TImode)
654 + return COSTS_N_INSNS (16);
656 + if (mode == DImode)
657 + return COSTS_N_INSNS (4);
659 + if (mode == HImode)
660 + return COSTS_N_INSNS (2);
662 + return COSTS_N_INSNS (3);
665 + if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC)
666 + return COSTS_N_INSNS (4);
667 + return COSTS_N_INSNS (1);
670 + /* Sign/Zero extensions of registers cost quite much since these
671 + instrcutions only take one register operand which means that gcc
672 + often must insert some move instrcutions */
673 + if (mode == QImode || mode == HImode)
674 + return (COSTS_N_INSNS (GET_CODE (XEXP (x, 0)) == MEM ? 0 : 1));
675 + return COSTS_N_INSNS (4);
677 + /* divmod operations */
678 + if (XINT (x, 1) == UNSPEC_UDIVMODSI4_INTERNAL
679 + || XINT (x, 1) == UNSPEC_DIVMODSI4_INTERNAL)
681 + return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16);
685 + return COSTS_N_INSNS (1);
690 +avr32_rtx_costs (rtx x, int code, int outer_code, int *total)
692 + *total = avr32_rtx_costs_1 (x, code, outer_code);
698 +avr32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED)
700 + /* Do not want symbols in the constant pool when compiling pic or if using
701 + address pseudo instructions. */
702 + return ((flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS)
703 + && avr32_find_symbol (x) != NULL_RTX);
707 +/* Table of machine attributes. */
708 +const struct attribute_spec avr32_attribute_table[] = {
709 + /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
710 + /* Interrupt Service Routines have special prologue and epilogue
712 + {"isr", 0, 1, false, false, false, avr32_handle_isr_attribute},
713 + {"interrupt", 0, 1, false, false, false, avr32_handle_isr_attribute},
714 + {"acall", 0, 1, false, true, true, avr32_handle_acall_attribute},
715 + {"naked", 0, 0, true, false, false, avr32_handle_fndecl_attribute},
716 + {"rmw_addressable", 0, 0, true, false, false, NULL},
717 + {NULL, 0, 0, false, false, false, NULL}
723 + const char *const arg;
724 + const unsigned long return_value;
728 +static const isr_attribute_arg isr_attribute_args[] = {
729 + {"FULL", AVR32_FT_ISR_FULL},
730 + {"full", AVR32_FT_ISR_FULL},
731 + {"HALF", AVR32_FT_ISR_HALF},
732 + {"half", AVR32_FT_ISR_HALF},
733 + {"NONE", AVR32_FT_ISR_NONE},
734 + {"none", AVR32_FT_ISR_NONE},
735 + {"UNDEF", AVR32_FT_ISR_NONE},
736 + {"undef", AVR32_FT_ISR_NONE},
737 + {"SWI", AVR32_FT_ISR_NONE},
738 + {"swi", AVR32_FT_ISR_NONE},
739 + {NULL, AVR32_FT_ISR_NONE}
742 +/* Returns the (interrupt) function type of the current
743 + function, or AVR32_FT_UNKNOWN if the type cannot be determined. */
745 +static unsigned long
746 +avr32_isr_value (tree argument)
748 + const isr_attribute_arg *ptr;
751 + /* No argument - default to ISR_NONE. */
752 + if (argument == NULL_TREE)
753 + return AVR32_FT_ISR_NONE;
755 + /* Get the value of the argument. */
756 + if (TREE_VALUE (argument) == NULL_TREE
757 + || TREE_CODE (TREE_VALUE (argument)) != STRING_CST)
758 + return AVR32_FT_UNKNOWN;
760 + arg = TREE_STRING_POINTER (TREE_VALUE (argument));
762 + /* Check it against the list of known arguments. */
763 + for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++)
764 + if (streq (arg, ptr->arg))
765 + return ptr->return_value;
767 + /* An unrecognized interrupt type. */
768 + return AVR32_FT_UNKNOWN;
774 +These hooks specify assembly directives for creating certain kinds
775 +of integer object. The TARGET_ASM_BYTE_OP directive creates a
776 +byte-sized object, the TARGET_ASM_ALIGNED_HI_OP one creates an
777 +aligned two-byte object, and so on. Any of the hooks may be
778 +NULL, indicating that no suitable directive is available.
780 +The compiler will print these strings at the start of a new line,
781 +followed immediately by the object's initial value. In most cases,
782 +the string should contain a tab, a pseudo-op, and then another tab.
784 +#undef TARGET_ASM_BYTE_OP
785 +#define TARGET_ASM_BYTE_OP "\t.byte\t"
786 +#undef TARGET_ASM_ALIGNED_HI_OP
787 +#define TARGET_ASM_ALIGNED_HI_OP "\t.align 1\n\t.short\t"
788 +#undef TARGET_ASM_ALIGNED_SI_OP
789 +#define TARGET_ASM_ALIGNED_SI_OP "\t.align 2\n\t.int\t"
790 +#undef TARGET_ASM_ALIGNED_DI_OP
791 +#define TARGET_ASM_ALIGNED_DI_OP NULL
792 +#undef TARGET_ASM_ALIGNED_TI_OP
793 +#define TARGET_ASM_ALIGNED_TI_OP NULL
794 +#undef TARGET_ASM_UNALIGNED_HI_OP
795 +#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
796 +#undef TARGET_ASM_UNALIGNED_SI_OP
797 +#define TARGET_ASM_UNALIGNED_SI_OP "\t.int\t"
798 +#undef TARGET_ASM_UNALIGNED_DI_OP
799 +#define TARGET_ASM_UNALIGNED_DI_OP NULL
800 +#undef TARGET_ASM_UNALIGNED_TI_OP
801 +#define TARGET_ASM_UNALIGNED_TI_OP NULL
803 +#undef TARGET_ASM_OUTPUT_MI_THUNK
804 +#define TARGET_ASM_OUTPUT_MI_THUNK avr32_output_mi_thunk
806 +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
807 +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
810 +avr32_output_mi_thunk (FILE * file,
811 + tree thunk ATTRIBUTE_UNUSED,
812 + HOST_WIDE_INT delta,
813 + HOST_WIDE_INT vcall_offset, tree function)
815 + int mi_delta = delta;
817 + (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) ?
818 + INTERNAL_REGNUM (11) : INTERNAL_REGNUM (12));
821 + if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")
824 + fputs ("\tpushm\tlr\n", file);
830 + if (avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21"))
832 + fprintf (file, "\tsub\t%s, %d\n", reg_names[this_regno], -mi_delta);
836 + /* Immediate is larger than k21 we must make us a temp register by
837 + pushing a register to the stack. */
838 + fprintf (file, "\tmov\tlr, lo(%d)\n", mi_delta);
839 + fprintf (file, "\torh\tlr, hi(%d)\n", mi_delta);
840 + fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]);
845 + if (vcall_offset != 0)
847 + fprintf (file, "\tld.w\tlr, %s[0]\n", reg_names[this_regno]);
848 + fprintf (file, "\tld.w\tlr, lr[%i]\n", (int) vcall_offset);
849 + fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]);
853 + if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")
856 + fputs ("\tpopm\tlr\n", file);
859 + /* Jump to the function. We assume that we can use an rjmp since the
860 + function to jump to is local and probably not too far away from
861 + the thunk. If this assumption proves to be wrong we could implement
862 + this jump by calculating the offset between the jump source and destination
863 + and put this in the constant pool and then perform an add to pc.
864 + This would also be legitimate PIC code. But for now we hope that an rjmp
865 + will be sufficient...
867 + fputs ("\trjmp\t", file);
868 + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
869 + fputc ('\n', file);
873 +/* Implements target hook vector_mode_supported. */
875 +avr32_vector_mode_supported (enum machine_mode mode)
877 + if ((mode == V2HImode) || (mode == V4QImode))
884 +#undef TARGET_INIT_LIBFUNCS
885 +#define TARGET_INIT_LIBFUNCS avr32_init_libfuncs
887 +#undef TARGET_INIT_BUILTINS
888 +#define TARGET_INIT_BUILTINS avr32_init_builtins
890 +#undef TARGET_EXPAND_BUILTIN
891 +#define TARGET_EXPAND_BUILTIN avr32_expand_builtin
893 +tree int_ftype_int, int_ftype_void, short_ftype_short, void_ftype_int_int,
894 + void_ftype_ptr_int;
895 +tree void_ftype_int, void_ftype_void, int_ftype_ptr_int;
896 +tree short_ftype_short, int_ftype_int_short, int_ftype_short_short,
897 + short_ftype_short_short;
898 +tree int_ftype_int_int, longlong_ftype_int_short, longlong_ftype_short_short;
899 +tree void_ftype_int_int_int_int_int, void_ftype_int_int_int;
900 +tree longlong_ftype_int_int, void_ftype_int_int_longlong;
901 +tree int_ftype_int_int_int, longlong_ftype_longlong_int_short;
902 +tree longlong_ftype_longlong_short_short, int_ftype_int_short_short;
904 +#define def_builtin(NAME, TYPE, CODE) \
905 + lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
906 + BUILT_IN_MD, NULL, NULL_TREE)
908 +#define def_mbuiltin(MASK, NAME, TYPE, CODE) \
912 + lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \
913 + BUILT_IN_MD, NULL, NULL_TREE); \
917 +struct builtin_description
919 + const unsigned int mask;
920 + const enum insn_code icode;
921 + const char *const name;
923 + const enum rtx_code comparison;
924 + const unsigned int flag;
928 +static const struct builtin_description bdesc_2arg[] = {
929 +#define DSP_BUILTIN(code, builtin, ftype) \
930 + { 1, CODE_FOR_##code, "__builtin_" #code , \
931 + AVR32_BUILTIN_##builtin, 0, 0, ftype }
933 + DSP_BUILTIN (mulsathh_h, MULSATHH_H, &short_ftype_short_short),
934 + DSP_BUILTIN (mulsathh_w, MULSATHH_W, &int_ftype_short_short),
935 + DSP_BUILTIN (mulsatrndhh_h, MULSATRNDHH_H, &short_ftype_short_short),
936 + DSP_BUILTIN (mulsatrndwh_w, MULSATRNDWH_W, &int_ftype_int_short),
937 + DSP_BUILTIN (mulsatwh_w, MULSATWH_W, &int_ftype_int_short),
938 + DSP_BUILTIN (satadd_h, SATADD_H, &short_ftype_short_short),
939 + DSP_BUILTIN (satsub_h, SATSUB_H, &short_ftype_short_short),
940 + DSP_BUILTIN (satadd_w, SATADD_W, &int_ftype_int_int),
941 + DSP_BUILTIN (satsub_w, SATSUB_W, &int_ftype_int_int),
942 + DSP_BUILTIN (mulwh_d, MULWH_D, &longlong_ftype_int_short),
943 + DSP_BUILTIN (mulnwh_d, MULNWH_D, &longlong_ftype_int_short)
948 +avr32_init_builtins (void)
951 + const struct builtin_description *d;
952 + tree endlink = void_list_node;
953 + tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
954 + tree longlong_endlink =
955 + tree_cons (NULL_TREE, long_long_integer_type_node, endlink);
956 + tree short_endlink =
957 + tree_cons (NULL_TREE, short_integer_type_node, endlink);
958 + tree void_endlink = tree_cons (NULL_TREE, void_type_node, endlink);
960 + /* int func (int) */
961 + int_ftype_int = build_function_type (integer_type_node, int_endlink);
963 + /* short func (short) */
965 + = build_function_type (short_integer_type_node, short_endlink);
967 + /* short func (short, short) */
968 + short_ftype_short_short
969 + = build_function_type (short_integer_type_node,
970 + tree_cons (NULL_TREE, short_integer_type_node,
973 + /* long long func (long long, short, short) */
974 + longlong_ftype_longlong_short_short
975 + = build_function_type (long_long_integer_type_node,
976 + tree_cons (NULL_TREE, long_long_integer_type_node,
977 + tree_cons (NULL_TREE,
978 + short_integer_type_node,
981 + /* long long func (short, short) */
982 + longlong_ftype_short_short
983 + = build_function_type (long_long_integer_type_node,
984 + tree_cons (NULL_TREE, short_integer_type_node,
987 + /* int func (int, int) */
989 + = build_function_type (integer_type_node,
990 + tree_cons (NULL_TREE, integer_type_node,
993 + /* long long func (int, int) */
994 + longlong_ftype_int_int
995 + = build_function_type (long_long_integer_type_node,
996 + tree_cons (NULL_TREE, integer_type_node,
999 + /* long long int func (long long, int, short) */
1000 + longlong_ftype_longlong_int_short
1001 + = build_function_type (long_long_integer_type_node,
1002 + tree_cons (NULL_TREE, long_long_integer_type_node,
1003 + tree_cons (NULL_TREE, integer_type_node,
1006 + /* long long int func (int, short) */
1007 + longlong_ftype_int_short
1008 + = build_function_type (long_long_integer_type_node,
1009 + tree_cons (NULL_TREE, integer_type_node,
1012 + /* int func (int, short, short) */
1013 + int_ftype_int_short_short
1014 + = build_function_type (integer_type_node,
1015 + tree_cons (NULL_TREE, integer_type_node,
1016 + tree_cons (NULL_TREE,
1017 + short_integer_type_node,
1020 + /* int func (short, short) */
1021 + int_ftype_short_short
1022 + = build_function_type (integer_type_node,
1023 + tree_cons (NULL_TREE, short_integer_type_node,
1026 + /* int func (int, short) */
1027 + int_ftype_int_short
1028 + = build_function_type (integer_type_node,
1029 + tree_cons (NULL_TREE, integer_type_node,
1032 + /* void func (int, int) */
1033 + void_ftype_int_int
1034 + = build_function_type (void_type_node,
1035 + tree_cons (NULL_TREE, integer_type_node,
1038 + /* void func (int, int, int) */
1039 + void_ftype_int_int_int
1040 + = build_function_type (void_type_node,
1041 + tree_cons (NULL_TREE, integer_type_node,
1042 + tree_cons (NULL_TREE, integer_type_node,
1045 + /* void func (int, int, long long) */
1046 + void_ftype_int_int_longlong
1047 + = build_function_type (void_type_node,
1048 + tree_cons (NULL_TREE, integer_type_node,
1049 + tree_cons (NULL_TREE, integer_type_node,
1050 + longlong_endlink)));
1052 + /* void func (int, int, int, int, int) */
1053 + void_ftype_int_int_int_int_int
1054 + = build_function_type (void_type_node,
1055 + tree_cons (NULL_TREE, integer_type_node,
1056 + tree_cons (NULL_TREE, integer_type_node,
1057 + tree_cons (NULL_TREE,
1058 + integer_type_node,
1061 + integer_type_node,
1064 + /* void func (void *, int) */
1065 + void_ftype_ptr_int
1066 + = build_function_type (void_type_node,
1067 + tree_cons (NULL_TREE, ptr_type_node, int_endlink));
1069 + /* void func (int) */
1070 + void_ftype_int = build_function_type (void_type_node, int_endlink);
1072 + /* void func (void) */
1073 + void_ftype_void = build_function_type (void_type_node, void_endlink);
1075 + /* int func (void) */
1076 + int_ftype_void = build_function_type (integer_type_node, void_endlink);
1078 + /* int func (void *, int) */
1080 + = build_function_type (integer_type_node,
1081 + tree_cons (NULL_TREE, ptr_type_node, int_endlink));
1083 + /* int func (int, int, int) */
1084 + int_ftype_int_int_int
1085 + = build_function_type (integer_type_node,
1086 + tree_cons (NULL_TREE, integer_type_node,
1087 + tree_cons (NULL_TREE, integer_type_node,
1090 + /* Initialize avr32 builtins. */
1091 + def_builtin ("__builtin_mfsr", int_ftype_int, AVR32_BUILTIN_MFSR);
1092 + def_builtin ("__builtin_mtsr", void_ftype_int_int, AVR32_BUILTIN_MTSR);
1093 + def_builtin ("__builtin_mfdr", int_ftype_int, AVR32_BUILTIN_MFDR);
1094 + def_builtin ("__builtin_mtdr", void_ftype_int_int, AVR32_BUILTIN_MTDR);
1095 + def_builtin ("__builtin_cache", void_ftype_ptr_int, AVR32_BUILTIN_CACHE);
1096 + def_builtin ("__builtin_sync", void_ftype_int, AVR32_BUILTIN_SYNC);
1097 + def_builtin ("__builtin_ssrf", void_ftype_int, AVR32_BUILTIN_SSRF);
1098 + def_builtin ("__builtin_csrf", void_ftype_int, AVR32_BUILTIN_CSRF);
1099 + def_builtin ("__builtin_tlbr", void_ftype_void, AVR32_BUILTIN_TLBR);
1100 + def_builtin ("__builtin_tlbs", void_ftype_void, AVR32_BUILTIN_TLBS);
1101 + def_builtin ("__builtin_tlbw", void_ftype_void, AVR32_BUILTIN_TLBW);
1102 + def_builtin ("__builtin_breakpoint", void_ftype_void,
1103 + AVR32_BUILTIN_BREAKPOINT);
1104 + def_builtin ("__builtin_xchg", int_ftype_ptr_int, AVR32_BUILTIN_XCHG);
1105 + def_builtin ("__builtin_ldxi", int_ftype_ptr_int, AVR32_BUILTIN_LDXI);
1106 + def_builtin ("__builtin_bswap_16", short_ftype_short,
1107 + AVR32_BUILTIN_BSWAP16);
1108 + def_builtin ("__builtin_bswap_32", int_ftype_int, AVR32_BUILTIN_BSWAP32);
1109 + def_builtin ("__builtin_cop", void_ftype_int_int_int_int_int,
1110 + AVR32_BUILTIN_COP);
1111 + def_builtin ("__builtin_mvcr_w", int_ftype_int_int, AVR32_BUILTIN_MVCR_W);
1112 + def_builtin ("__builtin_mvrc_w", void_ftype_int_int_int,
1113 + AVR32_BUILTIN_MVRC_W);
1114 + def_builtin ("__builtin_mvcr_d", longlong_ftype_int_int,
1115 + AVR32_BUILTIN_MVCR_D);
1116 + def_builtin ("__builtin_mvrc_d", void_ftype_int_int_longlong,
1117 + AVR32_BUILTIN_MVRC_D);
1118 + def_builtin ("__builtin_sats", int_ftype_int_int_int, AVR32_BUILTIN_SATS);
1119 + def_builtin ("__builtin_satu", int_ftype_int_int_int, AVR32_BUILTIN_SATU);
1120 + def_builtin ("__builtin_satrnds", int_ftype_int_int_int,
1121 + AVR32_BUILTIN_SATRNDS);
1122 + def_builtin ("__builtin_satrndu", int_ftype_int_int_int,
1123 + AVR32_BUILTIN_SATRNDU);
1124 + def_builtin ("__builtin_musfr", void_ftype_int, AVR32_BUILTIN_MUSFR);
1125 + def_builtin ("__builtin_mustr", int_ftype_void, AVR32_BUILTIN_MUSTR);
1126 + def_builtin ("__builtin_macsathh_w", int_ftype_int_short_short,
1127 + AVR32_BUILTIN_MACSATHH_W);
1128 + def_builtin ("__builtin_macwh_d", longlong_ftype_longlong_int_short,
1129 + AVR32_BUILTIN_MACWH_D);
1130 + def_builtin ("__builtin_machh_d", longlong_ftype_longlong_short_short,
1131 + AVR32_BUILTIN_MACHH_D);
1132 + def_builtin ("__builtin_mems", void_ftype_ptr_int, AVR32_BUILTIN_MEMS);
1133 + def_builtin ("__builtin_memt", void_ftype_ptr_int, AVR32_BUILTIN_MEMT);
1134 + def_builtin ("__builtin_memc", void_ftype_ptr_int, AVR32_BUILTIN_MEMC);
1136 + /* Add all builtins that are more or less simple operations on two
1138 + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
1140 + /* Use one of the operands; the target can have a different mode for
1141 + mask-generating compares. */
1146 + def_mbuiltin (d->mask, d->name, *(d->ftype), d->code);
1151 +/* Subroutine of avr32_expand_builtin to take care of binop insns. */
1154 +avr32_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
1157 + tree arg0 = TREE_VALUE (arglist);
1158 + tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1159 + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1160 + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1161 + enum machine_mode tmode = insn_data[icode].operand[0].mode;
1162 + enum machine_mode mode0 = insn_data[icode].operand[1].mode;
1163 + enum machine_mode mode1 = insn_data[icode].operand[2].mode;
1166 + || GET_MODE (target) != tmode
1167 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1168 + target = gen_reg_rtx (tmode);
1170 + /* In case the insn wants input operands in modes different from the
1172 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1174 + /* If op0 is already a reg we must cast it to the correct mode. */
1176 + op0 = convert_to_mode (mode0, op0, 1);
1178 + op0 = copy_to_mode_reg (mode0, op0);
1180 + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
1182 + /* If op1 is already a reg we must cast it to the correct mode. */
1184 + op1 = convert_to_mode (mode1, op1, 1);
1186 + op1 = copy_to_mode_reg (mode1, op1);
1188 + pat = GEN_FCN (icode) (target, op0, op1);
1195 +/* Expand an expression EXP that calls a built-in function,
1196 + with result going to TARGET if that's convenient
1197 + (and in mode MODE if that's convenient).
1198 + SUBTARGET may be used as the target for computing one of EXP's operands.
1199 + IGNORE is nonzero if the value is to be ignored. */
1202 +avr32_expand_builtin (tree exp,
1204 + rtx subtarget ATTRIBUTE_UNUSED,
1205 + enum machine_mode mode ATTRIBUTE_UNUSED,
1206 + int ignore ATTRIBUTE_UNUSED)
1208 + const struct builtin_description *d;
1210 + enum insn_code icode = 0;
1211 + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
1212 + tree arglist = TREE_OPERAND (exp, 1);
1213 + tree arg0, arg1, arg2;
1214 + rtx op0, op1, op2, pat;
1215 + enum machine_mode tmode, mode0, mode1;
1216 + enum machine_mode arg0_mode;
1217 + int fcode = DECL_FUNCTION_CODE (fndecl);
1224 + case AVR32_BUILTIN_SATS:
1225 + case AVR32_BUILTIN_SATU:
1226 + case AVR32_BUILTIN_SATRNDS:
1227 + case AVR32_BUILTIN_SATRNDU:
1229 + const char *fname;
1233 + case AVR32_BUILTIN_SATS:
1234 + icode = CODE_FOR_sats;
1237 + case AVR32_BUILTIN_SATU:
1238 + icode = CODE_FOR_satu;
1241 + case AVR32_BUILTIN_SATRNDS:
1242 + icode = CODE_FOR_satrnds;
1243 + fname = "satrnds";
1245 + case AVR32_BUILTIN_SATRNDU:
1246 + icode = CODE_FOR_satrndu;
1247 + fname = "satrndu";
1251 + arg0 = TREE_VALUE (arglist);
1252 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1253 + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
1254 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1255 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1256 + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
1258 + tmode = insn_data[icode].operand[0].mode;
1262 + || GET_MODE (target) != tmode
1263 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1264 + target = gen_reg_rtx (tmode);
1267 + if (!(*insn_data[icode].operand[0].predicate) (op0, GET_MODE (op0)))
1269 + op0 = copy_to_mode_reg (insn_data[icode].operand[0].mode, op0);
1272 + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode))
1274 + error ("Parameter 2 to __builtin_%s should be a constant number.",
1279 + if (!(*insn_data[icode].operand[1].predicate) (op2, SImode))
1281 + error ("Parameter 3 to __builtin_%s should be a constant number.",
1286 + emit_move_insn (target, op0);
1287 + pat = GEN_FCN (icode) (target, op1, op2);
1294 + case AVR32_BUILTIN_MUSTR:
1295 + icode = CODE_FOR_mustr;
1296 + tmode = insn_data[icode].operand[0].mode;
1299 + || GET_MODE (target) != tmode
1300 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1301 + target = gen_reg_rtx (tmode);
1302 + pat = GEN_FCN (icode) (target);
1308 + case AVR32_BUILTIN_MFSR:
1309 + icode = CODE_FOR_mfsr;
1310 + arg0 = TREE_VALUE (arglist);
1311 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1312 + tmode = insn_data[icode].operand[0].mode;
1313 + mode0 = insn_data[icode].operand[1].mode;
1315 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1317 + error ("Parameter 1 to __builtin_mfsr must be a constant number");
1321 + || GET_MODE (target) != tmode
1322 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1323 + target = gen_reg_rtx (tmode);
1324 + pat = GEN_FCN (icode) (target, op0);
1329 + case AVR32_BUILTIN_MTSR:
1330 + icode = CODE_FOR_mtsr;
1331 + arg0 = TREE_VALUE (arglist);
1332 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1333 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1334 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1335 + mode0 = insn_data[icode].operand[0].mode;
1336 + mode1 = insn_data[icode].operand[1].mode;
1338 + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
1340 + error ("Parameter 1 to __builtin_mtsr must be a constant number");
1341 + return gen_reg_rtx (mode0);
1343 + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
1344 + op1 = copy_to_mode_reg (mode1, op1);
1345 + pat = GEN_FCN (icode) (op0, op1);
1350 + case AVR32_BUILTIN_MFDR:
1351 + icode = CODE_FOR_mfdr;
1352 + arg0 = TREE_VALUE (arglist);
1353 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1354 + tmode = insn_data[icode].operand[0].mode;
1355 + mode0 = insn_data[icode].operand[1].mode;
1357 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1359 + error ("Parameter 1 to __builtin_mfdr must be a constant number");
1363 + || GET_MODE (target) != tmode
1364 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1365 + target = gen_reg_rtx (tmode);
1366 + pat = GEN_FCN (icode) (target, op0);
1371 + case AVR32_BUILTIN_MTDR:
1372 + icode = CODE_FOR_mtdr;
1373 + arg0 = TREE_VALUE (arglist);
1374 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1375 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1376 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1377 + mode0 = insn_data[icode].operand[0].mode;
1378 + mode1 = insn_data[icode].operand[1].mode;
1380 + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
1382 + error ("Parameter 1 to __builtin_mtdr must be a constant number");
1383 + return gen_reg_rtx (mode0);
1385 + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
1386 + op1 = copy_to_mode_reg (mode1, op1);
1387 + pat = GEN_FCN (icode) (op0, op1);
1392 + case AVR32_BUILTIN_CACHE:
1393 + icode = CODE_FOR_cache;
1394 + arg0 = TREE_VALUE (arglist);
1395 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1396 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1397 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1398 + mode0 = insn_data[icode].operand[0].mode;
1399 + mode1 = insn_data[icode].operand[1].mode;
1401 + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
1403 + error ("Parameter 2 to __builtin_cache must be a constant number");
1404 + return gen_reg_rtx (mode1);
1407 + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
1408 + op0 = copy_to_mode_reg (mode0, op0);
1410 + pat = GEN_FCN (icode) (op0, op1);
1415 + case AVR32_BUILTIN_SYNC:
1416 + case AVR32_BUILTIN_MUSFR:
1417 + case AVR32_BUILTIN_SSRF:
1418 + case AVR32_BUILTIN_CSRF:
1420 + const char *fname;
1424 + case AVR32_BUILTIN_SYNC:
1425 + icode = CODE_FOR_sync;
1428 + case AVR32_BUILTIN_MUSFR:
1429 + icode = CODE_FOR_musfr;
1432 + case AVR32_BUILTIN_SSRF:
1433 + icode = CODE_FOR_ssrf;
1436 + case AVR32_BUILTIN_CSRF:
1437 + icode = CODE_FOR_csrf;
1442 + arg0 = TREE_VALUE (arglist);
1443 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1444 + mode0 = insn_data[icode].operand[0].mode;
1446 + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
1448 + if (icode == CODE_FOR_musfr)
1449 + op0 = copy_to_mode_reg (mode0, op0);
1452 + error ("Parameter to __builtin_%s is illegal.", fname);
1453 + return gen_reg_rtx (mode0);
1456 + pat = GEN_FCN (icode) (op0);
1462 + case AVR32_BUILTIN_TLBR:
1463 + icode = CODE_FOR_tlbr;
1464 + pat = GEN_FCN (icode) (NULL_RTX);
1469 + case AVR32_BUILTIN_TLBS:
1470 + icode = CODE_FOR_tlbs;
1471 + pat = GEN_FCN (icode) (NULL_RTX);
1476 + case AVR32_BUILTIN_TLBW:
1477 + icode = CODE_FOR_tlbw;
1478 + pat = GEN_FCN (icode) (NULL_RTX);
1483 + case AVR32_BUILTIN_BREAKPOINT:
1484 + icode = CODE_FOR_breakpoint;
1485 + pat = GEN_FCN (icode) (NULL_RTX);
1490 + case AVR32_BUILTIN_XCHG:
1491 + icode = CODE_FOR_sync_lock_test_and_setsi;
1492 + arg0 = TREE_VALUE (arglist);
1493 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1494 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1495 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1496 + tmode = insn_data[icode].operand[0].mode;
1497 + mode0 = insn_data[icode].operand[1].mode;
1498 + mode1 = insn_data[icode].operand[2].mode;
1500 + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
1502 + op1 = copy_to_mode_reg (mode1, op1);
1505 + op0 = force_reg (GET_MODE (op0), op0);
1506 + op0 = gen_rtx_MEM (GET_MODE (op0), op0);
1507 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1510 + ("Parameter 1 to __builtin_xchg must be a pointer to an integer.");
1514 + || GET_MODE (target) != tmode
1515 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1516 + target = gen_reg_rtx (tmode);
1517 + pat = GEN_FCN (icode) (target, op0, op1);
1522 + case AVR32_BUILTIN_LDXI:
1523 + icode = CODE_FOR_ldxi;
1524 + arg0 = TREE_VALUE (arglist);
1525 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1526 + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
1527 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1528 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1529 + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
1530 + tmode = insn_data[icode].operand[0].mode;
1531 + mode0 = insn_data[icode].operand[1].mode;
1532 + mode1 = insn_data[icode].operand[2].mode;
1534 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1536 + op0 = copy_to_mode_reg (mode0, op0);
1539 + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
1541 + op1 = copy_to_mode_reg (mode1, op1);
1544 + if (!(*insn_data[icode].operand[3].predicate) (op2, SImode))
1547 + ("Parameter 3 to __builtin_ldxi must be a valid extract shift operand: (0|8|16|24)");
1548 + return gen_reg_rtx (mode0);
1552 + || GET_MODE (target) != tmode
1553 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1554 + target = gen_reg_rtx (tmode);
1555 + pat = GEN_FCN (icode) (target, op0, op1, op2);
1560 + case AVR32_BUILTIN_BSWAP16:
1562 + icode = CODE_FOR_bswap_16;
1563 + arg0 = TREE_VALUE (arglist);
1564 + arg0_mode = TYPE_MODE (TREE_TYPE (arg0));
1565 + mode0 = insn_data[icode].operand[1].mode;
1566 + if (arg0_mode != mode0)
1567 + arg0 = build1 (NOP_EXPR,
1568 + (*lang_hooks.types.type_for_mode) (mode0, 0), arg0);
1570 + op0 = expand_expr (arg0, NULL_RTX, HImode, 0);
1571 + tmode = insn_data[icode].operand[0].mode;
1574 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1576 + if ( CONST_INT_P (op0) )
1578 + HOST_WIDE_INT val = ( ((INTVAL (op0)&0x00ff) << 8) |
1579 + ((INTVAL (op0)&0xff00) >> 8) );
1580 + /* Sign extend 16-bit value to host wide int */
1581 + val <<= (HOST_BITS_PER_WIDE_INT - 16);
1582 + val >>= (HOST_BITS_PER_WIDE_INT - 16);
1583 + op0 = GEN_INT(val);
1585 + || GET_MODE (target) != tmode
1586 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1587 + target = gen_reg_rtx (tmode);
1588 + emit_move_insn(target, op0);
1592 + op0 = copy_to_mode_reg (mode0, op0);
1596 + || GET_MODE (target) != tmode
1597 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1599 + target = gen_reg_rtx (tmode);
1603 + pat = GEN_FCN (icode) (target, op0);
1610 + case AVR32_BUILTIN_BSWAP32:
1612 + icode = CODE_FOR_bswap_32;
1613 + arg0 = TREE_VALUE (arglist);
1614 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1615 + tmode = insn_data[icode].operand[0].mode;
1616 + mode0 = insn_data[icode].operand[1].mode;
1618 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1620 + if ( CONST_INT_P (op0) )
1622 + HOST_WIDE_INT val = ( ((INTVAL (op0)&0x000000ff) << 24) |
1623 + ((INTVAL (op0)&0x0000ff00) << 8) |
1624 + ((INTVAL (op0)&0x00ff0000) >> 8) |
1625 + ((INTVAL (op0)&0xff000000) >> 24) );
1626 + /* Sign extend 32-bit value to host wide int */
1627 + val <<= (HOST_BITS_PER_WIDE_INT - 32);
1628 + val >>= (HOST_BITS_PER_WIDE_INT - 32);
1629 + op0 = GEN_INT(val);
1631 + || GET_MODE (target) != tmode
1632 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1633 + target = gen_reg_rtx (tmode);
1634 + emit_move_insn(target, op0);
1638 + op0 = copy_to_mode_reg (mode0, op0);
1642 + || GET_MODE (target) != tmode
1643 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1644 + target = gen_reg_rtx (tmode);
1647 + pat = GEN_FCN (icode) (target, op0);
1654 + case AVR32_BUILTIN_MVCR_W:
1655 + case AVR32_BUILTIN_MVCR_D:
1657 + arg0 = TREE_VALUE (arglist);
1658 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1659 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1660 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1662 + if (fcode == AVR32_BUILTIN_MVCR_W)
1663 + icode = CODE_FOR_mvcrsi;
1665 + icode = CODE_FOR_mvcrdi;
1667 + tmode = insn_data[icode].operand[0].mode;
1670 + || GET_MODE (target) != tmode
1671 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1672 + target = gen_reg_rtx (tmode);
1674 + if (!(*insn_data[icode].operand[1].predicate) (op0, SImode))
1677 + ("Parameter 1 to __builtin_cop is not a valid coprocessor number.");
1678 + error ("Number should be between 0 and 7.");
1682 + if (!(*insn_data[icode].operand[2].predicate) (op1, SImode))
1685 + ("Parameter 2 to __builtin_cop is not a valid coprocessor register number.");
1686 + error ("Number should be between 0 and 15.");
1690 + pat = GEN_FCN (icode) (target, op0, op1);
1697 + case AVR32_BUILTIN_MACSATHH_W:
1698 + case AVR32_BUILTIN_MACWH_D:
1699 + case AVR32_BUILTIN_MACHH_D:
1701 + arg0 = TREE_VALUE (arglist);
1702 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1703 + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
1704 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1705 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1706 + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
1708 + icode = ((fcode == AVR32_BUILTIN_MACSATHH_W) ? CODE_FOR_macsathh_w :
1709 + (fcode == AVR32_BUILTIN_MACWH_D) ? CODE_FOR_macwh_d :
1710 + CODE_FOR_machh_d);
1712 + tmode = insn_data[icode].operand[0].mode;
1713 + mode0 = insn_data[icode].operand[1].mode;
1714 + mode1 = insn_data[icode].operand[2].mode;
1718 + || GET_MODE (target) != tmode
1719 + || !(*insn_data[icode].operand[0].predicate) (target, tmode))
1720 + target = gen_reg_rtx (tmode);
1722 + if (!(*insn_data[icode].operand[0].predicate) (op0, tmode))
1724 + /* If op0 is already a reg we must cast it to the correct mode. */
1726 + op0 = convert_to_mode (tmode, op0, 1);
1728 + op0 = copy_to_mode_reg (tmode, op0);
1731 + if (!(*insn_data[icode].operand[1].predicate) (op1, mode0))
1733 + /* If op1 is already a reg we must cast it to the correct mode. */
1735 + op1 = convert_to_mode (mode0, op1, 1);
1737 + op1 = copy_to_mode_reg (mode0, op1);
1740 + if (!(*insn_data[icode].operand[2].predicate) (op2, mode1))
1742 + /* If op1 is already a reg we must cast it to the correct mode. */
1744 + op2 = convert_to_mode (mode1, op2, 1);
1746 + op2 = copy_to_mode_reg (mode1, op2);
1749 + emit_move_insn (target, op0);
1751 + pat = GEN_FCN (icode) (target, op1, op2);
1757 + case AVR32_BUILTIN_MVRC_W:
1758 + case AVR32_BUILTIN_MVRC_D:
1760 + arg0 = TREE_VALUE (arglist);
1761 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1762 + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
1763 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1764 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1765 + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
1767 + if (fcode == AVR32_BUILTIN_MVRC_W)
1768 + icode = CODE_FOR_mvrcsi;
1770 + icode = CODE_FOR_mvrcdi;
1772 + if (!(*insn_data[icode].operand[0].predicate) (op0, SImode))
1774 + error ("Parameter 1 is not a valid coprocessor number.");
1775 + error ("Number should be between 0 and 7.");
1779 + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode))
1781 + error ("Parameter 2 is not a valid coprocessor register number.");
1782 + error ("Number should be between 0 and 15.");
1786 + if (GET_CODE (op2) == CONST_INT
1787 + || GET_CODE (op2) == CONST
1788 + || GET_CODE (op2) == SYMBOL_REF || GET_CODE (op2) == LABEL_REF)
1790 + op2 = force_const_mem (insn_data[icode].operand[2].mode, op2);
1793 + if (!(*insn_data[icode].operand[2].predicate) (op2, GET_MODE (op2)))
1794 + op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2);
1797 + pat = GEN_FCN (icode) (op0, op1, op2);
1804 + case AVR32_BUILTIN_COP:
1808 + icode = CODE_FOR_cop;
1809 + arg0 = TREE_VALUE (arglist);
1810 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1811 + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
1812 + arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
1814 + TREE_VALUE (TREE_CHAIN
1815 + (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))));
1816 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1817 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1818 + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
1819 + op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
1820 + op4 = expand_expr (arg4, NULL_RTX, VOIDmode, 0);
1822 + if (!(*insn_data[icode].operand[0].predicate) (op0, SImode))
1825 + ("Parameter 1 to __builtin_cop is not a valid coprocessor number.");
1826 + error ("Number should be between 0 and 7.");
1830 + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode))
1833 + ("Parameter 2 to __builtin_cop is not a valid coprocessor register number.");
1834 + error ("Number should be between 0 and 15.");
1838 + if (!(*insn_data[icode].operand[2].predicate) (op2, SImode))
1841 + ("Parameter 3 to __builtin_cop is not a valid coprocessor register number.");
1842 + error ("Number should be between 0 and 15.");
1846 + if (!(*insn_data[icode].operand[3].predicate) (op3, SImode))
1849 + ("Parameter 4 to __builtin_cop is not a valid coprocessor register number.");
1850 + error ("Number should be between 0 and 15.");
1854 + if (!(*insn_data[icode].operand[4].predicate) (op4, SImode))
1857 + ("Parameter 5 to __builtin_cop is not a valid coprocessor operation.");
1858 + error ("Number should be between 0 and 127.");
1862 + pat = GEN_FCN (icode) (op0, op1, op2, op3, op4);
1869 + case AVR32_BUILTIN_MEMS:
1870 + case AVR32_BUILTIN_MEMC:
1871 + case AVR32_BUILTIN_MEMT:
1874 + error ("Trying to use __builtin_mem(s/c/t) when target does not support RMW insns.");
1877 + case AVR32_BUILTIN_MEMS:
1878 + icode = CODE_FOR_iorsi3;
1880 + case AVR32_BUILTIN_MEMC:
1881 + icode = CODE_FOR_andsi3;
1883 + case AVR32_BUILTIN_MEMT:
1884 + icode = CODE_FOR_xorsi3;
1888 + arg0 = TREE_VALUE (arglist);
1889 + arg1 = TREE_VALUE (TREE_CHAIN (arglist));
1890 + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
1891 + if ( GET_CODE (op0) == SYMBOL_REF )
1892 + // This symbol must be RMW addressable
1893 + SYMBOL_REF_FLAGS (op0) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT);
1894 + op0 = gen_rtx_MEM(SImode, op0);
1895 + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
1896 + mode0 = insn_data[icode].operand[1].mode;
1899 + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
1901 + error ("Parameter 1 to __builtin_mem(s/c/t) must be a Ks15<<2 address or a rmw addressable symbol.");
1904 + if ( !CONST_INT_P (op1)
1905 + || INTVAL (op1) > 31
1906 + || INTVAL (op1) < 0 )
1907 + error ("Parameter 2 to __builtin_mem(s/c/t) must be a constant between 0 and 31.");
1909 + if ( fcode == AVR32_BUILTIN_MEMC )
1910 + op1 = GEN_INT((~(1 << INTVAL(op1)))&0xffffffff);
1912 + op1 = GEN_INT((1 << INTVAL(op1))&0xffffffff);
1913 + pat = GEN_FCN (icode) (op0, op0, op1);
1922 + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
1923 + if (d->code == fcode)
1924 + return avr32_expand_binop_builtin (d->icode, arglist, target);
1927 + /* @@@ Should really do something sensible here. */
1932 +/* Handle an "interrupt" or "isr" attribute;
1933 + arguments as in struct attribute_spec.handler. */
1936 +avr32_handle_isr_attribute (tree * node, tree name, tree args,
1937 + int flags, bool * no_add_attrs)
1939 + if (DECL_P (*node))
1941 + if (TREE_CODE (*node) != FUNCTION_DECL)
1943 + warning (OPT_Wattributes,"`%s' attribute only applies to functions",
1944 + IDENTIFIER_POINTER (name));
1945 + *no_add_attrs = true;
1947 + /* FIXME: the argument if any is checked for type attributes; should it
1948 + be checked for decl ones? */
1952 + if (TREE_CODE (*node) == FUNCTION_TYPE
1953 + || TREE_CODE (*node) == METHOD_TYPE)
1955 + if (avr32_isr_value (args) == AVR32_FT_UNKNOWN)
1957 + warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name));
1958 + *no_add_attrs = true;
1961 + else if (TREE_CODE (*node) == POINTER_TYPE
1962 + && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE
1963 + || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE)
1964 + && avr32_isr_value (args) != AVR32_FT_UNKNOWN)
1966 + *node = build_variant_type_copy (*node);
1967 + TREE_TYPE (*node) = build_type_attribute_variant
1968 + (TREE_TYPE (*node),
1969 + tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node))));
1970 + *no_add_attrs = true;
1974 + /* Possibly pass this attribute on from the type to a decl. */
1975 + if (flags & ((int) ATTR_FLAG_DECL_NEXT
1976 + | (int) ATTR_FLAG_FUNCTION_NEXT
1977 + | (int) ATTR_FLAG_ARRAY_NEXT))
1979 + *no_add_attrs = true;
1980 + return tree_cons (name, args, NULL_TREE);
1984 + warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name));
1992 +/* Handle an attribute requiring a FUNCTION_DECL;
1993 + arguments as in struct attribute_spec.handler. */
1995 +avr32_handle_fndecl_attribute (tree * node, tree name,
1996 + tree args ATTRIBUTE_UNUSED,
1997 + int flags ATTRIBUTE_UNUSED,
1998 + bool * no_add_attrs)
2000 + if (TREE_CODE (*node) != FUNCTION_DECL)
2002 + warning (OPT_Wattributes,"%qs attribute only applies to functions",
2003 + IDENTIFIER_POINTER (name));
2004 + *no_add_attrs = true;
2011 +/* Handle an acall attribute;
2012 + arguments as in struct attribute_spec.handler. */
2015 +avr32_handle_acall_attribute (tree * node, tree name,
2016 + tree args ATTRIBUTE_UNUSED,
2017 + int flags ATTRIBUTE_UNUSED, bool * no_add_attrs)
2019 + if (TREE_CODE (*node) == FUNCTION_TYPE || TREE_CODE (*node) == METHOD_TYPE)
2021 + warning (OPT_Wattributes,"`%s' attribute not yet supported...",
2022 + IDENTIFIER_POINTER (name));
2023 + *no_add_attrs = true;
2027 + warning (OPT_Wattributes,"`%s' attribute only applies to functions",
2028 + IDENTIFIER_POINTER (name));
2029 + *no_add_attrs = true;
2034 +/* Return 0 if the attributes for two types are incompatible, 1 if they
2035 + are compatible, and 2 if they are nearly compatible (which causes a
2036 + warning to be generated). */
2039 +avr32_comp_type_attributes (tree type1, tree type2)
2041 + int acall1, acall2, isr1, isr2, naked1, naked2;
2043 + /* Check for mismatch of non-default calling convention. */
2044 + if (TREE_CODE (type1) != FUNCTION_TYPE)
2047 + /* Check for mismatched call attributes. */
2048 + acall1 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type1)) != NULL;
2049 + acall2 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type2)) != NULL;
2050 + naked1 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type1)) != NULL;
2051 + naked2 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type2)) != NULL;
2052 + isr1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL;
2054 + isr1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL;
2056 + isr2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL;
2058 + isr2 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL;
2060 + if ((acall1 && isr2)
2061 + || (acall2 && isr1) || (naked1 && isr2) || (naked2 && isr1))
2068 +/* Computes the type of the current function. */
2070 +static unsigned long
2071 +avr32_compute_func_type (void)
2073 + unsigned long type = AVR32_FT_UNKNOWN;
2077 + if (TREE_CODE (current_function_decl) != FUNCTION_DECL)
2080 + /* Decide if the current function is volatile. Such functions never
2081 + return, and many memory cycles can be saved by not storing register
2082 + values that will never be needed again. This optimization was added to
2083 + speed up context switching in a kernel application. */
2085 + && TREE_NOTHROW (current_function_decl)
2086 + && TREE_THIS_VOLATILE (current_function_decl))
2087 + type |= AVR32_FT_VOLATILE;
2089 + if (cfun->static_chain_decl != NULL)
2090 + type |= AVR32_FT_NESTED;
2092 + attr = DECL_ATTRIBUTES (current_function_decl);
2094 + a = lookup_attribute ("isr", attr);
2095 + if (a == NULL_TREE)
2096 + a = lookup_attribute ("interrupt", attr);
2098 + if (a == NULL_TREE)
2099 + type |= AVR32_FT_NORMAL;
2101 + type |= avr32_isr_value (TREE_VALUE (a));
2104 + a = lookup_attribute ("acall", attr);
2105 + if (a != NULL_TREE)
2106 + type |= AVR32_FT_ACALL;
2108 + a = lookup_attribute ("naked", attr);
2109 + if (a != NULL_TREE)
2110 + type |= AVR32_FT_NAKED;
2115 +/* Returns the type of the current function. */
2117 +static unsigned long
2118 +avr32_current_func_type (void)
2120 + if (AVR32_FUNC_TYPE (cfun->machine->func_type) == AVR32_FT_UNKNOWN)
2121 + cfun->machine->func_type = avr32_compute_func_type ();
2123 + return cfun->machine->func_type;
2127 + This target hook should return true if we should not pass type solely
2128 + in registers. The file expr.h defines a definition that is usually appropriate,
2129 + refer to expr.h for additional documentation.
2132 +avr32_must_pass_in_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type)
2134 + if (type && AGGREGATE_TYPE_P (type)
2135 + /* If the alignment is less than the size then pass in the struct on
2137 + && ((unsigned int) TYPE_ALIGN_UNIT (type) <
2138 + (unsigned int) int_size_in_bytes (type))
2139 + /* If we support unaligned word accesses then structs of size 4 and 8
2140 + can have any alignment and still be passed in registers. */
2141 + && !(TARGET_UNALIGNED_WORD
2142 + && (int_size_in_bytes (type) == 4
2143 + || int_size_in_bytes (type) == 8))
2144 + /* Double word structs need only a word alignment. */
2145 + && !(int_size_in_bytes (type) == 8 && TYPE_ALIGN_UNIT (type) >= 4))
2148 + if (type && AGGREGATE_TYPE_P (type)
2149 + /* Structs of size 3,5,6,7 are always passed in registers. */
2150 + && (int_size_in_bytes (type) == 3
2151 + || int_size_in_bytes (type) == 5
2152 + || int_size_in_bytes (type) == 6 || int_size_in_bytes (type) == 7))
2156 + return (type && TREE_ADDRESSABLE (type));
2161 +avr32_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED)
2167 + This target hook should return true if an argument at the position indicated
2168 + by cum should be passed by reference. This predicate is queried after target
2169 + independent reasons for being passed by reference, such as TREE_ADDRESSABLE (type).
2171 + If the hook returns true, a copy of that argument is made in memory and a
2172 + pointer to the argument is passed instead of the argument itself. The pointer
2173 + is passed in whatever way is appropriate for passing a pointer to that type.
2176 +avr32_pass_by_reference (CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED,
2177 + enum machine_mode mode ATTRIBUTE_UNUSED,
2178 + tree type, bool named ATTRIBUTE_UNUSED)
2180 + return (type && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST));
2184 +avr32_arg_partial_bytes (CUMULATIVE_ARGS * pcum ATTRIBUTE_UNUSED,
2185 + enum machine_mode mode ATTRIBUTE_UNUSED,
2186 + tree type ATTRIBUTE_UNUSED,
2187 + bool named ATTRIBUTE_UNUSED)
2193 +struct gcc_target targetm = TARGET_INITIALIZER;
2196 + Table used to convert from register number in the assembler instructions and
2197 + the register numbers used in gcc.
2199 +const int avr32_function_arg_reglist[] = {
2200 + INTERNAL_REGNUM (12),
2201 + INTERNAL_REGNUM (11),
2202 + INTERNAL_REGNUM (10),
2203 + INTERNAL_REGNUM (9),
2204 + INTERNAL_REGNUM (8)
2207 +rtx avr32_compare_op0 = NULL_RTX;
2208 +rtx avr32_compare_op1 = NULL_RTX;
2209 +rtx avr32_compare_operator = NULL_RTX;
2210 +rtx avr32_acc_cache = NULL_RTX;
2213 + Returns nonzero if it is allowed to store a value of mode mode in hard
2214 + register number regno.
2217 +avr32_hard_regno_mode_ok (int regnr, enum machine_mode mode)
2219 + /* We allow only float modes in the fp-registers */
2220 + if (regnr >= FIRST_FP_REGNUM
2221 + && regnr <= LAST_FP_REGNUM && GET_MODE_CLASS (mode) != MODE_FLOAT)
2228 + case DImode: /* long long */
2229 + case DFmode: /* double */
2230 + case SCmode: /* __complex__ float */
2231 + case CSImode: /* __complex__ int */
2233 + { /* long long int not supported in r12, sp, lr
2239 + if (regnr % 2) /* long long int has to be refered in even
2245 + case CDImode: /* __complex__ long long */
2246 + case DCmode: /* __complex__ double */
2247 + case TImode: /* 16 bytes */
2250 + else if (regnr % 2)
2261 +avr32_rnd_operands (rtx add, rtx shift)
2263 + if (GET_CODE (shift) == CONST_INT &&
2264 + GET_CODE (add) == CONST_INT && INTVAL (shift) > 0)
2266 + if ((1 << (INTVAL (shift) - 1)) == INTVAL (add))
2276 +avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, const char *str)
2283 + HOST_WIDE_INT min_value = 0, max_value = 0;
2287 + size_str[0] = str[2];
2288 + size_str[1] = str[3];
2289 + size_str[2] = '\0';
2290 + const_size = atoi (size_str);
2292 + if (toupper (str[1]) == 'U')
2295 + max_value = (1 << const_size) - 1;
2297 + else if (toupper (str[1]) == 'S')
2299 + min_value = -(1 << (const_size - 1));
2300 + max_value = (1 << (const_size - 1)) - 1;
2308 + if (value >= min_value && value <= max_value)
2315 + return avr32_mask_upper_bits_operand (GEN_INT (value), VOIDmode);
2317 + return avr32_hi16_immediate_operand (GEN_INT (value), VOIDmode);
2319 + return one_bit_set_operand (GEN_INT (value), VOIDmode);
2321 + return one_bit_cleared_operand (GEN_INT (value), VOIDmode);
2323 + /* The lower 16-bits are set. */
2324 + return ((value & 0xffff) == 0xffff) ;
2331 +/*Compute mask of which floating-point registers needs saving upon
2332 + entry to this function*/
2333 +static unsigned long
2334 +avr32_compute_save_fp_reg_mask (void)
2336 + unsigned long func_type = avr32_current_func_type ();
2337 + unsigned int save_reg_mask = 0;
2339 + unsigned int max_reg = 7;
2340 + int save_all_call_used_regs = FALSE;
2342 + /* This only applies for hardware floating-point implementation. */
2343 + if (!TARGET_HARD_FLOAT)
2346 + if (IS_INTERRUPT (func_type))
2349 + /* Interrupt functions must not corrupt any registers, even call
2350 + clobbered ones. If this is a leaf function we can just examine the
2351 + registers used by the RTL, but otherwise we have to assume that
2352 + whatever function is called might clobber anything, and so we have
2353 + to save all the call-clobbered registers as well. */
2355 + save_all_call_used_regs = !current_function_is_leaf;
2358 + /* All used registers used must be saved */
2359 + for (reg = 0; reg <= max_reg; reg++)
2360 + if (regs_ever_live[INTERNAL_FP_REGNUM (reg)]
2361 + || (save_all_call_used_regs
2362 + && call_used_regs[INTERNAL_FP_REGNUM (reg)]))
2363 + save_reg_mask |= (1 << reg);
2365 + return save_reg_mask;
2368 +/*Compute mask of registers which needs saving upon function entry */
2369 +static unsigned long
2370 +avr32_compute_save_reg_mask (int push)
2372 + unsigned long func_type;
2373 + unsigned int save_reg_mask = 0;
2376 + func_type = avr32_current_func_type ();
2378 + if (IS_INTERRUPT (func_type))
2380 + unsigned int max_reg = 12;
2383 + /* Get the banking scheme for the interrupt */
2384 + switch (func_type)
2386 + case AVR32_FT_ISR_FULL:
2389 + case AVR32_FT_ISR_HALF:
2392 + case AVR32_FT_ISR_NONE:
2397 + /* Interrupt functions must not corrupt any registers, even call
2398 + clobbered ones. If this is a leaf function we can just examine the
2399 + registers used by the RTL, but otherwise we have to assume that
2400 + whatever function is called might clobber anything, and so we have
2401 + to save all the call-clobbered registers as well. */
2403 + /* Need not push the registers r8-r12 for AVR32A architectures, as this
2404 + is automatially done in hardware. We also do not have any shadow
2406 + if (TARGET_UARCH_AVR32A)
2409 + func_type = AVR32_FT_ISR_NONE;
2412 + /* All registers which are used and is not shadowed must be saved */
2413 + for (reg = 0; reg <= max_reg; reg++)
2414 + if (regs_ever_live[INTERNAL_REGNUM (reg)]
2415 + || (!current_function_is_leaf
2416 + && call_used_regs[INTERNAL_REGNUM (reg)]))
2417 + save_reg_mask |= (1 << reg);
2420 + if ((regs_ever_live[LR_REGNUM]
2421 + || !current_function_is_leaf || frame_pointer_needed)
2422 + /* Only non-shadowed register models */
2423 + && (func_type == AVR32_FT_ISR_NONE))
2424 + save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM));
2426 + /* Make sure that the GOT register is pushed. */
2427 + if (max_reg >= ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)
2428 + && current_function_uses_pic_offset_table)
2429 + save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM));
2434 + int use_pushm = optimize_size;
2436 + /* In the normal case we only need to save those registers which are
2437 + call saved and which are used by this function. */
2438 + for (reg = 0; reg <= 7; reg++)
2439 + if (regs_ever_live[INTERNAL_REGNUM (reg)]
2440 + && !call_used_regs[INTERNAL_REGNUM (reg)])
2441 + save_reg_mask |= (1 << reg);
2443 + /* Make sure that the GOT register is pushed. */
2444 + if (current_function_uses_pic_offset_table)
2445 + save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM));
2448 + /* If we optimize for size and do not have anonymous arguments: use
2449 + popm/pushm always */
2452 + if ((save_reg_mask & (1 << 0))
2453 + || (save_reg_mask & (1 << 1))
2454 + || (save_reg_mask & (1 << 2)) || (save_reg_mask & (1 << 3)))
2455 + save_reg_mask |= 0xf;
2457 + if ((save_reg_mask & (1 << 4))
2458 + || (save_reg_mask & (1 << 5))
2459 + || (save_reg_mask & (1 << 6)) || (save_reg_mask & (1 << 7)))
2460 + save_reg_mask |= 0xf0;
2462 + if ((save_reg_mask & (1 << 8)) || (save_reg_mask & (1 << 9)))
2463 + save_reg_mask |= 0x300;
2468 + if ((regs_ever_live[LR_REGNUM]
2469 + || !current_function_is_leaf
2472 + && !current_function_calls_eh_return) || frame_pointer_needed))
2475 + /* Never pop LR into PC for functions which
2476 + calls __builtin_eh_return, since we need to
2477 + fix the SP after the restoring of the registers
2478 + and before returning. */
2479 + || current_function_calls_eh_return)
2482 + save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM));
2487 + save_reg_mask |= (1 << ASM_REGNUM (PC_REGNUM));
2493 + /* Save registers so the exception handler can modify them. */
2494 + if (current_function_calls_eh_return)
2500 + reg = EH_RETURN_DATA_REGNO (i);
2501 + if (reg == INVALID_REGNUM)
2503 + save_reg_mask |= 1 << ASM_REGNUM (reg);
2507 + return save_reg_mask;
2510 +/*Compute total size in bytes of all saved registers */
2512 +avr32_get_reg_mask_size (int reg_mask)
2517 + for (reg = 0; reg <= 15; reg++)
2518 + if (reg_mask & (1 << reg))
2524 +/*Get a register from one of the registers which are saved onto the stack
2525 + upon function entry */
2528 +avr32_get_saved_reg (int save_reg_mask)
2532 + /* Find the first register which is saved in the saved_reg_mask */
2533 + for (reg = 0; reg <= 15; reg++)
2534 + if (save_reg_mask & (1 << reg))
2540 +/* Return 1 if it is possible to return using a single instruction. */
2542 +avr32_use_return_insn (int iscond)
2544 + unsigned int func_type = avr32_current_func_type ();
2545 + unsigned long saved_int_regs;
2546 + unsigned long saved_fp_regs;
2548 + /* Never use a return instruction before reload has run. */
2549 + if (!reload_completed)
2552 + /* Must adjust the stack for vararg functions. */
2553 + if (current_function_args_info.uses_anonymous_args)
2556 + /* If there a stack adjstment. */
2557 + if (get_frame_size ())
2560 + saved_int_regs = avr32_compute_save_reg_mask (TRUE);
2561 + saved_fp_regs = avr32_compute_save_fp_reg_mask ();
2563 + /* Functions which have saved fp-regs on the stack can not be performed in
2564 + one instruction */
2565 + if (saved_fp_regs)
2568 + /* Conditional returns can not be performed in one instruction if we need
2569 + to restore registers from the stack */
2570 + if (iscond && saved_int_regs)
2573 + /* Conditional return can not be used for interrupt handlers. */
2574 + if (iscond && IS_INTERRUPT (func_type))
2577 + /* For interrupt handlers which needs to pop registers */
2578 + if (saved_int_regs && IS_INTERRUPT (func_type))
2582 + /* If there are saved registers but the LR isn't saved, then we need two
2583 + instructions for the return. */
2584 + if (saved_int_regs && !(saved_int_regs & (1 << ASM_REGNUM (LR_REGNUM))))
2592 +/*Generate some function prologue info in the assembly file*/
2595 +avr32_target_asm_function_prologue (FILE * f, HOST_WIDE_INT frame_size)
2597 + if (IS_NAKED (avr32_current_func_type ()))
2599 + "\t# Function is naked: Prologue and epilogue provided by programmer\n");
2601 + if (IS_INTERRUPT (avr32_current_func_type ()))
2603 + switch (avr32_current_func_type ())
2605 + case AVR32_FT_ISR_FULL:
2607 + "\t# Interrupt Function: Fully shadowed register file\n");
2609 + case AVR32_FT_ISR_HALF:
2611 + "\t# Interrupt Function: Half shadowed register file\n");
2614 + case AVR32_FT_ISR_NONE:
2615 + fprintf (f, "\t# Interrupt Function: No shadowed register file\n");
2621 + fprintf (f, "\t# args = %i, frame = %li, pretend = %i\n",
2622 + current_function_args_size, frame_size,
2623 + current_function_pretend_args_size);
2625 + fprintf (f, "\t# frame_needed = %i, leaf_function = %i\n",
2626 + frame_pointer_needed, current_function_is_leaf);
2628 + fprintf (f, "\t# uses_anonymous_args = %i\n",
2629 + current_function_args_info.uses_anonymous_args);
2630 + if (current_function_calls_eh_return)
2631 + fprintf (f, "\t# Calls __builtin_eh_return.\n");
2636 +/* Generate and emit an insn that we will recognize as a pushm or stm.
2637 + Unfortunately, since this insn does not reflect very well the actual
2638 + semantics of the operation, we need to annotate the insn for the benefit
2639 + of DWARF2 frame unwind information. */
2641 +int avr32_convert_to_reglist16 (int reglist8_vect);
2644 +emit_multi_reg_push (int reglist, int usePUSHM)
2656 + insn = emit_insn (gen_pushm (gen_rtx_CONST_INT (SImode, reglist)));
2657 + reglist = avr32_convert_to_reglist16 (reglist);
2661 + insn = emit_insn (gen_stm (stack_pointer_rtx,
2662 + gen_rtx_CONST_INT (SImode, reglist),
2663 + gen_rtx_CONST_INT (SImode, 1)));
2666 + nr_regs = avr32_get_reg_mask_size (reglist) / 4;
2667 + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1));
2669 + for (i = 15; i >= 0; i--)
2671 + if (reglist & (1 << i))
2673 + reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (i));
2674 + tmp = gen_rtx_SET (VOIDmode,
2675 + gen_rtx_MEM (SImode,
2676 + plus_constant (stack_pointer_rtx,
2677 + 4 * index)), reg);
2678 + RTX_FRAME_RELATED_P (tmp) = 1;
2679 + XVECEXP (dwarf, 0, 1 + index++) = tmp;
2683 + tmp = gen_rtx_SET (SImode,
2684 + stack_pointer_rtx,
2685 + gen_rtx_PLUS (SImode,
2686 + stack_pointer_rtx,
2687 + GEN_INT (-4 * nr_regs)));
2688 + RTX_FRAME_RELATED_P (tmp) = 1;
2689 + XVECEXP (dwarf, 0, 0) = tmp;
2690 + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
2691 + REG_NOTES (insn));
2697 +emit_multi_fp_reg_push (int reglist)
2707 + insn = emit_insn (gen_stm_fp (stack_pointer_rtx,
2708 + gen_rtx_CONST_INT (SImode, reglist),
2709 + gen_rtx_CONST_INT (SImode, 1)));
2711 + nr_regs = avr32_get_reg_mask_size (reglist) / 4;
2712 + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1));
2714 + for (i = 15; i >= 0; i--)
2716 + if (reglist & (1 << i))
2718 + reg = gen_rtx_REG (SImode, INTERNAL_FP_REGNUM (i));
2719 + tmp = gen_rtx_SET (VOIDmode,
2720 + gen_rtx_MEM (SImode,
2721 + plus_constant (stack_pointer_rtx,
2722 + 4 * index)), reg);
2723 + RTX_FRAME_RELATED_P (tmp) = 1;
2724 + XVECEXP (dwarf, 0, 1 + index++) = tmp;
2728 + tmp = gen_rtx_SET (SImode,
2729 + stack_pointer_rtx,
2730 + gen_rtx_PLUS (SImode,
2731 + stack_pointer_rtx,
2732 + GEN_INT (-4 * nr_regs)));
2733 + RTX_FRAME_RELATED_P (tmp) = 1;
2734 + XVECEXP (dwarf, 0, 0) = tmp;
2735 + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf,
2736 + REG_NOTES (insn));
2741 +avr32_gen_load_multiple (rtx * regs, int count, rtx from,
2742 + int write_back, int in_struct_p, int scalar_p)
2749 + gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + (write_back ? 1 : 0)));
2753 + XVECEXP (result, 0, 0)
2754 + = gen_rtx_SET (GET_MODE (from), from,
2755 + plus_constant (from, count * 4));
2761 + for (j = 0; i < count; i++, j++)
2764 + rtx mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4));
2765 + MEM_IN_STRUCT_P (mem) = in_struct_p;
2766 + MEM_SCALAR_P (mem) = scalar_p;
2767 + unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, mem), UNSPEC_LDM);
2768 + XVECEXP (result, 0, i) = gen_rtx_SET (VOIDmode, regs[j], unspec);
2776 +avr32_gen_store_multiple (rtx * regs, int count, rtx to,
2777 + int in_struct_p, int scalar_p)
2782 + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
2784 + for (j = 0; i < count; i++, j++)
2786 + rtx mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4));
2787 + MEM_IN_STRUCT_P (mem) = in_struct_p;
2788 + MEM_SCALAR_P (mem) = scalar_p;
2789 + XVECEXP (result, 0, i)
2790 + = gen_rtx_SET (VOIDmode, mem,
2791 + gen_rtx_UNSPEC (VOIDmode,
2792 + gen_rtvec (1, regs[j]),
2793 + UNSPEC_STORE_MULTIPLE));
2800 +/* Move a block of memory if it is word aligned or we support unaligned
2801 + word memory accesses. The size must be maximum 64 bytes. */
2804 +avr32_gen_movmemsi (rtx * operands)
2806 + HOST_WIDE_INT bytes_to_go;
2808 + rtx st_src, st_dst;
2809 + int src_offset = 0, dst_offset = 0;
2811 + int dst_in_struct_p, src_in_struct_p;
2812 + int dst_scalar_p, src_scalar_p;
2815 + if (GET_CODE (operands[2]) != CONST_INT
2816 + || GET_CODE (operands[3]) != CONST_INT
2817 + || INTVAL (operands[2]) > 64
2818 + || ((INTVAL (operands[3]) & 3) && !TARGET_UNALIGNED_WORD))
2821 + unaligned = (INTVAL (operands[3]) & 3) != 0;
2825 + st_dst = XEXP (operands[0], 0);
2826 + st_src = XEXP (operands[1], 0);
2828 + dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]);
2829 + dst_scalar_p = MEM_SCALAR_P (operands[0]);
2830 + src_in_struct_p = MEM_IN_STRUCT_P (operands[1]);
2831 + src_scalar_p = MEM_SCALAR_P (operands[1]);
2833 + dst = copy_to_mode_reg (SImode, st_dst);
2834 + src = copy_to_mode_reg (SImode, st_src);
2836 + bytes_to_go = INTVAL (operands[2]);
2838 + while (bytes_to_go)
2840 + enum machine_mode move_mode;
2841 + /* (Seems to be a problem with reloads for the movti pattern so this is
2842 + disabled until that problem is resolved)
2843 + UPDATE: Problem seems to be solved now.... */
2844 + if (bytes_to_go >= GET_MODE_SIZE (TImode) && !unaligned
2845 + /* Do not emit ldm/stm for UC3 as ld.d/st.d is more optimal. */
2846 + && !TARGET_ARCH_UC)
2847 + move_mode = TImode;
2848 + else if ((bytes_to_go >= GET_MODE_SIZE (DImode)) && !unaligned)
2849 + move_mode = DImode;
2850 + else if (bytes_to_go >= GET_MODE_SIZE (SImode))
2851 + move_mode = SImode;
2853 + move_mode = QImode;
2857 + rtx dst_mem = gen_rtx_MEM (move_mode,
2858 + gen_rtx_PLUS (SImode, dst,
2859 + GEN_INT (dst_offset)));
2860 + dst_offset += GET_MODE_SIZE (move_mode);
2861 + if ( 0 /* This causes an error in GCC. Think there is
2862 + something wrong in the gcse pass which causes REQ_EQUIV notes
2863 + to be wrong so disabling it for now. */
2864 + && move_mode == TImode
2865 + && INTVAL (operands[2]) > GET_MODE_SIZE (TImode) )
2867 + src_mem = gen_rtx_MEM (move_mode,
2868 + gen_rtx_POST_INC (SImode, src));
2872 + src_mem = gen_rtx_MEM (move_mode,
2873 + gen_rtx_PLUS (SImode, src,
2874 + GEN_INT (src_offset)));
2875 + src_offset += GET_MODE_SIZE (move_mode);
2878 + bytes_to_go -= GET_MODE_SIZE (move_mode);
2880 + MEM_IN_STRUCT_P (dst_mem) = dst_in_struct_p;
2881 + MEM_SCALAR_P (dst_mem) = dst_scalar_p;
2883 + MEM_IN_STRUCT_P (src_mem) = src_in_struct_p;
2884 + MEM_SCALAR_P (src_mem) = src_scalar_p;
2885 + emit_move_insn (dst_mem, src_mem);
2895 +/*Expand the prologue instruction*/
2897 +avr32_expand_prologue (void)
2900 + unsigned long saved_reg_mask, saved_fp_reg_mask;
2903 + /* Naked functions does not have a prologue */
2904 + if (IS_NAKED (avr32_current_func_type ()))
2907 + saved_reg_mask = avr32_compute_save_reg_mask (TRUE);
2909 + if (saved_reg_mask)
2911 + /* Must push used registers */
2913 + /* Should we use POPM or LDM? */
2914 + int usePUSHM = TRUE;
2916 + if (((saved_reg_mask & (1 << 0)) ||
2917 + (saved_reg_mask & (1 << 1)) ||
2918 + (saved_reg_mask & (1 << 2)) || (saved_reg_mask & (1 << 3))))
2920 + /* One of R0-R3 should at least be pushed */
2921 + if (((saved_reg_mask & (1 << 0)) &&
2922 + (saved_reg_mask & (1 << 1)) &&
2923 + (saved_reg_mask & (1 << 2)) && (saved_reg_mask & (1 << 3))))
2925 + /* All should be pushed */
2934 + if (((saved_reg_mask & (1 << 4)) ||
2935 + (saved_reg_mask & (1 << 5)) ||
2936 + (saved_reg_mask & (1 << 6)) || (saved_reg_mask & (1 << 7))))
2938 + /* One of R4-R7 should at least be pushed */
2939 + if (((saved_reg_mask & (1 << 4)) &&
2940 + (saved_reg_mask & (1 << 5)) &&
2941 + (saved_reg_mask & (1 << 6)) && (saved_reg_mask & (1 << 7))))
2944 + /* All should be pushed */
2953 + if (((saved_reg_mask & (1 << 8)) || (saved_reg_mask & (1 << 9))))
2955 + /* One of R8-R9 should at least be pushed */
2956 + if (((saved_reg_mask & (1 << 8)) && (saved_reg_mask & (1 << 9))))
2959 + /* All should be pushed */
2968 + if (saved_reg_mask & (1 << 10))
2971 + if (saved_reg_mask & (1 << 11))
2974 + if (saved_reg_mask & (1 << 12))
2977 + if (saved_reg_mask & (1 << ASM_REGNUM (LR_REGNUM)))
2985 + insn = emit_multi_reg_push (reglist8, TRUE);
2989 + insn = emit_multi_reg_push (saved_reg_mask, FALSE);
2991 + RTX_FRAME_RELATED_P (insn) = 1;
2993 + /* Prevent this instruction from being scheduled after any other
2995 + emit_insn (gen_blockage ());
2998 + saved_fp_reg_mask = avr32_compute_save_fp_reg_mask ();
2999 + if (saved_fp_reg_mask)
3001 + insn = emit_multi_fp_reg_push (saved_fp_reg_mask);
3002 + RTX_FRAME_RELATED_P (insn) = 1;
3004 + /* Prevent this instruction from being scheduled after any other
3006 + emit_insn (gen_blockage ());
3009 + /* Set frame pointer */
3010 + if (frame_pointer_needed)
3012 + insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3013 + RTX_FRAME_RELATED_P (insn) = 1;
3016 + if (get_frame_size () > 0)
3018 + if (avr32_const_ok_for_constraint_p (get_frame_size (), 'K', "Ks21"))
3020 + insn = emit_insn (gen_rtx_SET (SImode,
3021 + stack_pointer_rtx,
3022 + gen_rtx_PLUS (SImode,
3023 + stack_pointer_rtx,
3028 + RTX_FRAME_RELATED_P (insn) = 1;
3032 + /* Immediate is larger than k21 We must either check if we can use
3033 + one of the pushed reegisters as temporary storage or we must
3034 + make us a temp register by pushing a register to the stack. */
3035 + rtx temp_reg, const_pool_entry, insn;
3036 + if (saved_reg_mask)
3039 + gen_rtx_REG (SImode,
3040 + INTERNAL_REGNUM (avr32_get_saved_reg
3041 + (saved_reg_mask)));
3045 + temp_reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (7));
3046 + emit_move_insn (gen_rtx_MEM
3048 + gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)),
3052 + const_pool_entry =
3053 + force_const_mem (SImode,
3054 + gen_rtx_CONST_INT (SImode, get_frame_size ()));
3055 + emit_move_insn (temp_reg, const_pool_entry);
3057 + insn = emit_insn (gen_rtx_SET (SImode,
3058 + stack_pointer_rtx,
3059 + gen_rtx_MINUS (SImode,
3060 + stack_pointer_rtx,
3063 + dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx,
3064 + gen_rtx_PLUS (SImode, stack_pointer_rtx,
3065 + GEN_INT (-get_frame_size ())));
3066 + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3067 + dwarf, REG_NOTES (insn));
3068 + RTX_FRAME_RELATED_P (insn) = 1;
3070 + if (!saved_reg_mask)
3073 + emit_move_insn (temp_reg,
3074 + gen_rtx_MEM (SImode,
3075 + gen_rtx_POST_INC (SImode,
3081 + /* Mark the temp register as dead */
3082 + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, temp_reg,
3083 + REG_NOTES (insn));
3088 + /* Prevent the the stack adjustment to be scheduled after any
3089 + instructions using the frame pointer. */
3090 + emit_insn (gen_blockage ());
3096 + avr32_load_pic_register ();
3098 + /* gcc does not know that load or call instructions might use the pic
3099 + register so it might schedule these instructions before the loading
3100 + of the pic register. To avoid this emit a barrier for now. TODO!
3101 + Find out a better way to let gcc know which instructions might use
3102 + the pic register. */
3103 + emit_insn (gen_blockage ());
3109 +avr32_set_return_address (rtx source, rtx scratch)
3112 + unsigned long saved_regs;
3114 + saved_regs = avr32_compute_save_reg_mask (TRUE);
3116 + if (!(saved_regs & (1 << ASM_REGNUM (LR_REGNUM))))
3117 + emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source);
3120 + if (frame_pointer_needed)
3121 + addr = gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM);
3123 + if (avr32_const_ok_for_constraint_p (get_frame_size (), 'K', "Ks16"))
3125 + addr = plus_constant (stack_pointer_rtx, get_frame_size ());
3129 + emit_insn (gen_movsi (scratch, GEN_INT (get_frame_size ())));
3132 + emit_move_insn (gen_rtx_MEM (Pmode, addr), source);
3138 +/* Return the length of INSN. LENGTH is the initial length computed by
3139 + attributes in the machine-description file. */
3142 +avr32_adjust_insn_length (rtx insn ATTRIBUTE_UNUSED,
3143 + int length ATTRIBUTE_UNUSED)
3149 +avr32_output_return_instruction (int single_ret_inst ATTRIBUTE_UNUSED,
3150 + int iscond ATTRIBUTE_UNUSED,
3151 + rtx cond ATTRIBUTE_UNUSED, rtx r12_imm)
3154 + unsigned long saved_reg_mask, saved_fp_reg_mask;
3155 + int insert_ret = TRUE;
3157 + int stack_adjustment = get_frame_size ();
3158 + unsigned int func_type = avr32_current_func_type ();
3159 + FILE *f = asm_out_file;
3161 + /* Naked functions does not have an epilogue */
3162 + if (IS_NAKED (func_type))
3165 + saved_fp_reg_mask = avr32_compute_save_fp_reg_mask ();
3167 + saved_reg_mask = avr32_compute_save_reg_mask (FALSE);
3169 + /* Reset frame pointer */
3170 + if (stack_adjustment > 0)
3172 + if (avr32_const_ok_for_constraint_p (stack_adjustment, 'I', "Is21"))
3174 + fprintf (f, "\tsub\tsp, %i # Reset Frame Pointer\n",
3175 + -stack_adjustment);
3179 + /* TODO! Is it safe to use r8 as scratch?? */
3180 + fprintf (f, "\tmov\tr8, lo(%i) # Reset Frame Pointer\n",
3181 + -stack_adjustment);
3182 + fprintf (f, "\torh\tr8, hi(%i) # Reset Frame Pointer\n",
3183 + -stack_adjustment);
3184 + fprintf (f, "\tadd\tsp, r8 # Reset Frame Pointer\n");
3188 + if (saved_fp_reg_mask)
3190 + char reglist[64]; /* 64 bytes should be enough... */
3191 + avr32_make_fp_reglist_w (saved_fp_reg_mask, (char *) reglist);
3192 + fprintf (f, "\tldcm.w\tcp0, sp++, %s\n", reglist);
3193 + if (saved_fp_reg_mask & ~0xff)
3195 + saved_fp_reg_mask &= ~0xff;
3196 + avr32_make_fp_reglist_d (saved_fp_reg_mask, (char *) reglist);
3197 + fprintf (f, "\tldcm.d\tcp0, sp++, %s\n", reglist);
3201 + if (saved_reg_mask)
3203 + /* Must pop used registers */
3205 + /* Should we use POPM or LDM? */
3206 + int usePOPM = TRUE;
3207 + if (((saved_reg_mask & (1 << 0)) ||
3208 + (saved_reg_mask & (1 << 1)) ||
3209 + (saved_reg_mask & (1 << 2)) || (saved_reg_mask & (1 << 3))))
3211 + /* One of R0-R3 should at least be popped */
3212 + if (((saved_reg_mask & (1 << 0)) &&
3213 + (saved_reg_mask & (1 << 1)) &&
3214 + (saved_reg_mask & (1 << 2)) && (saved_reg_mask & (1 << 3))))
3216 + /* All should be popped */
3225 + if (((saved_reg_mask & (1 << 4)) ||
3226 + (saved_reg_mask & (1 << 5)) ||
3227 + (saved_reg_mask & (1 << 6)) || (saved_reg_mask & (1 << 7))))
3229 + /* One of R0-R3 should at least be popped */
3230 + if (((saved_reg_mask & (1 << 4)) &&
3231 + (saved_reg_mask & (1 << 5)) &&
3232 + (saved_reg_mask & (1 << 6)) && (saved_reg_mask & (1 << 7))))
3235 + /* All should be popped */
3244 + if (((saved_reg_mask & (1 << 8)) || (saved_reg_mask & (1 << 9))))
3246 + /* One of R8-R9 should at least be pushed */
3247 + if (((saved_reg_mask & (1 << 8)) && (saved_reg_mask & (1 << 9))))
3250 + /* All should be pushed */
3259 + if (saved_reg_mask & (1 << 10))
3262 + if (saved_reg_mask & (1 << 11))
3265 + if (saved_reg_mask & (1 << 12))
3268 + if (saved_reg_mask & (1 << ASM_REGNUM (LR_REGNUM)))
3272 + if (saved_reg_mask & (1 << ASM_REGNUM (PC_REGNUM)))
3273 + /* Pop LR into PC. */
3278 + char reglist[64]; /* 64 bytes should be enough... */
3279 + avr32_make_reglist8 (reglist8, (char *) reglist);
3281 + if (reglist8 & 0x80)
3282 + /* This instruction is also a return */
3283 + insert_ret = FALSE;
3285 + if (r12_imm && !insert_ret)
3286 + fprintf (f, "\tpopm\t%s, r12=%li\n", reglist, INTVAL (r12_imm));
3288 + fprintf (f, "\tpopm\t%s\n", reglist);
3293 + char reglist[64]; /* 64 bytes should be enough... */
3294 + avr32_make_reglist16 (saved_reg_mask, (char *) reglist);
3295 + if (saved_reg_mask & (1 << ASM_REGNUM (PC_REGNUM)))
3296 + /* This instruction is also a return */
3297 + insert_ret = FALSE;
3299 + if (r12_imm && !insert_ret)
3300 + fprintf (f, "\tldm\tsp++, %s, r12=%li\n", reglist,
3301 + INTVAL (r12_imm));
3303 + fprintf (f, "\tldm\tsp++, %s\n", reglist);
3309 + /* Stack adjustment for exception handler. */
3310 + if (current_function_calls_eh_return)
3311 + fprintf (f, "\tadd\tsp, r%d\n", ASM_REGNUM (EH_RETURN_STACKADJ_REGNO));
3314 + if (IS_INTERRUPT (func_type))
3316 + fprintf (f, "\trete\n");
3318 + else if (insert_ret)
3321 + fprintf (f, "\tretal\t%li\n", INTVAL (r12_imm));
3323 + fprintf (f, "\tretal\tr12\n");
3327 +/* Function for converting a fp-register mask to a
3328 + reglistCPD8 register list string. */
3330 +avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string)
3334 + /* Make sure reglist_string is empty */
3335 + reglist_string[0] = '\0';
3337 + for (i = 0; i < NUM_FP_REGS; i += 2)
3339 + if (reglist_mask & (1 << i))
3341 + strlen (reglist_string) ?
3342 + sprintf (reglist_string, "%s, %s-%s", reglist_string,
3343 + reg_names[INTERNAL_FP_REGNUM (i)],
3344 + reg_names[INTERNAL_FP_REGNUM (i + 1)]) :
3345 + sprintf (reglist_string, "%s-%s",
3346 + reg_names[INTERNAL_FP_REGNUM (i)],
3347 + reg_names[INTERNAL_FP_REGNUM (i + 1)]);
3352 +/* Function for converting a fp-register mask to a
3353 + reglistCP8 register list string. */
3355 +avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string)
3359 + /* Make sure reglist_string is empty */
3360 + reglist_string[0] = '\0';
3362 + for (i = 0; i < NUM_FP_REGS; ++i)
3364 + if (reglist_mask & (1 << i))
3366 + strlen (reglist_string) ?
3367 + sprintf (reglist_string, "%s, %s", reglist_string,
3368 + reg_names[INTERNAL_FP_REGNUM (i)]) :
3369 + sprintf (reglist_string, "%s", reg_names[INTERNAL_FP_REGNUM (i)]);
3375 +avr32_make_reglist16 (int reglist16_vect, char *reglist16_string)
3379 + /* Make sure reglist16_string is empty */
3380 + reglist16_string[0] = '\0';
3382 + for (i = 0; i < 16; ++i)
3384 + if (reglist16_vect & (1 << i))
3386 + strlen (reglist16_string) ?
3387 + sprintf (reglist16_string, "%s, %s", reglist16_string,
3388 + reg_names[INTERNAL_REGNUM (i)]) :
3389 + sprintf (reglist16_string, "%s", reg_names[INTERNAL_REGNUM (i)]);
3395 +avr32_convert_to_reglist16 (int reglist8_vect)
3397 + int reglist16_vect = 0;
3398 + if (reglist8_vect & 0x1)
3399 + reglist16_vect |= 0xF;
3400 + if (reglist8_vect & 0x2)
3401 + reglist16_vect |= 0xF0;
3402 + if (reglist8_vect & 0x4)
3403 + reglist16_vect |= 0x300;
3404 + if (reglist8_vect & 0x8)
3405 + reglist16_vect |= 0x400;
3406 + if (reglist8_vect & 0x10)
3407 + reglist16_vect |= 0x800;
3408 + if (reglist8_vect & 0x20)
3409 + reglist16_vect |= 0x1000;
3410 + if (reglist8_vect & 0x40)
3411 + reglist16_vect |= 0x4000;
3412 + if (reglist8_vect & 0x80)
3413 + reglist16_vect |= 0x8000;
3415 + return reglist16_vect;
3419 +avr32_make_reglist8 (int reglist8_vect, char *reglist8_string)
3421 + /* Make sure reglist8_string is empty */
3422 + reglist8_string[0] = '\0';
3424 + if (reglist8_vect & 0x1)
3425 + sprintf (reglist8_string, "r0-r3");
3426 + if (reglist8_vect & 0x2)
3427 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r4-r7",
3428 + reglist8_string) :
3429 + sprintf (reglist8_string, "r4-r7");
3430 + if (reglist8_vect & 0x4)
3431 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r8-r9",
3432 + reglist8_string) :
3433 + sprintf (reglist8_string, "r8-r9");
3434 + if (reglist8_vect & 0x8)
3435 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r10",
3436 + reglist8_string) :
3437 + sprintf (reglist8_string, "r10");
3438 + if (reglist8_vect & 0x10)
3439 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r11",
3440 + reglist8_string) :
3441 + sprintf (reglist8_string, "r11");
3442 + if (reglist8_vect & 0x20)
3443 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r12",
3444 + reglist8_string) :
3445 + sprintf (reglist8_string, "r12");
3446 + if (reglist8_vect & 0x40)
3447 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, lr",
3448 + reglist8_string) :
3449 + sprintf (reglist8_string, "lr");
3450 + if (reglist8_vect & 0x80)
3451 + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, pc",
3452 + reglist8_string) :
3453 + sprintf (reglist8_string, "pc");
3457 +avr32_eh_return_data_regno (int n)
3459 + if (n >= 0 && n <= 3)
3462 + return INVALID_REGNUM;
3465 +/* Compute the distance from register FROM to register TO.
3466 + These can be the arg pointer, the frame pointer or
3467 + the stack pointer.
3468 + Typical stack layout looks like this:
3470 + old stack pointer -> | |
3473 + | | saved arguments for
3474 + | | vararg functions
3475 + arg_pointer -> | | /
3485 + stack ptr --> | | /
3493 + For a given funciton some or all of these stack compomnents
3494 + may not be needed, giving rise to the possibility of
3495 + eliminating some of the registers.
3497 + The values returned by this function must reflect the behaviour
3498 + of avr32_expand_prologue() and avr32_compute_save_reg_mask().
3500 + The sign of the number returned reflects the direction of stack
3501 + growth, so the values are positive for all eliminations except
3502 + from the soft frame pointer to the hard frame pointer. */
3506 +avr32_initial_elimination_offset (int from, int to)
3509 + int call_saved_regs = 0;
3510 + unsigned long saved_reg_mask, saved_fp_reg_mask;
3511 + unsigned int local_vars = get_frame_size ();
3513 + saved_reg_mask = avr32_compute_save_reg_mask (TRUE);
3514 + saved_fp_reg_mask = avr32_compute_save_fp_reg_mask ();
3516 + for (i = 0; i < 16; ++i)
3518 + if (saved_reg_mask & (1 << i))
3519 + call_saved_regs += 4;
3522 + for (i = 0; i < NUM_FP_REGS; ++i)
3524 + if (saved_fp_reg_mask & (1 << i))
3525 + call_saved_regs += 4;
3530 + case ARG_POINTER_REGNUM:
3533 + case STACK_POINTER_REGNUM:
3534 + return call_saved_regs + local_vars;
3535 + case FRAME_POINTER_REGNUM:
3536 + return call_saved_regs;
3540 + case FRAME_POINTER_REGNUM:
3543 + case STACK_POINTER_REGNUM:
3544 + return local_vars;
3555 + Returns a rtx used when passing the next argument to a function.
3556 + avr32_init_cumulative_args() and avr32_function_arg_advance() sets witch
3560 +avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode,
3561 + tree type, int named)
3565 + HOST_WIDE_INT arg_size, arg_rsize;
3568 + arg_size = int_size_in_bytes (type);
3572 + arg_size = GET_MODE_SIZE (mode);
3574 + arg_rsize = PUSH_ROUNDING (arg_size);
3577 + The last time this macro is called, it is called with mode == VOIDmode,
3578 + and its result is passed to the call or call_value pattern as operands 2
3579 + and 3 respectively. */
3580 + if (mode == VOIDmode)
3582 + return gen_rtx_CONST_INT (SImode, 22); /* ToDo: fixme. */
3585 + if ((*targetm.calls.must_pass_in_stack) (mode, type) || !named)
3590 + if (arg_rsize == 8)
3592 + /* use r11:r10 or r9:r8. */
3593 + if (!(GET_USED_INDEX (cum, 1) || GET_USED_INDEX (cum, 2)))
3595 + else if (!(GET_USED_INDEX (cum, 3) || GET_USED_INDEX (cum, 4)))
3600 + else if (arg_rsize == 4)
3601 + { /* Use first available register */
3603 + while (index <= LAST_CUM_REG_INDEX && GET_USED_INDEX (cum, index))
3605 + if (index > LAST_CUM_REG_INDEX)
3609 + SET_REG_INDEX (cum, index);
3611 + if (GET_REG_INDEX (cum) >= 0)
3612 + return gen_rtx_REG (mode,
3613 + avr32_function_arg_reglist[GET_REG_INDEX (cum)]);
3619 + Set the register used for passing the first argument to a function.
3622 +avr32_init_cumulative_args (CUMULATIVE_ARGS * cum,
3623 + tree fntype ATTRIBUTE_UNUSED,
3624 + rtx libname ATTRIBUTE_UNUSED,
3625 + tree fndecl ATTRIBUTE_UNUSED)
3627 + /* Set all registers as unused. */
3628 + SET_INDEXES_UNUSED (cum);
3630 + /* Reset uses_anonymous_args */
3631 + cum->uses_anonymous_args = 0;
3633 + /* Reset size of stack pushed arguments */
3634 + cum->stack_pushed_args_size = 0;
3638 + Set register used for passing the next argument to a function. Only the
3639 + Scratch Registers are used.
3644 + 13 r13 _SP_________
3645 + FIRST_CUM_REG 12 r12 _||_
3647 + 11 r10 _||_ Scratch Registers
3649 + LAST_SCRATCH_REG 9 r8 _\/_________
3661 +avr32_function_arg_advance (CUMULATIVE_ARGS * cum, enum machine_mode mode,
3662 + tree type, int named ATTRIBUTE_UNUSED)
3664 + HOST_WIDE_INT arg_size, arg_rsize;
3668 + arg_size = int_size_in_bytes (type);
3672 + arg_size = GET_MODE_SIZE (mode);
3674 + arg_rsize = PUSH_ROUNDING (arg_size);
3676 + /* It the argument had to be passed in stack, no register is used. */
3677 + if ((*targetm.calls.must_pass_in_stack) (mode, type))
3679 + cum->stack_pushed_args_size += PUSH_ROUNDING (int_size_in_bytes (type));
3683 + /* Mark the used registers as "used". */
3684 + if (GET_REG_INDEX (cum) >= 0)
3686 + SET_USED_INDEX (cum, GET_REG_INDEX (cum));
3687 + if (arg_rsize == 8)
3689 + SET_USED_INDEX (cum, (GET_REG_INDEX (cum) + 1));
3694 + /* Had to use stack */
3695 + cum->stack_pushed_args_size += arg_rsize;
3700 + Defines witch direction to go to find the next register to use if the
3701 + argument is larger then one register or for arguments shorter than an
3702 + int which is not promoted, such as the last part of structures with
3703 + size not a multiple of 4. */
3705 +avr32_function_arg_padding (enum machine_mode mode ATTRIBUTE_UNUSED,
3708 + /* Pad upward for all aggregates except byte and halfword sized aggregates
3709 + which can be passed in registers. */
3711 + && AGGREGATE_TYPE_P (type)
3712 + && (int_size_in_bytes (type) != 1)
3713 + && !((int_size_in_bytes (type) == 2)
3714 + && TYPE_ALIGN_UNIT (type) >= 2)
3715 + && (int_size_in_bytes (type) & 0x3))
3724 + Return a rtx used for the return value from a function call.
3727 +avr32_function_value (tree type, tree func, bool outgoing ATTRIBUTE_UNUSED)
3729 + if (avr32_return_in_memory (type, func))
3732 + if (int_size_in_bytes (type) <= 4)
3733 + if (avr32_return_in_msb (type))
3734 + /* Aggregates of size less than a word which does align the data in the
3735 + MSB must use SImode for r12. */
3736 + return gen_rtx_REG (SImode, RET_REGISTER);
3738 + return gen_rtx_REG (TYPE_MODE (type), RET_REGISTER);
3739 + else if (int_size_in_bytes (type) <= 8)
3740 + return gen_rtx_REG (TYPE_MODE (type), INTERNAL_REGNUM (11));
3746 + Return a rtx used for the return value from a library function call.
3749 +avr32_libcall_value (enum machine_mode mode)
3752 + if (GET_MODE_SIZE (mode) <= 4)
3753 + return gen_rtx_REG (mode, RET_REGISTER);
3754 + else if (GET_MODE_SIZE (mode) <= 8)
3755 + return gen_rtx_REG (mode, INTERNAL_REGNUM (11));
3760 +/* Return TRUE if X references a SYMBOL_REF. */
3762 +symbol_mentioned_p (rtx x)
3767 + if (GET_CODE (x) == SYMBOL_REF)
3770 + fmt = GET_RTX_FORMAT (GET_CODE (x));
3772 + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3774 + if (fmt[i] == 'E')
3778 + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3779 + if (symbol_mentioned_p (XVECEXP (x, i, j)))
3782 + else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i)))
3789 +/* Return TRUE if X references a LABEL_REF. */
3791 +label_mentioned_p (rtx x)
3796 + if (GET_CODE (x) == LABEL_REF)
3799 + fmt = GET_RTX_FORMAT (GET_CODE (x));
3800 + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3802 + if (fmt[i] == 'E')
3806 + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3807 + if (label_mentioned_p (XVECEXP (x, i, j)))
3810 + else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i)))
3817 +/* Return TRUE if X contains a MEM expression. */
3819 +mem_mentioned_p (rtx x)
3827 + fmt = GET_RTX_FORMAT (GET_CODE (x));
3828 + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3830 + if (fmt[i] == 'E')
3834 + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3835 + if (mem_mentioned_p (XVECEXP (x, i, j)))
3838 + else if (fmt[i] == 'e' && mem_mentioned_p (XEXP (x, i)))
3846 +avr32_legitimate_pic_operand_p (rtx x)
3849 + /* We can't have const, this must be broken down to a symbol. */
3850 + if (GET_CODE (x) == CONST)
3853 + /* Can't access symbols or labels via the constant pool either */
3854 + if ((GET_CODE (x) == SYMBOL_REF
3855 + && CONSTANT_POOL_ADDRESS_P (x)
3856 + && (symbol_mentioned_p (get_pool_constant (x))
3857 + || label_mentioned_p (get_pool_constant (x)))))
3865 +legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3869 + if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
3875 + if (no_new_pseudos)
3878 + reg = gen_reg_rtx (Pmode);
3883 + emit_move_insn (reg, orig);
3885 + /* Only set current function as using pic offset table if flag_pic is
3886 + set. This is because this function is also used if
3887 + TARGET_HAS_ASM_ADDR_PSEUDOS is set. */
3889 + current_function_uses_pic_offset_table = 1;
3891 + /* Put a REG_EQUAL note on this insn, so that it can be optimized by
3895 + else if (GET_CODE (orig) == CONST)
3900 + && GET_CODE (XEXP (orig, 0)) == PLUS
3901 + && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3906 + if (no_new_pseudos)
3909 + reg = gen_reg_rtx (Pmode);
3912 + if (GET_CODE (XEXP (orig, 0)) == PLUS)
3915 + legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3917 + legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3918 + base == reg ? 0 : reg);
3923 + if (GET_CODE (offset) == CONST_INT)
3925 + /* The base register doesn't really matter, we only want to test
3926 + the index for the appropriate mode. */
3927 + if (!avr32_const_ok_for_constraint_p (INTVAL (offset), 'I', "Is21"))
3929 + if (!no_new_pseudos)
3930 + offset = force_reg (Pmode, offset);
3935 + if (GET_CODE (offset) == CONST_INT)
3936 + return plus_constant (base, INTVAL (offset));
3939 + return gen_rtx_PLUS (Pmode, base, offset);
3945 +/* Generate code to load the PIC register. */
3947 +avr32_load_pic_register (void)
3950 + rtx global_offset_table;
3952 + if ((current_function_uses_pic_offset_table == 0) || TARGET_NO_INIT_GOT)
3958 + l1 = gen_label_rtx ();
3960 + global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3962 + gen_rtx_CONST (Pmode,
3963 + gen_rtx_MINUS (SImode, gen_rtx_LABEL_REF (Pmode, l1),
3964 + global_offset_table));
3965 + emit_insn (gen_pic_load_addr
3966 + (pic_offset_table_rtx, force_const_mem (SImode, pic_tmp)));
3967 + emit_insn (gen_pic_compute_got_from_pc (pic_offset_table_rtx, l1));
3969 + /* Need to emit this whether or not we obey regdecls, since setjmp/longjmp
3970 + can cause life info to screw up. */
3971 + emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3976 +/* This hook should return true if values of type type are returned at the most
3977 + significant end of a register (in other words, if they are padded at the
3978 + least significant end). You can assume that type is returned in a register;
3979 + the caller is required to check this. Note that the register provided by
3980 + FUNCTION_VALUE must be able to hold the complete return value. For example,
3981 + if a 1-, 2- or 3-byte structure is returned at the most significant end of a
3982 + 4-byte register, FUNCTION_VALUE should provide an SImode rtx. */
3984 +avr32_return_in_msb (tree type ATTRIBUTE_UNUSED)
3986 + /* if ( AGGREGATE_TYPE_P (type) ) if ((int_size_in_bytes(type) == 1) ||
3987 + ((int_size_in_bytes(type) == 2) && TYPE_ALIGN_UNIT(type) >= 2)) return
3988 + false; else return true; */
3995 + Returns one if a certain function value is going to be returned in memory
3996 + and zero if it is going to be returned in a register.
3998 + BLKmode and all other modes that is larger than 64 bits are returned in
4002 +avr32_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4004 + if (TYPE_MODE (type) == VOIDmode)
4007 + if (int_size_in_bytes (type) > (2 * UNITS_PER_WORD)
4008 + || int_size_in_bytes (type) == -1)
4013 + /* If we have an aggregate then use the same mechanism as when checking if
4014 + it should be passed on the stack. */
4016 + && AGGREGATE_TYPE_P (type)
4017 + && (*targetm.calls.must_pass_in_stack) (TYPE_MODE (type), type))
4024 +/* Output the constant part of the trampoline.
4025 + lddpc r0, pc[0x8:e] ; load static chain register
4026 + lddpc pc, pc[0x8:e] ; jump to subrutine
4027 + .long 0 ; Address to static chain,
4028 + ; filled in by avr32_initialize_trampoline()
4029 + .long 0 ; Address to subrutine,
4030 + ; filled in by avr32_initialize_trampoline()
4033 +avr32_trampoline_template (FILE * file)
4035 + fprintf (file, "\tlddpc r0, pc[8]\n");
4036 + fprintf (file, "\tlddpc pc, pc[8]\n");
4037 + /* make room for the address of the static chain. */
4038 + fprintf (file, "\t.long\t0\n");
4039 + /* make room for the address to the subrutine. */
4040 + fprintf (file, "\t.long\t0\n");
4045 + Initialize the variable parts of a trampoline.
4048 +avr32_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain)
4050 + /* Store the address to the static chain. */
4051 + emit_move_insn (gen_rtx_MEM
4052 + (SImode, plus_constant (addr, TRAMPOLINE_SIZE - 4)),
4055 + /* Store the address to the function. */
4056 + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, TRAMPOLINE_SIZE)),
4059 + emit_insn (gen_cache (gen_rtx_REG (SImode, 13),
4060 + gen_rtx_CONST_INT (SImode,
4061 + AVR32_CACHE_INVALIDATE_ICACHE)));
4064 +/* Return nonzero if X is valid as an addressing register. */
4066 +avr32_address_register_rtx_p (rtx x, int strict_p)
4070 + if (!register_operand(x, GET_MODE(x)))
4073 + /* If strict we require the register to be a hard register. */
4078 + regno = REGNO (x);
4081 + return REGNO_OK_FOR_BASE_P (regno);
4083 + return (regno <= LAST_REGNUM || regno >= FIRST_PSEUDO_REGISTER);
4086 +/* Return nonzero if INDEX is valid for an address index operand. */
4088 +avr32_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p)
4090 + enum rtx_code code = GET_CODE (index);
4092 + if (GET_MODE_SIZE (mode) > 8)
4095 + /* Standard coprocessor addressing modes. */
4096 + if (code == CONST_INT)
4098 + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT)
4099 + /* Coprocessor mem insns has a smaller reach than ordinary mem insns */
4100 + return CONST_OK_FOR_CONSTRAINT_P (INTVAL (index), 'K', "Ku14");
4102 + return CONST_OK_FOR_CONSTRAINT_P (INTVAL (index), 'K', "Ks16");
4105 + if (avr32_address_register_rtx_p (index, strict_p))
4110 + rtx xiop0 = XEXP (index, 0);
4111 + rtx xiop1 = XEXP (index, 1);
4112 + return ((avr32_address_register_rtx_p (xiop0, strict_p)
4113 + && power_of_two_operand (xiop1, SImode)
4114 + && (INTVAL (xiop1) <= 8))
4115 + || (avr32_address_register_rtx_p (xiop1, strict_p)
4116 + && power_of_two_operand (xiop0, SImode)
4117 + && (INTVAL (xiop0) <= 8)));
4119 + else if (code == ASHIFT)
4121 + rtx op = XEXP (index, 1);
4123 + return (avr32_address_register_rtx_p (XEXP (index, 0), strict_p)
4124 + && GET_CODE (op) == CONST_INT
4125 + && INTVAL (op) > 0 && INTVAL (op) <= 3);
4132 + Used in the GO_IF_LEGITIMATE_ADDRESS macro. Returns a nonzero value if
4133 + the RTX x is a legitimate memory address.
4135 + Returns NO_REGS if the address is not legatime, GENERAL_REGS or ALL_REGS
4139 +/* Forward declaration*/
4140 +int is_minipool_label (rtx label);
4143 +avr32_legitimate_address (enum machine_mode mode, rtx x, int strict)
4146 + switch (GET_CODE (x))
4149 + return avr32_address_register_rtx_p (x, strict);
4151 + return ((mode==SImode)
4152 + && CONST_OK_FOR_CONSTRAINT_P(INTVAL(x), 'K', "Ks17"));
4155 + rtx label = avr32_find_symbol (x);
4158 + ((CONSTANT_POOL_ADDRESS_P (label)
4160 + && (symbol_mentioned_p (get_pool_constant (label))
4161 + || label_mentioned_p (get_pool_constant (label)))))
4162 + /* TODO! Can this ever happen??? */
4163 + || ((GET_CODE (label) == LABEL_REF)
4164 + && GET_CODE (XEXP (label, 0)) == CODE_LABEL
4165 + && is_minipool_label (XEXP (label, 0)))
4166 + /*|| ((GET_CODE (label) == SYMBOL_REF)
4168 + && SYMBOL_REF_RMW_ADDR(label))*/))
4175 + if (GET_CODE (XEXP (x, 0)) == CODE_LABEL
4176 + && is_minipool_label (XEXP (x, 0)))
4183 + if (CONSTANT_POOL_ADDRESS_P (x)
4185 + && (symbol_mentioned_p (get_pool_constant (x))
4186 + || label_mentioned_p (get_pool_constant (x)))))
4188 + else if (SYMBOL_REF_RCALL_FUNCTION_P (x)
4189 + || (mode == SImode
4190 + && SYMBOL_REF_RMW_ADDR (x)))
4194 + case PRE_DEC: /* (pre_dec (...)) */
4195 + case POST_INC: /* (post_inc (...)) */
4196 + return avr32_address_register_rtx_p (XEXP (x, 0), strict);
4197 + case PLUS: /* (plus (...) (...)) */
4199 + rtx xop0 = XEXP (x, 0);
4200 + rtx xop1 = XEXP (x, 1);
4202 + return ((avr32_address_register_rtx_p (xop0, strict)
4203 + && avr32_legitimate_index_p (mode, xop1, strict))
4204 + || (avr32_address_register_rtx_p (xop1, strict)
4205 + && avr32_legitimate_index_p (mode, xop0, strict)));
4216 +avr32_const_ok_for_move (HOST_WIDE_INT c)
4218 + if ( TARGET_V2_INSNS )
4219 + return ( avr32_const_ok_for_constraint_p (c, 'K', "Ks21")
4220 + /* movh instruction */
4221 + || avr32_hi16_immediate_operand (GEN_INT(c), VOIDmode) );
4223 + return avr32_const_ok_for_constraint_p (c, 'K', "Ks21");
4227 +avr32_const_double_immediate (rtx value)
4229 + HOST_WIDE_INT hi, lo;
4231 + if (GET_CODE (value) != CONST_DOUBLE)
4234 + if (SCALAR_FLOAT_MODE_P (GET_MODE (value)))
4236 + HOST_WIDE_INT target_float[2];
4238 + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (value),
4239 + GET_MODE (value));
4240 + lo = target_float[0];
4241 + hi = target_float[1];
4245 + hi = CONST_DOUBLE_HIGH (value);
4246 + lo = CONST_DOUBLE_LOW (value);
4249 + if (avr32_const_ok_for_constraint_p (lo, 'K', "Ks21")
4250 + && (GET_MODE (value) == SFmode
4251 + || avr32_const_ok_for_constraint_p (hi, 'K', "Ks21")))
4261 +avr32_legitimate_constant_p (rtx x)
4263 + switch (GET_CODE (x))
4266 + /* Check if we should put large immediate into constant pool
4267 + or load them directly with mov/orh.*/
4268 + if (!avr32_imm_in_const_pool)
4271 + return avr32_const_ok_for_move (INTVAL (x));
4272 + case CONST_DOUBLE:
4273 + /* Check if we should put large immediate into constant pool
4274 + or load them directly with mov/orh.*/
4275 + if (!avr32_imm_in_const_pool)
4278 + if (GET_MODE (x) == SFmode
4279 + || GET_MODE (x) == DFmode || GET_MODE (x) == DImode)
4280 + return avr32_const_double_immediate (x);
4285 + return avr32_find_symbol (x) && (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS);
4288 + case CONST_VECTOR:
4291 + printf ("%s():\n", __FUNCTION__);
4298 +/* Strip any special encoding from labels */
4300 +avr32_strip_name_encoding (const char *name)
4302 + const char *stripped = name;
4306 + switch (stripped[0])
4309 + stripped = strchr (name + 1, '#') + 1;
4312 + stripped = &stripped[1];
4322 +/* Do anything needed before RTL is emitted for each function. */
4323 +static struct machine_function *
4324 +avr32_init_machine_status (void)
4326 + struct machine_function *machine;
4328 + (machine_function *) ggc_alloc_cleared (sizeof (machine_function));
4330 +#if AVR32_FT_UNKNOWN != 0
4331 + machine->func_type = AVR32_FT_UNKNOWN;
4334 + machine->minipool_label_head = 0;
4335 + machine->minipool_label_tail = 0;
4336 + machine->ifcvt_after_reload = 0;
4341 +avr32_init_expanders (void)
4343 + /* Arrange to initialize and mark the machine per-function status. */
4344 + init_machine_status = avr32_init_machine_status;
4348 +/* Return an RTX indicating where the return address to the
4349 + calling function can be found. */
4352 +avr32_return_addr (int count, rtx frame ATTRIBUTE_UNUSED)
4357 + return get_hard_reg_initial_val (Pmode, LR_REGNUM);
4362 +avr32_encode_section_info (tree decl, rtx rtl, int first)
4364 + default_encode_section_info(decl, rtl, first);
4366 + if ( TREE_CODE (decl) == VAR_DECL
4367 + && (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
4368 + && (lookup_attribute ("rmw_addressable", DECL_ATTRIBUTES (decl))
4369 + || TARGET_RMW_ADDRESSABLE_DATA) ){
4370 + if ( !TARGET_RMW || flag_pic )
4372 + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT);
4377 +avr32_asm_output_label (FILE * stream, const char *name)
4379 + name = avr32_strip_name_encoding (name);
4381 + /* Print the label. */
4382 + assemble_name (stream, name);
4383 + fprintf (stream, ":\n");
4389 +avr32_asm_weaken_label (FILE * stream, const char *name)
4391 + fprintf (stream, "\t.weak ");
4392 + assemble_name (stream, name);
4393 + fprintf (stream, "\n");
4397 + Checks if a labelref is equal to a reserved word in the assembler. If it is,
4398 + insert a '_' before the label name.
4401 +avr32_asm_output_labelref (FILE * stream, const char *name)
4403 + int verbatim = FALSE;
4404 + const char *stripped = name;
4405 + int strip_finished = FALSE;
4407 + while (!strip_finished)
4409 + switch (stripped[0])
4412 + stripped = strchr (name + 1, '#') + 1;
4415 + stripped = &stripped[1];
4419 + strip_finished = TRUE;
4425 + fputs (stripped, stream);
4427 + asm_fprintf (stream, "%U%s", stripped);
4433 + Check if the comparison in compare_exp is redundant
4434 + for the condition given in next_cond given that the
4435 + needed flags are already set by an earlier instruction.
4436 + Uses cc_prev_status to check this.
4438 + Returns NULL_RTX if the compare is not redundant
4439 + or the new condition to use in the conditional
4440 + instruction if the compare is redundant.
4443 +is_compare_redundant (rtx compare_exp, rtx next_cond)
4445 + int z_flag_valid = FALSE;
4446 + int n_flag_valid = FALSE;
4449 + if (GET_CODE (compare_exp) != COMPARE
4450 + && GET_CODE (compare_exp) != AND)
4454 + if (rtx_equal_p (cc_prev_status.mdep.value, compare_exp))
4456 + /* cc0 already contains the correct comparison -> delete cmp insn */
4460 + if (GET_MODE (compare_exp) != SImode)
4463 + switch (cc_prev_status.mdep.flags)
4467 + n_flag_valid = TRUE;
4470 + z_flag_valid = TRUE;
4473 + if (cc_prev_status.mdep.value
4474 + && GET_CODE (compare_exp) == COMPARE
4475 + && REG_P (XEXP (compare_exp, 0))
4476 + && REGNO (XEXP (compare_exp, 0)) == REGNO (cc_prev_status.mdep.value)
4477 + && GET_CODE (XEXP (compare_exp, 1)) == CONST_INT
4478 + && next_cond != NULL_RTX)
4480 + if (INTVAL (XEXP (compare_exp, 1)) == 0
4482 + && (GET_CODE (next_cond) == EQ || GET_CODE (next_cond) == NE))
4483 + /* We can skip comparison Z flag is already reflecting ops[0] */
4485 + else if (n_flag_valid
4486 + && ((INTVAL (XEXP (compare_exp, 1)) == 0
4487 + && (GET_CODE (next_cond) == GE
4488 + || GET_CODE (next_cond) == LT))
4489 + || (INTVAL (XEXP (compare_exp, 1)) == -1
4490 + && (GET_CODE (next_cond) == GT
4491 + || GET_CODE (next_cond) == LE))))
4493 + /* We can skip comparison N flag is already reflecting ops[0],
4494 + which means that we can use the mi/pl conditions to check if
4495 + ops[0] is GE or LT 0. */
4496 + if ((GET_CODE (next_cond) == GE) || (GET_CODE (next_cond) == GT))
4498 + gen_rtx_UNSPEC (GET_MODE (next_cond), gen_rtvec (2, cc0_rtx, const0_rtx),
4502 + gen_rtx_UNSPEC (GET_MODE (next_cond), gen_rtvec (2, cc0_rtx, const0_rtx),
4510 +/* Updates cc_status. */
4512 +avr32_notice_update_cc (rtx exp, rtx insn)
4514 + enum attr_cc attr_cc = get_attr_cc (insn);
4516 + if ( attr_cc == CC_SET_Z_IF_NOT_V2 )
4517 + if (TARGET_V2_INSNS)
4518 + attr_cc = CC_NONE;
4520 + attr_cc = CC_SET_Z;
4527 + /* Check if the function call returns a value in r12 */
4528 + if (REG_P (recog_data.operand[0])
4529 + && REGNO (recog_data.operand[0]) == RETVAL_REGNUM)
4531 + cc_status.flags = 0;
4532 + cc_status.mdep.value =
4533 + gen_rtx_COMPARE (SImode, recog_data.operand[0], const0_rtx);
4534 + cc_status.mdep.flags = CC_SET_VNCZ;
4535 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4541 + /* Check that compare will not be optimized away if so nothing should
4543 + rtx compare_exp = SET_SRC (exp);
4544 + /* Check if we have a tst expression. If so convert it to a
4545 + compare with 0. */
4546 + if ( REG_P (SET_SRC (exp)) )
4547 + compare_exp = gen_rtx_COMPARE (GET_MODE (SET_SRC (exp)),
4551 + if (is_compare_redundant (compare_exp, get_next_insn_cond (insn)) ==
4555 + /* Reset the nonstandard flag */
4557 + cc_status.flags = 0;
4558 + cc_status.mdep.value = compare_exp;
4559 + cc_status.mdep.flags = CC_SET_VNCZ;
4560 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4564 + case CC_CMP_COND_INSN:
4566 + /* Conditional insn that emit the compare itself. */
4568 + rtx cmp_op0, cmp_op1;
4571 + rtx next_insn = next_nonnote_insn (insn);
4573 + if ( GET_CODE (exp) == COND_EXEC )
4575 + cmp_op0 = XEXP (COND_EXEC_TEST (exp), 0);
4576 + cmp_op1 = XEXP (COND_EXEC_TEST (exp), 1);
4577 + cond = COND_EXEC_TEST (exp);
4578 + dest = SET_DEST (COND_EXEC_CODE (exp));
4582 + /* If then else conditional. compare operands are in operands
4584 + cmp_op0 = recog_data.operand[4];
4585 + cmp_op1 = recog_data.operand[5];
4586 + cond = recog_data.operand[1];
4587 + dest = SET_DEST (exp);
4590 + if ( GET_CODE (cmp_op0) == AND )
4593 + cmp = gen_rtx_COMPARE (GET_MODE (cmp_op0),
4597 + /* Check if the conditional insns updates a register present
4598 + in the comparison, if so then we must reset the cc_status. */
4600 + && (reg_mentioned_p (dest, cmp_op0)
4601 + || reg_mentioned_p (dest, cmp_op1))
4602 + && GET_CODE (exp) != COND_EXEC )
4606 + else if (is_compare_redundant (cmp, cond) == NULL_RTX)
4608 + /* Reset the nonstandard flag */
4610 + if ( GET_CODE (cmp_op0) == AND )
4612 + cc_status.flags = CC_INVERTED;
4613 + cc_status.mdep.flags = CC_SET_Z;
4617 + cc_status.flags = 0;
4618 + cc_status.mdep.flags = CC_SET_VNCZ;
4620 + cc_status.mdep.value = cmp;
4621 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4625 + /* Check if we have a COND_EXEC insn which updates one
4626 + of the registers in the compare status. */
4628 + && (reg_mentioned_p (dest, cmp_op0)
4629 + || reg_mentioned_p (dest, cmp_op1))
4630 + && GET_CODE (exp) == COND_EXEC )
4631 + cc_status.mdep.cond_exec_cmp_clobbered = 1;
4633 + if ( cc_status.mdep.cond_exec_cmp_clobbered
4634 + && GET_CODE (exp) == COND_EXEC
4635 + && next_insn != NULL
4636 + && INSN_P (next_insn)
4637 + && !(GET_CODE (PATTERN (next_insn)) == COND_EXEC
4638 + && rtx_equal_p (XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 0), cmp_op0)
4639 + && rtx_equal_p (XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 1), cmp_op1)
4640 + && (GET_CODE (COND_EXEC_TEST (PATTERN (next_insn))) == GET_CODE (cond)
4641 + || GET_CODE (COND_EXEC_TEST (PATTERN (next_insn))) == reverse_condition (GET_CODE (cond)))) )
4643 + /* We have a sequence of conditional insns where the compare status has been clobbered
4644 + since the compare no longer reflects the content of the values to compare. */
4646 + cc_status.mdep.cond_exec_cmp_clobbered = 1;
4651 + case CC_FPCOMPARE:
4652 + /* Check that floating-point compare will not be optimized away if so
4653 + nothing should be done */
4654 + if (!rtx_equal_p (cc_prev_status.mdep.fpvalue, SET_SRC (exp)))
4656 + /* cc0 already contains the correct comparison -> delete cmp insn */
4657 + /* Reset the nonstandard flag */
4658 + cc_status.mdep.fpvalue = SET_SRC (exp);
4659 + cc_status.mdep.fpflags = CC_SET_CZ;
4662 + case CC_FROM_FPCC:
4663 + /* Flags are updated with flags from Floating-point coprocessor, set
4664 + CC_NOT_SIGNED flag since the flags are set so that unsigned
4665 + condidion codes can be used directly. */
4667 + cc_status.flags = CC_NOT_SIGNED;
4668 + cc_status.mdep.value = cc_status.mdep.fpvalue;
4669 + cc_status.mdep.flags = cc_status.mdep.fpflags;
4672 + /* Bit load is kind of like an inverted testsi, because the Z flag is
4675 + cc_status.flags = CC_INVERTED;
4676 + cc_status.mdep.value = SET_SRC (exp);
4677 + cc_status.mdep.flags = CC_SET_Z;
4678 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4681 + /* Insn does not affect CC at all. Check if the instruction updates
4682 + some of the register currently reflected in cc0 */
4684 + if ((GET_CODE (exp) == SET)
4685 + && (cc_status.value1 || cc_status.value2 || cc_status.mdep.value)
4686 + && (reg_mentioned_p (SET_DEST (exp), cc_status.value1)
4687 + || reg_mentioned_p (SET_DEST (exp), cc_status.value2)
4688 + || reg_mentioned_p (SET_DEST (exp), cc_status.mdep.value)))
4693 + /* If this is a parallel we must step through each of the parallel
4695 + if (GET_CODE (exp) == PARALLEL)
4698 + for (i = 0; i < XVECLEN (exp, 0); ++i)
4700 + rtx vec_exp = XVECEXP (exp, 0, i);
4701 + if ((GET_CODE (vec_exp) == SET)
4702 + && (cc_status.value1 || cc_status.value2
4703 + || cc_status.mdep.value)
4704 + && (reg_mentioned_p (SET_DEST (vec_exp), cc_status.value1)
4705 + || reg_mentioned_p (SET_DEST (vec_exp),
4707 + || reg_mentioned_p (SET_DEST (vec_exp),
4708 + cc_status.mdep.value)))
4715 + /* Check if we have memory opartions with post_inc or pre_dec on the
4716 + register currently reflected in cc0 */
4717 + if (GET_CODE (exp) == SET
4718 + && GET_CODE (SET_SRC (exp)) == MEM
4719 + && (GET_CODE (XEXP (SET_SRC (exp), 0)) == POST_INC
4720 + || GET_CODE (XEXP (SET_SRC (exp), 0)) == PRE_DEC)
4723 + (XEXP (XEXP (SET_SRC (exp), 0), 0), cc_status.value1)
4724 + || reg_mentioned_p (XEXP (XEXP (SET_SRC (exp), 0), 0),
4726 + || reg_mentioned_p (XEXP (XEXP (SET_SRC (exp), 0), 0),
4727 + cc_status.mdep.value)))
4730 + if (GET_CODE (exp) == SET
4731 + && GET_CODE (SET_DEST (exp)) == MEM
4732 + && (GET_CODE (XEXP (SET_DEST (exp), 0)) == POST_INC
4733 + || GET_CODE (XEXP (SET_DEST (exp), 0)) == PRE_DEC)
4736 + (XEXP (XEXP (SET_DEST (exp), 0), 0), cc_status.value1)
4737 + || reg_mentioned_p (XEXP (XEXP (SET_DEST (exp), 0), 0),
4739 + || reg_mentioned_p (XEXP (XEXP (SET_DEST (exp), 0), 0),
4740 + cc_status.mdep.value)))
4746 + cc_status.mdep.value = recog_data.operand[0];
4747 + cc_status.mdep.flags = CC_SET_VNCZ;
4748 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4753 + cc_status.mdep.value = recog_data.operand[0];
4754 + cc_status.mdep.flags = CC_SET_NCZ;
4755 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4760 + cc_status.mdep.value = recog_data.operand[0];
4761 + cc_status.mdep.flags = CC_SET_CZ;
4762 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4767 + cc_status.mdep.value = recog_data.operand[0];
4768 + cc_status.mdep.flags = CC_SET_Z;
4769 + cc_status.mdep.cond_exec_cmp_clobbered = 0;
4783 + Outputs to stdio stream stream the assembler syntax for an instruction
4784 + operand x. x is an RTL expression.
4787 +avr32_print_operand (FILE * stream, rtx x, int code)
4791 + if ( code == '?' )
4793 + /* Predicable instruction, print condition code */
4795 + /* If the insn should not be conditional then do nothing. */
4796 + if ( current_insn_predicate == NULL_RTX )
4799 + /* Set x to the predicate to force printing
4800 + the condition later on. */
4801 + x = current_insn_predicate;
4803 + /* Reverse condition if useing bld insn. */
4804 + if ( GET_CODE (XEXP(current_insn_predicate,0)) == AND )
4805 + x = reversed_condition (current_insn_predicate);
4807 + else if ( code == '!' )
4809 + /* Output compare for conditional insn if needed. */
4811 + gcc_assert ( current_insn_predicate != NULL_RTX );
4812 + new_cond = avr32_output_cmp(current_insn_predicate,
4813 + GET_MODE(XEXP(current_insn_predicate,0)),
4814 + XEXP(current_insn_predicate,0),
4815 + XEXP(current_insn_predicate,1));
4817 + /* Check if the new condition is a special avr32 condition
4818 + specified using UNSPECs. If so we must handle it differently. */
4819 + if ( GET_CODE (new_cond) == UNSPEC )
4821 + current_insn_predicate =
4822 + gen_rtx_UNSPEC (CCmode,
4824 + XEXP(current_insn_predicate,0),
4825 + XEXP(current_insn_predicate,1)),
4826 + XINT (new_cond, 1));
4830 + PUT_CODE(current_insn_predicate, GET_CODE(new_cond));
4835 + switch (GET_CODE (x))
4838 + switch (XINT (x, 1))
4840 + case UNSPEC_COND_PL:
4842 + fputs ("mi", stream);
4844 + fputs ("pl", stream);
4846 + case UNSPEC_COND_MI:
4848 + fputs ("pl", stream);
4850 + fputs ("mi", stream);
4858 + fputs ("ne", stream);
4860 + fputs ("eq", stream);
4864 + fputs ("eq", stream);
4866 + fputs ("ne", stream);
4870 + fputs ("le", stream);
4872 + fputs ("gt", stream);
4876 + fputs ("ls", stream);
4878 + fputs ("hi", stream);
4882 + fputs ("ge", stream);
4884 + fputs ("lt", stream);
4888 + fputs ("hs", stream);
4890 + fputs ("lo", stream);
4894 + fputs ("lt", stream);
4896 + fputs ("ge", stream);
4900 + fputs ("lo", stream);
4902 + fputs ("hs", stream);
4906 + fputs ("gt", stream);
4908 + fputs ("le", stream);
4912 + fputs ("hi", stream);
4914 + fputs ("ls", stream);
4918 + HOST_WIDE_INT value = INTVAL (x);
4923 + if ( HOST_BITS_PER_WIDE_INT > BITS_PER_WORD )
4925 + /* A const_int can be used to represent DImode constants. */
4926 + value >>= BITS_PER_WORD;
4928 + /* We might get a const_int immediate for setting a DI register,
4929 + we then must then return the correct sign extended DI. The most
4930 + significant word is just a sign extension. */
4931 + else if (value < 0)
4941 + /* Set to bit position of first bit set in immediate */
4942 + int i, bitpos = 32;
4943 + for (i = 0; i < 32; i++)
4944 + if (value & (1 << i))
4954 + /* Set to bit position of first bit cleared in immediate */
4955 + int i, bitpos = 32;
4956 + for (i = 0; i < 32; i++)
4957 + if (!(value & (1 << i)))
4972 + sprintf (op, "r0-r3");
4974 + strlen (op) ? sprintf (op, "%s, r4-r7", op) : sprintf (op,
4977 + strlen (op) ? sprintf (op, "%s, r8-r9", op) : sprintf (op,
4980 + strlen (op) ? sprintf (op, "%s, r10", op) : sprintf (op,
4983 + strlen (op) ? sprintf (op, "%s, r11", op) : sprintf (op,
4986 + strlen (op) ? sprintf (op, "%s, r12", op) : sprintf (op,
4989 + strlen (op) ? sprintf (op, "%s, lr", op) : sprintf (op, "lr");
4991 + strlen (op) ? sprintf (op, "%s, pc", op) : sprintf (op, "pc");
4993 + fputs (op, stream);
4999 + char reglist16_string[100];
5001 + reglist16_string[0] = '\0';
5003 + for (i = 0; i < 16; ++i)
5005 + if (value & (1 << i))
5007 + strlen (reglist16_string) ? sprintf (reglist16_string,
5013 + sprintf (reglist16_string, "%s",
5014 + reg_names[INTERNAL_REGNUM (i)]);
5017 + fputs (reglist16_string, stream);
5023 + char reglist_string[100];
5024 + avr32_make_fp_reglist_w (value, (char *) reglist_string);
5025 + fputs (reglist_string, stream);
5031 + char reglist_string[100];
5032 + avr32_make_fp_reglist_d (value, (char *) reglist_string);
5033 + fputs (reglist_string, stream);
5037 + /* Print halfword part of word */
5038 + fputs (value ? "b" : "t", stream);
5043 + fprintf (stream, "%d", value);
5046 + case CONST_DOUBLE:
5048 + HOST_WIDE_INT hi, lo;
5049 + if (SCALAR_FLOAT_MODE_P (GET_MODE (x)))
5051 + HOST_WIDE_INT target_float[2];
5053 + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (x),
5055 + /* For doubles the most significant part starts at index 0. */
5056 + if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD)
5058 + hi = target_float[0];
5059 + lo = target_float[1];
5063 + lo = target_float[0];
5068 + hi = CONST_DOUBLE_HIGH (x);
5069 + lo = CONST_DOUBLE_LOW (x);
5073 + fprintf (stream, "%ld", hi);
5075 + fprintf (stream, "%ld", lo);
5080 + output_addr_const (stream, XEXP (XEXP (x, 0), 0));
5081 + fprintf (stream, "+%ld", INTVAL (XEXP (XEXP (x, 0), 1)));
5084 + /* Swap register name if the register is DImode or DFmode. */
5085 + if (GET_MODE (x) == DImode || GET_MODE (x) == DFmode)
5087 + /* Double register must have an even numbered address */
5088 + gcc_assert (!(REGNO (x) % 2));
5090 + fputs (reg_names[true_regnum (x)], stream);
5092 + fputs (reg_names[true_regnum (x) + 1], stream);
5094 + else if (GET_MODE (x) == TImode)
5099 + fputs (reg_names[true_regnum (x)], stream);
5102 + fputs (reg_names[true_regnum (x) + 1], stream);
5105 + fputs (reg_names[true_regnum (x) + 2], stream);
5108 + fputs (reg_names[true_regnum (x) + 3], stream);
5111 + fprintf (stream, "%s, %s, %s, %s",
5112 + reg_names[true_regnum (x) + 3],
5113 + reg_names[true_regnum (x) + 2],
5114 + reg_names[true_regnum (x) + 1],
5115 + reg_names[true_regnum (x)]);
5121 + fputs (reg_names[true_regnum (x)], stream);
5127 + output_addr_const (stream, x);
5130 + switch (GET_CODE (XEXP (x, 0)))
5134 + output_addr_const (stream, XEXP (x, 0));
5137 + switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5140 + output_addr_const (stream, XEXP (XEXP (x, 0), 0));
5148 + avr32_print_operand (stream, XEXP (x, 0), 0);
5150 + fputs ("[0]", stream);
5153 + fputs ("--", stream);
5154 + avr32_print_operand (stream, XEXP (XEXP (x, 0), 0), 0);
5157 + avr32_print_operand (stream, XEXP (XEXP (x, 0), 0), 0);
5158 + fputs ("++", stream);
5162 + rtx op0 = XEXP (XEXP (x, 0), 0);
5163 + rtx op1 = XEXP (XEXP (x, 0), 1);
5164 + rtx base = NULL_RTX, offset = NULL_RTX;
5166 + if (avr32_address_register_rtx_p (op0, 1))
5171 + else if (avr32_address_register_rtx_p (op1, 1))
5173 + /* Operands are switched. */
5178 + gcc_assert (base && offset
5179 + && avr32_address_register_rtx_p (base, 1)
5180 + && avr32_legitimate_index_p (GET_MODE (x), offset,
5183 + avr32_print_operand (stream, base, 0);
5184 + fputs ("[", stream);
5185 + avr32_print_operand (stream, offset, 0);
5186 + fputs ("]", stream);
5190 + output_addr_const (stream, XEXP (XEXP (XEXP (x, 0), 0), 0));
5191 + fprintf (stream, " + %ld",
5192 + INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)));
5195 + avr32_print_operand (stream, XEXP (x, 0), 0);
5203 + int value = INTVAL (XEXP (x, 1));
5205 + /* Convert immediate in multiplication into a shift immediate */
5220 + fprintf (stream, "%s << %i", reg_names[true_regnum (XEXP (x, 0))],
5225 + if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5226 + fprintf (stream, "%s << %i", reg_names[true_regnum (XEXP (x, 0))],
5227 + (int) INTVAL (XEXP (x, 1)));
5228 + else if (REG_P (XEXP (x, 1)))
5229 + fprintf (stream, "%s << %s", reg_names[true_regnum (XEXP (x, 0))],
5230 + reg_names[true_regnum (XEXP (x, 1))]);
5237 + if (GET_CODE (XEXP (x, 1)) == CONST_INT)
5238 + fprintf (stream, "%s >> %i", reg_names[true_regnum (XEXP (x, 0))],
5239 + (int) INTVAL (XEXP (x, 1)));
5240 + else if (REG_P (XEXP (x, 1)))
5241 + fprintf (stream, "%s >> %s", reg_names[true_regnum (XEXP (x, 0))],
5242 + reg_names[true_regnum (XEXP (x, 1))]);
5247 + fprintf (stream, ">>");
5251 + /* Load store multiple */
5253 + int count = XVECLEN (x, 0);
5254 + int reglist16 = 0;
5255 + char reglist16_string[100];
5257 + for (i = 0; i < count; ++i)
5259 + rtx vec_elm = XVECEXP (x, 0, i);
5260 + if (GET_MODE (vec_elm) != SET)
5262 + debug_rtx (vec_elm);
5263 + internal_error ("Unknown element in parallel expression!");
5265 + if (GET_MODE (XEXP (vec_elm, 0)) == REG)
5267 + /* Load multiple */
5268 + reglist16 |= 1 << ASM_REGNUM (REGNO (XEXP (vec_elm, 0)));
5272 + /* Store multiple */
5273 + reglist16 |= 1 << ASM_REGNUM (REGNO (XEXP (vec_elm, 1)));
5277 + avr32_make_reglist16 (reglist16, reglist16_string);
5278 + fputs (reglist16_string, stream);
5285 + rtx op0 = XEXP (x, 0);
5286 + rtx op1 = XEXP (x, 1);
5287 + rtx base = NULL_RTX, offset = NULL_RTX;
5289 + if (avr32_address_register_rtx_p (op0, 1))
5294 + else if (avr32_address_register_rtx_p (op1, 1))
5296 + /* Operands are switched. */
5301 + gcc_assert (base && offset
5302 + && avr32_address_register_rtx_p (base, 1)
5303 + && avr32_legitimate_index_p (GET_MODE (x), offset, 1));
5305 + avr32_print_operand (stream, base, 0);
5306 + fputs ("[", stream);
5307 + avr32_print_operand (stream, offset, 0);
5308 + fputs ("]", stream);
5319 + internal_error ("Illegal expression for avr32_print_operand");
5324 +avr32_get_note_reg_equiv (rtx insn)
5328 + note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
5330 + if (note != NULL_RTX)
5331 + return XEXP (note, 0);
5337 + Outputs to stdio stream stream the assembler syntax for an instruction
5338 + operand that is a memory reference whose address is x. x is an RTL
5344 +avr32_print_operand_address (FILE * stream, rtx x)
5346 + fprintf (stream, "(%d) /* address */", REGNO (x));
5349 +/* Return true if _GLOBAL_OFFSET_TABLE_ symbol is mentioned. */
5351 +avr32_got_mentioned_p (rtx addr)
5353 + if (GET_CODE (addr) == MEM)
5354 + addr = XEXP (addr, 0);
5355 + while (GET_CODE (addr) == CONST)
5356 + addr = XEXP (addr, 0);
5357 + if (GET_CODE (addr) == SYMBOL_REF)
5359 + return streq (XSTR (addr, 0), "_GLOBAL_OFFSET_TABLE_");
5361 + if (GET_CODE (addr) == PLUS || GET_CODE (addr) == MINUS)
5365 + l1 = avr32_got_mentioned_p (XEXP (addr, 0));
5366 + l2 = avr32_got_mentioned_p (XEXP (addr, 1));
5373 +/* Find the symbol in an address expression. */
5376 +avr32_find_symbol (rtx addr)
5378 + if (GET_CODE (addr) == MEM)
5379 + addr = XEXP (addr, 0);
5381 + while (GET_CODE (addr) == CONST)
5382 + addr = XEXP (addr, 0);
5384 + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
5386 + if (GET_CODE (addr) == PLUS)
5390 + l1 = avr32_find_symbol (XEXP (addr, 0));
5391 + l2 = avr32_find_symbol (XEXP (addr, 1));
5392 + if (l1 != NULL_RTX && l2 == NULL_RTX)
5394 + else if (l1 == NULL_RTX && l2 != NULL_RTX)
5402 +/* Routines for manipulation of the constant pool. */
5404 +/* AVR32 instructions cannot load a large constant directly into a
5405 + register; they have to come from a pc relative load. The constant
5406 + must therefore be placed in the addressable range of the pc
5407 + relative load. Depending on the precise pc relative load
5408 + instruction the range is somewhere between 256 bytes and 4k. This
5409 + means that we often have to dump a constant inside a function, and
5410 + generate code to branch around it.
5412 + It is important to minimize this, since the branches will slow
5413 + things down and make the code larger.
5415 + Normally we can hide the table after an existing unconditional
5416 + branch so that there is no interruption of the flow, but in the
5417 + worst case the code looks like this:
5435 + We fix this by performing a scan after scheduling, which notices
5436 + which instructions need to have their operands fetched from the
5437 + constant table and builds the table.
5439 + The algorithm starts by building a table of all the constants that
5440 + need fixing up and all the natural barriers in the function (places
5441 + where a constant table can be dropped without breaking the flow).
5442 + For each fixup we note how far the pc-relative replacement will be
5443 + able to reach and the offset of the instruction into the function.
5445 + Having built the table we then group the fixes together to form
5446 + tables that are as large as possible (subject to addressing
5447 + constraints) and emit each table of constants after the last
5448 + barrier that is within range of all the instructions in the group.
5449 + If a group does not contain a barrier, then we forcibly create one
5450 + by inserting a jump instruction into the flow. Once the table has
5451 + been inserted, the insns are then modified to reference the
5452 + relevant entry in the pool.
5454 + Possible enhancements to the algorithm (not implemented) are:
5456 + 1) For some processors and object formats, there may be benefit in
5457 + aligning the pools to the start of cache lines; this alignment
5458 + would need to be taken into account when calculating addressability
5461 +/* These typedefs are located at the start of this file, so that
5462 + they can be used in the prototypes there. This comment is to
5463 + remind readers of that fact so that the following structures
5464 + can be understood more easily.
5466 + typedef struct minipool_node Mnode;
5467 + typedef struct minipool_fixup Mfix; */
5469 +struct minipool_node
5471 + /* Doubly linked chain of entries. */
5474 + /* The maximum offset into the code that this entry can be placed. While
5475 + pushing fixes for forward references, all entries are sorted in order of
5476 + increasing max_address. */
5477 + HOST_WIDE_INT max_address;
5478 + /* Similarly for an entry inserted for a backwards ref. */
5479 + HOST_WIDE_INT min_address;
5480 + /* The number of fixes referencing this entry. This can become zero if we
5481 + "unpush" an entry. In this case we ignore the entry when we come to
5484 + /* The offset from the start of the minipool. */
5485 + HOST_WIDE_INT offset;
5486 + /* The value in table. */
5488 + /* The mode of value. */
5489 + enum machine_mode mode;
5490 + /* The size of the value. */
5494 +struct minipool_fixup
5498 + HOST_WIDE_INT address;
5500 + enum machine_mode mode;
5504 + HOST_WIDE_INT forwards;
5505 + HOST_WIDE_INT backwards;
5509 +/* Fixes less than a word need padding out to a word boundary. */
5510 +#define MINIPOOL_FIX_SIZE(mode, value) \
5511 + (IS_FORCE_MINIPOOL(value) ? 0 : \
5512 + (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4))
5514 +#define IS_FORCE_MINIPOOL(x) \
5515 + (GET_CODE(x) == UNSPEC && \
5516 + XINT(x, 1) == UNSPEC_FORCE_MINIPOOL)
5518 +static Mnode *minipool_vector_head;
5519 +static Mnode *minipool_vector_tail;
5521 +/* The linked list of all minipool fixes required for this function. */
5522 +Mfix *minipool_fix_head;
5523 +Mfix *minipool_fix_tail;
5524 +/* The fix entry for the current minipool, once it has been placed. */
5525 +Mfix *minipool_barrier;
5527 +/* Determines if INSN is the start of a jump table. Returns the end
5528 + of the TABLE or NULL_RTX. */
5530 +is_jump_table (rtx insn)
5534 + if (GET_CODE (insn) == JUMP_INSN
5535 + && JUMP_LABEL (insn) != NULL
5536 + && ((table = next_real_insn (JUMP_LABEL (insn)))
5537 + == next_real_insn (insn))
5539 + && GET_CODE (table) == JUMP_INSN
5540 + && (GET_CODE (PATTERN (table)) == ADDR_VEC
5541 + || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC))
5547 +static HOST_WIDE_INT
5548 +get_jump_table_size (rtx insn)
5550 + /* ADDR_VECs only take room if read-only data does into the text section. */
5551 + if (JUMP_TABLES_IN_TEXT_SECTION
5552 +#if !defined(READONLY_DATA_SECTION_ASM_OP)
5557 + rtx body = PATTERN (insn);
5558 + int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0;
5560 + return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt);
5566 +/* Move a minipool fix MP from its current location to before MAX_MP.
5567 + If MAX_MP is NULL, then MP doesn't need moving, but the addressing
5568 + constraints may need updating. */
5570 +move_minipool_fix_forward_ref (Mnode * mp, Mnode * max_mp,
5571 + HOST_WIDE_INT max_address)
5573 + /* This should never be true and the code below assumes these are
5578 + if (max_mp == NULL)
5580 + if (max_address < mp->max_address)
5581 + mp->max_address = max_address;
5585 + if (max_address > max_mp->max_address - mp->fix_size)
5586 + mp->max_address = max_mp->max_address - mp->fix_size;
5588 + mp->max_address = max_address;
5590 + /* Unlink MP from its current position. Since max_mp is non-null,
5591 + mp->prev must be non-null. */
5592 + mp->prev->next = mp->next;
5593 + if (mp->next != NULL)
5594 + mp->next->prev = mp->prev;
5596 + minipool_vector_tail = mp->prev;
5598 + /* Re-insert it before MAX_MP. */
5599 + mp->next = max_mp;
5600 + mp->prev = max_mp->prev;
5601 + max_mp->prev = mp;
5603 + if (mp->prev != NULL)
5604 + mp->prev->next = mp;
5606 + minipool_vector_head = mp;
5609 + /* Save the new entry. */
5612 + /* Scan over the preceding entries and adjust their addresses as required.
5614 + while (mp->prev != NULL
5615 + && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5617 + mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5624 +/* Add a constant to the minipool for a forward reference. Returns the
5625 + node added or NULL if the constant will not fit in this pool. */
5627 +add_minipool_forward_ref (Mfix * fix)
5629 + /* If set, max_mp is the first pool_entry that has a lower constraint than
5630 + the one we are trying to add. */
5631 + Mnode *max_mp = NULL;
5632 + HOST_WIDE_INT max_address = fix->address + fix->forwards;
5635 + /* If this fix's address is greater than the address of the first entry,
5636 + then we can't put the fix in this pool. We subtract the size of the
5637 + current fix to ensure that if the table is fully packed we still have
5638 + enough room to insert this value by suffling the other fixes forwards. */
5639 + if (minipool_vector_head &&
5640 + fix->address >= minipool_vector_head->max_address - fix->fix_size)
5643 + /* Scan the pool to see if a constant with the same value has already been
5644 + added. While we are doing this, also note the location where we must
5645 + insert the constant if it doesn't already exist. */
5646 + for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5648 + if (GET_CODE (fix->value) == GET_CODE (mp->value)
5649 + && fix->mode == mp->mode
5650 + && (GET_CODE (fix->value) != CODE_LABEL
5651 + || (CODE_LABEL_NUMBER (fix->value)
5652 + == CODE_LABEL_NUMBER (mp->value)))
5653 + && rtx_equal_p (fix->value, mp->value))
5655 + /* More than one fix references this entry. */
5657 + return move_minipool_fix_forward_ref (mp, max_mp, max_address);
5660 + /* Note the insertion point if necessary. */
5661 + if (max_mp == NULL && mp->max_address > max_address)
5666 + /* The value is not currently in the minipool, so we need to create a new
5667 + entry for it. If MAX_MP is NULL, the entry will be put on the end of
5668 + the list since the placement is less constrained than any existing
5669 + entry. Otherwise, we insert the new fix before MAX_MP and, if
5670 + necessary, adjust the constraints on the other entries. */
5671 + mp = xmalloc (sizeof (*mp));
5672 + mp->fix_size = fix->fix_size;
5673 + mp->mode = fix->mode;
5674 + mp->value = fix->value;
5676 + /* Not yet required for a backwards ref. */
5677 + mp->min_address = -65536;
5679 + if (max_mp == NULL)
5681 + mp->max_address = max_address;
5683 + mp->prev = minipool_vector_tail;
5685 + if (mp->prev == NULL)
5687 + minipool_vector_head = mp;
5688 + minipool_vector_label = gen_label_rtx ();
5691 + mp->prev->next = mp;
5693 + minipool_vector_tail = mp;
5697 + if (max_address > max_mp->max_address - mp->fix_size)
5698 + mp->max_address = max_mp->max_address - mp->fix_size;
5700 + mp->max_address = max_address;
5702 + mp->next = max_mp;
5703 + mp->prev = max_mp->prev;
5704 + max_mp->prev = mp;
5705 + if (mp->prev != NULL)
5706 + mp->prev->next = mp;
5708 + minipool_vector_head = mp;
5711 + /* Save the new entry. */
5714 + /* Scan over the preceding entries and adjust their addresses as required.
5716 + while (mp->prev != NULL
5717 + && mp->prev->max_address > mp->max_address - mp->prev->fix_size)
5719 + mp->prev->max_address = mp->max_address - mp->prev->fix_size;
5727 +move_minipool_fix_backward_ref (Mnode * mp, Mnode * min_mp,
5728 + HOST_WIDE_INT min_address)
5730 + HOST_WIDE_INT offset;
5732 + /* This should never be true, and the code below assumes these are
5737 + if (min_mp == NULL)
5739 + if (min_address > mp->min_address)
5740 + mp->min_address = min_address;
5744 + /* We will adjust this below if it is too loose. */
5745 + mp->min_address = min_address;
5747 + /* Unlink MP from its current position. Since min_mp is non-null,
5748 + mp->next must be non-null. */
5749 + mp->next->prev = mp->prev;
5750 + if (mp->prev != NULL)
5751 + mp->prev->next = mp->next;
5753 + minipool_vector_head = mp->next;
5755 + /* Reinsert it after MIN_MP. */
5756 + mp->prev = min_mp;
5757 + mp->next = min_mp->next;
5758 + min_mp->next = mp;
5759 + if (mp->next != NULL)
5760 + mp->next->prev = mp;
5762 + minipool_vector_tail = mp;
5768 + for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5770 + mp->offset = offset;
5771 + if (mp->refcount > 0)
5772 + offset += mp->fix_size;
5774 + if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size)
5775 + mp->next->min_address = mp->min_address + mp->fix_size;
5781 +/* Add a constant to the minipool for a backward reference. Returns the
5782 + node added or NULL if the constant will not fit in this pool.
5784 + Note that the code for insertion for a backwards reference can be
5785 + somewhat confusing because the calculated offsets for each fix do
5786 + not take into account the size of the pool (which is still under
5789 +add_minipool_backward_ref (Mfix * fix)
5791 + /* If set, min_mp is the last pool_entry that has a lower constraint than
5792 + the one we are trying to add. */
5793 + Mnode *min_mp = NULL;
5794 + /* This can be negative, since it is only a constraint. */
5795 + HOST_WIDE_INT min_address = fix->address - fix->backwards;
5798 + /* If we can't reach the current pool from this insn, or if we can't insert
5799 + this entry at the end of the pool without pushing other fixes out of
5800 + range, then we don't try. This ensures that we can't fail later on. */
5801 + if (min_address >= minipool_barrier->address
5802 + || (minipool_vector_tail->min_address + fix->fix_size
5803 + >= minipool_barrier->address))
5806 + /* Scan the pool to see if a constant with the same value has already been
5807 + added. While we are doing this, also note the location where we must
5808 + insert the constant if it doesn't already exist. */
5809 + for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev)
5811 + if (GET_CODE (fix->value) == GET_CODE (mp->value)
5812 + && fix->mode == mp->mode
5813 + && (GET_CODE (fix->value) != CODE_LABEL
5814 + || (CODE_LABEL_NUMBER (fix->value)
5815 + == CODE_LABEL_NUMBER (mp->value)))
5816 + && rtx_equal_p (fix->value, mp->value)
5817 + /* Check that there is enough slack to move this entry to the end
5818 + of the table (this is conservative). */
5819 + && (mp->max_address
5820 + > (minipool_barrier->address
5821 + + minipool_vector_tail->offset
5822 + + minipool_vector_tail->fix_size)))
5825 + return move_minipool_fix_backward_ref (mp, min_mp, min_address);
5828 + if (min_mp != NULL)
5829 + mp->min_address += fix->fix_size;
5832 + /* Note the insertion point if necessary. */
5833 + if (mp->min_address < min_address)
5837 + else if (mp->max_address
5838 + < minipool_barrier->address + mp->offset + fix->fix_size)
5840 + /* Inserting before this entry would push the fix beyond its
5841 + maximum address (which can happen if we have re-located a
5842 + forwards fix); force the new fix to come after it. */
5844 + min_address = mp->min_address + fix->fix_size;
5849 + /* We need to create a new entry. */
5850 + mp = xmalloc (sizeof (*mp));
5851 + mp->fix_size = fix->fix_size;
5852 + mp->mode = fix->mode;
5853 + mp->value = fix->value;
5855 + mp->max_address = minipool_barrier->address + 65536;
5857 + mp->min_address = min_address;
5859 + if (min_mp == NULL)
5862 + mp->next = minipool_vector_head;
5864 + if (mp->next == NULL)
5866 + minipool_vector_tail = mp;
5867 + minipool_vector_label = gen_label_rtx ();
5870 + mp->next->prev = mp;
5872 + minipool_vector_head = mp;
5876 + mp->next = min_mp->next;
5877 + mp->prev = min_mp;
5878 + min_mp->next = mp;
5880 + if (mp->next != NULL)
5881 + mp->next->prev = mp;
5883 + minipool_vector_tail = mp;
5886 + /* Save the new entry. */
5894 + /* Scan over the following entries and adjust their offsets. */
5895 + while (mp->next != NULL)
5897 + if (mp->next->min_address < mp->min_address + mp->fix_size)
5898 + mp->next->min_address = mp->min_address + mp->fix_size;
5901 + mp->next->offset = mp->offset + mp->fix_size;
5903 + mp->next->offset = mp->offset;
5912 +assign_minipool_offsets (Mfix * barrier)
5914 + HOST_WIDE_INT offset = 0;
5917 + minipool_barrier = barrier;
5919 + for (mp = minipool_vector_head; mp != NULL; mp = mp->next)
5921 + mp->offset = offset;
5923 + if (mp->refcount > 0)
5924 + offset += mp->fix_size;
5928 +/* Print a symbolic form of X to the debug file, F. */
5930 +avr32_print_value (FILE * f, rtx x)
5932 + switch (GET_CODE (x))
5935 + fprintf (f, "0x%x", (int) INTVAL (x));
5938 + case CONST_DOUBLE:
5939 + fprintf (f, "<0x%lx,0x%lx>", (long) XWINT (x, 2), (long) XWINT (x, 3));
5942 + case CONST_VECTOR:
5947 + for (i = 0; i < CONST_VECTOR_NUNITS (x); i++)
5949 + fprintf (f, "0x%x", (int) INTVAL (CONST_VECTOR_ELT (x, i)));
5950 + if (i < (CONST_VECTOR_NUNITS (x) - 1))
5957 + case CONST_STRING:
5958 + fprintf (f, "\"%s\"", XSTR (x, 0));
5962 + fprintf (f, "`%s'", XSTR (x, 0));
5966 + fprintf (f, "L%d", INSN_UID (XEXP (x, 0)));
5970 + avr32_print_value (f, XEXP (x, 0));
5974 + avr32_print_value (f, XEXP (x, 0));
5976 + avr32_print_value (f, XEXP (x, 1));
5980 + fprintf (f, "pc");
5984 + fprintf (f, "????");
5990 +is_minipool_label (rtx label)
5992 + minipool_labels *cur_mp_label = cfun->machine->minipool_label_head;
5994 + if (GET_CODE (label) != CODE_LABEL)
5997 + while (cur_mp_label)
5999 + if (CODE_LABEL_NUMBER (label)
6000 + == CODE_LABEL_NUMBER (cur_mp_label->label))
6002 + cur_mp_label = cur_mp_label->next;
6008 +new_minipool_label (rtx label)
6010 + if (!cfun->machine->minipool_label_head)
6012 + cfun->machine->minipool_label_head =
6013 + ggc_alloc (sizeof (minipool_labels));
6014 + cfun->machine->minipool_label_tail = cfun->machine->minipool_label_head;
6015 + cfun->machine->minipool_label_head->label = label;
6016 + cfun->machine->minipool_label_head->next = 0;
6017 + cfun->machine->minipool_label_head->prev = 0;
6021 + cfun->machine->minipool_label_tail->next =
6022 + ggc_alloc (sizeof (minipool_labels));
6023 + cfun->machine->minipool_label_tail->next->label = label;
6024 + cfun->machine->minipool_label_tail->next->next = 0;
6025 + cfun->machine->minipool_label_tail->next->prev =
6026 + cfun->machine->minipool_label_tail;
6027 + cfun->machine->minipool_label_tail =
6028 + cfun->machine->minipool_label_tail->next;
6032 +/* Output the literal table */
6034 +dump_minipool (rtx scan)
6040 + fprintf (dump_file,
6041 + ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n",
6042 + INSN_UID (scan), (unsigned long) minipool_barrier->address, 4);
6044 + scan = emit_insn_after (gen_consttable_start (), scan);
6045 + scan = emit_insn_after (gen_align_4 (), scan);
6046 + scan = emit_label_after (minipool_vector_label, scan);
6047 + new_minipool_label (minipool_vector_label);
6049 + for (mp = minipool_vector_head; mp != NULL; mp = nmp)
6051 + if (mp->refcount > 0)
6055 + fprintf (dump_file,
6056 + ";; Offset %u, min %ld, max %ld ",
6057 + (unsigned) mp->offset, (unsigned long) mp->min_address,
6058 + (unsigned long) mp->max_address);
6059 + avr32_print_value (dump_file, mp->value);
6060 + fputc ('\n', dump_file);
6063 + switch (mp->fix_size)
6065 +#ifdef HAVE_consttable_4
6067 + scan = emit_insn_after (gen_consttable_4 (mp->value), scan);
6071 +#ifdef HAVE_consttable_8
6073 + scan = emit_insn_after (gen_consttable_8 (mp->value), scan);
6077 +#ifdef HAVE_consttable_16
6079 + scan = emit_insn_after (gen_consttable_16 (mp->value), scan);
6084 + /* This can happen for force-minipool entries which just are
6085 + there to force the minipool to be generate. */
6097 + minipool_vector_head = minipool_vector_tail = NULL;
6098 + scan = emit_insn_after (gen_consttable_end (), scan);
6099 + scan = emit_barrier_after (scan);
6102 +/* Return the cost of forcibly inserting a barrier after INSN. */
6104 +avr32_barrier_cost (rtx insn)
6106 + /* Basing the location of the pool on the loop depth is preferable, but at
6107 + the moment, the basic block information seems to be corrupt by this
6108 + stage of the compilation. */
6109 + int base_cost = 50;
6110 + rtx next = next_nonnote_insn (insn);
6112 + if (next != NULL && GET_CODE (next) == CODE_LABEL)
6115 + switch (GET_CODE (insn))
6118 + /* It will always be better to place the table before the label, rather
6127 + return base_cost - 10;
6130 + return base_cost + 10;
6134 +/* Find the best place in the insn stream in the range
6135 + (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier.
6136 + Create the barrier by inserting a jump and add a new fix entry for
6139 +create_fix_barrier (Mfix * fix, HOST_WIDE_INT max_address)
6141 + HOST_WIDE_INT count = 0;
6143 + rtx from = fix->insn;
6144 + rtx selected = from;
6145 + int selected_cost;
6146 + HOST_WIDE_INT selected_address;
6148 + HOST_WIDE_INT max_count = max_address - fix->address;
6149 + rtx label = gen_label_rtx ();
6151 + selected_cost = avr32_barrier_cost (from);
6152 + selected_address = fix->address;
6154 + while (from && count < max_count)
6159 + /* This code shouldn't have been called if there was a natural barrier
6161 + if (GET_CODE (from) == BARRIER)
6164 + /* Count the length of this insn. */
6165 + count += get_attr_length (from);
6167 + /* If there is a jump table, add its length. */
6168 + tmp = is_jump_table (from);
6171 + count += get_jump_table_size (tmp);
6173 + /* Jump tables aren't in a basic block, so base the cost on the
6174 + dispatch insn. If we select this location, we will still put
6175 + the pool after the table. */
6176 + new_cost = avr32_barrier_cost (from);
6178 + if (count < max_count && new_cost <= selected_cost)
6181 + selected_cost = new_cost;
6182 + selected_address = fix->address + count;
6185 + /* Continue after the dispatch table. */
6186 + from = NEXT_INSN (tmp);
6190 + new_cost = avr32_barrier_cost (from);
6192 + if (count < max_count && new_cost <= selected_cost)
6195 + selected_cost = new_cost;
6196 + selected_address = fix->address + count;
6199 + from = NEXT_INSN (from);
6202 + /* Create a new JUMP_INSN that branches around a barrier. */
6203 + from = emit_jump_insn_after (gen_jump (label), selected);
6204 + JUMP_LABEL (from) = label;
6205 + barrier = emit_barrier_after (from);
6206 + emit_label_after (label, barrier);
6208 + /* Create a minipool barrier entry for the new barrier. */
6209 + new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*new_fix));
6210 + new_fix->insn = barrier;
6211 + new_fix->address = selected_address;
6212 + new_fix->next = fix->next;
6213 + fix->next = new_fix;
6218 +/* Record that there is a natural barrier in the insn stream at
6221 +push_minipool_barrier (rtx insn, HOST_WIDE_INT address)
6223 + Mfix *fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*fix));
6226 + fix->address = address;
6229 + if (minipool_fix_head != NULL)
6230 + minipool_fix_tail->next = fix;
6232 + minipool_fix_head = fix;
6234 + minipool_fix_tail = fix;
6237 +/* Record INSN, which will need fixing up to load a value from the
6238 + minipool. ADDRESS is the offset of the insn since the start of the
6239 + function; LOC is a pointer to the part of the insn which requires
6240 + fixing; VALUE is the constant that must be loaded, which is of type
6243 +push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx * loc,
6244 + enum machine_mode mode, rtx value)
6246 + Mfix *fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*fix));
6247 + rtx body = PATTERN (insn);
6250 + fix->address = address;
6253 + fix->fix_size = MINIPOOL_FIX_SIZE (mode, value);
6254 + fix->value = value;
6256 + if (GET_CODE (body) == PARALLEL)
6258 + /* Mcall : Ks16 << 2 */
6259 + fix->forwards = ((1 << 15) - 1) << 2;
6260 + fix->backwards = (1 << 15) << 2;
6262 + else if (GET_CODE (body) == SET
6263 + && GET_MODE_SIZE (GET_MODE (SET_DEST (body))) == 4)
6266 + if (TARGET_HARD_FLOAT
6267 + && GET_MODE_CLASS (GET_MODE (SET_DEST (body))) == MODE_FLOAT)
6269 + /* Ldc0.w : Ku12 << 2 */
6270 + fix->forwards = ((1 << 12) - 1) << 2;
6271 + fix->backwards = 0;
6275 + if (optimize_size)
6277 + /* Lddpc : Ku7 << 2 */
6278 + fix->forwards = ((1 << 7) - 1) << 2;
6279 + fix->backwards = 0;
6284 + fix->forwards = ((1 << 15) - 4);
6285 + fix->backwards = (1 << 15);
6289 + else if (GET_CODE (body) == SET
6290 + && GET_MODE_SIZE (GET_MODE (SET_DEST (body))) == 8)
6292 + /* Double word load */
6293 + if (TARGET_HARD_FLOAT
6294 + && GET_MODE_CLASS (GET_MODE (SET_DEST (body))) == MODE_FLOAT)
6296 + /* Ldc0.d : Ku12 << 2 */
6297 + fix->forwards = ((1 << 12) - 1) << 2;
6298 + fix->backwards = 0;
6303 + fix->forwards = ((1 << 15) - 4);
6304 + fix->backwards = (1 << 15);
6307 + else if (GET_CODE (body) == UNSPEC_VOLATILE
6308 + && XINT (body, 1) == VUNSPEC_MVRC)
6310 + /* Coprocessor load */
6311 + /* Ldc : Ku8 << 2 */
6312 + fix->forwards = ((1 << 8) - 1) << 2;
6313 + fix->backwards = 0;
6317 + /* Assume worst case which is lddpc insn. */
6318 + fix->forwards = ((1 << 7) - 1) << 2;
6319 + fix->backwards = 0;
6322 + fix->minipool = NULL;
6324 + /* If an insn doesn't have a range defined for it, then it isn't expecting
6325 + to be reworked by this code. Better to abort now than to generate duff
6327 + if (fix->forwards == 0 && fix->backwards == 0)
6332 + fprintf (dump_file,
6333 + ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ",
6334 + GET_MODE_NAME (mode),
6335 + INSN_UID (insn), (unsigned long) address,
6336 + -1 * (long) fix->backwards, (long) fix->forwards);
6337 + avr32_print_value (dump_file, fix->value);
6338 + fprintf (dump_file, "\n");
6341 + /* Add it to the chain of fixes. */
6344 + if (minipool_fix_head != NULL)
6345 + minipool_fix_tail->next = fix;
6347 + minipool_fix_head = fix;
6349 + minipool_fix_tail = fix;
6352 +/* Scan INSN and note any of its operands that need fixing.
6353 + If DO_PUSHES is false we do not actually push any of the fixups
6354 + needed. The function returns TRUE is any fixups were needed/pushed.
6355 + This is used by avr32_memory_load_p() which needs to know about loads
6356 + of constants that will be converted into minipool loads. */
6358 +note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes)
6360 + bool result = false;
6363 + extract_insn (insn);
6365 + if (!constrain_operands (1))
6366 + fatal_insn_not_found (insn);
6368 + if (recog_data.n_alternatives == 0)
6371 + /* Fill in recog_op_alt with information about the constraints of this
6373 + preprocess_constraints ();
6375 + for (opno = 0; opno < recog_data.n_operands; opno++)
6379 + /* Things we need to fix can only occur in inputs. */
6380 + if (recog_data.operand_type[opno] != OP_IN)
6383 + op = recog_data.operand[opno];
6385 + if (avr32_const_pool_ref_operand (op, GET_MODE (op)))
6389 + rtx cop = avoid_constant_pool_reference (op);
6391 + /* Casting the address of something to a mode narrower than a
6392 + word can cause avoid_constant_pool_reference() to return the
6393 + pool reference itself. That's no good to us here. Lets
6394 + just hope that we can use the constant pool value directly.
6397 + cop = get_pool_constant (XEXP (op, 0));
6399 + push_minipool_fix (insn, address,
6400 + recog_data.operand_loc[opno],
6401 + recog_data.operand_mode[opno], cop);
6406 + else if (TARGET_HAS_ASM_ADDR_PSEUDOS
6407 + && avr32_address_operand (op, GET_MODE (op)))
6409 + /* Handle pseudo instructions using a direct address. These pseudo
6410 + instructions might need entries in the constant pool and we must
6411 + therefor create a constant pool for them, in case the
6412 + assembler/linker needs to insert entries. */
6415 + /* Push a dummy constant pool entry so that the .cpool
6416 + directive should be inserted on the appropriate place in the
6417 + code even if there are no real constant pool entries. This
6418 + is used by the assembler and linker to know where to put
6419 + generated constant pool entries. */
6420 + push_minipool_fix (insn, address,
6421 + recog_data.operand_loc[opno],
6422 + recog_data.operand_mode[opno],
6423 + gen_rtx_UNSPEC (VOIDmode,
6424 + gen_rtvec (1, const0_rtx),
6425 + UNSPEC_FORCE_MINIPOOL));
6435 +avr32_insn_is_cast (rtx insn)
6438 + if (NONJUMP_INSN_P (insn)
6439 + && GET_CODE (PATTERN (insn)) == SET
6440 + && (GET_CODE (SET_SRC (PATTERN (insn))) == ZERO_EXTEND
6441 + || GET_CODE (SET_SRC (PATTERN (insn))) == SIGN_EXTEND)
6442 + && REG_P (XEXP (SET_SRC (PATTERN (insn)), 0))
6443 + && REG_P (SET_DEST (PATTERN (insn))))
6449 + Replace all occurances of reg FROM with reg TO in X */
6452 +avr32_replace_reg (rtx x, rtx from, rtx to)
6457 + gcc_assert ( REG_P (from) && REG_P (to) );
6459 + /* Allow this function to make replacements in EXPR_LISTs. */
6463 + if (rtx_equal_p (x, from))
6466 + if (GET_CODE (x) == SUBREG)
6468 + rtx new = avr32_replace_reg (SUBREG_REG (x), from, to);
6470 + if (GET_CODE (new) == CONST_INT)
6472 + x = simplify_subreg (GET_MODE (x), new,
6473 + GET_MODE (SUBREG_REG (x)),
6478 + SUBREG_REG (x) = new;
6482 + else if (GET_CODE (x) == ZERO_EXTEND)
6484 + rtx new = avr32_replace_reg (XEXP (x, 0), from, to);
6486 + if (GET_CODE (new) == CONST_INT)
6488 + x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
6489 + new, GET_MODE (XEXP (x, 0)));
6493 + XEXP (x, 0) = new;
6498 + fmt = GET_RTX_FORMAT (GET_CODE (x));
6499 + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
6501 + if (fmt[i] == 'e')
6502 + XEXP (x, i) = avr32_replace_reg (XEXP (x, i), from, to);
6503 + else if (fmt[i] == 'E')
6504 + for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6505 + XVECEXP (x, i, j) = avr32_replace_reg (XVECEXP (x, i, j), from, to);
6512 +/* FIXME: The level of nesting in this function is way too deep. It needs to be
6515 +avr32_reorg_optimization (void)
6517 + rtx first = get_first_nonnote_insn ();
6520 + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
6523 + /* Scan through all insns looking for cast operations. */
6526 + fprintf (dump_file, ";; Deleting redundant cast operations:\n");
6528 + for (insn = first; insn; insn = NEXT_INSN (insn))
6530 + rtx reg, src_reg, scan;
6531 + enum machine_mode mode;
6535 + if (avr32_insn_is_cast (insn)
6536 + && (GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == QImode
6537 + || GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == HImode))
6539 + mode = GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0));
6540 + reg = SET_DEST (PATTERN (insn));
6541 + src_reg = XEXP (SET_SRC (PATTERN (insn)), 0);
6548 + unused_cast = false;
6549 + label_ref = NULL_RTX;
6550 + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan))
6552 + /* Check if we have reached the destination of a simple
6553 + conditional jump which we have already scanned past. If so,
6554 + we can safely continue scanning. */
6555 + if (LABEL_P (scan) && label_ref != NULL_RTX)
6557 + if (CODE_LABEL_NUMBER (scan) ==
6558 + CODE_LABEL_NUMBER (XEXP (label_ref, 0)))
6559 + label_ref = NULL_RTX;
6564 + if (!INSN_P (scan))
6567 + /* For conditional jumps we can manage to keep on scanning if
6568 + we meet the destination label later on before any new jump
6570 + if (GET_CODE (scan) == JUMP_INSN)
6572 + if (any_condjump_p (scan) && label_ref == NULL_RTX)
6573 + label_ref = condjump_label (scan);
6578 + /* Check if we have a call and the register is used as an argument. */
6580 + && find_reg_fusage (scan, USE, reg) )
6583 + if (!reg_mentioned_p (reg, PATTERN (scan)))
6586 + /* Check if casted register is used in this insn */
6587 + if ((regno_use_in (REGNO (reg), PATTERN (scan)) != NULL_RTX)
6588 + && (GET_MODE (regno_use_in (REGNO (reg), PATTERN (scan))) ==
6591 + /* If not used in the source to the set or in a memory
6592 + expression in the destiantion then the register is used
6593 + as a destination and is really dead. */
6594 + if (single_set (scan)
6595 + && GET_CODE (PATTERN (scan)) == SET
6596 + && REG_P (SET_DEST (PATTERN (scan)))
6597 + && !regno_use_in (REGNO (reg), SET_SRC (PATTERN (scan)))
6598 + && label_ref == NULL_RTX)
6600 + unused_cast = true;
6605 + /* Check if register is dead or set in this insn */
6606 + if (dead_or_set_p (scan, reg))
6608 + unused_cast = true;
6613 + /* Check if we have unresolved conditional jumps */
6614 + if (label_ref != NULL_RTX)
6619 + if (REGNO (reg) == REGNO (XEXP (SET_SRC (PATTERN (insn)), 0)))
6621 + /* One operand cast, safe to delete */
6624 + fprintf (dump_file,
6625 + ";; INSN %i removed, casted register %i value not used.\n",
6626 + INSN_UID (insn), REGNO (reg));
6628 + SET_INSN_DELETED (insn);
6629 + /* Force the instruction to be recognized again */
6630 + INSN_CODE (insn) = -1;
6634 + /* Two operand cast, which really could be substituted with
6635 + a move, if the source register is dead after the cast
6636 + insn and then the insn which sets the source register
6637 + could instead directly set the destination register for
6638 + the cast. As long as there are no insns in between which
6639 + uses the register. */
6640 + rtx link = NULL_RTX;
6642 + rtx src_reg = XEXP (SET_SRC (PATTERN (insn)), 0);
6643 + unused_cast = false;
6645 + if (!find_reg_note (insn, REG_DEAD, src_reg))
6648 + /* Search for the insn which sets the source register */
6649 + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1))
6651 + if (REG_NOTE_KIND (link) != 0)
6653 + set = single_set (XEXP (link, 0));
6654 + if (set && rtx_equal_p (src_reg, SET_DEST (set)))
6656 + link = XEXP (link, 0);
6661 + /* Found no link or link is a call insn where we can not
6662 + change the destination register */
6663 + if (link == NULL_RTX || CALL_P (link))
6666 + /* Scan through all insn between link and insn */
6667 + for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan))
6669 + /* Don't try to trace forward past a CODE_LABEL if we
6670 + haven't seen INSN yet. Ordinarily, we will only
6671 + find the setting insn in LOG_LINKS if it is in the
6672 + same basic block. However, cross-jumping can insert
6673 + code labels in between the load and the call, and
6674 + can result in situations where a single call insn
6675 + may have two targets depending on where we came
6678 + if (GET_CODE (scan) == CODE_LABEL)
6681 + if (!INSN_P (scan))
6684 + /* Don't try to trace forward past a JUMP. To optimize
6685 + safely, we would have to check that all the
6686 + instructions at the jump destination did not use REG.
6689 + if (GET_CODE (scan) == JUMP_INSN)
6694 + if (!reg_mentioned_p (src_reg, PATTERN (scan)))
6697 + /* We have reached the cast insn */
6700 + /* We can remove cast and replace the destination
6701 + register of the link insn with the destination
6705 + fprintf (dump_file,
6706 + ";; INSN %i removed, casted value unused. "
6707 + "Destination of removed cast operation: register %i, folded into INSN %i.\n",
6708 + INSN_UID (insn), REGNO (reg),
6711 + /* Update link insn */
6712 + SET_DEST (PATTERN (link)) =
6713 + gen_rtx_REG (mode, REGNO (reg));
6714 + /* Force the instruction to be recognized again */
6715 + INSN_CODE (link) = -1;
6718 + SET_INSN_DELETED (insn);
6719 + /* Force the instruction to be recognized again */
6720 + INSN_CODE (insn) = -1;
6729 + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
6732 + /* Scan through all insns looking for shifted add operations */
6735 + fprintf (dump_file,
6736 + ";; Deleting redundant shifted add operations:\n");
6738 + for (insn = first; insn; insn = NEXT_INSN (insn))
6740 + rtx reg, mem_expr, scan, op0, op1;
6741 + int add_only_used_as_pointer;
6744 + && GET_CODE (PATTERN (insn)) == SET
6745 + && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS
6746 + && (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == MULT
6747 + || GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == ASHIFT)
6748 + && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1)) ==
6749 + CONST_INT && REG_P (SET_DEST (PATTERN (insn)))
6750 + && REG_P (XEXP (SET_SRC (PATTERN (insn)), 1))
6751 + && REG_P (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0)))
6753 + reg = SET_DEST (PATTERN (insn));
6754 + mem_expr = SET_SRC (PATTERN (insn));
6755 + op0 = XEXP (XEXP (mem_expr, 0), 0);
6756 + op1 = XEXP (mem_expr, 1);
6763 + /* Scan forward the check if the result of the shifted add
6764 + operation is only used as an address in memory operations and
6765 + that the operands to the shifted add are not clobbered. */
6766 + add_only_used_as_pointer = false;
6767 + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan))
6769 + if (!INSN_P (scan))
6772 + /* Don't try to trace forward past a JUMP or CALL. To optimize
6773 + safely, we would have to check that all the instructions at
6774 + the jump destination did not use REG. */
6776 + if (GET_CODE (scan) == JUMP_INSN)
6781 + /* If used in a call insn then we cannot optimize it away */
6782 + if (CALL_P (scan) && find_regno_fusage (scan, USE, REGNO (reg)))
6785 + /* If any of the operands of the shifted add are clobbered we
6786 + cannot optimize the shifted adda away */
6787 + if ((reg_set_p (op0, scan) && (REGNO (op0) != REGNO (reg)))
6788 + || (reg_set_p (op1, scan) && (REGNO (op1) != REGNO (reg))))
6791 + if (!reg_mentioned_p (reg, PATTERN (scan)))
6794 + /* If used any other place than as a pointer or as the
6795 + destination register we failed */
6796 + if (!(single_set (scan)
6797 + && GET_CODE (PATTERN (scan)) == SET
6798 + && ((MEM_P (SET_DEST (PATTERN (scan)))
6799 + && REG_P (XEXP (SET_DEST (PATTERN (scan)), 0))
6800 + && REGNO (XEXP (SET_DEST (PATTERN (scan)), 0)) == REGNO (reg))
6801 + || (MEM_P (SET_SRC (PATTERN (scan)))
6802 + && REG_P (XEXP (SET_SRC (PATTERN (scan)), 0))
6804 + (SET_SRC (PATTERN (scan)), 0)) == REGNO (reg))))
6805 + && !(GET_CODE (PATTERN (scan)) == SET
6806 + && REG_P (SET_DEST (PATTERN (scan)))
6807 + && !regno_use_in (REGNO (reg),
6808 + SET_SRC (PATTERN (scan)))))
6811 + /* We cannot replace the pointer in TImode insns
6812 + as these has a differene addressing mode than the other
6814 + if ( GET_MODE (SET_DEST (PATTERN (scan))) == TImode )
6817 + /* Check if register is dead or set in this insn */
6818 + if (dead_or_set_p (scan, reg))
6820 + add_only_used_as_pointer = true;
6825 + if (add_only_used_as_pointer)
6827 + /* Lets delete the add insn and replace all memory references
6828 + which uses the pointer with the full expression. */
6831 + fprintf (dump_file,
6832 + ";; Deleting INSN %i since address expression can be folded into all "
6833 + "memory references using this expression\n",
6836 + SET_INSN_DELETED (insn);
6837 + /* Force the instruction to be recognized again */
6838 + INSN_CODE (insn) = -1;
6840 + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan))
6842 + if (!INSN_P (scan))
6845 + if (!reg_mentioned_p (reg, PATTERN (scan)))
6848 + /* If used any other place than as a pointer or as the
6849 + destination register we failed */
6850 + if ((single_set (scan)
6851 + && GET_CODE (PATTERN (scan)) == SET
6852 + && ((MEM_P (SET_DEST (PATTERN (scan)))
6853 + && REG_P (XEXP (SET_DEST (PATTERN (scan)), 0))
6854 + && REGNO (XEXP (SET_DEST (PATTERN (scan)), 0)) ==
6855 + REGNO (reg)) || (MEM_P (SET_SRC (PATTERN (scan)))
6858 + (SET_SRC (PATTERN (scan)),
6862 + (SET_SRC (PATTERN (scan)),
6863 + 0)) == REGNO (reg)))))
6867 + fprintf (dump_file,
6868 + ";; Register %i replaced by indexed address in INSN %i\n",
6869 + REGNO (reg), INSN_UID (scan));
6871 + if (MEM_P (SET_DEST (PATTERN (scan))))
6872 + XEXP (SET_DEST (PATTERN (scan)), 0) = mem_expr;
6874 + XEXP (SET_SRC (PATTERN (scan)), 0) = mem_expr;
6877 + /* Check if register is dead or set in this insn */
6878 + if (dead_or_set_p (scan, reg))
6889 + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0)))
6892 + /* Scan through all insns looking for conditional register to
6893 + register move operations */
6896 + fprintf (dump_file,
6897 + ";; Folding redundant conditional move operations:\n");
6899 + for (insn = first; insn; insn = next_nonnote_insn (insn))
6901 + rtx src_reg, dst_reg, scan, test;
6904 + && GET_CODE (PATTERN (insn)) == COND_EXEC
6905 + && GET_CODE (COND_EXEC_CODE (PATTERN (insn))) == SET
6906 + && REG_P (SET_SRC (COND_EXEC_CODE (PATTERN (insn))))
6907 + && REG_P (SET_DEST (COND_EXEC_CODE (PATTERN (insn))))
6908 + && find_reg_note (insn, REG_DEAD, SET_SRC (COND_EXEC_CODE (PATTERN (insn)))))
6910 + src_reg = SET_SRC (COND_EXEC_CODE (PATTERN (insn)));
6911 + dst_reg = SET_DEST (COND_EXEC_CODE (PATTERN (insn)));
6912 + test = COND_EXEC_TEST (PATTERN (insn));
6919 + /* Scan backward through the rest of insns in this if-then or if-else
6920 + block and check if we can fold the move into another of the conditional
6921 + insns in the same block. */
6922 + scan = prev_nonnote_insn (insn);
6923 + while (INSN_P (scan)
6924 + && GET_CODE (PATTERN (scan)) == COND_EXEC
6925 + && rtx_equal_p (COND_EXEC_TEST (PATTERN (scan)), test))
6927 + rtx pattern = COND_EXEC_CODE (PATTERN (scan));
6928 + if ( GET_CODE (pattern) == PARALLEL )
6929 + pattern = XVECEXP (pattern, 0, 0);
6931 + if ( reg_set_p (src_reg, pattern) )
6933 + /* Fold in the destination register for the cond. move
6934 + into this insn. */
6935 + SET_DEST (pattern) = dst_reg;
6938 + fprintf (dump_file,
6939 + ";; Deleting INSN %i since this operation can be folded into INSN %i\n",
6940 + INSN_UID (insn), INSN_UID (scan));
6943 + /* Scan and check if any of the insns in between uses the src_reg. We
6944 + must then replace it with the dst_reg. */
6945 + while ( (scan = next_nonnote_insn (scan)) != insn ){
6946 + avr32_replace_reg (scan, src_reg, dst_reg);
6948 + /* Delete the insn. */
6949 + SET_INSN_DELETED (insn);
6951 + /* Force the instruction to be recognized again */
6952 + INSN_CODE (insn) = -1;
6956 + /* If the destination register is used but not set in this insn
6957 + we cannot fold. */
6958 + if ( reg_mentioned_p (dst_reg, pattern) )
6961 + scan = prev_nonnote_insn (scan);
6968 +/* Exported to toplev.c.
6970 + Do a final pass over the function, just before delayed branch
6977 + HOST_WIDE_INT address = 0;
6980 + minipool_fix_head = minipool_fix_tail = NULL;
6982 + /* The first insn must always be a note, or the code below won't scan it
6984 + insn = get_insns ();
6985 + if (GET_CODE (insn) != NOTE)
6988 + /* Scan all the insns and record the operands that will need fixing. */
6989 + for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn))
6991 + if (GET_CODE (insn) == BARRIER)
6992 + push_minipool_barrier (insn, address);
6993 + else if (INSN_P (insn))
6997 + note_invalid_constants (insn, address, true);
6998 + address += get_attr_length (insn);
7000 + /* If the insn is a vector jump, add the size of the table and skip
7002 + if ((table = is_jump_table (insn)) != NULL)
7004 + address += get_jump_table_size (table);
7010 + fix = minipool_fix_head;
7012 + /* Now scan the fixups and perform the required changes. */
7017 + Mfix *last_added_fix;
7018 + Mfix *last_barrier = NULL;
7021 + /* Skip any further barriers before the next fix. */
7022 + while (fix && GET_CODE (fix->insn) == BARRIER)
7025 + /* No more fixes. */
7029 + last_added_fix = NULL;
7031 + for (ftmp = fix; ftmp; ftmp = ftmp->next)
7033 + if (GET_CODE (ftmp->insn) == BARRIER)
7035 + if (ftmp->address >= minipool_vector_head->max_address)
7038 + last_barrier = ftmp;
7040 + else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL)
7043 + last_added_fix = ftmp; /* Keep track of the last fix added.
7047 + /* If we found a barrier, drop back to that; any fixes that we could
7048 + have reached but come after the barrier will now go in the next
7050 + if (last_barrier != NULL)
7052 + /* Reduce the refcount for those fixes that won't go into this pool
7054 + for (fdel = last_barrier->next;
7055 + fdel && fdel != ftmp; fdel = fdel->next)
7057 + fdel->minipool->refcount--;
7058 + fdel->minipool = NULL;
7061 + ftmp = last_barrier;
7065 + /* ftmp is first fix that we can't fit into this pool and there no
7066 + natural barriers that we could use. Insert a new barrier in the
7067 + code somewhere between the previous fix and this one, and
7068 + arrange to jump around it. */
7069 + HOST_WIDE_INT max_address;
7071 + /* The last item on the list of fixes must be a barrier, so we can
7072 + never run off the end of the list of fixes without last_barrier
7077 + max_address = minipool_vector_head->max_address;
7078 + /* Check that there isn't another fix that is in range that we
7079 + couldn't fit into this pool because the pool was already too
7080 + large: we need to put the pool before such an instruction. */
7081 + if (ftmp->address < max_address)
7082 + max_address = ftmp->address;
7084 + last_barrier = create_fix_barrier (last_added_fix, max_address);
7087 + assign_minipool_offsets (last_barrier);
7091 + if (GET_CODE (ftmp->insn) != BARRIER
7092 + && ((ftmp->minipool = add_minipool_backward_ref (ftmp))
7096 + ftmp = ftmp->next;
7099 + /* Scan over the fixes we have identified for this pool, fixing them up
7100 + and adding the constants to the pool itself. */
7101 + for (this_fix = fix; this_fix && ftmp != this_fix;
7102 + this_fix = this_fix->next)
7103 + if (GET_CODE (this_fix->insn) != BARRIER
7104 + /* Do nothing for entries present just to force the insertion of
7106 + && !IS_FORCE_MINIPOOL (this_fix->value))
7108 + rtx addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode,
7109 + minipool_vector_label),
7110 + this_fix->minipool->offset);
7111 + *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
7114 + dump_minipool (last_barrier->insn);
7118 + /* Free the minipool memory. */
7119 + obstack_free (&minipool_obstack, minipool_startobj);
7121 + avr32_reorg_optimization ();
7126 + Hook for doing some final scanning of instructions. Does nothing yet...*/
7128 +avr32_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED,
7129 + rtx * opvec ATTRIBUTE_UNUSED,
7130 + int noperands ATTRIBUTE_UNUSED)
7136 +/* Function for changing the condition on the next instruction,
7137 + should be used when emmiting compare instructions and
7138 + the condition of the next instruction needs to change.
7141 +set_next_insn_cond (rtx cur_insn, rtx new_cond)
7143 + rtx next_insn = next_nonnote_insn (cur_insn);
7144 + if ((next_insn != NULL_RTX)
7145 + && (INSN_P (next_insn)))
7147 + if ((GET_CODE (PATTERN (next_insn)) == SET)
7148 + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE))
7150 + /* Branch instructions */
7151 + XEXP (SET_SRC (PATTERN (next_insn)), 0) = new_cond;
7152 + /* Force the instruction to be recognized again */
7153 + INSN_CODE (next_insn) = -1;
7156 + else if ((GET_CODE (PATTERN (next_insn)) == SET)
7157 + && avr32_comparison_operator (SET_SRC (PATTERN (next_insn)),
7158 + GET_MODE (SET_SRC (PATTERN (next_insn)))))
7160 + /* scc with no compare */
7161 + SET_SRC (PATTERN (next_insn)) = new_cond;
7162 + /* Force the instruction to be recognized again */
7163 + INSN_CODE (next_insn) = -1;
7166 + else if (GET_CODE (PATTERN (next_insn)) == COND_EXEC)
7168 + if ( GET_CODE (new_cond) == UNSPEC )
7170 + COND_EXEC_TEST (PATTERN (next_insn)) =
7171 + gen_rtx_UNSPEC (CCmode,
7173 + XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 0),
7174 + XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 1)),
7175 + XINT (new_cond, 1));
7179 + PUT_CODE(COND_EXEC_TEST (PATTERN (next_insn)), GET_CODE(new_cond));
7187 +/* Function for obtaining the condition for the next instruction
7191 +get_next_insn_cond (rtx cur_insn)
7193 + rtx next_insn = next_nonnote_insn (cur_insn);
7194 + rtx cond = NULL_RTX;
7195 + if (next_insn != NULL_RTX
7196 + && INSN_P (next_insn))
7198 + if ((GET_CODE (PATTERN (next_insn)) == SET)
7199 + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE))
7201 + /* Branch and cond if then else instructions */
7202 + cond = XEXP (SET_SRC (PATTERN (next_insn)), 0);
7204 + else if ((GET_CODE (PATTERN (next_insn)) == SET)
7205 + && avr32_comparison_operator (SET_SRC (PATTERN (next_insn)),
7206 + GET_MODE (SET_SRC (PATTERN (next_insn)))))
7208 + /* scc with no compare */
7209 + cond = SET_SRC (PATTERN (next_insn));
7211 + else if (GET_CODE (PATTERN (next_insn)) == COND_EXEC)
7213 + cond = COND_EXEC_TEST (PATTERN (next_insn));
7221 +avr32_output_cmp (rtx cond, enum machine_mode mode, rtx op0, rtx op1)
7224 + rtx new_cond = NULL_RTX;
7226 + rtx compare_pattern;
7230 + if ( GET_CODE (op0) == AND )
7231 + compare_pattern = op0;
7233 + compare_pattern = gen_rtx_COMPARE (mode, op0, op1);
7235 + new_cond = is_compare_redundant (compare_pattern, cond);
7237 + if (new_cond != NULL_RTX)
7240 + /* Check if we are inserting a bit-load instead of a compare. */
7241 + if ( GET_CODE (op0) == AND )
7243 + ops[0] = XEXP (op0, 0);
7244 + ops[1] = XEXP (op0, 1);
7245 + output_asm_insn ("bld\t%0, %p1", ops);
7249 + /* Insert compare */
7253 + output_asm_insn ("cp.b\t%0, %1", ops);
7256 + output_asm_insn ("cp.h\t%0, %1", ops);
7259 + output_asm_insn ("cp.w\t%0, %1", ops);
7262 + if (GET_CODE (op1) != REG)
7263 + output_asm_insn ("cp.w\t%0, %1\ncpc\t%m0", ops);
7265 + output_asm_insn ("cp.w\t%0, %1\ncpc\t%m0, %m1", ops);
7268 + internal_error ("Unknown comparison mode");
7276 +avr32_load_multiple_operation (rtx op,
7277 + enum machine_mode mode ATTRIBUTE_UNUSED)
7279 + int count = XVECLEN (op, 0);
7280 + unsigned int dest_regno;
7283 + int i = 1, base = 0;
7285 + if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
7288 + /* Check to see if this might be a write-back. */
7289 + if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS)
7294 + /* Now check it more carefully. */
7295 + if (GET_CODE (SET_DEST (elt)) != REG
7296 + || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG
7297 + || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT
7298 + || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4)
7302 + /* Perform a quick check so we don't blow up below. */
7304 + || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
7305 + || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG
7306 + || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != UNSPEC)
7309 + dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1)));
7310 + src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0);
7312 + for (; i < count; i++)
7314 + elt = XVECEXP (op, 0, i);
7316 + if (GET_CODE (elt) != SET
7317 + || GET_CODE (SET_DEST (elt)) != REG
7318 + || GET_MODE (SET_DEST (elt)) != SImode
7319 + || GET_CODE (SET_SRC (elt)) != UNSPEC)
7327 +avr32_store_multiple_operation (rtx op,
7328 + enum machine_mode mode ATTRIBUTE_UNUSED)
7330 + int count = XVECLEN (op, 0);
7336 + if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET)
7339 + /* Perform a quick check so we don't blow up below. */
7341 + || GET_CODE (XVECEXP (op, 0, i - 1)) != SET
7342 + || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM
7343 + || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != UNSPEC)
7346 + src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1)));
7347 + dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0);
7349 + for (; i < count; i++)
7351 + elt = XVECEXP (op, 0, i);
7353 + if (GET_CODE (elt) != SET
7354 + || GET_CODE (SET_DEST (elt)) != MEM
7355 + || GET_MODE (SET_DEST (elt)) != SImode
7356 + || GET_CODE (SET_SRC (elt)) != UNSPEC)
7364 +avr32_valid_macmac_bypass (rtx insn_out, rtx insn_in)
7366 + /* Check if they use the same accumulator */
7368 + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in))))
7377 +avr32_valid_mulmac_bypass (rtx insn_out, rtx insn_in)
7380 + Check if the mul instruction produces the accumulator for the mac
7383 + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in))))
7391 +avr32_store_bypass (rtx insn_out, rtx insn_in)
7393 + /* Only valid bypass if the output result is used as an src in the store
7394 + instruction, NOT if used as a pointer or base. */
7396 + (SET_DEST (PATTERN (insn_out)), SET_SRC (PATTERN (insn_in))))
7405 +avr32_mul_waw_bypass (rtx insn_out, rtx insn_in)
7407 + /* Check if the register holding the result from the mul instruction is
7408 + used as a result register in the input instruction. */
7410 + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in))))
7419 +avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in)
7421 + /* Check if the first loaded word in insn_out is used in insn_in. */
7423 + rtx second_loaded_reg;
7425 + /* If this is a double alu operation then the bypass is not valid */
7426 + if ((get_attr_type (insn_in) == TYPE_ALU
7427 + || get_attr_type (insn_in) == TYPE_ALU2)
7428 + && (GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (insn_out)))) > 4))
7431 + /* Get the destination register in the load */
7432 + if (!REG_P (SET_DEST (PATTERN (insn_out))))
7435 + dst_reg = SET_DEST (PATTERN (insn_out));
7436 + second_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 1);
7438 + if (!reg_mentioned_p (second_loaded_reg, PATTERN (insn_in)))
7446 +avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in)
7449 + Check if the two first loaded word in insn_out are used in insn_in. */
7451 + rtx third_loaded_reg, fourth_loaded_reg;
7453 + /* Get the destination register in the load */
7454 + if (!REG_P (SET_DEST (PATTERN (insn_out))))
7457 + dst_reg = SET_DEST (PATTERN (insn_out));
7458 + third_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 2);
7459 + fourth_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 3);
7461 + if (!reg_mentioned_p (third_loaded_reg, PATTERN (insn_in))
7462 + && !reg_mentioned_p (fourth_loaded_reg, PATTERN (insn_in)))
7473 +avr32_ifcvt_modify_test (ce_if_block_t *ce_info,
7482 + || test == NULL_RTX
7483 + || !reg_mentioned_p (cc0_rtx, test))
7486 + branch_insn = BB_END (ce_info->test_bb);
7487 + cmp_test = PATTERN(prev_nonnote_insn (branch_insn));
7489 + if (GET_CODE(cmp_test) != SET
7490 + || !CC0_P(XEXP(cmp_test, 0)) )
7493 + if ( GET_CODE(SET_SRC(cmp_test)) == COMPARE ){
7494 + compare_op0 = XEXP(SET_SRC(cmp_test), 0);
7495 + compare_op1 = XEXP(SET_SRC(cmp_test), 1);
7497 + compare_op0 = SET_SRC(cmp_test);
7498 + compare_op1 = const0_rtx;
7501 + return gen_rtx_fmt_ee (GET_CODE(test), GET_MODE (compare_op0),
7502 + compare_op0, compare_op1);
7508 +avr32_ifcvt_modify_insn (ce_if_block_t *ce_info,
7511 + int *num_true_changes){
7512 + rtx test = COND_EXEC_TEST(pattern);
7513 + rtx op = COND_EXEC_CODE(pattern);
7515 + rtx cond_exec_insn;
7516 + int inputs_set_outside_ifblock = 1;
7517 + basic_block current_bb = BLOCK_FOR_INSN (insn);
7519 + enum machine_mode mode = GET_MODE (XEXP (op, 0));
7521 + if (CC0_P(XEXP(test, 0)))
7522 + test = avr32_ifcvt_modify_test (ce_info,
7525 + pattern = gen_rtx_COND_EXEC (VOIDmode, test, op);
7527 + if ( !reload_completed )
7531 + int max_insns = MAX_CONDITIONAL_EXECUTE;
7536 + /* Check if the insn is not suitable for conditional
7538 + start_sequence ();
7539 + cond_exec_insn = emit_insn (pattern);
7540 + if ( recog_memoized (cond_exec_insn) < 0
7541 + && !no_new_pseudos )
7543 + /* Insn is not suitable for conditional execution, try
7544 + to fix it up by using an extra scratch register or
7545 + by pulling the operation outside the if-then-else
7546 + and then emiting a conditional move inside the if-then-else. */
7548 + if ( GET_CODE (op) != SET
7549 + || !REG_P (SET_DEST (op))
7550 + || GET_CODE (SET_SRC (op)) == IF_THEN_ELSE
7551 + || GET_MODE_SIZE (mode) > UNITS_PER_WORD )
7554 + /* Check if any of the input operands to the insn is set inside the
7556 + if ( current_bb->index == ce_info->then_bb->index )
7557 + start = PREV_INSN (BB_HEAD (ce_info->then_bb));
7559 + start = PREV_INSN (BB_HEAD (ce_info->else_bb));
7562 + for ( bb_insn = next_nonnote_insn (start); bb_insn != insn; bb_insn = next_nonnote_insn (bb_insn) )
7564 + rtx set = single_set (bb_insn);
7566 + if ( set && reg_mentioned_p (SET_DEST (set), SET_SRC (op)))
7568 + inputs_set_outside_ifblock = 0;
7573 + cmp_insn = prev_nonnote_insn (BB_END (ce_info->test_bb));
7576 + /* Check if we can insert more insns. */
7577 + num_insns = ( ce_info->num_then_insns +
7578 + ce_info->num_else_insns +
7579 + ce_info->num_cond_clobber_insns +
7580 + ce_info->num_extra_move_insns );
7582 + if ( ce_info->num_else_insns != 0 )
7585 + if ( num_insns >= max_insns )
7588 + /* Check if we have an instruction which might be converted to
7589 + conditional form if we give it a scratch register to clobber. */
7592 + rtx scratch_reg = gen_reg_rtx (mode);
7593 + rtx new_pattern = copy_rtx (pattern);
7594 + rtx set_src = SET_SRC (COND_EXEC_CODE (new_pattern));
7596 + rtx clobber = gen_rtx_CLOBBER (mode, scratch_reg);
7597 + rtx vec[2] = { COND_EXEC_CODE (new_pattern), clobber };
7598 + COND_EXEC_CODE (new_pattern) = gen_rtx_PARALLEL (mode, gen_rtvec_v (2, vec));
7600 + start_sequence ();
7601 + clobber_insn = emit_insn (new_pattern);
7603 + if ( recog_memoized (clobber_insn) >= 0
7604 + && ( ( GET_RTX_LENGTH (GET_CODE (set_src)) == 2
7605 + && CONST_INT_P (XEXP (set_src, 1))
7606 + && avr32_const_ok_for_constraint_p (INTVAL (XEXP (set_src, 1)), 'K', "Ks08") )
7607 + || !ce_info->else_bb
7608 + || current_bb->index == ce_info->else_bb->index ))
7611 + /* Force the insn to be recognized again. */
7612 + INSN_CODE (insn) = -1;
7614 + /* If this is the first change in this IF-block then
7615 + signal that we have made a change. */
7616 + if ( ce_info->num_cond_clobber_insns == 0
7617 + && ce_info->num_extra_move_insns == 0 )
7618 + *num_true_changes += 1;
7620 + ce_info->num_cond_clobber_insns++;
7623 + fprintf (dump_file,
7624 + "\nReplacing INSN %d with an insn using a scratch register for later ifcvt passes...\n",
7627 + return COND_EXEC_CODE (new_pattern);
7632 + if ( inputs_set_outside_ifblock )
7634 + /* Check if the insn before the cmp is an and which used
7635 + together with the cmp can be optimized into a bld. If
7636 + so then we should try to put the insn before the and
7637 + so that we can catch the bld peephole. */
7639 + rtx insn_before_cmp_insn = prev_nonnote_insn (cmp_insn);
7640 + if (insn_before_cmp_insn
7641 + && (set = single_set (insn_before_cmp_insn))
7642 + && GET_CODE (SET_SRC (set)) == AND
7643 + && one_bit_set_operand (XEXP (SET_SRC (set), 1), SImode)
7644 + /* Also make sure that the insn does not set any
7645 + of the input operands to the insn we are pulling out. */
7646 + && !reg_mentioned_p (SET_DEST (set), SET_SRC (op)) )
7647 + cmp_insn = prev_nonnote_insn (cmp_insn);
7649 + /* We can try to put the operation outside the if-then-else
7650 + blocks and insert a move. */
7651 + if ( !insn_invalid_p (insn)
7652 + /* Do not allow conditional insns to be moved outside the
7654 + && !reg_mentioned_p (cc0_rtx, insn)
7655 + /* We cannot move memory loads outside of the if-then-else
7656 + since the memory access should not be perfomed if the
7657 + condition is not met. */
7658 + && !mem_mentioned_p (SET_SRC (op)) )
7660 + rtx scratch_reg = gen_reg_rtx (mode);
7661 + rtx op_pattern = copy_rtx (op);
7662 + rtx new_insn, seq;
7663 + rtx link, prev_link;
7664 + op = copy_rtx (op);
7665 + /* Emit the operation to a temp reg before the compare,
7666 + and emit a move inside the if-then-else, hoping that the
7667 + whole if-then-else can be converted to conditional
7669 + SET_DEST (op_pattern) = scratch_reg;
7670 + start_sequence ();
7671 + new_insn = emit_insn (op_pattern);
7672 + seq = get_insns();
7675 + /* Check again that the insn is valid. For some insns the insn might
7676 + become invalid if the destination register is changed. Ie. for mulacc
7678 + if ( insn_invalid_p (new_insn) )
7681 + emit_insn_before_setloc (seq, cmp_insn, INSN_LOCATOR (insn));
7684 + fprintf (dump_file,
7685 + "\nMoving INSN %d out of IF-block by adding INSN %d...\n",
7686 + INSN_UID (insn), INSN_UID (new_insn));
7688 + ce_info->extra_move_insns[ce_info->num_extra_move_insns] = insn;
7689 + ce_info->moved_insns[ce_info->num_extra_move_insns] = new_insn;
7690 + XEXP (op, 1) = scratch_reg;
7691 + /* Force the insn to be recognized again. */
7692 + INSN_CODE (insn) = -1;
7694 + /* Move REG_DEAD notes to the moved insn. */
7695 + prev_link = NULL_RTX;
7696 + for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
7698 + if (REG_NOTE_KIND (link) == REG_DEAD)
7700 + /* Add the REG_DEAD note to the new insn. */
7701 + rtx dead_reg = XEXP (link, 0);
7702 + REG_NOTES (new_insn) = gen_rtx_EXPR_LIST (REG_DEAD, dead_reg, REG_NOTES (new_insn));
7703 + /* Remove the REG_DEAD note from the insn we convert to a move. */
7705 + XEXP (prev_link, 1) = XEXP (link, 1);
7707 + REG_NOTES (insn) = XEXP (link, 1);
7714 + /* Add a REG_DEAD note to signal that the scratch register is dead. */
7715 + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, scratch_reg, REG_NOTES (insn));
7717 + /* If this is the first change in this IF-block then
7718 + signal that we have made a change. */
7719 + if ( ce_info->num_cond_clobber_insns == 0
7720 + && ce_info->num_extra_move_insns == 0 )
7721 + *num_true_changes += 1;
7723 + ce_info->num_extra_move_insns++;
7728 + /* We failed to fixup the insns, so this if-then-else can not be made
7729 + conditional. Just return NULL_RTX so that the if-then-else conversion
7730 + for this if-then-else will be cancelled. */
7737 + /* Signal that we have started if conversion after reload, which means
7738 + that it should be safe to split all the predicable clobber insns which
7739 + did not become cond_exec back into a simpler form if possible. */
7740 + cfun->machine->ifcvt_after_reload = 1;
7747 +avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info,
7748 + int *num_true_changes)
7752 + if ( ce_info->num_extra_move_insns > 0
7753 + && ce_info->num_cond_clobber_insns == 0)
7754 + /* Signal that we did not do any changes after all. */
7755 + *num_true_changes -= 1;
7757 + /* Remove any inserted move insns. */
7758 + for ( n = 0; n < ce_info->num_extra_move_insns; n++ )
7760 + rtx link, prev_link;
7762 + /* Remove REG_DEAD note since we are not needing the scratch register anyway. */
7763 + prev_link = NULL_RTX;
7764 + for (link = REG_NOTES (ce_info->extra_move_insns[n]); link; link = XEXP (link, 1))
7766 + if (REG_NOTE_KIND (link) == REG_DEAD)
7769 + XEXP (prev_link, 1) = XEXP (link, 1);
7771 + REG_NOTES (ce_info->extra_move_insns[n]) = XEXP (link, 1);
7779 + /* Revert all reg_notes for the moved insn. */
7780 + for (link = REG_NOTES (ce_info->moved_insns[n]); link; link = XEXP (link, 1))
7782 + REG_NOTES (ce_info->extra_move_insns[n]) = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link),
7784 + REG_NOTES (ce_info->extra_move_insns[n]));
7787 + /* Remove the moved insn. */
7788 + remove_insn ( ce_info->moved_insns[n] );
7792 +/* Function returning TRUE if INSN with OPERANDS is a splittable
7793 + conditional immediate clobber insn. We assume that the insn is
7794 + already a conditional immediate clobber insns and do not check
7797 +avr32_cond_imm_clobber_splittable (rtx insn,
7800 + if ( (REGNO (operands[0]) != REGNO (operands[1]))
7801 + && (logical_binary_operator (SET_SRC (XVECEXP (PATTERN (insn),0,0)), VOIDmode)
7802 + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == PLUS
7803 + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'I', "Is16"))
7804 + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == MINUS
7805 + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks16"))) )
7811 +/* Function for getting an integer value from a const_int or const_double
7812 + expression regardless of the HOST_WIDE_INT size. Each target cpu word
7813 + will be put into the val array where the LSW will be stored at the lowest
7814 + address and so forth. Assumes that const_expr is either a const_int or
7815 + const_double. Only valid for modes which have sizes that are a multiple
7819 +avr32_get_intval (enum machine_mode mode,
7821 + HOST_WIDE_INT *val)
7823 + int words_in_mode = GET_MODE_SIZE (mode)/UNITS_PER_WORD;
7824 + const int words_in_const_int = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD;
7826 + if ( GET_CODE(const_expr) == CONST_DOUBLE ){
7827 + HOST_WIDE_INT hi = CONST_DOUBLE_HIGH(const_expr);
7828 + HOST_WIDE_INT lo = CONST_DOUBLE_LOW(const_expr);
7829 + /* Evaluate hi and lo values of const_double. */
7830 + avr32_get_intval (mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0),
7833 + avr32_get_intval (mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0),
7835 + &val[words_in_const_int]);
7836 + } else if ( GET_CODE(const_expr) == CONST_INT ){
7837 + HOST_WIDE_INT value = INTVAL(const_expr);
7839 + for ( word = 0; (word < words_in_mode) && (word < words_in_const_int); word++ ){
7840 + /* Shift word up to the MSW and shift down again to extract the
7841 + word and sign-extend. */
7842 + int lshift = (words_in_const_int - word - 1) * BITS_PER_WORD;
7843 + int rshift = (words_in_const_int-1) * BITS_PER_WORD;
7844 + val[word] = (value << lshift) >> rshift;
7847 + for ( ; word < words_in_mode; word++ ){
7848 + /* Just put the sign bits in the remaining words. */
7849 + val[word] = value < 0 ? -1 : 0;
7855 +avr32_split_const_expr (enum machine_mode mode,
7856 + enum machine_mode new_mode,
7861 + int words_in_intval = GET_MODE_SIZE (mode)/UNITS_PER_WORD;
7862 + int words_in_split_values = GET_MODE_SIZE (new_mode)/UNITS_PER_WORD;
7863 + const int words_in_const_int = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD;
7864 + HOST_WIDE_INT *val = alloca (words_in_intval * UNITS_PER_WORD);
7866 + avr32_get_intval (mode, expr, val);
7868 + for ( i=0; i < (words_in_intval/words_in_split_values); i++ )
7870 + HOST_WIDE_INT value_lo = 0, value_hi = 0;
7871 + for ( word = 0; word < words_in_split_values; word++ )
7873 + if ( word >= words_in_const_int )
7874 + value_hi |= ((val[i * words_in_split_values + word] &
7875 + (((HOST_WIDE_INT)1 << BITS_PER_WORD)-1))
7876 + << (BITS_PER_WORD * (word - words_in_const_int)));
7878 + value_lo |= ((val[i * words_in_split_values + word] &
7879 + (((HOST_WIDE_INT)1 << BITS_PER_WORD)-1))
7880 + << (BITS_PER_WORD * word));
7882 + split_expr[i] = immed_double_const(value_lo, value_hi, new_mode);
7887 +/* Set up library functions to comply to AVR32 ABI */
7890 +avr32_init_libfuncs (void)
7892 + /* Convert gcc run-time function names to AVR32 ABI names */
7894 + /* Double-precision floating-point arithmetic. */
7895 + set_optab_libfunc (neg_optab, DFmode, NULL);
7897 + /* Double-precision comparisons. */
7898 + set_optab_libfunc (eq_optab, DFmode, "__avr32_f64_cmp_eq");
7899 + set_optab_libfunc (ne_optab, DFmode, NULL);
7900 + set_optab_libfunc (lt_optab, DFmode, "__avr32_f64_cmp_lt");
7901 + set_optab_libfunc (le_optab, DFmode, NULL);
7902 + set_optab_libfunc (ge_optab, DFmode, "__avr32_f64_cmp_ge");
7903 + set_optab_libfunc (gt_optab, DFmode, NULL);
7905 + /* Single-precision floating-point arithmetic. */
7906 + set_optab_libfunc (smul_optab, SFmode, "__avr32_f32_mul");
7907 + set_optab_libfunc (neg_optab, SFmode, NULL);
7909 + /* Single-precision comparisons. */
7910 + set_optab_libfunc (eq_optab, SFmode, "__avr32_f32_cmp_eq");
7911 + set_optab_libfunc (ne_optab, SFmode, NULL);
7912 + set_optab_libfunc (lt_optab, SFmode, "__avr32_f32_cmp_lt");
7913 + set_optab_libfunc (le_optab, SFmode, NULL);
7914 + set_optab_libfunc (ge_optab, SFmode, "__avr32_f32_cmp_ge");
7915 + set_optab_libfunc (gt_optab, SFmode, NULL);
7917 + /* Floating-point to integer conversions. */
7918 + set_conv_libfunc (sfix_optab, SImode, DFmode, "__avr32_f64_to_s32");
7919 + set_conv_libfunc (ufix_optab, SImode, DFmode, "__avr32_f64_to_u32");
7920 + set_conv_libfunc (sfix_optab, DImode, DFmode, "__avr32_f64_to_s64");
7921 + set_conv_libfunc (ufix_optab, DImode, DFmode, "__avr32_f64_to_u64");
7922 + set_conv_libfunc (sfix_optab, SImode, SFmode, "__avr32_f32_to_s32");
7923 + set_conv_libfunc (ufix_optab, SImode, SFmode, "__avr32_f32_to_u32");
7924 + set_conv_libfunc (sfix_optab, DImode, SFmode, "__avr32_f32_to_s64");
7925 + set_conv_libfunc (ufix_optab, DImode, SFmode, "__avr32_f32_to_u64");
7927 + /* Conversions between floating types. */
7928 + set_conv_libfunc (trunc_optab, SFmode, DFmode, "__avr32_f64_to_f32");
7929 + set_conv_libfunc (sext_optab, DFmode, SFmode, "__avr32_f32_to_f64");
7931 + /* Integer to floating-point conversions. Table 8. */
7932 + set_conv_libfunc (sfloat_optab, DFmode, SImode, "__avr32_s32_to_f64");
7933 + set_conv_libfunc (sfloat_optab, DFmode, DImode, "__avr32_s64_to_f64");
7934 + set_conv_libfunc (sfloat_optab, SFmode, SImode, "__avr32_s32_to_f32");
7935 + set_conv_libfunc (sfloat_optab, SFmode, DImode, "__avr32_s64_to_f32");
7936 + set_conv_libfunc (ufloat_optab, DFmode, SImode, "__avr32_u32_to_f64");
7937 + set_conv_libfunc (ufloat_optab, SFmode, SImode, "__avr32_u32_to_f32");
7938 + /* TODO: Add these to gcc library functions */
7939 + //set_conv_libfunc (ufloat_optab, DFmode, DImode, NULL);
7940 + //set_conv_libfunc (ufloat_optab, SFmode, DImode, NULL);
7942 + /* Long long. Table 9. */
7943 + set_optab_libfunc (smul_optab, DImode, "__avr32_mul64");
7944 + set_optab_libfunc (sdiv_optab, DImode, "__avr32_sdiv64");
7945 + set_optab_libfunc (udiv_optab, DImode, "__avr32_udiv64");
7946 + set_optab_libfunc (smod_optab, DImode, "__avr32_smod64");
7947 + set_optab_libfunc (umod_optab, DImode, "__avr32_umod64");
7948 + set_optab_libfunc (ashl_optab, DImode, "__avr32_lsl64");
7949 + set_optab_libfunc (lshr_optab, DImode, "__avr32_lsr64");
7950 + set_optab_libfunc (ashr_optab, DImode, "__avr32_asr64");
7952 + /* Floating point library functions which have fast versions. */
7953 + if ( TARGET_FAST_FLOAT )
7955 + set_optab_libfunc (sdiv_optab, DFmode, "__avr32_f64_div_fast");
7956 + set_optab_libfunc (smul_optab, DFmode, "__avr32_f64_mul_fast");
7957 + set_optab_libfunc (add_optab, DFmode, "__avr32_f64_add_fast");
7958 + set_optab_libfunc (sub_optab, DFmode, "__avr32_f64_sub_fast");
7959 + set_optab_libfunc (add_optab, SFmode, "__avr32_f32_add_fast");
7960 + set_optab_libfunc (sub_optab, SFmode, "__avr32_f32_sub_fast");
7961 + set_optab_libfunc (sdiv_optab, SFmode, "__avr32_f32_div_fast");
7965 + set_optab_libfunc (sdiv_optab, DFmode, "__avr32_f64_div");
7966 + set_optab_libfunc (smul_optab, DFmode, "__avr32_f64_mul");
7967 + set_optab_libfunc (add_optab, DFmode, "__avr32_f64_add");
7968 + set_optab_libfunc (sub_optab, DFmode, "__avr32_f64_sub");
7969 + set_optab_libfunc (add_optab, SFmode, "__avr32_f32_add");
7970 + set_optab_libfunc (sub_optab, SFmode, "__avr32_f32_sub");
7971 + set_optab_libfunc (sdiv_optab, SFmode, "__avr32_f32_div");
7975 +++ b/gcc/config/avr32/avr32-elf.h
7978 + Elf specific definitions.
7979 + Copyright 2003-2006 Atmel Corporation.
7981 + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
7983 + This file is part of GCC.
7985 + This program is free software; you can redistribute it and/or modify
7986 + it under the terms of the GNU General Public License as published by
7987 + the Free Software Foundation; either version 2 of the License, or
7988 + (at your option) any later version.
7990 + This program is distributed in the hope that it will be useful,
7991 + but WITHOUT ANY WARRANTY; without even the implied warranty of
7992 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7993 + GNU General Public License for more details.
7995 + You should have received a copy of the GNU General Public License
7996 + along with this program; if not, write to the Free Software
7997 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
8000 +/*****************************************************************************
8001 + * Controlling the Compilator Driver, 'gcc'
8002 + *****************************************************************************/
8004 +/* Run-time Target Specification. */
8005 +#undef TARGET_VERSION
8006 +#define TARGET_VERSION fputs (" (AVR32 GNU with ELF)", stderr);
8009 +Another C string constant used much like LINK_SPEC. The
8010 +difference between the two is that STARTFILE_SPEC is used at
8011 +the very beginning of the command given to the linker.
8013 +If this macro is not defined, a default is provided that loads the
8014 +standard C startup file from the usual place. See gcc.c.
8016 +#undef STARTFILE_SPEC
8017 +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s"
8020 +#define LINK_SPEC "%{muse-oscall:--defsym __do_not_use_oscall_coproc__=0} %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}} %{mpart=uc3a3revd:-mavr32elf_uc3a3256s;:%{mpart=*:-mavr32elf_%*}} %{mcpu=*:-mavr32elf_%*}"
8024 +Another C string constant used much like LINK_SPEC. The
8025 +difference between the two is that ENDFILE_SPEC is used at
8026 +the very end of the command given to the linker.
8028 +Do not define this macro if it does not need to do anything.
8030 +#undef ENDFILE_SPEC
8031 +#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
8034 +/* Target CPU builtins. */
8035 +#define TARGET_CPU_CPP_BUILTINS() \
8038 + builtin_define ("__avr32__"); \
8039 + builtin_define ("__AVR32__"); \
8040 + builtin_define ("__AVR32_ELF__"); \
8041 + builtin_define (avr32_part->macro); \
8042 + builtin_define (avr32_arch->macro); \
8043 + if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \
8044 + builtin_define ("__AVR32_AVR32A__"); \
8046 + builtin_define ("__AVR32_AVR32B__"); \
8047 + if (TARGET_UNALIGNED_WORD) \
8048 + builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \
8049 + if (TARGET_SIMD) \
8050 + builtin_define ("__AVR32_HAS_SIMD__"); \
8052 + builtin_define ("__AVR32_HAS_DSP__"); \
8054 + builtin_define ("__AVR32_HAS_RMW__"); \
8055 + if (TARGET_BRANCH_PRED) \
8056 + builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \
8057 + if (TARGET_FAST_FLOAT) \
8058 + builtin_define ("__AVR32_FAST_FLOAT__"); \
8062 +++ b/gcc/config/avr32/avr32.h
8065 + Definitions of target machine for AVR32.
8066 + Copyright 2003-2006 Atmel Corporation.
8068 + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
8069 + Initial porting by Anders �dland.
8071 + This file is part of GCC.
8073 + This program is free software; you can redistribute it and/or modify
8074 + it under the terms of the GNU General Public License as published by
8075 + the Free Software Foundation; either version 2 of the License, or
8076 + (at your option) any later version.
8078 + This program is distributed in the hope that it will be useful,
8079 + but WITHOUT ANY WARRANTY; without even the implied warranty of
8080 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8081 + GNU General Public License for more details.
8083 + You should have received a copy of the GNU General Public License
8084 + along with this program; if not, write to the Free Software
8085 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
8087 +#ifndef GCC_AVR32_H
8088 +#define GCC_AVR32_H
8091 +#ifndef OBJECT_FORMAT_ELF
8092 +#error avr32.h included before elfos.h
8095 +#ifndef LOCAL_LABEL_PREFIX
8096 +#define LOCAL_LABEL_PREFIX "."
8099 +#ifndef SUBTARGET_CPP_SPEC
8100 +#define SUBTARGET_CPP_SPEC "-D__ELF__"
8104 +extern struct rtx_def *avr32_compare_op0;
8105 +extern struct rtx_def *avr32_compare_op1;
8108 +extern struct rtx_def *avr32_acc_cache;
8110 +/* cache instruction op5 codes */
8111 +#define AVR32_CACHE_INVALIDATE_ICACHE 1
8113 +/* These bits describe the different types of function supported
8114 + by the AVR32 backend. They are exclusive. ie a function cannot be both a
8115 + normal function and an interworked function, for example. Knowing the
8116 + type of a function is important for determining its prologue and
8117 + epilogue sequences.
8118 + Note value 7 is currently unassigned. Also note that the interrupt
8119 + function types all have bit 2 set, so that they can be tested for easily.
8120 + Note that 0 is deliberately chosen for AVR32_FT_UNKNOWN so that when the
8121 + machine_function structure is initialized (to zero) func_type will
8122 + default to unknown. This will force the first use of avr32_current_func_type
8123 + to call avr32_compute_func_type. */
8124 +#define AVR32_FT_UNKNOWN 0 /* Type has not yet been determined.
8126 +#define AVR32_FT_NORMAL 1 /* Your normal, straightforward
8128 +#define AVR32_FT_ACALL 2 /* An acall function. */
8129 +#define AVR32_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */
8130 +#define AVR32_FT_ISR_FULL 4 /* A fully shadowed interrupt mode. */
8131 +#define AVR32_FT_ISR_HALF 5 /* A half shadowed interrupt mode. */
8132 +#define AVR32_FT_ISR_NONE 6 /* No shadow registers. */
8134 +#define AVR32_FT_TYPE_MASK ((1 << 3) - 1)
8136 +/* In addition functions can have several type modifiers,
8137 + outlined by these bit masks: */
8138 +#define AVR32_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR
8140 +#define AVR32_FT_NAKED (1 << 3) /* No prologue or epilogue. */
8141 +#define AVR32_FT_VOLATILE (1 << 4) /* Does not return. */
8142 +#define AVR32_FT_NESTED (1 << 5) /* Embedded inside another
8145 +/* Some macros to test these flags. */
8146 +#define AVR32_FUNC_TYPE(t) (t & AVR32_FT_TYPE_MASK)
8147 +#define IS_INTERRUPT(t) (t & AVR32_FT_INTERRUPT)
8148 +#define IS_VOLATILE(t) (t & AVR32_FT_VOLATILE)
8149 +#define IS_NAKED(t) (t & AVR32_FT_NAKED)
8150 +#define IS_NESTED(t) (t & AVR32_FT_NESTED)
8152 +#define SYMBOL_FLAG_RMW_ADDR_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT
8153 +#define SYMBOL_REF_RMW_ADDR(RTX) \
8154 + ((SYMBOL_REF_FLAGS (RTX) & (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT)) != 0)
8157 +typedef struct minipool_labels
8158 +GTY ((chain_next ("%h.next"), chain_prev ("%h.prev")))
8161 + struct minipool_labels *prev;
8162 + struct minipool_labels *next;
8165 +/* A C structure for machine-specific, per-function data.
8166 + This is added to the cfun structure. */
8168 +typedef struct machine_function
8171 + /* Records the type of the current function. */
8172 + unsigned long func_type;
8173 + /* List of minipool labels, use for checking if code label is valid in a
8174 + memory expression */
8175 + minipool_labels *minipool_label_head;
8176 + minipool_labels *minipool_label_tail;
8177 + int ifcvt_after_reload;
8178 +} machine_function;
8180 +/* Initialize data used by insn expanders. This is called from insn_emit,
8181 + once for every function before code is generated. */
8182 +#define INIT_EXPANDERS avr32_init_expanders ()
8184 +/******************************************************************************
8186 + *****************************************************************************/
8189 +#define ASM_SPEC "%{fpic:--pic} %{mrelax|O*:%{mno-relax|O0|O1: ;:--linkrelax}} %{march=ucr2nomul:-march=ucr2;:%{march=*:-march=%*}} %{mpart=uc3a3revd:-mpart=uc3a3256s;:%{mpart=*:-mpart=%*}}"
8192 +#ifndef MULTILIB_DEFAULTS
8193 +#define MULTILIB_DEFAULTS { "march=ap", "" }
8196 +/******************************************************************************
8197 + * Run-time Target Specification
8198 + *****************************************************************************/
8199 +#ifndef TARGET_VERSION
8200 +#define TARGET_VERSION fprintf(stderr, " (AVR32, GNU assembler syntax)");
8204 +/* Part types. Keep this in sync with the order of avr32_part_types in avr32.c*/
8207 + PART_TYPE_AVR32_NONE,
8208 + PART_TYPE_AVR32_AP7000,
8209 + PART_TYPE_AVR32_AP7001,
8210 + PART_TYPE_AVR32_AP7002,
8211 + PART_TYPE_AVR32_AP7200,
8212 + PART_TYPE_AVR32_UC3A0128,
8213 + PART_TYPE_AVR32_UC3A0256,
8214 + PART_TYPE_AVR32_UC3A0512,
8215 + PART_TYPE_AVR32_UC3A0512ES,
8216 + PART_TYPE_AVR32_UC3A1128,
8217 + PART_TYPE_AVR32_UC3A1256,
8218 + PART_TYPE_AVR32_UC3A1512,
8219 + PART_TYPE_AVR32_UC3A1512ES,
8220 + PART_TYPE_AVR32_UC3A3REVD,
8221 + PART_TYPE_AVR32_UC3A364,
8222 + PART_TYPE_AVR32_UC3A364S,
8223 + PART_TYPE_AVR32_UC3A3128,
8224 + PART_TYPE_AVR32_UC3A3128S,
8225 + PART_TYPE_AVR32_UC3A3256,
8226 + PART_TYPE_AVR32_UC3A3256S,
8227 + PART_TYPE_AVR32_UC3B064,
8228 + PART_TYPE_AVR32_UC3B0128,
8229 + PART_TYPE_AVR32_UC3B0256,
8230 + PART_TYPE_AVR32_UC3B0256ES,
8231 + PART_TYPE_AVR32_UC3B164,
8232 + PART_TYPE_AVR32_UC3B1128,
8233 + PART_TYPE_AVR32_UC3B1256,
8234 + PART_TYPE_AVR32_UC3B1256ES
8237 +/* Microarchitectures. */
8238 +enum microarchitecture_type
8240 + UARCH_TYPE_AVR32A,
8241 + UARCH_TYPE_AVR32B,
8245 +/* Architectures types which specifies the pipeline.
8246 + Keep this in sync with avr32_arch_types in avr32.c
8247 + and the pipeline attribute in avr32.md */
8248 +enum architecture_type
8250 + ARCH_TYPE_AVR32_AP,
8251 + ARCH_TYPE_AVR32_UCR1,
8252 + ARCH_TYPE_AVR32_UCR2,
8253 + ARCH_TYPE_AVR32_UCR2NOMUL,
8254 + ARCH_TYPE_AVR32_NONE
8257 +/* Flag specifying if the cpu has support for DSP instructions.*/
8258 +#define FLAG_AVR32_HAS_DSP (1 << 0)
8259 +/* Flag specifying if the cpu has support for Read-Modify-Write
8261 +#define FLAG_AVR32_HAS_RMW (1 << 1)
8262 +/* Flag specifying if the cpu has support for SIMD instructions. */
8263 +#define FLAG_AVR32_HAS_SIMD (1 << 2)
8264 +/* Flag specifying if the cpu has support for unaligned memory word access. */
8265 +#define FLAG_AVR32_HAS_UNALIGNED_WORD (1 << 3)
8266 +/* Flag specifying if the cpu has support for branch prediction. */
8267 +#define FLAG_AVR32_HAS_BRANCH_PRED (1 << 4)
8268 +/* Flag specifying if the cpu has support for a return stack. */
8269 +#define FLAG_AVR32_HAS_RETURN_STACK (1 << 5)
8270 +/* Flag specifying if the cpu has caches. */
8271 +#define FLAG_AVR32_HAS_CACHES (1 << 6)
8272 +/* Flag specifying if the cpu has support for v2 insns. */
8273 +#define FLAG_AVR32_HAS_V2_INSNS (1 << 7)
8274 +/* Flag specifying that the cpu has buggy mul insns. */
8275 +#define FLAG_AVR32_HAS_NO_MUL_INSNS (1 << 8)
8277 +/* Structure for holding information about different avr32 CPUs/parts */
8280 + const char *const name;
8281 + enum part_type part_type;
8282 + enum architecture_type arch_type;
8283 + /* Must lie outside user's namespace. NULL == no macro. */
8284 + const char *const macro;
8287 +/* Structure for holding information about different avr32 pipeline
8291 + const char *const name;
8292 + enum architecture_type arch_type;
8293 + enum microarchitecture_type uarch_type;
8294 + const unsigned long feature_flags;
8295 + /* Must lie outside user's namespace. NULL == no macro. */
8296 + const char *const macro;
8299 +extern const struct part_type_s *avr32_part;
8300 +extern const struct arch_type_s *avr32_arch;
8302 +#define TARGET_SIMD (avr32_arch->feature_flags & FLAG_AVR32_HAS_SIMD)
8303 +#define TARGET_DSP (avr32_arch->feature_flags & FLAG_AVR32_HAS_DSP)
8304 +#define TARGET_RMW (avr32_arch->feature_flags & FLAG_AVR32_HAS_RMW)
8305 +#define TARGET_UNALIGNED_WORD (avr32_arch->feature_flags & FLAG_AVR32_HAS_UNALIGNED_WORD)
8306 +#define TARGET_BRANCH_PRED (avr32_arch->feature_flags & FLAG_AVR32_HAS_BRANCH_PRED)
8307 +#define TARGET_RETURN_STACK (avr32_arch->feature_flags & FLAG_AVR32_HAS_RETURN_STACK)
8308 +#define TARGET_V2_INSNS (avr32_arch->feature_flags & FLAG_AVR32_HAS_V2_INSNS)
8309 +#define TARGET_CACHES (avr32_arch->feature_flags & FLAG_AVR32_HAS_CACHES)
8310 +#define TARGET_NO_MUL_INSNS (avr32_arch->feature_flags & FLAG_AVR32_HAS_NO_MUL_INSNS)
8311 +#define TARGET_ARCH_AP (avr32_arch->arch_type == ARCH_TYPE_AVR32_AP)
8312 +#define TARGET_ARCH_UCR1 (avr32_arch->arch_type == ARCH_TYPE_AVR32_UCR1)
8313 +#define TARGET_ARCH_UCR2 (avr32_arch->arch_type == ARCH_TYPE_AVR32_UCR2)
8314 +#define TARGET_ARCH_UC (TARGET_ARCH_UCR1 || TARGET_ARCH_UCR2)
8315 +#define TARGET_UARCH_AVR32A (avr32_arch->uarch_type == UARCH_TYPE_AVR32A)
8316 +#define TARGET_UARCH_AVR32B (avr32_arch->uarch_type == UARCH_TYPE_AVR32B)
8318 +#define CAN_DEBUG_WITHOUT_FP
8323 +/******************************************************************************
8325 + *****************************************************************************/
8328 +Define this macro to have the value 1 if the most significant bit in a
8329 +byte has the lowest number; otherwise define it to have the value zero.
8330 +This means that bit-field instructions count from the most significant
8331 +bit. If the machine has no bit-field instructions, then this must still
8332 +be defined, but it doesn't matter which value it is defined to. This
8333 +macro need not be a constant.
8335 +This macro does not affect the way structure fields are packed into
8336 +bytes or words; that is controlled by BYTES_BIG_ENDIAN.
8338 +#define BITS_BIG_ENDIAN 0
8341 +Define this macro to have the value 1 if the most significant byte in a
8342 +word has the lowest number. This macro need not be a constant.
8345 + Data is stored in an big-endian way.
8347 +#define BYTES_BIG_ENDIAN 1
8350 +Define this macro to have the value 1 if, in a multiword object, the
8351 +most significant word has the lowest number. This applies to both
8352 +memory locations and registers; GCC fundamentally assumes that the
8353 +order of words in memory is the same as the order in registers. This
8354 +macro need not be a constant.
8357 + Data is stored in an bin-endian way.
8359 +#define WORDS_BIG_ENDIAN 1
8362 +Define this macro if WORDS_BIG_ENDIAN is not constant. This must be a
8363 +constant value with the same meaning as WORDS_BIG_ENDIAN, which will be
8364 +used only when compiling libgcc2.c. Typically the value will be set
8365 +based on preprocessor defines.
8367 +#define LIBGCC2_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN
8370 +Define this macro to have the value 1 if DFmode, XFmode or
8371 +TFmode floating point numbers are stored in memory with the word
8372 +containing the sign bit at the lowest address; otherwise define it to
8373 +have the value 0. This macro need not be a constant.
8375 +You need not define this macro if the ordering is the same as for
8376 +multi-word integers.
8378 +/* #define FLOAT_WORDS_BIG_ENDIAN 1 */
8381 +Define this macro to be the number of bits in an addressable storage
8382 +unit (byte); normally 8.
8384 +#define BITS_PER_UNIT 8
8387 +Number of bits in a word; normally 32.
8389 +#define BITS_PER_WORD 32
8392 +Maximum number of bits in a word. If this is undefined, the default is
8393 +BITS_PER_WORD. Otherwise, it is the constant value that is the
8394 +largest value that BITS_PER_WORD can have at run-time.
8396 +/* MAX_BITS_PER_WORD not defined*/
8399 +Number of storage units in a word; normally 4.
8401 +#define UNITS_PER_WORD 4
8404 +Minimum number of units in a word. If this is undefined, the default is
8405 +UNITS_PER_WORD. Otherwise, it is the constant value that is the
8406 +smallest value that UNITS_PER_WORD can have at run-time.
8408 +/* MIN_UNITS_PER_WORD not defined */
8411 +Width of a pointer, in bits. You must specify a value no wider than the
8412 +width of Pmode. If it is not equal to the width of Pmode,
8413 +you must define POINTERS_EXTEND_UNSIGNED.
8415 +#define POINTER_SIZE 32
8418 +A C expression whose value is greater than zero if pointers that need to be
8419 +extended from being POINTER_SIZE bits wide to Pmode are to
8420 +be zero-extended and zero if they are to be sign-extended. If the value
8421 +is less then zero then there must be an "ptr_extend" instruction that
8422 +extends a pointer from POINTER_SIZE to Pmode.
8424 +You need not define this macro if the POINTER_SIZE is equal
8425 +to the width of Pmode.
8427 +/* #define POINTERS_EXTEND_UNSIGNED */
8430 +A Macro to update M and UNSIGNEDP when an object whose type
8431 +is TYPE and which has the specified mode and signedness is to be
8432 +stored in a register. This macro is only called when TYPE is a
8435 +On most RISC machines, which only have operations that operate on a full
8436 +register, define this macro to set M to word_mode if
8437 +M is an integer mode narrower than BITS_PER_WORD. In most
8438 +cases, only integer modes should be widened because wider-precision
8439 +floating-point operations are usually more expensive than their narrower
8442 +For most machines, the macro definition does not change UNSIGNEDP.
8443 +However, some machines, have instructions that preferentially handle
8444 +either signed or unsigned quantities of certain modes. For example, on
8445 +the DEC Alpha, 32-bit loads from memory and 32-bit add instructions
8446 +sign-extend the result to 64 bits. On such machines, set
8447 +UNSIGNEDP according to which kind of extension is more efficient.
8449 +Do not define this macro if it would never modify M.
8451 +#define PROMOTE_MODE(M, UNSIGNEDP, TYPE) \
8453 + if (GET_MODE_CLASS (M) == MODE_INT \
8454 + && GET_MODE_SIZE (M) < 4) \
8456 + if (M == QImode) \
8458 + else if (M == SImode) \
8464 +#define PROMOTE_FUNCTION_MODE(M, UNSIGNEDP, TYPE) \
8466 + if (GET_MODE_CLASS (M) == MODE_INT \
8467 + && GET_MODE_SIZE (M) < 4) \
8473 +/* Define if operations between registers always perform the operation
8474 + on the full register even if a narrower mode is specified. */
8475 +#define WORD_REGISTER_OPERATIONS
8477 +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
8478 + will either zero-extend or sign-extend. The value of this macro should
8479 + be the code that says which one of the two operations is implicitly
8480 + done, UNKNOWN if not known. */
8481 +#define LOAD_EXTEND_OP(MODE) \
8482 + (((MODE) == QImode) ? ZERO_EXTEND \
8483 + : ((MODE) == HImode) ? SIGN_EXTEND : UNKNOWN)
8487 +Define this macro if the promotion described by PROMOTE_MODE
8488 +should only be performed for outgoing function arguments or
8489 +function return values, as specified by PROMOTE_FUNCTION_ARGS
8490 +and PROMOTE_FUNCTION_RETURN, respectively.
8492 +/* #define PROMOTE_FOR_CALL_ONLY */
8495 +Normal alignment required for function parameters on the stack, in
8496 +bits. All stack parameters receive at least this much alignment
8497 +regardless of data type. On most machines, this is the same as the
8498 +size of an integer.
8500 +#define PARM_BOUNDARY 32
8503 +Define this macro to the minimum alignment enforced by hardware for the
8504 +stack pointer on this machine. The definition is a C expression for the
8505 +desired alignment (measured in bits). This value is used as a default
8506 +if PREFERRED_STACK_BOUNDARY is not defined. On most machines,
8507 +this should be the same as PARM_BOUNDARY.
8509 +#define STACK_BOUNDARY 32
8512 +Define this macro if you wish to preserve a certain alignment for the
8513 +stack pointer, greater than what the hardware enforces. The definition
8514 +is a C expression for the desired alignment (measured in bits). This
8515 +macro must evaluate to a value equal to or larger than
8518 +#define PREFERRED_STACK_BOUNDARY (TARGET_FORCE_DOUBLE_ALIGN ? 64 : 32 )
8521 +Alignment required for a function entry point, in bits.
8523 +#define FUNCTION_BOUNDARY 16
8526 +Biggest alignment that any data type can require on this machine, in bits.
8528 +#define BIGGEST_ALIGNMENT (TARGET_FORCE_DOUBLE_ALIGN ? 64 : 32 )
8531 +If defined, the smallest alignment, in bits, that can be given to an
8532 +object that can be referenced in one operation, without disturbing any
8533 +nearby object. Normally, this is BITS_PER_UNIT, but may be larger
8534 +on machines that don't have byte or half-word store operations.
8536 +#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT
8540 +An integer expression for the size in bits of the largest integer machine mode that
8541 +should actually be used. All integer machine modes of this size or smaller can be
8542 +used for structures and unions with the appropriate sizes. If this macro is undefined,
8543 +GET_MODE_BITSIZE (DImode) is assumed.*/
8544 +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode)
8548 +If defined, a C expression to compute the alignment given to a constant
8549 +that is being placed in memory. CONSTANT is the constant and
8550 +BASIC_ALIGN is the alignment that the object would ordinarily
8551 +have. The value of this macro is used instead of that alignment to
8554 +If this macro is not defined, then BASIC_ALIGN is used.
8556 +The typical use of this macro is to increase alignment for string
8557 +constants to be word aligned so that strcpy calls that copy
8558 +constants can be done inline.
8560 +#define CONSTANT_ALIGNMENT(CONSTANT, BASIC_ALIGN) \
8561 + ((TREE_CODE(CONSTANT) == STRING_CST) ? BITS_PER_WORD : BASIC_ALIGN)
8563 +/* Try to align string to a word. */
8564 +#define DATA_ALIGNMENT(TYPE, ALIGN) \
8565 + ({(TREE_CODE (TYPE) == ARRAY_TYPE \
8566 + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
8567 + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN));})
8569 +/* Try to align local store strings to a word. */
8570 +#define LOCAL_ALIGNMENT(TYPE, ALIGN) \
8571 + ({(TREE_CODE (TYPE) == ARRAY_TYPE \
8572 + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
8573 + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN));})
8576 +Define this macro to be the value 1 if instructions will fail to work
8577 +if given data not on the nominal alignment. If instructions will merely
8578 +go slower in that case, define this macro as 0.
8580 +#define STRICT_ALIGNMENT 1
8583 +Define this if you wish to imitate the way many other C compilers handle
8584 +alignment of bit-fields and the structures that contain them.
8586 +The behavior is that the type written for a bit-field (int,
8587 +short, or other integer type) imposes an alignment for the
8588 +entire structure, as if the structure really did contain an ordinary
8589 +field of that type. In addition, the bit-field is placed within the
8590 +structure so that it would fit within such a field, not crossing a
8593 +Thus, on most machines, a bit-field whose type is written as int
8594 +would not cross a four-byte boundary, and would force four-byte
8595 +alignment for the whole structure. (The alignment used may not be four
8596 +bytes; it is controlled by the other alignment parameters.)
8598 +If the macro is defined, its definition should be a C expression;
8599 +a nonzero value for the expression enables this behavior.
8601 +Note that if this macro is not defined, or its value is zero, some
8602 +bit-fields may cross more than one alignment boundary. The compiler can
8603 +support such references if there are insv, extv, and
8604 +extzv insns that can directly reference memory.
8606 +The other known way of making bit-fields work is to define
8607 +STRUCTURE_SIZE_BOUNDARY as large as BIGGEST_ALIGNMENT.
8608 +Then every structure can be accessed with fullwords.
8610 +Unless the machine has bit-field instructions or you define
8611 +STRUCTURE_SIZE_BOUNDARY that way, you must define
8612 +PCC_BITFIELD_TYPE_MATTERS to have a nonzero value.
8614 +If your aim is to make GCC use the same conventions for laying out
8615 +bit-fields as are used by another compiler, here is how to investigate
8616 +what the other compiler does. Compile and run this program:
8634 + printf ("Size of foo1 is %d\n",
8635 + sizeof (struct foo1));
8636 + printf ("Size of foo2 is %d\n",
8637 + sizeof (struct foo2));
8641 +If this prints 2 and 5, then the compiler's behavior is what you would
8642 +get from PCC_BITFIELD_TYPE_MATTERS.
8644 +#define PCC_BITFIELD_TYPE_MATTERS 1
8647 +/******************************************************************************
8648 + * Layout of Source Language Data Types
8649 + *****************************************************************************/
8652 +A C expression for the size in bits of the type int on the
8653 +target machine. If you don't define this, the default is one word.
8655 +#define INT_TYPE_SIZE 32
8658 +A C expression for the size in bits of the type short on the
8659 +target machine. If you don't define this, the default is half a word. (If
8660 +this would be less than one storage unit, it is rounded up to one unit.)
8662 +#define SHORT_TYPE_SIZE 16
8665 +A C expression for the size in bits of the type long on the
8666 +target machine. If you don't define this, the default is one word.
8668 +#define LONG_TYPE_SIZE 32
8672 +A C expression for the size in bits of the type long long on the
8673 +target machine. If you don't define this, the default is two
8674 +words. If you want to support GNU Ada on your machine, the value of this
8675 +macro must be at least 64.
8677 +#define LONG_LONG_TYPE_SIZE 64
8680 +A C expression for the size in bits of the type char on the
8681 +target machine. If you don't define this, the default is
8684 +#define CHAR_TYPE_SIZE 8
8688 +A C expression for the size in bits of the C++ type bool and
8689 +C99 type _Bool on the target machine. If you don't define
8690 +this, and you probably shouldn't, the default is CHAR_TYPE_SIZE.
8692 +#define BOOL_TYPE_SIZE 8
8696 +An expression whose value is 1 or 0, according to whether the type
8697 +char should be signed or unsigned by default. The user can
8698 +always override this default with the options -fsigned-char
8699 +and -funsigned-char.
8701 +/* We are using unsigned char */
8702 +#define DEFAULT_SIGNED_CHAR 0
8706 +A C expression for a string describing the name of the data type to use
8707 +for size values. The typedef name size_t is defined using the
8708 +contents of the string.
8710 +The string can contain more than one keyword. If so, separate them with
8711 +spaces, and write first any length keyword, then unsigned if
8712 +appropriate, and finally int. The string must exactly match one
8713 +of the data type names defined in the function
8714 +init_decl_processing in the file c-decl.c. You may not
8715 +omit int or change the order - that would cause the compiler to
8718 +If you don't define this macro, the default is "long unsigned int".
8720 +#define SIZE_TYPE "long unsigned int"
8723 +A C expression for a string describing the name of the data type to use
8724 +for the result of subtracting two pointers. The typedef name
8725 +ptrdiff_t is defined using the contents of the string. See
8726 +SIZE_TYPE above for more information.
8728 +If you don't define this macro, the default is "long int".
8730 +#define PTRDIFF_TYPE "long int"
8734 +A C expression for the size in bits of the data type for wide
8735 +characters. This is used in cpp, which cannot make use of
8738 +#define WCHAR_TYPE_SIZE 32
8742 +A C expression for a string describing the name of the data type to
8743 +use for wide characters passed to printf and returned from
8744 +getwc. The typedef name wint_t is defined using the
8745 +contents of the string. See SIZE_TYPE above for more
8748 +If you don't define this macro, the default is "unsigned int".
8750 +#define WINT_TYPE "unsigned int"
8753 +A C expression for a string describing the name of the data type that
8754 +can represent any value of any standard or extended signed integer type.
8755 +The typedef name intmax_t is defined using the contents of the
8756 +string. See SIZE_TYPE above for more information.
8758 +If you don't define this macro, the default is the first of
8759 +"int", "long int", or "long long int" that has as
8760 +much precision as long long int.
8762 +#define INTMAX_TYPE "long long int"
8765 +A C expression for a string describing the name of the data type that
8766 +can represent any value of any standard or extended unsigned integer
8767 +type. The typedef name uintmax_t is defined using the contents
8768 +of the string. See SIZE_TYPE above for more information.
8770 +If you don't define this macro, the default is the first of
8771 +"unsigned int", "long unsigned int", or "long long unsigned int"
8772 +that has as much precision as long long unsigned int.
8774 +#define UINTMAX_TYPE "long long unsigned int"
8777 +/******************************************************************************
8779 + *****************************************************************************/
8781 +/* Convert from gcc internal register number to register number
8782 + used in assembly code */
8783 +#define ASM_REGNUM(reg) (LAST_REGNUM - (reg))
8784 +#define ASM_FP_REGNUM(reg) (LAST_FP_REGNUM - (reg))
8786 +/* Convert between register number used in assembly to gcc
8787 + internal register number */
8788 +#define INTERNAL_REGNUM(reg) (LAST_REGNUM - (reg))
8789 +#define INTERNAL_FP_REGNUM(reg) (LAST_FP_REGNUM - (reg))
8791 +/** Basic Characteristics of Registers **/
8794 +Number of hardware registers known to the compiler. They receive
8795 +numbers 0 through FIRST_PSEUDO_REGISTER-1; thus, the first
8796 +pseudo register's number really is assigned the number
8797 +FIRST_PSEUDO_REGISTER.
8799 +#define FIRST_PSEUDO_REGISTER (LAST_FP_REGNUM + 1)
8801 +#define FIRST_REGNUM 0
8802 +#define LAST_REGNUM 15
8803 +#define NUM_FP_REGS 16
8804 +#define FIRST_FP_REGNUM 16
8805 +#define LAST_FP_REGNUM (16+NUM_FP_REGS-1)
8808 +An initializer that says which registers are used for fixed purposes
8809 +all throughout the compiled code and are therefore not available for
8810 +general allocation. These would include the stack pointer, the frame
8811 +pointer (except on machines where that can be used as a general
8812 +register when no frame pointer is needed), the program counter on
8813 +machines where that is considered one of the addressable registers,
8814 +and any other numbered register with a standard use.
8816 +This information is expressed as a sequence of numbers, separated by
8817 +commas and surrounded by braces. The nth number is 1 if
8818 +register n is fixed, 0 otherwise.
8820 +The table initialized from this macro, and the table initialized by
8821 +the following one, may be overridden at run time either automatically,
8822 +by the actions of the macro CONDITIONAL_REGISTER_USAGE, or by
8823 +the user with the command options -ffixed-[reg],
8824 +-fcall-used-[reg] and -fcall-saved-[reg].
8827 +/* The internal gcc register numbers are reversed
8828 + compared to the real register numbers since
8829 + gcc expects data types stored over multiple
8830 + registers in the register file to be big endian
8831 + if the memory layout is big endian. But this
8832 + is not the case for avr32 so we fake a big
8833 + endian register file. */
8835 +#define FIXED_REGISTERS { \
8836 + 1, /* Program Counter */ \
8837 + 0, /* Link Register */ \
8838 + 1, /* Stack Pointer */ \
8871 +Like FIXED_REGISTERS but has 1 for each register that is
8872 +clobbered (in general) by function calls as well as for fixed
8873 +registers. This macro therefore identifies the registers that are not
8874 +available for general allocation of values that must live across
8877 +If a register has 0 in CALL_USED_REGISTERS, the compiler
8878 +automatically saves it on function entry and restores it on function
8879 +exit, if the register is used within the function.
8881 +#define CALL_USED_REGISTERS { \
8882 + 1, /* Program Counter */ \
8883 + 0, /* Link Register */ \
8884 + 1, /* Stack Pointer */ \
8916 +/* Interrupt functions can only use registers that have already been
8917 + saved by the prologue, even if they would normally be
8918 + call-clobbered. */
8919 +#define HARD_REGNO_RENAME_OK(SRC, DST) \
8920 + (! IS_INTERRUPT (cfun->machine->func_type) || \
8921 + regs_ever_live[DST])
8925 +Zero or more C statements that may conditionally modify five variables
8926 +fixed_regs, call_used_regs, global_regs,
8927 +reg_names, and reg_class_contents, to take into account
8928 +any dependence of these register sets on target flags. The first three
8929 +of these are of type char [] (interpreted as Boolean vectors).
8930 +global_regs is a const char *[], and
8931 +reg_class_contents is a HARD_REG_SET. Before the macro is
8932 +called, fixed_regs, call_used_regs,
8933 +reg_class_contents, and reg_names have been initialized
8934 +from FIXED_REGISTERS, CALL_USED_REGISTERS,
8935 +REG_CLASS_CONTENTS, and REGISTER_NAMES, respectively.
8936 +global_regs has been cleared, and any -ffixed-[reg],
8937 +-fcall-used-[reg] and -fcall-saved-[reg]
8938 +command options have been applied.
8940 +You need not define this macro if it has no work to do.
8942 +If the usage of an entire class of registers depends on the target
8943 +flags, you may indicate this to GCC by using this macro to modify
8944 +fixed_regs and call_used_regs to 1 for each of the
8945 +registers in the classes which should not be used by GCC. Also define
8946 +the macro REG_CLASS_FROM_LETTER to return NO_REGS if it
8947 +is called with a letter for a class that shouldn't be used.
8949 + (However, if this class is not included in GENERAL_REGS and all
8950 +of the insn patterns whose constraints permit this class are
8951 +controlled by target switches, then GCC will automatically avoid using
8952 +these registers when the target switches are opposed to them.)
8954 +#define CONDITIONAL_REGISTER_USAGE \
8959 + if (TARGET_SOFT_FLOAT) \
8961 + for (regno = FIRST_FP_REGNUM; \
8962 + regno <= LAST_FP_REGNUM; ++regno) \
8963 + fixed_regs[regno] = call_used_regs[regno] = 1; \
8967 + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
8968 + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
8975 +If the program counter has a register number, define this as that
8976 +register number. Otherwise, do not define it.
8979 +#define LAST_AVR32_REGNUM 16
8982 +/** Order of Allocation of Registers **/
8985 +If defined, an initializer for a vector of integers, containing the
8986 +numbers of hard registers in the order in which GCC should prefer
8987 +to use them (from most preferred to least).
8989 +If this macro is not defined, registers are used lowest numbered first
8990 +(all else being equal).
8992 +One use of this macro is on machines where the highest numbered
8993 +registers must always be saved and the save-multiple-registers
8994 +instruction supports only sequences of consecutive registers. On such
8995 +machines, define REG_ALLOC_ORDER to be an initializer that lists
8996 +the highest numbered allocable register first.
8998 +#define REG_ALLOC_ORDER \
9000 + INTERNAL_REGNUM(8), \
9001 + INTERNAL_REGNUM(9), \
9002 + INTERNAL_REGNUM(10), \
9003 + INTERNAL_REGNUM(11), \
9004 + INTERNAL_REGNUM(12), \
9006 + INTERNAL_REGNUM(7), \
9007 + INTERNAL_REGNUM(6), \
9008 + INTERNAL_REGNUM(5), \
9009 + INTERNAL_REGNUM(4), \
9010 + INTERNAL_REGNUM(3), \
9011 + INTERNAL_REGNUM(2), \
9012 + INTERNAL_REGNUM(1), \
9013 + INTERNAL_REGNUM(0), \
9014 + INTERNAL_FP_REGNUM(15), \
9015 + INTERNAL_FP_REGNUM(14), \
9016 + INTERNAL_FP_REGNUM(13), \
9017 + INTERNAL_FP_REGNUM(12), \
9018 + INTERNAL_FP_REGNUM(11), \
9019 + INTERNAL_FP_REGNUM(10), \
9020 + INTERNAL_FP_REGNUM(9), \
9021 + INTERNAL_FP_REGNUM(8), \
9022 + INTERNAL_FP_REGNUM(7), \
9023 + INTERNAL_FP_REGNUM(6), \
9024 + INTERNAL_FP_REGNUM(5), \
9025 + INTERNAL_FP_REGNUM(4), \
9026 + INTERNAL_FP_REGNUM(3), \
9027 + INTERNAL_FP_REGNUM(2), \
9028 + INTERNAL_FP_REGNUM(1), \
9029 + INTERNAL_FP_REGNUM(0), \
9035 +/** How Values Fit in Registers **/
9038 +A C expression for the number of consecutive hard registers, starting
9039 +at register number REGNO, required to hold a value of mode
9042 +On a machine where all registers are exactly one word, a suitable
9043 +definition of this macro is
9045 +#define HARD_REGNO_NREGS(REGNO, MODE) \
9046 + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \
9049 +#define HARD_REGNO_NREGS(REGNO, MODE) \
9050 + ((unsigned int)((GET_MODE_SIZE(MODE) + UNITS_PER_WORD -1 ) / UNITS_PER_WORD))
9053 +A C expression that is nonzero if it is permissible to store a value
9054 +of mode MODE in hard register number REGNO (or in several
9055 +registers starting with that one). For a machine where all registers
9056 +are equivalent, a suitable definition is
9058 + #define HARD_REGNO_MODE_OK(REGNO, MODE) 1
9060 +You need not include code to check for the numbers of fixed registers,
9061 +because the allocation mechanism considers them to be always occupied.
9063 +On some machines, double-precision values must be kept in even/odd
9064 +register pairs. You can implement that by defining this macro to reject
9065 +odd register numbers for such modes.
9067 +The minimum requirement for a mode to be OK in a register is that the
9068 +mov[mode] instruction pattern support moves between the
9069 +register and other hard register in the same class and that moving a
9070 +value into the register and back out not alter it.
9072 +Since the same instruction used to move word_mode will work for
9073 +all narrower integer modes, it is not necessary on any machine for
9074 +HARD_REGNO_MODE_OK to distinguish between these modes, provided
9075 +you define patterns movhi, etc., to take advantage of this. This
9076 +is useful because of the interaction between HARD_REGNO_MODE_OK
9077 +and MODES_TIEABLE_P; it is very desirable for all integer modes
9080 +Many machines have special registers for floating point arithmetic.
9081 +Often people assume that floating point machine modes are allowed only
9082 +in floating point registers. This is not true. Any registers that
9083 +can hold integers can safely hold a floating point machine
9084 +mode, whether or not floating arithmetic can be done on it in those
9085 +registers. Integer move instructions can be used to move the values.
9087 +On some machines, though, the converse is true: fixed-point machine
9088 +modes may not go in floating registers. This is true if the floating
9089 +registers normalize any value stored in them, because storing a
9090 +non-floating value there would garble it. In this case,
9091 +HARD_REGNO_MODE_OK should reject fixed-point machine modes in
9092 +floating registers. But if the floating registers do not automatically
9093 +normalize, if you can store any bit pattern in one and retrieve it
9094 +unchanged without a trap, then any machine mode may go in a floating
9095 +register, so you can define this macro to say so.
9097 +The primary significance of special floating registers is rather that
9098 +they are the registers acceptable in floating point arithmetic
9099 +instructions. However, this is of no concern to
9100 +HARD_REGNO_MODE_OK. You handle it by writing the proper
9101 +constraints for those instructions.
9103 +On some machines, the floating registers are especially slow to access,
9104 +so that it is better to store a value in a stack frame than in such a
9105 +register if floating point arithmetic is not being done. As long as the
9106 +floating registers are not in class GENERAL_REGS, they will not
9107 +be used unless some pattern's constraint asks for one.
9109 +#define HARD_REGNO_MODE_OK(REGNO, MODE) avr32_hard_regno_mode_ok(REGNO, MODE)
9112 +A C expression that is nonzero if a value of mode
9113 +MODE1 is accessible in mode MODE2 without copying.
9115 +If HARD_REGNO_MODE_OK(R, MODE1) and
9116 +HARD_REGNO_MODE_OK(R, MODE2) are always the same for
9117 +any R, then MODES_TIEABLE_P(MODE1, MODE2)
9118 +should be nonzero. If they differ for any R, you should define
9119 +this macro to return zero unless some other mechanism ensures the
9120 +accessibility of the value in a narrower mode.
9122 +You should define this macro to return nonzero in as many cases as
9123 +possible since doing so will allow GCC to perform better register
9126 +#define MODES_TIEABLE_P(MODE1, MODE2) \
9127 + (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
9131 +/******************************************************************************
9132 + * Register Classes
9133 + *****************************************************************************/
9136 +An enumeral type that must be defined with all the register class names
9137 +as enumeral values. NO_REGS must be first. ALL_REGS
9138 +must be the last register class, followed by one more enumeral value,
9139 +LIM_REG_CLASSES, which is not a register class but rather
9140 +tells how many classes there are.
9142 +Each register class has a number, which is the value of casting
9143 +the class name to type int. The number serves as an index
9144 +in many of the tables described below.
9156 +The number of distinct register classes, defined as follows:
9157 + #define N_REG_CLASSES (int) LIM_REG_CLASSES
9159 +#define N_REG_CLASSES (int)LIM_REG_CLASSES
9162 +An initializer containing the names of the register classes as C string
9163 +constants. These names are used in writing some of the debugging dumps.
9165 +#define REG_CLASS_NAMES \
9169 + "FLOATING_POINT_REGS", \
9174 +An initializer containing the contents of the register classes, as integers
9175 +which are bit masks. The nth integer specifies the contents of class
9176 +n. The way the integer mask is interpreted is that
9177 +register r is in the class if mask & (1 << r) is 1.
9179 +When the machine has more than 32 registers, an integer does not suffice.
9180 +Then the integers are replaced by sub-initializers, braced groupings containing
9181 +several integers. Each sub-initializer must be suitable as an initializer
9182 +for the type HARD_REG_SET which is defined in hard-reg-set.h.
9183 +In this situation, the first integer in each sub-initializer corresponds to
9184 +registers 0 through 31, the second integer to registers 32 through 63, and
9187 +#define REG_CLASS_CONTENTS { \
9188 + {0x00000000}, /* NO_REGS */ \
9189 + {0x0000FFFF}, /* GENERAL_REGS */ \
9190 + {0xFFFF0000}, /* FP_REGS */ \
9191 + {0x7FFFFFFF}, /* ALL_REGS */ \
9196 +A C expression whose value is a register class containing hard register
9197 +REGNO. In general there is more than one such class; choose a class
9198 +which is minimal, meaning that no smaller class also contains the
9201 +#define REGNO_REG_CLASS(REGNO) ((REGNO < 16) ? GENERAL_REGS : FP_REGS)
9204 +A macro whose definition is the name of the class to which a valid
9205 +base register must belong. A base register is one used in an address
9206 +which is the register value plus a displacement.
9208 +#define BASE_REG_CLASS GENERAL_REGS
9211 +This is a variation of the BASE_REG_CLASS macro which allows
9212 +the selection of a base register in a mode depenedent manner. If
9213 +mode is VOIDmode then it should return the same value as
9216 +#define MODE_BASE_REG_CLASS(MODE) BASE_REG_CLASS
9219 +A macro whose definition is the name of the class to which a valid
9220 +index register must belong. An index register is one used in an
9221 +address where its value is either multiplied by a scale factor or
9222 +added to another register (as well as added to a displacement).
9224 +#define INDEX_REG_CLASS BASE_REG_CLASS
9227 +A C expression which defines the machine-dependent operand constraint
9228 +letters for register classes. If CHAR is such a letter, the
9229 +value should be the register class corresponding to it. Otherwise,
9230 +the value should be NO_REGS. The register letter r,
9231 +corresponding to class GENERAL_REGS, will not be passed
9232 +to this macro; you do not need to handle it.
9234 +#define REG_CLASS_FROM_LETTER(CHAR) ((CHAR) == 'f' ? FP_REGS : NO_REGS)
9237 +/* These assume that REGNO is a hard or pseudo reg number.
9238 + They give nonzero only if REGNO is a hard reg of the suitable class
9239 + or a pseudo reg currently allocated to a suitable hard reg.
9240 + Since they use reg_renumber, they are safe only once reg_renumber
9241 + has been allocated, which happens in local-alloc.c. */
9242 +#define TEST_REGNO(R, TEST, VALUE) \
9243 + ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE))
9246 +A C expression which is nonzero if register number num is suitable for use as a base
9247 +register in operand addresses. It may be either a suitable hard register or a pseudo
9248 +register that has been allocated such a hard register.
9250 +#define REGNO_OK_FOR_BASE_P(NUM) TEST_REGNO(NUM, <=, LAST_REGNUM)
9253 +A C expression which is nonzero if register number NUM is
9254 +suitable for use as an index register in operand addresses. It may be
9255 +either a suitable hard register or a pseudo register that has been
9256 +allocated such a hard register.
9258 +The difference between an index register and a base register is that
9259 +the index register may be scaled. If an address involves the sum of
9260 +two registers, neither one of them scaled, then either one may be
9261 +labeled the ``base'' and the other the ``index''; but whichever
9262 +labeling is used must fit the machine's constraints of which registers
9263 +may serve in each capacity. The compiler will try both labelings,
9264 +looking for one that is valid, and will reload one or both registers
9265 +only if neither labeling works.
9267 +#define REGNO_OK_FOR_INDEX_P(NUM) TEST_REGNO(NUM, <=, LAST_REGNUM)
9270 +A C expression that places additional restrictions on the register class
9271 +to use when it is necessary to copy value X into a register in class
9272 +CLASS. The value is a register class; perhaps CLASS, or perhaps
9273 +another, smaller class. On many machines, the following definition is
9274 +safe: #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS
9276 +Sometimes returning a more restrictive class makes better code. For
9277 +example, on the 68000, when X is an integer constant that is in range
9278 +for a 'moveq' instruction, the value of this macro is always
9279 +DATA_REGS as long as CLASS includes the data registers.
9280 +Requiring a data register guarantees that a 'moveq' will be used.
9282 +If X is a const_double, by returning NO_REGS
9283 +you can force X into a memory constant. This is useful on
9284 +certain machines where immediate floating values cannot be loaded into
9285 +certain kinds of registers.
9287 +#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
9292 +A C expression for the maximum number of consecutive registers
9293 +of class CLASS needed to hold a value of mode MODE.
9295 +This is closely related to the macro HARD_REGNO_NREGS. In fact,
9296 +the value of the macro CLASS_MAX_NREGS(CLASS, MODE)
9297 +should be the maximum value of HARD_REGNO_NREGS(REGNO, MODE)
9298 +for all REGNO values in the class CLASS.
9300 +This macro helps control the handling of multiple-word values
9301 +in the reload pass.
9303 +#define CLASS_MAX_NREGS(CLASS, MODE) /* ToDo:fixme */ \
9304 + (unsigned int)((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
9308 + Using CONST_OK_FOR_CONSTRAINT_P instead of CONS_OK_FOR_LETTER_P
9309 + in order to support constraints with more than one letter.
9310 + Only two letters are then used for constant constraints,
9311 + the letter 'K' and the letter 'I'. The constraint starting with
9312 + these letters must consist of four characters. The character following
9313 + 'K' or 'I' must be either 'u' (unsigned) or 's' (signed) to specify
9314 + if the constant is zero or sign extended. The last two characters specify
9315 + the length in bits of the constant. The base constraint letter 'I' means
9316 + that this is an negated constant, meaning that actually -VAL should be
9317 + checked to lie withing the valid range instead of VAL which is used when
9318 + 'K' is the base constraint letter.
9322 +#define CONSTRAINT_LEN(C, STR) \
9323 + ( ((C) == 'K' || (C) == 'I') ? 4 : \
9324 + ((C) == 'R') ? 5 : \
9325 + ((C) == 'P') ? -1 : \
9326 + DEFAULT_CONSTRAINT_LEN((C), (STR)) )
9328 +#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
9329 + avr32_const_ok_for_constraint_p(VALUE, C, STR)
9332 +A C expression that defines the machine-dependent operand constraint
9333 +letters that specify particular ranges of const_double values ('G' or 'H').
9335 +If C is one of those letters, the expression should check that
9336 +VALUE, an RTX of code const_double, is in the appropriate
9337 +range and return 1 if so, 0 otherwise. If C is not one of those
9338 +letters, the value should be 0 regardless of VALUE.
9340 +const_double is used for all floating-point constants and for
9341 +DImode fixed-point constants. A given letter can accept either
9342 +or both kinds of values. It can use GET_MODE to distinguish
9343 +between these kinds.
9345 +#define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \
9346 + ((C) == 'G' ? avr32_const_double_immediate(OP) : 0)
9349 +A C expression that defines the optional machine-dependent constraint
9350 +letters that can be used to segregate specific types of operands, usually
9351 +memory references, for the target machine. Any letter that is not
9352 +elsewhere defined and not matched by REG_CLASS_FROM_LETTER
9353 +may be used. Normally this macro will not be defined.
9355 +If it is required for a particular target machine, it should return 1
9356 +if VALUE corresponds to the operand type represented by the
9357 +constraint letter C. If C is not defined as an extra
9358 +constraint, the value returned should be 0 regardless of VALUE.
9360 +For example, on the ROMP, load instructions cannot have their output
9361 +in r0 if the memory reference contains a symbolic address. Constraint
9362 +letter 'Q' is defined as representing a memory address that does
9363 +not contain a symbolic address. An alternative is specified with
9364 +a 'Q' constraint on the input and 'r' on the output. The next
9365 +alternative specifies 'm' on the input and a register class that
9366 +does not include r0 on the output.
9368 +#define EXTRA_CONSTRAINT_STR(OP, C, STR) \
9369 + ((C) == 'W' ? avr32_address_operand(OP, GET_MODE(OP)) : \
9370 + (C) == 'R' ? (avr32_indirect_register_operand(OP, GET_MODE(OP)) || \
9371 + (avr32_imm_disp_memory_operand(OP, GET_MODE(OP)) \
9372 + && avr32_const_ok_for_constraint_p( \
9373 + INTVAL(XEXP(XEXP(OP, 0), 1)), \
9374 + (STR)[1], &(STR)[1]))) : \
9375 + (C) == 'S' ? avr32_indexed_memory_operand(OP, GET_MODE(OP)) : \
9376 + (C) == 'T' ? avr32_const_pool_ref_operand(OP, GET_MODE(OP)) : \
9377 + (C) == 'U' ? SYMBOL_REF_RCALL_FUNCTION_P(OP) : \
9378 + (C) == 'Z' ? avr32_cop_memory_operand(OP, GET_MODE(OP)) : \
9379 + (C) == 'Q' ? avr32_non_rmw_memory_operand(OP, GET_MODE(OP)) : \
9380 + (C) == 'Y' ? avr32_rmw_memory_operand(OP, GET_MODE(OP)) : \
9384 +#define EXTRA_MEMORY_CONSTRAINT(C, STR) ( ((C) == 'R') || \
9391 +/* Returns nonzero if op is a function SYMBOL_REF which
9392 + can be called using an rcall instruction */
9393 +#define SYMBOL_REF_RCALL_FUNCTION_P(op) \
9394 + ( GET_CODE(op) == SYMBOL_REF \
9395 + && SYMBOL_REF_FUNCTION_P(op) \
9396 + && SYMBOL_REF_LOCAL_P(op) \
9397 + && !SYMBOL_REF_EXTERNAL_P(op) \
9398 + && !TARGET_HAS_ASM_ADDR_PSEUDOS )
9400 +/******************************************************************************
9401 + * Stack Layout and Calling Conventions
9402 + *****************************************************************************/
9404 +/** Basic Stack Layout **/
9407 +Define this macro if pushing a word onto the stack moves the stack
9408 +pointer to a smaller address.
9410 +When we say, ``define this macro if ...,'' it means that the
9411 +compiler checks this macro only with #ifdef so the precise
9412 +definition used does not matter.
9414 +/* pushm decrece SP: *(--SP) <-- Rx */
9415 +#define STACK_GROWS_DOWNWARD
9418 +This macro defines the operation used when something is pushed
9419 +on the stack. In RTL, a push operation will be
9420 +(set (mem (STACK_PUSH_CODE (reg sp))) ...)
9422 +The choices are PRE_DEC, POST_DEC, PRE_INC,
9423 +and POST_INC. Which of these is correct depends on
9424 +the stack direction and on whether the stack pointer points
9425 +to the last item on the stack or whether it points to the
9426 +space for the next item on the stack.
9428 +The default is PRE_DEC when STACK_GROWS_DOWNWARD is
9429 +defined, which is almost always right, and PRE_INC otherwise,
9430 +which is often wrong.
9432 +/* pushm: *(--SP) <-- Rx */
9433 +#define STACK_PUSH_CODE PRE_DEC
9435 +/* Define this to nonzero if the nominal address of the stack frame
9436 + is at the high-address end of the local variables;
9437 + that is, each additional local variable allocated
9438 + goes at a more negative offset in the frame. */
9439 +#define FRAME_GROWS_DOWNWARD 1
9443 +Offset from the frame pointer to the first local variable slot to be allocated.
9445 +If FRAME_GROWS_DOWNWARD, find the next slot's offset by
9446 +subtracting the first slot's length from STARTING_FRAME_OFFSET.
9447 +Otherwise, it is found by adding the length of the first slot to the
9448 +value STARTING_FRAME_OFFSET.
9449 + (i'm not sure if the above is still correct.. had to change it to get
9450 + rid of an overfull. --mew 2feb93 )
9452 +#define STARTING_FRAME_OFFSET 0
9455 +Offset from the stack pointer register to the first location at which
9456 +outgoing arguments are placed. If not specified, the default value of
9457 +zero is used. This is the proper value for most machines.
9459 +If ARGS_GROW_DOWNWARD, this is the offset to the location above
9460 +the first location at which outgoing arguments are placed.
9462 +#define STACK_POINTER_OFFSET 0
9465 +Offset from the argument pointer register to the first argument's
9466 +address. On some machines it may depend on the data type of the
9469 +If ARGS_GROW_DOWNWARD, this is the offset to the location above
9470 +the first argument's address.
9472 +#define FIRST_PARM_OFFSET(FUNDECL) 0
9476 +A C expression whose value is RTL representing the address in a stack
9477 +frame where the pointer to the caller's frame is stored. Assume that
9478 +FRAMEADDR is an RTL expression for the address of the stack frame
9481 +If you don't define this macro, the default is to return the value
9482 +of FRAMEADDR - that is, the stack frame address is also the
9483 +address of the stack word that points to the previous frame.
9485 +#define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) plus_constant ((FRAMEADDR), 4)
9489 +A C expression whose value is RTL representing the value of the return
9490 +address for the frame COUNT steps up from the current frame, after
9491 +the prologue. FRAMEADDR is the frame pointer of the COUNT
9492 +frame, or the frame pointer of the COUNT - 1 frame if
9493 +RETURN_ADDR_IN_PREVIOUS_FRAME is defined.
9495 +The value of the expression must always be the correct address when
9496 +COUNT is zero, but may be NULL_RTX if there is not way to
9497 +determine the return address of other frames.
9499 +#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) avr32_return_addr(COUNT, FRAMEADDR)
9503 +A C expression whose value is RTL representing the location of the
9504 +incoming return address at the beginning of any function, before the
9505 +prologue. This RTL is either a REG, indicating that the return
9506 +value is saved in 'REG', or a MEM representing a location in
9509 +You only need to define this macro if you want to support call frame
9510 +debugging information like that provided by DWARF 2.
9512 +If this RTL is a REG, you should also define
9513 +DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO).
9515 +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM)
9520 +A C expression whose value is an integer giving the offset, in bytes,
9521 +from the value of the stack pointer register to the top of the stack
9522 +frame at the beginning of any function, before the prologue. The top of
9523 +the frame is defined to be the value of the stack pointer in the
9524 +previous frame, just before the call instruction.
9526 +You only need to define this macro if you want to support call frame
9527 +debugging information like that provided by DWARF 2.
9529 +#define INCOMING_FRAME_SP_OFFSET 0
9532 +/** Exception Handling Support **/
9534 +/* Use setjump/longjump for exception handling. */
9535 +#define DWARF2_UNWIND_INFO 0
9536 +#define MUST_USE_SJLJ_EXCEPTIONS 1
9539 +A C expression whose value is the Nth register number used for
9540 +data by exception handlers, or INVALID_REGNUM if fewer than
9541 +N registers are usable.
9543 +The exception handling library routines communicate with the exception
9544 +handlers via a set of agreed upon registers. Ideally these registers
9545 +should be call-clobbered; it is possible to use call-saved registers,
9546 +but may negatively impact code size. The target must support at least
9547 +2 data registers, but should define 4 if there are enough free registers.
9549 +You must define this macro if you want to support call frame exception
9550 +handling like that provided by DWARF 2.
9555 +#define EH_RETURN_DATA_REGNO(N) \
9556 + ((N<3) ? INTERNAL_REGNUM(N+9) : INVALID_REGNUM)
9559 +A C expression whose value is RTL representing a location in which
9560 +to store a stack adjustment to be applied before function return.
9561 +This is used to unwind the stack to an exception handler's call frame.
9562 +It will be assigned zero on code paths that return normally.
9564 +Typically this is a call-clobbered hard register that is otherwise
9565 +untouched by the epilogue, but could also be a stack slot.
9567 +You must define this macro if you want to support call frame exception
9568 +handling like that provided by DWARF 2.
9573 +#define EH_RETURN_STACKADJ_REGNO INTERNAL_REGNUM(8)
9574 +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG(SImode, EH_RETURN_STACKADJ_REGNO)
9577 +A C expression whose value is RTL representing a location in which
9578 +to store the address of an exception handler to which we should
9579 +return. It will not be assigned on code paths that return normally.
9581 +Typically this is the location in the call frame at which the normal
9582 +return address is stored. For targets that return by popping an
9583 +address off the stack, this might be a memory address just below
9584 +the target call frame rather than inside the current call
9585 +frame. EH_RETURN_STACKADJ_RTX will have already been assigned,
9586 +so it may be used to calculate the location of the target call frame.
9588 +Some targets have more complex requirements than storing to an
9589 +address calculable during initial code generation. In that case
9590 +the eh_return instruction pattern should be used instead.
9592 +If you want to support call frame exception handling, you must
9593 +define either this macro or the eh_return instruction pattern.
9596 + We define the eh_return instruction pattern, so this isn't needed.
9598 +/* #define EH_RETURN_HANDLER_RTX gen_rtx_REG(Pmode, RET_REGISTER) */
9601 + This macro chooses the encoding of pointers embedded in the
9602 + exception handling sections. If at all possible, this should be
9603 + defined such that the exception handling section will not require
9604 + dynamic relocations, and so may be read-only.
9606 + code is 0 for data, 1 for code labels, 2 for function
9607 + pointers. global is true if the symbol may be affected by dynamic
9608 + relocations. The macro should return a combination of the DW_EH_PE_*
9609 + defines as found in dwarf2.h.
9611 + If this macro is not defined, pointers will not be encoded but
9612 + represented directly.
9614 +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \
9615 + ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \
9616 + | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \
9617 + | DW_EH_PE_sdata4)
9619 +/* ToDo: The rest of this subsection */
9621 +/** Specifying How Stack Checking is Done **/
9622 +/* ToDo: All in this subsection */
9624 +/** Registers That Address the Stack Frame **/
9627 +The register number of the stack pointer register, which must also be a
9628 +fixed register according to FIXED_REGISTERS. On most machines,
9629 +the hardware determines which register this is.
9631 +/* Using r13 as stack pointer. */
9632 +#define STACK_POINTER_REGNUM INTERNAL_REGNUM(13)
9635 +The register number of the frame pointer register, which is used to
9636 +access automatic variables in the stack frame. On some machines, the
9637 +hardware determines which register this is. On other machines, you can
9638 +choose any register you wish for this purpose.
9641 +#define FRAME_POINTER_REGNUM INTERNAL_REGNUM(7)
9646 +The register number of the arg pointer register, which is used to access
9647 +the function's argument list. On some machines, this is the same as the
9648 +frame pointer register. On some machines, the hardware determines which
9649 +register this is. On other machines, you can choose any register you
9650 +wish for this purpose. If this is not the same register as the frame
9651 +pointer register, then you must mark it as a fixed register according to
9652 +FIXED_REGISTERS, or arrange to be able to eliminate it (see Section
9653 +10.10.5 [Elimination], page 224).
9656 +#define ARG_POINTER_REGNUM INTERNAL_REGNUM(4)
9660 +Register numbers used for passing a function's static chain pointer. If
9661 +register windows are used, the register number as seen by the called
9662 +function is STATIC_CHAIN_INCOMING_REGNUM, while the register
9663 +number as seen by the calling function is STATIC_CHAIN_REGNUM. If
9664 +these registers are the same, STATIC_CHAIN_INCOMING_REGNUM need
9667 +The static chain register need not be a fixed register.
9669 +If the static chain is passed in memory, these macros should not be
9670 +defined; instead, the next two macros should be defined.
9673 +#define STATIC_CHAIN_REGNUM INTERNAL_REGNUM(0)
9676 +/** Eliminating Frame Pointer and Arg Pointer **/
9679 +A C expression which is nonzero if a function must have and use a frame
9680 +pointer. This expression is evaluated in the reload pass. If its value is
9681 +nonzero the function will have a frame pointer.
9683 +The expression can in principle examine the current function and decide
9684 +according to the facts, but on most machines the constant 0 or the
9685 +constant 1 suffices. Use 0 when the machine allows code to be generated
9686 +with no frame pointer, and doing so saves some time or space. Use 1
9687 +when there is no possible advantage to avoiding a frame pointer.
9689 +In certain cases, the compiler does not know how to produce valid code
9690 +without a frame pointer. The compiler recognizes those cases and
9691 +automatically gives the function a frame pointer regardless of what
9692 +FRAME_POINTER_REQUIRED says. You don't need to worry about
9695 +In a function that does not require a frame pointer, the frame pointer
9696 +register can be allocated for ordinary usage, unless you mark it as a
9697 +fixed register. See FIXED_REGISTERS for more information.
9699 +/* We need the frame pointer when compiling for profiling */
9700 +#define FRAME_POINTER_REQUIRED (current_function_profile)
9703 +A C statement to store in the variable DEPTH_VAR the difference
9704 +between the frame pointer and the stack pointer values immediately after
9705 +the function prologue. The value would be computed from information
9706 +such as the result of get_frame_size () and the tables of
9707 +registers regs_ever_live and call_used_regs.
9709 +If ELIMINABLE_REGS is defined, this macro will be not be used and
9710 +need not be defined. Otherwise, it must be defined even if
9711 +FRAME_POINTER_REQUIRED is defined to always be true; in that
9712 +case, you may set DEPTH_VAR to anything.
9714 +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) ((DEPTH_VAR) = get_frame_size())
9717 +If defined, this macro specifies a table of register pairs used to
9718 +eliminate unneeded registers that point into the stack frame. If it is not
9719 +defined, the only elimination attempted by the compiler is to replace
9720 +references to the frame pointer with references to the stack pointer.
9722 +The definition of this macro is a list of structure initializations, each
9723 +of which specifies an original and replacement register.
9725 +On some machines, the position of the argument pointer is not known until
9726 +the compilation is completed. In such a case, a separate hard register
9727 +must be used for the argument pointer. This register can be eliminated by
9728 +replacing it with either the frame pointer or the argument pointer,
9729 +depending on whether or not the frame pointer has been eliminated.
9731 +In this case, you might specify:
9732 + #define ELIMINABLE_REGS \
9733 + {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
9734 + {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
9735 + {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
9737 +Note that the elimination of the argument pointer with the stack pointer is
9738 +specified first since that is the preferred elimination.
9740 +#define ELIMINABLE_REGS \
9742 + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
9743 + { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \
9744 + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM } \
9748 +A C expression that returns nonzero if the compiler is allowed to try
9749 +to replace register number FROM with register number
9750 +TO. This macro need only be defined if ELIMINABLE_REGS
9751 +is defined, and will usually be the constant 1, since most of the cases
9752 +preventing register elimination are things that the compiler already
9755 +#define CAN_ELIMINATE(FROM, TO) 1
9758 +This macro is similar to INITIAL_FRAME_POINTER_OFFSET. It
9759 +specifies the initial difference between the specified pair of
9760 +registers. This macro must be defined if ELIMINABLE_REGS is
9763 +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
9764 + ((OFFSET) = avr32_initial_elimination_offset(FROM, TO))
9766 +/** Passing Function Arguments on the Stack **/
9770 +A C expression. If nonzero, push insns will be used to pass
9771 +outgoing arguments.
9772 +If the target machine does not have a push instruction, set it to zero.
9773 +That directs GCC to use an alternate strategy: to
9774 +allocate the entire argument block and then store the arguments into
9775 +it. When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too.
9777 +#define PUSH_ARGS 1
9781 +A C expression that is the number of bytes actually pushed onto the
9782 +stack when an instruction attempts to push NPUSHED bytes.
9784 +On some machines, the definition
9786 + #define PUSH_ROUNDING(BYTES) (BYTES)
9788 +will suffice. But on other machines, instructions that appear
9789 +to push one byte actually push two bytes in an attempt to maintain
9790 +alignment. Then the definition should be
9792 + #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
9794 +/* Push 4 bytes at the time. */
9795 +#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3)
9798 +A C expression. If nonzero, the maximum amount of space required for
9799 +outgoing arguments will be computed and placed into the variable
9800 +current_function_outgoing_args_size. No space will be pushed
9801 +onto the stack for each call; instead, the function prologue should
9802 +increase the stack frame size by this amount.
9804 +Setting both PUSH_ARGS and ACCUMULATE_OUTGOING_ARGS is not proper.
9806 +#define ACCUMULATE_OUTGOING_ARGS 0
9812 +A C expression that should indicate the number of bytes of its own
9813 +arguments that a function pops on returning, or 0 if the
9814 +function pops no arguments and the caller must therefore pop them all
9815 +after the function returns.
9817 +FUNDECL is a C variable whose value is a tree node that describes
9818 +the function in question. Normally it is a node of type
9819 +FUNCTION_DECL that describes the declaration of the function.
9820 +From this you can obtain the DECL_ATTRIBUTES of the function.
9822 +FUNTYPE is a C variable whose value is a tree node that
9823 +describes the function in question. Normally it is a node of type
9824 +FUNCTION_TYPE that describes the data type of the function.
9825 +From this it is possible to obtain the data types of the value and
9826 +arguments (if known).
9828 +When a call to a library function is being considered, FUNDECL
9829 +will contain an identifier node for the library function. Thus, if
9830 +you need to distinguish among various library functions, you can do so
9831 +by their names. Note that ``library function'' in this context means
9832 +a function used to perform arithmetic, whose name is known specially
9833 +in the compiler and was not mentioned in the C code being compiled.
9835 +STACK_SIZE is the number of bytes of arguments passed on the
9836 +stack. If a variable number of bytes is passed, it is zero, and
9837 +argument popping will always be the responsibility of the calling function.
9839 +On the VAX, all functions always pop their arguments, so the definition
9840 +of this macro is STACK_SIZE. On the 68000, using the standard
9841 +calling convention, no functions pop their arguments, so the value of
9842 +the macro is always 0 in this case. But an alternative calling
9843 +convention is available in which functions that take a fixed number of
9844 +arguments pop them but other functions (such as printf) pop
9845 +nothing (the caller pops all). When this convention is in use,
9846 +FUNTYPE is examined to determine whether a function takes a fixed
9847 +number of arguments.
9849 +#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0
9852 +/*Return true if this function can we use a single return instruction*/
9853 +#define USE_RETURN_INSN(ISCOND) avr32_use_return_insn(ISCOND)
9856 +A C expression that should indicate the number of bytes a call sequence
9857 +pops off the stack. It is added to the value of RETURN_POPS_ARGS
9858 +when compiling a function call.
9860 +CUM is the variable in which all arguments to the called function
9861 +have been accumulated.
9863 +On certain architectures, such as the SH5, a call trampoline is used
9864 +that pops certain registers off the stack, depending on the arguments
9865 +that have been passed to the function. Since this is a property of the
9866 +call site, not of the called function, RETURN_POPS_ARGS is not
9869 +#define CALL_POPS_ARGS(CUM) 0
9871 +/* Passing Arguments in Registers */
9874 +A C expression that controls whether a function argument is passed
9875 +in a register, and which register.
9877 +The arguments are CUM, which summarizes all the previous
9878 +arguments; MODE, the machine mode of the argument; TYPE,
9879 +the data type of the argument as a tree node or 0 if that is not known
9880 +(which happens for C support library functions); and NAMED,
9881 +which is 1 for an ordinary argument and 0 for nameless arguments that
9882 +correspond to '...' in the called function's prototype.
9883 +TYPE can be an incomplete type if a syntax error has previously
9886 +The value of the expression is usually either a reg RTX for the
9887 +hard register in which to pass the argument, or zero to pass the
9888 +argument on the stack.
9890 +For machines like the VAX and 68000, where normally all arguments are
9891 +pushed, zero suffices as a definition.
9893 +The value of the expression can also be a parallel RTX. This is
9894 +used when an argument is passed in multiple locations. The mode of the
9895 +of the parallel should be the mode of the entire argument. The
9896 +parallel holds any number of expr_list pairs; each one
9897 +describes where part of the argument is passed. In each
9898 +expr_list the first operand must be a reg RTX for the hard
9899 +register in which to pass this part of the argument, and the mode of the
9900 +register RTX indicates how large this part of the argument is. The
9901 +second operand of the expr_list is a const_int which gives
9902 +the offset in bytes into the entire argument of where this part starts.
9903 +As a special exception the first expr_list in the parallel
9904 +RTX may have a first operand of zero. This indicates that the entire
9905 +argument is also stored on the stack.
9907 +The last time this macro is called, it is called with MODE == VOIDmode,
9908 +and its result is passed to the call or call_value
9909 +pattern as operands 2 and 3 respectively.
9911 +The usual way to make the ISO library 'stdarg.h' work on a machine
9912 +where some arguments are usually passed in registers, is to cause
9913 +nameless arguments to be passed on the stack instead. This is done
9914 +by making FUNCTION_ARG return 0 whenever NAMED is 0.
9916 +You may use the macro MUST_PASS_IN_STACK (MODE, TYPE)
9917 +in the definition of this macro to determine if this argument is of a
9918 +type that must be passed in the stack. If REG_PARM_STACK_SPACE
9919 +is not defined and FUNCTION_ARG returns nonzero for such an
9920 +argument, the compiler will abort. If REG_PARM_STACK_SPACE is
9921 +defined, the argument will be computed in the stack and then loaded into
9924 +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
9925 + avr32_function_arg(&(CUM), MODE, TYPE, NAMED)
9931 +A C type for declaring a variable that is used as the first argument of
9932 +FUNCTION_ARG and other related values. For some target machines,
9933 +the type int suffices and can hold the number of bytes of
9936 +There is no need to record in CUMULATIVE_ARGS anything about the
9937 +arguments that have been passed on the stack. The compiler has other
9938 +variables to keep track of that. For target machines on which all
9939 +arguments are passed on the stack, there is no need to store anything in
9940 +CUMULATIVE_ARGS; however, the data structure must exist and
9941 +should not be empty, so use int.
9943 +typedef struct avr32_args
9945 + /* Index representing the argument register the current function argument
9948 + /* A mask with bits representing the argument registers: if a bit is set
9949 + then this register is used for an arguemnt */
9951 + /* TRUE if this function has anonymous arguments */
9952 + int uses_anonymous_args;
9953 + /* The size in bytes of the named arguments pushed on the stack */
9954 + int stack_pushed_args_size;
9955 + /* Set to true if this function needs a Return Value Pointer */
9961 +#define FIRST_CUM_REG_INDEX 0
9962 +#define LAST_CUM_REG_INDEX 4
9963 +#define GET_REG_INDEX(CUM) ((CUM)->index)
9964 +#define SET_REG_INDEX(CUM, INDEX) ((CUM)->index = (INDEX));
9965 +#define GET_USED_INDEX(CUM, INDEX) ((CUM)->used_index & (1 << (INDEX)))
9966 +#define SET_USED_INDEX(CUM, INDEX) \
9970 + (CUM)->used_index |= (1 << (INDEX)); \
9973 +#define SET_INDEXES_UNUSED(CUM) ((CUM)->used_index = 0)
9977 + A C statement (sans semicolon) for initializing the variable cum for the
9978 + state at the beginning of the argument list. The variable has type
9979 + CUMULATIVE_ARGS. The value of FNTYPE is the tree node for the data type of
9980 + the function which will receive the args, or 0 if the args are to a compiler
9981 + support library function. For direct calls that are not libcalls, FNDECL
9982 + contain the declaration node of the function. FNDECL is also set when
9983 + INIT_CUMULATIVE_ARGS is used to find arguments for the function being
9984 + compiled. N_NAMED_ARGS is set to the number of named arguments, including a
9985 + structure return address if it is passed as a parameter, when making a call.
9986 + When processing incoming arguments, N_NAMED_ARGS is set to -1.
9988 + When processing a call to a compiler support library function, LIBNAME
9989 + identifies which one. It is a symbol_ref rtx which contains the name of the
9990 + function, as a string. LIBNAME is 0 when an ordinary C function call is
9991 + being processed. Thus, each time this macro is called, either LIBNAME or
9992 + FNTYPE is nonzero, but never both of them at once.
9994 +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
9995 + avr32_init_cumulative_args(&(CUM), FNTYPE, LIBNAME, FNDECL)
9999 +A C statement (sans semicolon) to update the summarizer variable
10000 +CUM to advance past an argument in the argument list. The
10001 +values MODE, TYPE and NAMED describe that argument.
10002 +Once this is done, the variable CUM is suitable for analyzing
10003 +the following argument with FUNCTION_ARG, etc.
10005 +This macro need not do anything if the argument in question was passed
10006 +on the stack. The compiler knows how to track the amount of stack space
10007 +used for arguments without any special help.
10009 +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
10010 + avr32_function_arg_advance(&(CUM), MODE, TYPE, NAMED)
10013 +If defined, a C expression which determines whether, and in which direction,
10014 +to pad out an argument with extra space. The value should be of type
10015 +enum direction: either 'upward' to pad above the argument,
10016 +'downward' to pad below, or 'none' to inhibit padding.
10018 +The amount of padding is always just enough to reach the next
10019 +multiple of FUNCTION_ARG_BOUNDARY; this macro does not control
10022 +This macro has a default definition which is right for most systems.
10023 +For little-endian machines, the default is to pad upward. For
10024 +big-endian machines, the default is to pad downward for an argument of
10025 +constant size shorter than an int, and upward otherwise.
10027 +#define FUNCTION_ARG_PADDING(MODE, TYPE) \
10028 + avr32_function_arg_padding(MODE, TYPE)
10031 + Specify padding for the last element of a block move between registers
10032 + and memory. First is nonzero if this is the only element. Defining
10033 + this macro allows better control of register function parameters on
10034 + big-endian machines, without using PARALLEL rtl. In particular,
10035 + MUST_PASS_IN_STACK need not test padding and mode of types in registers,
10036 + as there is no longer a "wrong" part of a register; For example, a three
10037 + byte aggregate may be passed in the high part of a register if so required.
10039 +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
10040 + avr32_function_arg_padding(MODE, TYPE)
10043 +If defined, a C expression which determines whether the default
10044 +implementation of va_arg will attempt to pad down before reading the
10045 +next argument, if that argument is smaller than its aligned space as
10046 +controlled by PARM_BOUNDARY. If this macro is not defined, all such
10047 +arguments are padded down if BYTES_BIG_ENDIAN is true.
10049 +#define PAD_VARARGS_DOWN \
10050 + (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward)
10054 +A C expression that is nonzero if REGNO is the number of a hard
10055 +register in which function arguments are sometimes passed. This does
10056 +not include implicit arguments such as the static chain and
10057 +the structure-value address. On many machines, no registers can be
10058 +used for this purpose since all function arguments are pushed on the
10062 + Use r8 - r12 for function arguments.
10064 +#define FUNCTION_ARG_REGNO_P(REGNO) \
10065 + (REGNO >= 3 && REGNO <= 7)
10067 +/* Number of registers used for passing function arguments */
10068 +#define NUM_ARG_REGS 5
10071 +If defined, the order in which arguments are loaded into their
10072 +respective argument registers is reversed so that the last
10073 +argument is loaded first. This macro only affects arguments
10074 +passed in registers.
10076 +/* #define LOAD_ARGS_REVERSED */
10078 +/** How Scalar Function Values Are Returned **/
10080 +/* AVR32 is using r12 as return register. */
10081 +#define RET_REGISTER (15 - 12)
10085 +A C expression to create an RTX representing the place where a library
10086 +function returns a value of mode MODE. If the precise function
10087 +being called is known, FUNC is a tree node
10088 +(FUNCTION_DECL) for it; otherwise, func is a null
10089 +pointer. This makes it possible to use a different value-returning
10090 +convention for specific functions when all their calls are
10093 +Note that "library function" in this context means a compiler
10094 +support routine, used to perform arithmetic, whose name is known
10095 +specially by the compiler and was not mentioned in the C code being
10098 +The definition of LIBRARY_VALUE need not be concerned aggregate
10099 +data types, because none of the library functions returns such types.
10101 +#define LIBCALL_VALUE(MODE) avr32_libcall_value(MODE)
10104 +A C expression that is nonzero if REGNO is the number of a hard
10105 +register in which the values of called function may come back.
10107 +A register whose use for returning values is limited to serving as the
10108 +second of a pair (for a value of type double, say) need not be
10109 +recognized by this macro. So for most machines, this definition
10111 + #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
10113 +If the machine has register windows, so that the caller and the called
10114 +function use different registers for the return value, this macro
10115 +should recognize only the caller's register numbers.
10118 + When returning a value of mode DImode, r11:r10 is used, else r12 is used.
10120 +#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RET_REGISTER \
10121 + || (REGNO) == INTERNAL_REGNUM(11))
10124 +/** How Large Values Are Returned **/
10128 +Define this macro to be 1 if all structure and union return values must be
10129 +in memory. Since this results in slower code, this should be defined
10130 +only if needed for compatibility with other compilers or with an ABI.
10131 +If you define this macro to be 0, then the conventions used for structure
10132 +and union return values are decided by the RETURN_IN_MEMORY macro.
10134 +If not defined, this defaults to the value 1.
10136 +#define DEFAULT_PCC_STRUCT_RETURN 0
10141 +/** Generating Code for Profiling **/
10144 +A C statement or compound statement to output to FILE some
10145 +assembler code to call the profiling subroutine mcount.
10147 +The details of how mcount expects to be called are determined by
10148 +your operating system environment, not by GCC. To figure them out,
10149 +compile a small program for profiling using the system's installed C
10150 +compiler and look at the assembler code that results.
10152 +Older implementations of mcount expect the address of a counter
10153 +variable to be loaded into some register. The name of this variable is
10154 +'LP' followed by the number LABELNO, so you would generate
10155 +the name using 'LP%d' in a fprintf.
10158 +#ifndef FUNCTION_PROFILER
10159 +#define FUNCTION_PROFILER(FILE, LABELNO) \
10160 + fprintf((FILE), "/* profiler %d */", (LABELNO))
10164 +/*****************************************************************************
10165 + * Trampolines for Nested Functions *
10166 + *****************************************************************************/
10169 +A C statement to output, on the stream FILE, assembler code for a
10170 +block of data that contains the constant parts of a trampoline. This
10171 +code should not include a label - the label is taken care of
10174 +If you do not define this macro, it means no template is needed
10175 +for the target. Do not define this macro on systems where the block move
10176 +code to copy the trampoline into place would be larger than the code
10177 +to generate it on the spot.
10179 +/* ToDo: correct? */
10180 +#define TRAMPOLINE_TEMPLATE(FILE) avr32_trampoline_template(FILE);
10184 +A C expression for the size in bytes of the trampoline, as an integer.
10187 +#define TRAMPOLINE_SIZE 0x0C
10190 +Alignment required for trampolines, in bits.
10192 +If you don't define this macro, the value of BIGGEST_ALIGNMENT
10193 +is used for aligning trampolines.
10195 +#define TRAMPOLINE_ALIGNMENT 16
10198 +A C statement to initialize the variable parts of a trampoline.
10199 +ADDR is an RTX for the address of the trampoline; FNADDR is
10200 +an RTX for the address of the nested function; STATIC_CHAIN is an
10201 +RTX for the static chain value that should be passed to the function
10202 +when it is called.
10204 +#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \
10205 + avr32_initialize_trampoline(ADDR, FNADDR, STATIC_CHAIN)
10208 +/******************************************************************************
10209 + * Implicit Calls to Library Routines
10210 + *****************************************************************************/
10212 +/* Tail calling. */
10214 +/* A C expression that evaluates to true if it is ok to perform a sibling
10216 +#define FUNCTION_OK_FOR_SIBCALL(DECL) 0
10218 +#define OVERRIDE_OPTIONS avr32_override_options ()
10220 +#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) avr32_optimization_options (LEVEL, SIZE)
10222 +/******************************************************************************
10223 + * Addressing Modes
10224 + *****************************************************************************/
10227 +A C expression that is nonzero if the machine supports pre-increment,
10228 +pre-decrement, post-increment, or post-decrement addressing respectively.
10231 + AVR32 supports Rp++ and --Rp
10233 +#define HAVE_PRE_INCREMENT 0
10234 +#define HAVE_PRE_DECREMENT 1
10235 +#define HAVE_POST_INCREMENT 1
10236 +#define HAVE_POST_DECREMENT 0
10239 +A C expression that is nonzero if the machine supports pre- or
10240 +post-address side-effect generation involving constants other than
10241 +the size of the memory operand.
10243 +#define HAVE_PRE_MODIFY_DISP 0
10244 +#define HAVE_POST_MODIFY_DISP 0
10247 +A C expression that is nonzero if the machine supports pre- or
10248 +post-address side-effect generation involving a register displacement.
10250 +#define HAVE_PRE_MODIFY_REG 0
10251 +#define HAVE_POST_MODIFY_REG 0
10254 +A C expression that is 1 if the RTX X is a constant which
10255 +is a valid address. On most machines, this can be defined as
10256 +CONSTANT_P (X), but a few machines are more restrictive
10257 +in which constant addresses are supported.
10259 +CONSTANT_P accepts integer-values expressions whose values are
10260 +not explicitly known, such as symbol_ref, label_ref, and
10261 +high expressions and const arithmetic expressions, in
10262 +addition to const_int and const_double expressions.
10264 +#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X)
10267 +A number, the maximum number of registers that can appear in a valid
10268 +memory address. Note that it is up to you to specify a value equal to
10269 +the maximum number that GO_IF_LEGITIMATE_ADDRESS would ever
10272 +#define MAX_REGS_PER_ADDRESS 2
10275 +A C compound statement with a conditional goto LABEL;
10276 +executed if X (an RTX) is a legitimate memory address on the
10277 +target machine for a memory operand of mode MODE.
10279 +It usually pays to define several simpler macros to serve as
10280 +subroutines for this one. Otherwise it may be too complicated to
10283 +This macro must exist in two variants: a strict variant and a
10284 +non-strict one. The strict variant is used in the reload pass. It
10285 +must be defined so that any pseudo-register that has not been
10286 +allocated a hard register is considered a memory reference. In
10287 +contexts where some kind of register is required, a pseudo-register
10288 +with no hard register must be rejected.
10290 +The non-strict variant is used in other passes. It must be defined to
10291 +accept all pseudo-registers in every context where some kind of
10292 +register is required.
10294 +Compiler source files that want to use the strict variant of this
10295 +macro define the macro REG_OK_STRICT. You should use an
10296 +#ifdef REG_OK_STRICT conditional to define the strict variant
10297 +in that case and the non-strict variant otherwise.
10299 +Subroutines to check for acceptable registers for various purposes (one
10300 +for base registers, one for index registers, and so on) are typically
10301 +among the subroutines used to define GO_IF_LEGITIMATE_ADDRESS.
10302 +Then only these subroutine macros need have two variants; the higher
10303 +levels of macros may be the same whether strict or not.
10305 +Normally, constant addresses which are the sum of a symbol_ref
10306 +and an integer are stored inside a const RTX to mark them as
10307 +constant. Therefore, there is no need to recognize such sums
10308 +specifically as legitimate addresses. Normally you would simply
10309 +recognize any const as legitimate.
10311 +Usually PRINT_OPERAND_ADDRESS is not prepared to handle constant
10312 +sums that are not marked with const. It assumes that a naked
10313 +plus indicates indexing. If so, then you must reject such
10314 +naked constant sums as illegitimate addresses, so that none of them will
10315 +be given to PRINT_OPERAND_ADDRESS.
10317 +On some machines, whether a symbolic address is legitimate depends on
10318 +the section that the address refers to. On these machines, define the
10319 +macro ENCODE_SECTION_INFO to store the information into the
10320 +symbol_ref, and then check for it here. When you see a
10321 +const, you will have to look inside it to find the
10322 +symbol_ref in order to determine the section.
10324 +The best way to modify the name string is by adding text to the
10325 +beginning, with suitable punctuation to prevent any ambiguity. Allocate
10326 +the new name in saveable_obstack. You will have to modify
10327 +ASM_OUTPUT_LABELREF to remove and decode the added text and
10328 +output the name accordingly, and define STRIP_NAME_ENCODING to
10329 +access the original name string.
10331 +You can check the information stored here into the symbol_ref in
10332 +the definitions of the macros GO_IF_LEGITIMATE_ADDRESS and
10333 +PRINT_OPERAND_ADDRESS.
10335 +#ifdef REG_OK_STRICT
10336 +# define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
10339 + if (avr32_legitimate_address(MODE, X, 1)) \
10344 +# define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
10347 + if (avr32_legitimate_address(MODE, X, 0)) \
10356 +A C compound statement that attempts to replace X with a valid
10357 +memory address for an operand of mode MODE. win will be a
10358 +C statement label elsewhere in the code; the macro definition may use
10360 + GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
10362 +to avoid further processing if the address has become legitimate.
10364 +X will always be the result of a call to break_out_memory_refs,
10365 +and OLDX will be the operand that was given to that function to produce
10368 +The code generated by this macro should not alter the substructure of
10369 +X. If it transforms X into a more legitimate form, it
10370 +should assign X (which will always be a C variable) a new value.
10372 +It is not necessary for this macro to come up with a legitimate
10373 +address. The compiler has standard ways of doing so in all cases. In
10374 +fact, it is safe for this macro to do nothing. But often a
10375 +machine-dependent strategy can generate better code.
10377 +#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
10380 + if (GET_CODE(X) == PLUS \
10381 + && GET_CODE(XEXP(X, 0)) == REG \
10382 + && GET_CODE(XEXP(X, 1)) == CONST_INT \
10383 + && !CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(X, 1)), \
10386 + rtx index = force_reg(SImode, XEXP(X, 1)); \
10387 + X = gen_rtx_PLUS( SImode, XEXP(X, 0), index); \
10389 + GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN); \
10395 +A C statement or compound statement with a conditional
10396 +goto LABEL; executed if memory address X (an RTX) can have
10397 +different meanings depending on the machine mode of the memory
10398 +reference it is used for or if the address is valid for some modes
10401 +Autoincrement and autodecrement addresses typically have mode-dependent
10402 +effects because the amount of the increment or decrement is the size
10403 +of the operand being addressed. Some machines have other mode-dependent
10404 +addresses. Many RISC machines have no mode-dependent addresses.
10406 +You may assume that ADDR is a valid address for the machine.
10408 +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \
10411 + if (GET_CODE (ADDR) == POST_INC \
10412 + || GET_CODE (ADDR) == PRE_DEC) \
10418 +A C expression that is nonzero if X is a legitimate constant for
10419 +an immediate operand on the target machine. You can assume that
10420 +X satisfies CONSTANT_P, so you need not check this. In fact,
10421 +'1' is a suitable definition for this macro on machines where
10422 +anything CONSTANT_P is valid.
10424 +#define LEGITIMATE_CONSTANT_P(X) avr32_legitimate_constant_p(X)
10427 +/******************************************************************************
10428 + * Condition Code Status
10429 + *****************************************************************************/
10432 +C code for a data type which is used for declaring the mdep
10433 +component of cc_status. It defaults to int.
10435 +This macro is not used on machines that do not use cc0.
10444 + int cond_exec_cmp_clobbered;
10445 +} avr32_status_reg;
10448 +#define CC_STATUS_MDEP avr32_status_reg
10451 +A C expression to initialize the mdep field to "empty".
10452 +The default definition does nothing, since most machines don't use
10453 +the field anyway. If you want to use the field, you should probably
10454 +define this macro to initialize it.
10456 +This macro is not used on machines that do not use cc0.
10459 +#define CC_STATUS_MDEP_INIT \
10460 + (cc_status.mdep.flags = CC_NONE , cc_status.mdep.cond_exec_cmp_clobbered = 0, cc_status.mdep.value = 0)
10462 +#define FPCC_STATUS_INIT \
10463 + (cc_status.mdep.fpflags = CC_NONE , cc_status.mdep.fpvalue = 0)
10466 +A C compound statement to set the components of cc_status
10467 +appropriately for an insn INSN whose body is EXP. It is
10468 +this macro's responsibility to recognize insns that set the condition
10469 +code as a byproduct of other activity as well as those that explicitly
10472 +This macro is not used on machines that do not use cc0.
10474 +If there are insns that do not set the condition code but do alter
10475 +other machine registers, this macro must check to see whether they
10476 +invalidate the expressions that the condition code is recorded as
10477 +reflecting. For example, on the 68000, insns that store in address
10478 +registers do not set the condition code, which means that usually
10479 +NOTICE_UPDATE_CC can leave cc_status unaltered for such
10480 +insns. But suppose that the previous insn set the condition code
10481 +based on location 'a4@@(102)' and the current insn stores a new
10482 +value in 'a4'. Although the condition code is not changed by
10483 +this, it will no longer be true that it reflects the contents of
10484 +'a4@@(102)'. Therefore, NOTICE_UPDATE_CC must alter
10485 +cc_status in this case to say that nothing is known about the
10486 +condition code value.
10488 +The definition of NOTICE_UPDATE_CC must be prepared to deal
10489 +with the results of peephole optimization: insns whose patterns are
10490 +parallel RTXs containing various reg, mem or
10491 +constants which are just the operands. The RTL structure of these
10492 +insns is not sufficient to indicate what the insns actually do. What
10493 +NOTICE_UPDATE_CC should do when it sees one is just to run
10496 +A possible definition of NOTICE_UPDATE_CC is to call a function
10497 +that looks at an attribute (see Insn Attributes) named, for example,
10498 +'cc'. This avoids having detailed information about patterns in
10499 +two places, the 'md' file and in NOTICE_UPDATE_CC.
10502 +#define NOTICE_UPDATE_CC(EXP, INSN) avr32_notice_update_cc(EXP, INSN)
10507 +/******************************************************************************
10508 + * Describing Relative Costs of Operations
10509 + *****************************************************************************/
10514 +A C expression for the cost of moving data of mode MODE from a
10515 +register in class FROM to one in class TO. The classes are
10516 +expressed using the enumeration values such as GENERAL_REGS. A
10517 +value of 2 is the default; other values are interpreted relative to
10520 +It is not required that the cost always equal 2 when FROM is the
10521 +same as TO; on some machines it is expensive to move between
10522 +registers if they are not general registers.
10524 +If reload sees an insn consisting of a single set between two
10525 +hard registers, and if REGISTER_MOVE_COST applied to their
10526 +classes returns a value of 2, reload does not check to ensure that the
10527 +constraints of the insn are met. Setting a cost of other than 2 will
10528 +allow reload to verify that the constraints are met. You should do this
10529 +if the movm pattern's constraints do not allow such copying.
10531 +#define REGISTER_MOVE_COST(MODE, FROM, TO) \
10532 + ((GET_MODE_SIZE(MODE) <= 4) ? 2: \
10533 + (GET_MODE_SIZE(MODE) <= 8) ? 3: \
10537 +A C expression for the cost of moving data of mode MODE between a
10538 +register of class CLASS and memory; IN is zero if the value
10539 +is to be written to memory, nonzero if it is to be read in. This cost
10540 +is relative to those in REGISTER_MOVE_COST. If moving between
10541 +registers and memory is more expensive than between two registers, you
10542 +should define this macro to express the relative cost.
10544 +If you do not define this macro, GCC uses a default cost of 4 plus
10545 +the cost of copying via a secondary reload register, if one is
10546 +needed. If your machine requires a secondary reload register to copy
10547 +between memory and a register of CLASS but the reload mechanism is
10548 +more complex than copying via an intermediate, define this macro to
10549 +reflect the actual cost of the move.
10551 +GCC defines the function memory_move_secondary_cost if
10552 +secondary reloads are needed. It computes the costs due to copying via
10553 +a secondary register. If your machine copies from memory using a
10554 +secondary register in the conventional way but the default base value of
10555 +4 is not correct for your machine, define this macro to add some other
10556 +value to the result of that function. The arguments to that function
10557 +are the same as to this macro.
10560 + Memory moves are costly
10562 +#define MEMORY_MOVE_COST(MODE, CLASS, IN) \
10563 + (((IN) ? ((GET_MODE_SIZE(MODE) < 4) ? 4 : \
10564 + (GET_MODE_SIZE(MODE) > 8) ? 6 : \
10566 + : ((GET_MODE_SIZE(MODE) > 8) ? 6 : 3)))
10569 +A C expression for the cost of a branch instruction. A value of 1 is
10570 +the default; other values are interpreted relative to that.
10572 + /* Try to use conditionals as much as possible */
10573 +#define BRANCH_COST (TARGET_BRANCH_PRED ? 3 : 4)
10575 +/*A C expression for the maximum number of instructions to execute via conditional
10576 + execution instructions instead of a branch. A value of BRANCH_COST+1 is the default
10577 + if the machine does not use cc0, and 1 if it does use cc0.*/
10578 +#define MAX_CONDITIONAL_EXECUTE 4
10581 +Define this macro as a C expression which is nonzero if accessing less
10582 +than a word of memory (i.e.: a char or a short) is no
10583 +faster than accessing a word of memory, i.e., if such access
10584 +require more than one instruction or if there is no difference in cost
10585 +between byte and (aligned) word loads.
10587 +When this macro is not defined, the compiler will access a field by
10588 +finding the smallest containing object; when it is defined, a fullword
10589 +load will be used if alignment permits. Unless bytes accesses are
10590 +faster than word accesses, using word accesses is preferable since it
10591 +may eliminate subsequent memory access if subsequent accesses occur to
10592 +other fields in the same word of the structure, but to different bytes.
10594 +#define SLOW_BYTE_ACCESS 1
10598 +Define this macro if it is as good or better to call a constant
10599 +function address than to call an address kept in a register.
10601 +#define NO_FUNCTION_CSE
10604 +/******************************************************************************
10605 + * Adjusting the Instruction Scheduler
10606 + *****************************************************************************/
10608 +/*****************************************************************************
10609 + * Dividing the Output into Sections (Texts, Data, ...) *
10610 + *****************************************************************************/
10613 +A C expression whose value is a string, including spacing, containing the
10614 +assembler operation that should precede instructions and read-only data.
10615 +Normally "\t.text" is right.
10617 +#define TEXT_SECTION_ASM_OP "\t.text"
10619 +A C statement that switches to the default section containing instructions.
10620 +Normally this is not needed, as simply defining TEXT_SECTION_ASM_OP
10621 +is enough. The MIPS port uses this to sort all functions after all data
10624 +/* #define TEXT_SECTION */
10627 +A C expression whose value is a string, including spacing, containing the
10628 +assembler operation to identify the following data as writable initialized
10629 +data. Normally "\t.data" is right.
10631 +#define DATA_SECTION_ASM_OP "\t.data"
10634 +If defined, a C expression whose value is a string, including spacing,
10635 +containing the assembler operation to identify the following data as
10636 +shared data. If not defined, DATA_SECTION_ASM_OP will be used.
10640 +A C expression whose value is a string, including spacing, containing
10641 +the assembler operation to identify the following data as read-only
10644 +#undef READONLY_DATA_SECTION_ASM_OP
10645 +#define READONLY_DATA_SECTION_ASM_OP \
10646 + ((TARGET_USE_RODATA_SECTION) ? \
10647 + "\t.section\t.rodata" : \
10648 + TEXT_SECTION_ASM_OP )
10652 +If defined, a C expression whose value is a string, including spacing,
10653 +containing the assembler operation to identify the following data as
10654 +uninitialized global data. If not defined, and neither
10655 +ASM_OUTPUT_BSS nor ASM_OUTPUT_ALIGNED_BSS are defined,
10656 +uninitialized global data will be output in the data section if
10657 +-fno-common is passed, otherwise ASM_OUTPUT_COMMON will be
10660 +#define BSS_SECTION_ASM_OP "\t.section\t.bss"
10663 +If defined, a C expression whose value is a string, including spacing,
10664 +containing the assembler operation to identify the following data as
10665 +uninitialized global shared data. If not defined, and
10666 +BSS_SECTION_ASM_OP is, the latter will be used.
10668 +/*#define SHARED_BSS_SECTION_ASM_OP "\trseg\tshared_bbs_section:data:noroot(0)\n"*/
10670 +If defined, a C expression whose value is a string, including spacing,
10671 +containing the assembler operation to identify the following data as
10672 +initialization code. If not defined, GCC will assume such a section does
10675 +#undef INIT_SECTION_ASM_OP
10676 +#define INIT_SECTION_ASM_OP "\t.section\t.init"
10679 +If defined, a C expression whose value is a string, including spacing,
10680 +containing the assembler operation to identify the following data as
10681 +finalization code. If not defined, GCC will assume such a section does
10684 +#undef FINI_SECTION_ASM_OP
10685 +#define FINI_SECTION_ASM_OP "\t.section\t.fini"
10688 +If defined, an ASM statement that switches to a different section
10689 +via SECTION_OP, calls FUNCTION, and switches back to
10690 +the text section. This is used in crtstuff.c if
10691 +INIT_SECTION_ASM_OP or FINI_SECTION_ASM_OP to calls
10692 +to initialization and finalization functions from the init and fini
10693 +sections. By default, this macro uses a simple function call. Some
10694 +ports need hand-crafted assembly code to avoid dependencies on
10695 +registers initialized in the function prologue or to ensure that
10696 +constant pools don't end up too far way in the text section.
10698 +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \
10699 + asm ( SECTION_OP "\n" \
10700 + "mcall r6[" USER_LABEL_PREFIX #FUNC "@got]\n" \
10701 + TEXT_SECTION_ASM_OP);
10705 +Define this macro to be an expression with a nonzero value if jump
10706 +tables (for tablejump insns) should be output in the text
10707 +section, along with the assembler instructions. Otherwise, the
10708 +readonly data section is used.
10710 +This macro is irrelevant if there is no separate readonly data section.
10712 +/* Put jump tables in text section if we have caches. Otherwise assume that
10713 + loading data from code memory is slow. */
10714 +#define JUMP_TABLES_IN_TEXT_SECTION \
10715 + (TARGET_CACHES ? 1 : 0)
10718 +/******************************************************************************
10719 + * Position Independent Code (PIC)
10720 + *****************************************************************************/
10722 +#ifndef AVR32_ALWAYS_PIC
10723 +#define AVR32_ALWAYS_PIC 0
10726 +/* GOT is set to r6 */
10727 +#define PIC_OFFSET_TABLE_REGNUM INTERNAL_REGNUM(6)
10730 +A C expression that is nonzero if X is a legitimate immediate
10731 +operand on the target machine when generating position independent code.
10732 +You can assume that X satisfies CONSTANT_P, so you need not
10733 +check this. You can also assume flag_pic is true, so you need not
10734 +check it either. You need not define this macro if all constants
10735 +(including SYMBOL_REF) can be immediate operands when generating
10736 +position independent code.
10738 +/* We can't directly access anything that contains a symbol,
10739 + nor can we indirect via the constant pool. */
10740 +#define LEGITIMATE_PIC_OPERAND_P(X) avr32_legitimate_pic_operand_p(X)
10743 +/* We need to know when we are making a constant pool; this determines
10744 + whether data needs to be in the GOT or can be referenced via a GOT
10746 +extern int making_const_table;
10748 +/******************************************************************************
10749 + * Defining the Output Assembler Language
10750 + *****************************************************************************/
10754 +A C string constant describing how to begin a comment in the target
10755 +assembler language. The compiler assumes that the comment will end at
10756 +the end of the line.
10758 +#define ASM_COMMENT_START "# "
10761 +A C string constant for text to be output before each asm
10762 +statement or group of consecutive ones. Normally this is
10763 +"#APP", which is a comment that has no effect on most
10764 +assemblers but tells the GNU assembler that it must check the lines
10765 +that follow for all valid assembler constructs.
10768 +#define ASM_APP_ON "#APP\n"
10771 +A C string constant for text to be output after each asm
10772 +statement or group of consecutive ones. Normally this is
10773 +"#NO_APP", which tells the GNU assembler to resume making the
10774 +time-saving assumptions that are valid for ordinary compiler output.
10776 +#undef ASM_APP_OFF
10777 +#define ASM_APP_OFF "#NO_APP\n"
10781 +#define FILE_ASM_OP "\t.file\n"
10782 +#define IDENT_ASM_OP "\t.ident\t"
10783 +#define SET_ASM_OP "\t.set\t"
10787 + * Output assembly directives to switch to section name. The section
10788 + * should have attributes as specified by flags, which is a bit mask
10789 + * of the SECTION_* flags defined in 'output.h'. If align is nonzero,
10790 + * it contains an alignment in bytes to be used for the section,
10791 + * otherwise some target default should be used. Only targets that
10792 + * must specify an alignment within the section directive need pay
10793 + * attention to align -- we will still use ASM_OUTPUT_ALIGN.
10795 + * NOTE: This one must not be moved to avr32.c
10797 +#undef TARGET_ASM_NAMED_SECTION
10798 +#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section
10802 +You may define this macro as a C expression. You should define the
10803 +expression to have a nonzero value if GCC should output the constant
10804 +pool for a function before the code for the function, or a zero value if
10805 +GCC should output the constant pool after the function. If you do
10806 +not define this macro, the usual case, GCC will output the constant
10807 +pool before the function.
10809 +#define CONSTANT_POOL_BEFORE_FUNCTION 0
10813 +Define this macro as a C expression which is nonzero if the constant
10814 +EXP, of type tree, should be output after the code for a
10815 +function. The compiler will normally output all constants before the
10816 +function; you need not define this macro if this is OK.
10818 +#define CONSTANT_AFTER_FUNCTION_P(EXP) 1
10822 +Define this macro as a C expression which is nonzero if C is
10823 +used as a logical line separator by the assembler.
10825 +If you do not define this macro, the default is that only
10826 +the character ';' is treated as a logical line separator.
10828 +#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '\n')
10831 +/** Output of Uninitialized Variables **/
10834 +A C statement (sans semicolon) to output to the stdio stream
10835 +STREAM the assembler definition of a common-label named
10836 +NAME whose size is SIZE bytes. The variable ROUNDED
10837 +is the size rounded up to whatever alignment the caller wants.
10839 +Use the expression assemble_name(STREAM, NAME) to
10840 +output the name itself; before and after that, output the additional
10841 +assembler syntax for defining the name, and a newline.
10843 +This macro controls how the assembler definitions of uninitialized
10844 +common global variables are output.
10847 +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
10848 + avr32_asm_output_common(STREAM, NAME, SIZE, ROUNDED)
10851 +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
10854 + fputs ("\t.comm ", (FILE)); \
10855 + assemble_name ((FILE), (NAME)); \
10856 + fprintf ((FILE), ",%d\n", (SIZE)); \
10861 + * Like ASM_OUTPUT_BSS except takes the required alignment as a
10862 + * separate, explicit argument. If you define this macro, it is used
10863 + * in place of ASM_OUTPUT_BSS, and gives you more flexibility in
10864 + * handling the required alignment of the variable. The alignment is
10865 + * specified as the number of bits.
10867 + * Try to use function asm_output_aligned_bss defined in file varasm.c
10868 + * when defining this macro.
10870 +#define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGNMENT) \
10871 + asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGNMENT)
10874 +A C statement (sans semicolon) to output to the stdio stream
10875 +STREAM the assembler definition of a local-common-label named
10876 +NAME whose size is SIZE bytes. The variable ROUNDED
10877 +is the size rounded up to whatever alignment the caller wants.
10879 +Use the expression assemble_name(STREAM, NAME) to
10880 +output the name itself; before and after that, output the additional
10881 +assembler syntax for defining the name, and a newline.
10883 +This macro controls how the assembler definitions of uninitialized
10884 +static variables are output.
10886 +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
10889 + fputs ("\t.lcomm ", (FILE)); \
10890 + assemble_name ((FILE), (NAME)); \
10891 + fprintf ((FILE), ",%d, %d\n", (SIZE), 2); \
10897 +A C statement (sans semicolon) to output to the stdio stream
10898 +STREAM the assembler definition of a label named NAME.
10899 +Use the expression assemble_name(STREAM, NAME) to
10900 +output the name itself; before and after that, output the additional
10901 +assembler syntax for defining the name, and a newline.
10903 +#define ASM_OUTPUT_LABEL(STREAM, NAME) avr32_asm_output_label(STREAM, NAME)
10905 +/* A C string containing the appropriate assembler directive to
10906 + * specify the size of a symbol, without any arguments. On systems
10907 + * that use ELF, the default (in 'config/elfos.h') is '"\t.size\t"';
10908 + * on other systems, the default is not to define this macro.
10910 + * Define this macro only if it is correct to use the default
10911 + * definitions of ASM_ OUTPUT_SIZE_DIRECTIVE and
10912 + * ASM_OUTPUT_MEASURED_SIZE for your system. If you need your own
10913 + * custom definitions of those macros, or if you do not need explicit
10914 + * symbol sizes at all, do not define this macro.
10916 +#define SIZE_ASM_OP "\t.size\t"
10920 +A C statement (sans semicolon) to output to the stdio stream
10921 +STREAM some commands that will make the label NAME global;
10922 +that is, available for reference from other files. Use the expression
10923 +assemble_name(STREAM, NAME) to output the name
10924 +itself; before and after that, output the additional assembler syntax
10925 +for making that name global, and a newline.
10927 +#define GLOBAL_ASM_OP "\t.globl\t"
10932 +A C expression which evaluates to true if the target supports weak symbols.
10934 +If you don't define this macro, defaults.h provides a default
10935 +definition. If either ASM_WEAKEN_LABEL or ASM_WEAKEN_DECL
10936 +is defined, the default definition is '1'; otherwise, it is
10937 +'0'. Define this macro if you want to control weak symbol support
10938 +with a compiler flag such as -melf.
10940 +#define SUPPORTS_WEAK 1
10943 +A C statement (sans semicolon) to output to the stdio stream
10944 +STREAM a reference in assembler syntax to a label named
10945 +NAME. This should add '_' to the front of the name, if that
10946 +is customary on your operating system, as it is in most Berkeley Unix
10947 +systems. This macro is used in assemble_name.
10949 +#define ASM_OUTPUT_LABELREF(STREAM, NAME) \
10950 + avr32_asm_output_labelref(STREAM, NAME)
10955 +A C expression to assign to OUTVAR (which is a variable of type
10956 +char *) a newly allocated string made from the string
10957 +NAME and the number NUMBER, with some suitable punctuation
10958 +added. Use alloca to get space for the string.
10960 +The string will be used as an argument to ASM_OUTPUT_LABELREF to
10961 +produce an assembler label for an internal static variable whose name is
10962 +NAME. Therefore, the string must be such as to result in valid
10963 +assembler code. The argument NUMBER is different each time this
10964 +macro is executed; it prevents conflicts between similarly-named
10965 +internal static variables in different scopes.
10967 +Ideally this string should not be a valid C identifier, to prevent any
10968 +conflict with the user's own symbols. Most assemblers allow periods
10969 +or percent signs in assembler symbols; putting at least one of these
10970 +between the name and the number will suffice.
10972 +#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \
10975 + (OUTVAR) = (char *) alloca (strlen ((NAME)) + 10); \
10976 + sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)); \
10981 +/** Macros Controlling Initialization Routines **/
10985 +If defined, main will not call __main as described above.
10986 +This macro should be defined for systems that control start-up code
10987 +on a symbol-by-symbol basis, such as OSF/1, and should not
10988 +be defined explicitly for systems that support INIT_SECTION_ASM_OP.
10991 + __main is not defined when debugging.
10993 +#define HAS_INIT_SECTION
10996 +/** Output of Assembler Instructions **/
10999 +A C initializer containing the assembler's names for the machine
11000 +registers, each one as a C string constant. This is what translates
11001 +register numbers in the compiler into assembler language.
11004 +#define REGISTER_NAMES \
11025 +A C compound statement to output to stdio stream STREAM the
11026 +assembler syntax for an instruction operand X. X is an
11029 +CODE is a value that can be used to specify one of several ways
11030 +of printing the operand. It is used when identical operands must be
11031 +printed differently depending on the context. CODE comes from
11032 +the '%' specification that was used to request printing of the
11033 +operand. If the specification was just '%digit' then
11034 +CODE is 0; if the specification was '%ltr digit'
11035 +then CODE is the ASCII code for ltr.
11037 +If X is a register, this macro should print the register's name.
11038 +The names can be found in an array reg_names whose type is
11039 +char *[]. reg_names is initialized from REGISTER_NAMES.
11041 +When the machine description has a specification '%punct'
11042 +(a '%' followed by a punctuation character), this macro is called
11043 +with a null pointer for X and the punctuation character for
11046 +#define PRINT_OPERAND(STREAM, X, CODE) avr32_print_operand(STREAM, X, CODE)
11048 +/* A C statement to be executed just prior to the output of
11049 + assembler code for INSN, to modify the extracted operands so
11050 + they will be output differently.
11052 + Here the argument OPVEC is the vector containing the operands
11053 + extracted from INSN, and NOPERANDS is the number of elements of
11054 + the vector which contain meaningful data for this insn.
11055 + The contents of this vector are what will be used to convert the insn
11056 + template into assembler code, so you can change the assembler output
11057 + by changing the contents of the vector. */
11058 +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
11059 + avr32_final_prescan_insn ((INSN), (OPVEC), (NOPERANDS))
11062 +A C expression which evaluates to true if CODE is a valid
11063 +punctuation character for use in the PRINT_OPERAND macro. If
11064 +PRINT_OPERAND_PUNCT_VALID_P is not defined, it means that no
11065 +punctuation characters (except for the standard one, '%') are used
11068 +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
11069 + (((CODE) == '?') \
11070 + || ((CODE) == '!'))
11073 +A C compound statement to output to stdio stream STREAM the
11074 +assembler syntax for an instruction operand that is a memory reference
11075 +whose address is X. X is an RTL expression.
11077 +On some machines, the syntax for a symbolic address depends on the
11078 +section that the address refers to. On these machines, define the macro
11079 +ENCODE_SECTION_INFO to store the information into the
11080 +symbol_ref, and then check for it here. (see Assembler Format.)
11082 +#define PRINT_OPERAND_ADDRESS(STREAM, X) avr32_print_operand_address(STREAM, X)
11085 +/** Output of Dispatch Tables **/
11088 + * A C statement to output to the stdio stream stream an assembler
11089 + * pseudo-instruction to generate a difference between two
11090 + * labels. value and rel are the numbers of two internal labels. The
11091 + * definitions of these labels are output using
11092 + * (*targetm.asm_out.internal_label), and they must be printed in the
11093 + * same way here. For example,
11095 + * fprintf (stream, "\t.word L%d-L%d\n",
11098 + * You must provide this macro on machines where the addresses in a
11099 + * dispatch table are relative to the table's own address. If defined,
11100 + * GCC will also use this macro on all machines when producing
11101 + * PIC. body is the body of the ADDR_DIFF_VEC; it is provided so that
11102 + * the mode and flags can be read.
11104 +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
11105 + fprintf(STREAM, "\tbral\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
11108 +This macro should be provided on machines where the addresses
11109 +in a dispatch table are absolute.
11111 +The definition should be a C statement to output to the stdio stream
11112 +STREAM an assembler pseudo-instruction to generate a reference to
11113 +a label. VALUE is the number of an internal label whose
11114 +definition is output using ASM_OUTPUT_INTERNAL_LABEL.
11117 +fprintf(STREAM, "\t.word L%d\n", VALUE)
11120 +#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
11121 + fprintf(STREAM, "\t.long %sL%d\n", LOCAL_LABEL_PREFIX, VALUE)
11123 +/** Assembler Commands for Exception Regions */
11125 +/* ToDo: All of this subsection */
11127 +/** Assembler Commands for Alignment */
11131 +A C statement to output to the stdio stream STREAM an assembler
11132 +command to advance the location counter to a multiple of 2 to the
11133 +POWER bytes. POWER will be a C expression of type int.
11135 +#define ASM_OUTPUT_ALIGN(STREAM, POWER) \
11138 + if ((POWER) != 0) \
11139 + fprintf(STREAM, "\t.align\t%d\n", POWER); \
11144 +Like ASM_OUTPUT_ALIGN, except that the \nop" instruction is used for padding, if
11147 +#define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \
11148 + fprintf(STREAM, "\t.balignw\t%d, 0xd703\n", (1 << POWER))
11152 +/******************************************************************************
11153 + * Controlling Debugging Information Format
11154 + *****************************************************************************/
11156 +/* How to renumber registers for dbx and gdb. */
11157 +#define DBX_REGISTER_NUMBER(REGNO) ASM_REGNUM (REGNO)
11159 +/* The DWARF 2 CFA column which tracks the return address. */
11160 +#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM(LR_REGNUM)
11163 +Define this macro if GCC should produce dwarf version 2 format
11164 +debugging output in response to the -g option.
11166 +To support optional call frame debugging information, you must also
11167 +define INCOMING_RETURN_ADDR_RTX and either set
11168 +RTX_FRAME_RELATED_P on the prologue insns if you use RTL for the
11169 +prologue, or call dwarf2out_def_cfa and dwarf2out_reg_save
11170 +as appropriate from TARGET_ASM_FUNCTION_PROLOGUE if you don't.
11172 +#define DWARF2_DEBUGGING_INFO 1
11175 +#define DWARF2_ASM_LINE_DEBUG_INFO 1
11176 +#define DWARF2_FRAME_INFO 1
11179 +/******************************************************************************
11180 + * Miscellaneous Parameters
11181 + *****************************************************************************/
11186 +An alias for a machine mode name. This is the machine mode that
11187 +elements of a jump-table should have.
11189 +#define CASE_VECTOR_MODE SImode
11192 +Define this macro to be a C expression to indicate when jump-tables
11193 +should contain relative addresses. If jump-tables never contain
11194 +relative addresses, then you need not define this macro.
11196 +#define CASE_VECTOR_PC_RELATIVE 0
11198 +/* Increase the threshold for using table jumps on the UC arch. */
11199 +#define CASE_VALUES_THRESHOLD (TARGET_BRANCH_PRED ? 4 : 7)
11202 +The maximum number of bytes that a single instruction can move quickly
11203 +between memory and registers or between two memory locations.
11205 +#define MOVE_MAX (2*UNITS_PER_WORD)
11208 +/* A C expression that is nonzero if on this machine the number of bits actually used
11209 + for the count of a shift operation is equal to the number of bits needed to represent
11210 + the size of the object being shifted. When this macro is nonzero, the compiler will
11211 + assume that it is safe to omit a sign-extend, zero-extend, and certain bitwise 'and'
11212 + instructions that truncates the count of a shift operation. On machines that have
11213 + instructions that act on bit-fields at variable positions, which may include 'bit test'
11214 + 378 GNU Compiler Collection (GCC) Internals
11215 + instructions, a nonzero SHIFT_COUNT_TRUNCATED also enables deletion of truncations
11216 + of the values that serve as arguments to bit-field instructions.
11217 + If both types of instructions truncate the count (for shifts) and position (for bit-field
11218 + operations), or if no variable-position bit-field instructions exist, you should define
11220 + However, on some machines, such as the 80386 and the 680x0, truncation only applies
11221 + to shift operations and not the (real or pretended) bit-field operations. Define SHIFT_
11222 + COUNT_TRUNCATED to be zero on such machines. Instead, add patterns to the 'md' file
11223 + that include the implied truncation of the shift instructions.
11224 + You need not de ne this macro if it would always have the value of zero. */
11225 +#define SHIFT_COUNT_TRUNCATED 1
11228 +A C expression which is nonzero if on this machine it is safe to
11229 +convert an integer of INPREC bits to one of OUTPREC
11230 +bits (where OUTPREC is smaller than INPREC) by merely
11231 +operating on it as if it had only OUTPREC bits.
11233 +On many machines, this expression can be 1.
11235 +When TRULY_NOOP_TRUNCATION returns 1 for a pair of sizes for
11236 +modes for which MODES_TIEABLE_P is 0, suboptimal code can result.
11237 +If this is the case, making TRULY_NOOP_TRUNCATION return 0 in
11238 +such cases may improve things.
11240 +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
11243 +An alias for the machine mode for pointers. On most machines, define
11244 +this to be the integer mode corresponding to the width of a hardware
11245 +pointer; SImode on 32-bit machine or DImode on 64-bit machines.
11246 +On some machines you must define this to be one of the partial integer
11247 +modes, such as PSImode.
11249 +The width of Pmode must be at least as large as the value of
11250 +POINTER_SIZE. If it is not equal, you must define the macro
11251 +POINTERS_EXTEND_UNSIGNED to specify how pointers are extended
11254 +#define Pmode SImode
11257 +An alias for the machine mode used for memory references to functions
11258 +being called, in call RTL expressions. On most machines this
11261 +#define FUNCTION_MODE SImode
11264 +#define REG_S_P(x) \
11265 + (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (XEXP (x, 0))))
11268 +/* If defined, modifies the length assigned to instruction INSN as a
11269 + function of the context in which it is used. LENGTH is an lvalue
11270 + that contains the initially computed length of the insn and should
11271 + be updated with the correct length of the insn. */
11272 +#define ADJUST_INSN_LENGTH(INSN, LENGTH) \
11273 + ((LENGTH) = avr32_adjust_insn_length ((INSN), (LENGTH)))
11276 +#define CLZ_DEFINED_VALUE_AT_ZERO(mode, value) \
11277 + (value = 32, (mode == SImode))
11279 +#define CTZ_DEFINED_VALUE_AT_ZERO(mode, value) \
11280 + (value = 32, (mode == SImode))
11282 +#define UNITS_PER_SIMD_WORD UNITS_PER_WORD
11284 +#define STORE_FLAG_VALUE 1
11287 +/* IF-conversion macros. */
11288 +#define IFCVT_MODIFY_INSN( CE_INFO, PATTERN, INSN ) \
11290 + (PATTERN) = avr32_ifcvt_modify_insn (CE_INFO, PATTERN, INSN, &num_true_changes); \
11293 +#define IFCVT_EXTRA_FIELDS \
11294 + int num_cond_clobber_insns; \
11295 + int num_extra_move_insns; \
11296 + rtx extra_move_insns[MAX_CONDITIONAL_EXECUTE]; \
11297 + rtx moved_insns[MAX_CONDITIONAL_EXECUTE];
11299 +#define IFCVT_INIT_EXTRA_FIELDS( CE_INFO ) \
11301 + (CE_INFO)->num_cond_clobber_insns = 0; \
11302 + (CE_INFO)->num_extra_move_insns = 0; \
11306 +#define IFCVT_MODIFY_CANCEL( CE_INFO ) avr32_ifcvt_modify_cancel (CE_INFO, &num_true_changes)
11308 +#define IFCVT_ALLOW_MODIFY_TEST_IN_INSN 1
11309 +#define IFCVT_COND_EXEC_BEFORE_RELOAD (TARGET_COND_EXEC_BEFORE_RELOAD)
11311 +enum avr32_builtins
11313 + AVR32_BUILTIN_MTSR,
11314 + AVR32_BUILTIN_MFSR,
11315 + AVR32_BUILTIN_MTDR,
11316 + AVR32_BUILTIN_MFDR,
11317 + AVR32_BUILTIN_CACHE,
11318 + AVR32_BUILTIN_SYNC,
11319 + AVR32_BUILTIN_SSRF,
11320 + AVR32_BUILTIN_CSRF,
11321 + AVR32_BUILTIN_TLBR,
11322 + AVR32_BUILTIN_TLBS,
11323 + AVR32_BUILTIN_TLBW,
11324 + AVR32_BUILTIN_BREAKPOINT,
11325 + AVR32_BUILTIN_XCHG,
11326 + AVR32_BUILTIN_LDXI,
11327 + AVR32_BUILTIN_BSWAP16,
11328 + AVR32_BUILTIN_BSWAP32,
11329 + AVR32_BUILTIN_COP,
11330 + AVR32_BUILTIN_MVCR_W,
11331 + AVR32_BUILTIN_MVRC_W,
11332 + AVR32_BUILTIN_MVCR_D,
11333 + AVR32_BUILTIN_MVRC_D,
11334 + AVR32_BUILTIN_MULSATHH_H,
11335 + AVR32_BUILTIN_MULSATHH_W,
11336 + AVR32_BUILTIN_MULSATRNDHH_H,
11337 + AVR32_BUILTIN_MULSATRNDWH_W,
11338 + AVR32_BUILTIN_MULSATWH_W,
11339 + AVR32_BUILTIN_MACSATHH_W,
11340 + AVR32_BUILTIN_SATADD_H,
11341 + AVR32_BUILTIN_SATSUB_H,
11342 + AVR32_BUILTIN_SATADD_W,
11343 + AVR32_BUILTIN_SATSUB_W,
11344 + AVR32_BUILTIN_MULWH_D,
11345 + AVR32_BUILTIN_MULNWH_D,
11346 + AVR32_BUILTIN_MACWH_D,
11347 + AVR32_BUILTIN_MACHH_D,
11348 + AVR32_BUILTIN_MUSFR,
11349 + AVR32_BUILTIN_MUSTR,
11350 + AVR32_BUILTIN_SATS,
11351 + AVR32_BUILTIN_SATU,
11352 + AVR32_BUILTIN_SATRNDS,
11353 + AVR32_BUILTIN_SATRNDU,
11354 + AVR32_BUILTIN_MEMS,
11355 + AVR32_BUILTIN_MEMC,
11356 + AVR32_BUILTIN_MEMT
11360 +#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) \
11361 + ((MODE == SFmode) || (MODE == DFmode))
11363 +#define RENAME_LIBRARY_SET ".set"
11365 +/* Make ABI_NAME an alias for __GCC_NAME. */
11366 +#define RENAME_LIBRARY(GCC_NAME, ABI_NAME) \
11367 + __asm__ (".globl\t__avr32_" #ABI_NAME "\n" \
11368 + ".set\t__avr32_" #ABI_NAME \
11369 + ", __" #GCC_NAME "\n");
11371 +/* Give libgcc functions avr32 ABI name. */
11373 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, mul64)
11376 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divdi3, sdiv64)
11379 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivdi3, udiv64)
11382 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (moddi3, smod64)
11385 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (umoddi3, umod64)
11388 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashldi3, lsl64)
11391 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (lshrdi3, lsr64)
11394 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashrdi3, asr64)
11398 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f32_to_s64)
11400 +#ifdef L_fixunssfdi
11401 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f32_to_u64)
11403 +#ifdef L_floatdidf
11404 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, s64_to_f64)
11406 +#ifdef L_floatdisf
11407 +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, s64_to_f32)
11412 +++ b/gcc/config/avr32/avr32.md
11414 +;; AVR32 machine description file.
11415 +;; Copyright 2003-2006 Atmel Corporation.
11417 +;; Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
11419 +;; This file is part of GCC.
11421 +;; This program is free software; you can redistribute it and/or modify
11422 +;; it under the terms of the GNU General Public License as published by
11423 +;; the Free Software Foundation; either version 2 of the License, or
11424 +;; (at your option) any later version.
11426 +;; This program is distributed in the hope that it will be useful,
11427 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
11428 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11429 +;; GNU General Public License for more details.
11431 +;; You should have received a copy of the GNU General Public License
11432 +;; along with this program; if not, write to the Free Software
11433 +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
11435 +;; -*- Mode: Scheme -*-
11437 +(define_attr "type" "alu,alu2,alu_sat,mulhh,mulwh,mulww_w,mulww_d,div,machh_w,macww_w,macww_d,branch,call,load,load_rm,store,load2,load4,store2,store4,fmul,fcmps,fcmpd,fcast,fmv,fmvcpu,fldd,fstd,flds,fsts,fstm"
11438 + (const_string "alu"))
11441 +(define_attr "cc" "none,set_vncz,set_ncz,set_cz,set_z,set_z_if_not_v2,bld,compare,cmp_cond_insn,clobber,call_set,fpcompare,from_fpcc"
11442 + (const_string "none"))
11445 +; NB! Keep this in sync with enum architecture_type in avr32.h
11446 +(define_attr "pipeline" "ap,ucr1,ucr2,ucr2nomul"
11447 + (const (symbol_ref "avr32_arch->arch_type")))
11449 +; Insn length in bytes
11450 +(define_attr "length" ""
11453 +; Signal if an insn is predicable and hence can be conditionally executed.
11454 +(define_attr "predicable" "no,yes" (const_string "no"))
11456 +;; Uses of UNSPEC in this file:
11458 + [(UNSPEC_PUSHM 0)
11460 + (UNSPEC_UDIVMODSI4_INTERNAL 2)
11461 + (UNSPEC_DIVMODSI4_INTERNAL 3)
11464 + (UNSPEC_MOVSICC 6)
11465 + (UNSPEC_ADDSICC 7)
11466 + (UNSPEC_COND_MI 8)
11467 + (UNSPEC_COND_PL 9)
11468 + (UNSPEC_PIC_SYM 10)
11469 + (UNSPEC_PIC_BASE 11)
11470 + (UNSPEC_STORE_MULTIPLE 12)
11471 + (UNSPEC_STMFP 13)
11472 + (UNSPEC_FPCC_TO_REG 14)
11473 + (UNSPEC_REG_TO_CC 15)
11474 + (UNSPEC_FORCE_MINIPOOL 16)
11477 + (UNSPEC_SATRNDS 19)
11478 + (UNSPEC_SATRNDU 20)
11482 + [(VUNSPEC_EPILOGUE 0)
11483 + (VUNSPEC_CACHE 1)
11486 + (VUNSPEC_BLOCKAGE 4)
11491 + (VUNSPEC_BREAKPOINT 9)
11492 + (VUNSPEC_MTDR 10)
11493 + (VUNSPEC_MFDR 11)
11494 + (VUNSPEC_MVCR 12)
11495 + (VUNSPEC_MVRC 13)
11497 + (VUNSPEC_ALIGN 15)
11498 + (VUNSPEC_POOL_START 16)
11499 + (VUNSPEC_POOL_END 17)
11500 + (VUNSPEC_POOL_4 18)
11501 + (VUNSPEC_POOL_8 19)
11502 + (VUNSPEC_POOL_16 20)
11503 + (VUNSPEC_MUSFR 21)
11504 + (VUNSPEC_MUSTR 22)
11505 + (VUNSPEC_SYNC_CMPXCHG 23)
11506 + (VUNSPEC_SYNC_SET_LOCK_AND_LOAD 24)
11507 + (VUNSPEC_SYNC_STORE_IF_LOCK 25)
11508 + (VUNSPEC_EH_RETURN 26)
11510 + (VUNSPEC_CSRF 28)
11511 + (VUNSPEC_SSRF 29)
11518 + ;; Return Register = R12 = 15 - 12 = 3
11519 + (RETVAL_REGNUM 3)
11520 + ;; SP = R13 = 15 - 13 = 2
11522 + ;; LR = R14 = 15 - 14 = 1
11524 + ;; PC = R15 = 15 - 15 = 0
11526 + ;; FPSR = GENERAL_REGS + 1 = 17
11533 +;;******************************************************************************
11535 +;;******************************************************************************
11537 +;; Integer Modes for basic alu insns
11538 +(define_mode_macro INTM [SI HI QI])
11539 +(define_mode_attr alu_cc_attr [(SI "set_vncz") (HI "clobber") (QI "clobber")])
11541 +;; Move word modes
11542 +(define_mode_macro MOVM [SI V2HI V4QI])
11544 +;; For mov/addcc insns
11545 +(define_mode_macro ADDCC [SI HI QI])
11546 +(define_mode_macro MOVCC [SF SI HI QI])
11547 +(define_mode_macro CMP [DI SI HI QI])
11548 +(define_mode_attr store_postfix [(SF ".w") (SI ".w") (HI ".h") (QI ".b")])
11549 +(define_mode_attr load_postfix [(SF ".w") (SI ".w") (HI ".sh") (QI ".ub")])
11550 +(define_mode_attr load_postfix_s [(SI ".w") (HI ".sh") (QI ".sb")])
11551 +(define_mode_attr load_postfix_u [(SI ".w") (HI ".uh") (QI ".ub")])
11552 +(define_mode_attr pred_mem_constraint [(SF "RKu11") (SI "RKu11") (HI "RKu10") (QI "RKu09")])
11553 +(define_mode_attr cmp_constraint [(DI "rKu20") (SI "rKs21") (HI "r") (QI "r")])
11554 +(define_mode_attr cmp_predicate [(DI "register_immediate_operand")
11555 + (SI "register_const_int_operand")
11556 + (HI "register_operand")
11557 + (QI "register_operand")])
11558 +(define_mode_attr cmp_length [(DI "6")
11563 +;; For all conditional insns
11564 +(define_code_macro any_cond [eq ne gt ge lt le gtu geu ltu leu])
11565 +(define_code_attr cond [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt") (le "le")
11566 + (gtu "hi") (geu "hs") (ltu "lo") (leu "ls")])
11567 +(define_code_attr invcond [(eq "ne") (ne "eq") (gt "le") (ge "lt") (lt "ge") (le "gt")
11568 + (gtu "ls") (geu "lo") (ltu "hs") (leu "hi")])
11570 +;; For logical operations
11571 +(define_code_macro logical [and ior xor])
11572 +(define_code_attr logical_insn [(and "and") (ior "or") (xor "eor")])
11574 +;; Predicable operations with three register operands
11575 +(define_code_macro predicable_op3 [and ior xor plus minus])
11576 +(define_code_attr predicable_insn3 [(and "and") (ior "or") (xor "eor") (plus "add") (minus "sub")])
11577 +(define_code_attr predicable_commutative3 [(and "%") (ior "%") (xor "%") (plus "%") (minus "")])
11579 +;; Load the predicates
11580 +(include "predicates.md")
11583 +;;******************************************************************************
11584 +;; Automaton pipeline description for avr32
11585 +;;******************************************************************************
11587 +(define_automaton "avr32_ap")
11590 +(define_cpu_unit "is" "avr32_ap")
11591 +(define_cpu_unit "a1,m1,da" "avr32_ap")
11592 +(define_cpu_unit "a2,m2,d" "avr32_ap")
11594 +;;Alu instructions
11595 +(define_insn_reservation "alu_op" 1
11596 + (and (eq_attr "pipeline" "ap")
11597 + (eq_attr "type" "alu"))
11600 +(define_insn_reservation "alu2_op" 2
11601 + (and (eq_attr "pipeline" "ap")
11602 + (eq_attr "type" "alu2"))
11603 + "is,is+a1,a1+a2,a2")
11605 +(define_insn_reservation "alu_sat_op" 2
11606 + (and (eq_attr "pipeline" "ap")
11607 + (eq_attr "type" "alu_sat"))
11611 +;;Mul instructions
11612 +(define_insn_reservation "mulhh_op" 2
11613 + (and (eq_attr "pipeline" "ap")
11614 + (eq_attr "type" "mulhh,mulwh"))
11617 +(define_insn_reservation "mulww_w_op" 3
11618 + (and (eq_attr "pipeline" "ap")
11619 + (eq_attr "type" "mulww_w"))
11620 + "is,m1,m1+m2,m2")
11622 +(define_insn_reservation "mulww_d_op" 5
11623 + (and (eq_attr "pipeline" "ap")
11624 + (eq_attr "type" "mulww_d"))
11625 + "is,m1,m1+m2,m1+m2,m2,m2")
11627 +(define_insn_reservation "div_op" 33
11628 + (and (eq_attr "pipeline" "ap")
11629 + (eq_attr "type" "div"))
11630 + "is,m1,m1*31 + m2*31,m2")
11632 +(define_insn_reservation "machh_w_op" 3
11633 + (and (eq_attr "pipeline" "ap")
11634 + (eq_attr "type" "machh_w"))
11638 +(define_insn_reservation "macww_w_op" 4
11639 + (and (eq_attr "pipeline" "ap")
11640 + (eq_attr "type" "macww_w"))
11644 +(define_insn_reservation "macww_d_op" 6
11645 + (and (eq_attr "pipeline" "ap")
11646 + (eq_attr "type" "macww_d"))
11647 + "is*2,m1,m1+m2,m1+m2,m2")
11649 +;;Bypasses for Mac instructions, because of accumulator cache.
11650 +;;Set latency as low as possible in order to let the compiler let
11651 +;;mul -> mac and mac -> mac combinations which use the same
11652 +;;accumulator cache be placed close together to avoid any
11653 +;;instructions which can ruin the accumulator cache come inbetween.
11654 +(define_bypass 4 "machh_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
11655 +(define_bypass 5 "macww_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
11656 +(define_bypass 7 "macww_d_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
11658 +(define_bypass 3 "mulhh_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
11659 +(define_bypass 4 "mulww_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
11660 +(define_bypass 6 "mulww_d_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass")
11663 +;;Bypasses for all mul/mac instructions followed by an instruction
11664 +;;which reads the output AND writes the result to the same register.
11665 +;;This will generate an Write After Write hazard which gives an
11666 +;;extra cycle before the result is ready.
11667 +(define_bypass 0 "machh_w_op" "machh_w_op" "avr32_valid_macmac_bypass")
11668 +(define_bypass 0 "macww_w_op" "macww_w_op" "avr32_valid_macmac_bypass")
11669 +(define_bypass 0 "macww_d_op" "macww_d_op" "avr32_valid_macmac_bypass")
11671 +(define_bypass 0 "mulhh_op" "machh_w_op" "avr32_valid_mulmac_bypass")
11672 +(define_bypass 0 "mulww_w_op" "macww_w_op" "avr32_valid_mulmac_bypass")
11673 +(define_bypass 0 "mulww_d_op" "macww_d_op" "avr32_valid_mulmac_bypass")
11675 +;;Branch and call instructions
11676 +;;We assume that all branches and rcalls are predicted correctly :-)
11677 +;;while calls use a lot of cycles.
11678 +(define_insn_reservation "branch_op" 0
11679 + (and (eq_attr "pipeline" "ap")
11680 + (eq_attr "type" "branch"))
11683 +(define_insn_reservation "call_op" 10
11684 + (and (eq_attr "pipeline" "ap")
11685 + (eq_attr "type" "call"))
11689 +;;Load store instructions
11690 +(define_insn_reservation "load_op" 2
11691 + (and (eq_attr "pipeline" "ap")
11692 + (eq_attr "type" "load"))
11695 +(define_insn_reservation "load_rm_op" 3
11696 + (and (eq_attr "pipeline" "ap")
11697 + (eq_attr "type" "load_rm"))
11701 +(define_insn_reservation "store_op" 0
11702 + (and (eq_attr "pipeline" "ap")
11703 + (eq_attr "type" "store"))
11707 +(define_insn_reservation "load_double_op" 3
11708 + (and (eq_attr "pipeline" "ap")
11709 + (eq_attr "type" "load2"))
11712 +(define_insn_reservation "load_quad_op" 4
11713 + (and (eq_attr "pipeline" "ap")
11714 + (eq_attr "type" "load4"))
11715 + "is,da,da+d,da+d,d")
11717 +(define_insn_reservation "store_double_op" 0
11718 + (and (eq_attr "pipeline" "ap")
11719 + (eq_attr "type" "store2"))
11723 +(define_insn_reservation "store_quad_op" 0
11724 + (and (eq_attr "pipeline" "ap")
11725 + (eq_attr "type" "store4"))
11726 + "is,da,da+d,da+d,d")
11728 +;;For store the operand to write to memory is read in d and
11729 +;;the real latency between any instruction and a store is therefore
11730 +;;one less than for the instructions which reads the operands in the first
11731 +;;excecution stage
11732 +(define_bypass 2 "load_double_op" "store_double_op" "avr32_store_bypass")
11733 +(define_bypass 3 "load_quad_op" "store_quad_op" "avr32_store_bypass")
11734 +(define_bypass 1 "load_op" "store_op" "avr32_store_bypass")
11735 +(define_bypass 2 "load_rm_op" "store_op" "avr32_store_bypass")
11736 +(define_bypass 1 "alu_sat_op" "store_op" "avr32_store_bypass")
11737 +(define_bypass 1 "alu2_op" "store_op" "avr32_store_bypass")
11738 +(define_bypass 1 "mulhh_op" "store_op" "avr32_store_bypass")
11739 +(define_bypass 2 "mulww_w_op" "store_op" "avr32_store_bypass")
11740 +(define_bypass 4 "mulww_d_op" "store_op" "avr32_store_bypass" )
11741 +(define_bypass 2 "machh_w_op" "store_op" "avr32_store_bypass")
11742 +(define_bypass 3 "macww_w_op" "store_op" "avr32_store_bypass")
11743 +(define_bypass 5 "macww_d_op" "store_op" "avr32_store_bypass")
11746 +; Bypass for load double operation. If only the first loaded word is needed
11747 +; then the latency is 2
11748 +(define_bypass 2 "load_double_op"
11749 + "load_op,load_rm_op,alu_sat_op, alu2_op, alu_op, mulhh_op, mulww_w_op,
11750 + mulww_d_op, machh_w_op, macww_w_op, macww_d_op"
11751 + "avr32_valid_load_double_bypass")
11753 +; Bypass for load quad operation. If only the first or second loaded word is needed
11754 +; we set the latency to 2
11755 +(define_bypass 2 "load_quad_op"
11756 + "load_op,load_rm_op,alu_sat_op, alu2_op, alu_op, mulhh_op, mulww_w_op,
11757 + mulww_d_op, machh_w_op, macww_w_op, macww_d_op"
11758 + "avr32_valid_load_quad_bypass")
11761 +;;******************************************************************************
11762 +;; End of Automaton pipeline description for avr32
11763 +;;******************************************************************************
11766 + [(match_operator 0 "avr32_comparison_operator"
11767 + [(match_operand:CMP 1 "register_operand" "r")
11768 + (match_operand:CMP 2 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")])]
11769 + "TARGET_V2_INSNS"
11774 + [(match_operator 0 "avr32_comparison_operator"
11775 + [(and:SI (match_operand:SI 1 "register_operand" "r")
11776 + (match_operand:SI 2 "one_bit_set_operand" "i"))
11778 + "TARGET_V2_INSNS"
11782 +;;=============================================================================
11784 +;;-----------------------------------------------------------------------------
11787 +;;== char - 8 bits ============================================================
11788 +(define_expand "movqi"
11789 + [(set (match_operand:QI 0 "nonimmediate_operand" "")
11790 + (match_operand:QI 1 "general_operand" ""))]
11793 + if ( !no_new_pseudos ){
11794 + if (GET_CODE (operands[1]) == MEM && optimize){
11795 + rtx reg = gen_reg_rtx (SImode);
11797 + emit_insn (gen_zero_extendqisi2 (reg, operands[1]));
11798 + operands[1] = gen_lowpart (QImode, reg);
11801 + /* One of the ops has to be in a register. */
11802 + if (GET_CODE (operands[0]) == MEM)
11803 + operands[1] = force_reg (QImode, operands[1]);
11808 +(define_insn "*movqi_internal"
11809 + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r")
11810 + (match_operand:QI 1 "general_operand" "rKs08,m,r,i"))]
11811 + "register_operand (operands[0], QImode)
11812 + || register_operand (operands[1], QImode)"
11818 + [(set_attr "length" "2,4,4,4")
11819 + (set_attr "type" "alu,load_rm,store,alu")])
11823 +;;== short - 16 bits ==========================================================
11824 +(define_expand "movhi"
11825 + [(set (match_operand:HI 0 "nonimmediate_operand" "")
11826 + (match_operand:HI 1 "general_operand" ""))]
11829 + if ( !no_new_pseudos ){
11830 + if (GET_CODE (operands[1]) == MEM && optimize){
11831 + rtx reg = gen_reg_rtx (SImode);
11833 + emit_insn (gen_extendhisi2 (reg, operands[1]));
11834 + operands[1] = gen_lowpart (HImode, reg);
11837 + /* One of the ops has to be in a register. */
11838 + if (GET_CODE (operands[0]) == MEM)
11839 + operands[1] = force_reg (HImode, operands[1]);
11845 +(define_insn "*movhi_internal"
11846 + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r")
11847 + (match_operand:HI 1 "general_operand" "rKs08,m,r,i"))]
11848 + "register_operand (operands[0], HImode)
11849 + || register_operand (operands[1], HImode)"
11855 + [(set_attr "length" "2,4,4,4")
11856 + (set_attr "type" "alu,load_rm,store,alu")])
11859 +;;== int - 32 bits ============================================================
11861 +(define_expand "movmisalignsi"
11862 + [(set (match_operand:SI 0 "nonimmediate_operand" "")
11863 + (match_operand:SI 1 "nonimmediate_operand" ""))]
11864 + "TARGET_UNALIGNED_WORD"
11870 +(define_expand "mov<mode>"
11871 + [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "")
11872 + (match_operand:MOVM 1 "avr32_non_rmw_general_operand" ""))]
11876 + /* One of the ops has to be in a register. */
11877 + if (GET_CODE (operands[0]) == MEM)
11878 + operands[1] = force_reg (<MODE>mode, operands[1]);
11881 + /* Check for out of range immediate constants as these may
11882 + occur during reloading, since it seems like reload does
11883 + not check if the immediate is legitimate. Don't know if
11884 + this is a bug? */
11885 + if ( reload_in_progress
11886 + && avr32_imm_in_const_pool
11887 + && GET_CODE(operands[1]) == CONST_INT
11888 + && !avr32_const_ok_for_constraint_p(INTVAL(operands[1]), 'K', "Ks21") ){
11889 + operands[1] = force_const_mem(SImode, operands[1]);
11892 + /* Check for RMW memory operands. They are not allowed for mov operations
11893 + only the atomic memc/s/t operations */
11894 + if ( !reload_in_progress
11895 + && avr32_rmw_memory_operand (operands[0], <MODE>mode) ){
11896 + operands[0] = copy_rtx (operands[0]);
11897 + XEXP(operands[0], 0) = force_reg (<MODE>mode, XEXP(operands[0], 0));
11900 + if ( !reload_in_progress
11901 + && avr32_rmw_memory_operand (operands[1], <MODE>mode) ){
11902 + operands[1] = copy_rtx (operands[1]);
11903 + XEXP(operands[1], 0) = force_reg (<MODE>mode, XEXP(operands[1], 0));
11906 + if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS)
11907 + && !avr32_legitimate_pic_operand_p(operands[1]) )
11908 + operands[1] = legitimize_pic_address (operands[1], <MODE>mode,
11909 + (no_new_pseudos ? operands[0] : 0));
11910 + else if ( flag_pic && avr32_address_operand(operands[1], GET_MODE(operands[1])) )
11911 + /* If we have an address operand then this function uses the pic register. */
11912 + current_function_uses_pic_offset_table = 1;
11917 +(define_insn "mov<mode>_internal"
11918 + [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "=r, r, r,r,r,Q,r")
11919 + (match_operand:MOVM 1 "avr32_non_rmw_general_operand" "rKs08,Ks21,J,n,Q,r,W"))]
11920 + "(register_operand (operands[0], <MODE>mode)
11921 + || register_operand (operands[1], <MODE>mode))
11922 + && !avr32_rmw_memory_operand (operands[0], <MODE>mode)
11923 + && !avr32_rmw_memory_operand (operands[1], <MODE>mode)"
11925 + switch (which_alternative) {
11927 + case 1: return "mov\t%0, %1";
11929 + if ( TARGET_V2_INSNS )
11930 + return "movh\t%0, hi(%1)";
11931 + /* Fallthrough */
11932 + case 3: return "mov\t%0, lo(%1)\;orh\t%0,hi(%1)";
11934 + if ( (REG_P(XEXP(operands[1], 0))
11935 + && REGNO(XEXP(operands[1], 0)) == SP_REGNUM)
11936 + || (GET_CODE(XEXP(operands[1], 0)) == PLUS
11937 + && REGNO(XEXP(XEXP(operands[1], 0), 0)) == SP_REGNUM
11938 + && GET_CODE(XEXP(XEXP(operands[1], 0), 1)) == CONST_INT
11939 + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) % 4 == 0
11940 + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) <= 0x1FC) )
11941 + return "lddsp\t%0, %1";
11942 + else if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])) )
11943 + return "lddpc\t%0, %1";
11945 + return "ld.w\t%0, %1";
11947 + if ( (REG_P(XEXP(operands[0], 0))
11948 + && REGNO(XEXP(operands[0], 0)) == SP_REGNUM)
11949 + || (GET_CODE(XEXP(operands[0], 0)) == PLUS
11950 + && REGNO(XEXP(XEXP(operands[0], 0), 0)) == SP_REGNUM
11951 + && GET_CODE(XEXP(XEXP(operands[0], 0), 1)) == CONST_INT
11952 + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) % 4 == 0
11953 + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) <= 0x1FC) )
11954 + return "stdsp\t%0, %1";
11956 + return "st.w\t%0, %1";
11958 + if ( TARGET_HAS_ASM_ADDR_PSEUDOS )
11959 + return "lda.w\t%0, %1";
11961 + return "ld.w\t%0, r6[%1@got]";
11967 + [(set_attr "length" "2,4,4,8,4,4,8")
11968 + (set_attr "type" "alu,alu,alu,alu2,load,store,load")
11969 + (set_attr "cc" "none,none,set_z_if_not_v2,set_z,none,none,clobber")])
11972 +(define_expand "reload_out_rmw_memory_operand"
11973 + [(set (match_operand:SI 2 "register_operand" "=r")
11974 + (match_operand:SI 0 "address_operand" ""))
11975 + (set (mem:SI (match_dup 2))
11976 + (match_operand:SI 1 "register_operand" ""))]
11979 + operands[0] = XEXP(operands[0], 0);
11983 +(define_expand "reload_in_rmw_memory_operand"
11984 + [(set (match_operand:SI 2 "register_operand" "=r")
11985 + (match_operand:SI 1 "address_operand" ""))
11986 + (set (match_operand:SI 0 "register_operand" "")
11987 + (mem:SI (match_dup 2)))]
11990 + operands[1] = XEXP(operands[1], 0);
11995 +;; These instructions are for loading constants which cannot be loaded
11996 +;; directly from the constant pool because the offset is too large
11997 +;; high and lo_sum are used even tough for our case it should be
11998 +;; low and high sum :-)
11999 +(define_insn "mov_symbol_lo"
12000 + [(set (match_operand:SI 0 "register_operand" "=r")
12001 + (high:SI (match_operand:SI 1 "immediate_operand" "i" )))]
12003 + "mov\t%0, lo(%1)"
12004 + [(set_attr "type" "alu")
12005 + (set_attr "length" "4")]
12008 +(define_insn "add_symbol_hi"
12009 + [(set (match_operand:SI 0 "register_operand" "=r")
12010 + (lo_sum:SI (match_dup 0)
12011 + (match_operand:SI 1 "immediate_operand" "i" )))]
12013 + "orh\t%0, hi(%1)"
12014 + [(set_attr "type" "alu")
12015 + (set_attr "length" "4")]
12020 +;; When generating pic, we need to load the symbol offset into a register.
12021 +;; So that the optimizer does not confuse this with a normal symbol load
12022 +;; we use an unspec. The offset will be loaded from a constant pool entry,
12023 +;; since that is the only type of relocation we can use.
12024 +(define_insn "pic_load_addr"
12025 + [(set (match_operand:SI 0 "register_operand" "=r")
12026 + (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC_SYM))]
12027 + "flag_pic && CONSTANT_POOL_ADDRESS_P(XEXP(operands[1], 0))"
12029 + [(set_attr "type" "load")
12030 + (set_attr "length" "4")]
12033 +(define_insn "pic_compute_got_from_pc"
12034 + [(set (match_operand:SI 0 "register_operand" "+r")
12035 + (unspec:SI [(minus:SI (pc)
12036 + (match_dup 0))] UNSPEC_PIC_BASE))
12037 + (use (label_ref (match_operand 1 "" "")))]
12040 + (*targetm.asm_out.internal_label) (asm_out_file, "L",
12041 + CODE_LABEL_NUMBER (operands[1]));
12042 + return \"rsub\t%0, pc\";
12044 + [(set_attr "cc" "clobber")
12045 + (set_attr "length" "2")]
12048 +;;== long long int - 64 bits ==================================================
12050 +(define_expand "movdi"
12051 + [(set (match_operand:DI 0 "nonimmediate_operand" "")
12052 + (match_operand:DI 1 "general_operand" ""))]
12056 + /* One of the ops has to be in a register. */
12057 + if (GET_CODE (operands[0]) != REG)
12058 + operands[1] = force_reg (DImode, operands[1]);
12063 +(define_insn_and_split "*movdi_internal"
12064 + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r, r, r,r,r,m")
12065 + (match_operand:DI 1 "general_operand" "r, Ks08,Ks21,G,n,m,r"))]
12066 + "register_operand (operands[0], DImode)
12067 + || register_operand (operands[1], DImode)"
12069 + switch (which_alternative ){
12077 + if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])))
12078 + return "ld.d\t%0, pc[%1 - .]";
12080 + return "ld.d\t%0, %1";
12082 + return "st.d\t%0, %1";
12087 +;; Lets split all reg->reg or imm->reg transfers into two SImode transfers
12088 + "reload_completed &&
12089 + (REG_P (operands[0]) &&
12090 + (REG_P (operands[1])
12091 + || GET_CODE (operands[1]) == CONST_INT
12092 + || GET_CODE (operands[1]) == CONST_DOUBLE))"
12093 + [(set (match_dup 0) (match_dup 1))
12094 + (set (match_dup 2) (match_dup 3))]
12096 + operands[2] = gen_highpart (SImode, operands[0]);
12097 + operands[0] = gen_lowpart (SImode, operands[0]);
12098 + if ( REG_P(operands[1]) ){
12099 + operands[3] = gen_highpart(SImode, operands[1]);
12100 + operands[1] = gen_lowpart(SImode, operands[1]);
12101 + } else if ( GET_CODE(operands[1]) == CONST_DOUBLE
12102 + || GET_CODE(operands[1]) == CONST_INT ){
12103 + rtx split_const[2];
12104 + avr32_split_const_expr (DImode, SImode, operands[1], split_const);
12105 + operands[3] = split_const[1];
12106 + operands[1] = split_const[0];
12108 + internal_error("Illegal operand[1] for movdi split!");
12112 + [(set_attr "length" "*,*,*,*,*,4,4")
12113 + (set_attr "type" "*,*,*,*,*,load2,store2")
12114 + (set_attr "cc" "*,*,*,*,*,none,none")])
12117 +;;== 128 bits ==================================================
12118 +(define_expand "movti"
12119 + [(set (match_operand:TI 0 "nonimmediate_operand" "")
12120 + (match_operand:TI 1 "nonimmediate_operand" ""))]
12124 + /* One of the ops has to be in a register. */
12125 + if (GET_CODE (operands[0]) != REG)
12126 + operands[1] = force_reg (TImode, operands[1]);
12128 + /* We must fix any pre_dec for loads and post_inc stores */
12129 + if ( GET_CODE (operands[0]) == MEM
12130 + && GET_CODE (XEXP(operands[0],0)) == POST_INC ){
12131 + emit_move_insn(gen_rtx_MEM(TImode, XEXP(XEXP(operands[0],0),0)), operands[1]);
12132 + emit_insn(gen_addsi3(XEXP(XEXP(operands[0],0),0), XEXP(XEXP(operands[0],0),0), GEN_INT(GET_MODE_SIZE(TImode))));
12136 + if ( GET_CODE (operands[1]) == MEM
12137 + && GET_CODE (XEXP(operands[1],0)) == PRE_DEC ){
12138 + emit_insn(gen_addsi3(XEXP(XEXP(operands[1],0),0), XEXP(XEXP(operands[1],0),0), GEN_INT(-GET_MODE_SIZE(TImode))));
12139 + emit_move_insn(operands[0], gen_rtx_MEM(TImode, XEXP(XEXP(operands[1],0),0)));
12145 +(define_insn_and_split "*movti_internal"
12146 + [(set (match_operand:TI 0 "avr32_movti_dst_operand" "=r,&r, r, <RKu00,r,r")
12147 + (match_operand:TI 1 "avr32_movti_src_operand" " r,RKu00>,RKu00,r, n,T"))]
12148 + "(register_operand (operands[0], TImode)
12149 + || register_operand (operands[1], TImode))"
12151 + switch (which_alternative ){
12157 + return "ldm\t%p1, %0";
12159 + return "stm\t%p0, %1";
12161 + return "ld.d\t%U0, pc[%1 - .]\;ld.d\t%B0, pc[%1 - . + 8]";
12165 + "reload_completed &&
12166 + (REG_P (operands[0]) &&
12167 + (REG_P (operands[1])
12168 + /* If this is a load from the constant pool we split it into
12169 + two double loads. */
12170 + || (GET_CODE (operands[1]) == MEM
12171 + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
12172 + && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
12173 + /* If this is a load where the pointer register is a part
12174 + of the register list, we must split it into two double
12175 + loads in order for it to be exception safe. */
12176 + || (GET_CODE (operands[1]) == MEM
12177 + && register_operand (XEXP (operands[1], 0), SImode)
12178 + && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0)))
12179 + || GET_CODE (operands[1]) == CONST_INT
12180 + || GET_CODE (operands[1]) == CONST_DOUBLE))"
12181 + [(set (match_dup 0) (match_dup 1))
12182 + (set (match_dup 2) (match_dup 3))]
12184 + operands[2] = simplify_gen_subreg ( DImode, operands[0],
12186 + operands[0] = simplify_gen_subreg ( DImode, operands[0],
12188 + if ( REG_P(operands[1]) ){
12189 + operands[3] = simplify_gen_subreg ( DImode, operands[1],
12191 + operands[1] = simplify_gen_subreg ( DImode, operands[1],
12193 + } else if ( GET_CODE(operands[1]) == CONST_DOUBLE
12194 + || GET_CODE(operands[1]) == CONST_INT ){
12195 + rtx split_const[2];
12196 + avr32_split_const_expr (TImode, DImode, operands[1], split_const);
12197 + operands[3] = split_const[1];
12198 + operands[1] = split_const[0];
12199 + } else if (avr32_const_pool_ref_operand (operands[1], GET_MODE(operands[1]))){
12200 + rtx split_const[2];
12201 + rtx cop = avoid_constant_pool_reference (operands[1]);
12202 + if (operands[1] == cop)
12203 + cop = get_pool_constant (XEXP (operands[1], 0));
12204 + avr32_split_const_expr (TImode, DImode, cop, split_const);
12205 + operands[3] = force_const_mem (DImode, split_const[1]);
12206 + operands[1] = force_const_mem (DImode, split_const[0]);
12208 + rtx ptr_reg = XEXP (operands[1], 0);
12209 + operands[1] = gen_rtx_MEM (DImode,
12210 + gen_rtx_PLUS ( SImode,
12213 + operands[3] = gen_rtx_MEM (DImode,
12216 + /* Check if the first load will clobber the pointer.
12217 + If so, we must switch the order of the operations. */
12218 + if ( reg_overlap_mentioned_p (operands[0], ptr_reg) )
12220 + /* We need to switch the order of the operations
12221 + so that the pointer register does not get clobbered
12222 + after the first double word load. */
12224 + tmp = operands[0];
12225 + operands[0] = operands[2];
12226 + operands[2] = tmp;
12227 + tmp = operands[1];
12228 + operands[1] = operands[3];
12229 + operands[3] = tmp;
12235 + [(set_attr "length" "*,*,4,4,*,8")
12236 + (set_attr "type" "*,*,load4,store4,*,load4")])
12239 +;;== float - 32 bits ==========================================================
12240 +(define_expand "movsf"
12241 + [(set (match_operand:SF 0 "nonimmediate_operand" "")
12242 + (match_operand:SF 1 "general_operand" ""))]
12247 + /* One of the ops has to be in a register. */
12248 + if (GET_CODE (operands[0]) != REG)
12249 + operands[1] = force_reg (SFmode, operands[1]);
12253 +(define_insn "*movsf_internal"
12254 + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m")
12255 + (match_operand:SF 1 "general_operand" "r, G,F,m,r"))]
12256 + "(register_operand (operands[0], SFmode)
12257 + || register_operand (operands[1], SFmode))"
12259 + switch (which_alternative) {
12261 + case 1: return "mov\t%0, %1";
12264 + HOST_WIDE_INT target_float[2];
12265 + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode);
12266 + if ( TARGET_V2_INSNS
12267 + && avr32_hi16_immediate_operand (GEN_INT (target_float[0]), VOIDmode) )
12268 + return "movh\t%0, hi(%1)";
12270 + return "mov\t%0, lo(%1)\;orh\t%0, hi(%1)";
12273 + if ( (REG_P(XEXP(operands[1], 0))
12274 + && REGNO(XEXP(operands[1], 0)) == SP_REGNUM)
12275 + || (GET_CODE(XEXP(operands[1], 0)) == PLUS
12276 + && REGNO(XEXP(XEXP(operands[1], 0), 0)) == SP_REGNUM
12277 + && GET_CODE(XEXP(XEXP(operands[1], 0), 1)) == CONST_INT
12278 + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) % 4 == 0
12279 + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) <= 0x1FC) )
12280 + return "lddsp\t%0, %1";
12281 + else if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])) )
12282 + return "lddpc\t%0, %1";
12284 + return "ld.w\t%0, %1";
12286 + if ( (REG_P(XEXP(operands[0], 0))
12287 + && REGNO(XEXP(operands[0], 0)) == SP_REGNUM)
12288 + || (GET_CODE(XEXP(operands[0], 0)) == PLUS
12289 + && REGNO(XEXP(XEXP(operands[0], 0), 0)) == SP_REGNUM
12290 + && GET_CODE(XEXP(XEXP(operands[0], 0), 1)) == CONST_INT
12291 + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) % 4 == 0
12292 + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) <= 0x1FC) )
12293 + return "stdsp\t%0, %1";
12295 + return "st.w\t%0, %1";
12301 + [(set_attr "length" "2,4,8,4,4")
12302 + (set_attr "type" "alu,alu,alu2,load,store")
12303 + (set_attr "cc" "none,none,clobber,none,none")])
12307 +;;== double - 64 bits =========================================================
12308 +(define_expand "movdf"
12309 + [(set (match_operand:DF 0 "nonimmediate_operand" "")
12310 + (match_operand:DF 1 "general_operand" ""))]
12313 + /* One of the ops has to be in a register. */
12314 + if (GET_CODE (operands[0]) != REG){
12315 + operands[1] = force_reg (DFmode, operands[1]);
12320 +(define_insn_and_split "*movdf_internal"
12321 + [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,r,r,m")
12322 + (match_operand:DF 1 "general_operand" " r,G,F,m,r"))]
12323 + "TARGET_SOFT_FLOAT
12324 + && (register_operand (operands[0], DFmode)
12325 + || register_operand (operands[1], DFmode))"
12327 + switch (which_alternative ){
12333 + if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])))
12334 + return "ld.d\t%0, pc[%1 - .]";
12336 + return "ld.d\t%0, %1";
12338 + return "st.d\t%0, %1";
12343 + "TARGET_SOFT_FLOAT
12344 + && reload_completed
12345 + && (REG_P (operands[0])
12346 + && (REG_P (operands[1])
12347 + || GET_CODE (operands[1]) == CONST_DOUBLE))"
12348 + [(set (match_dup 0) (match_dup 1))
12349 + (set (match_dup 2) (match_dup 3))]
12352 + operands[2] = gen_highpart (SImode, operands[0]);
12353 + operands[0] = gen_lowpart (SImode, operands[0]);
12354 + operands[3] = gen_highpart(SImode, operands[1]);
12355 + operands[1] = gen_lowpart(SImode, operands[1]);
12359 + [(set_attr "length" "*,*,*,4,4")
12360 + (set_attr "type" "*,*,*,load2,store2")
12361 + (set_attr "cc" "*,*,*,none,none")])
12364 +;;=============================================================================
12365 +;; Conditional Moves
12366 +;;=============================================================================
12367 +(define_insn "ld<mode>_predicable"
12368 + [(set (match_operand:MOVCC 0 "register_operand" "=r")
12369 + (match_operand:MOVCC 1 "avr32_non_rmw_memory_operand" "<MOVCC:pred_mem_constraint>"))]
12370 + "TARGET_V2_INSNS"
12371 + "ld<MOVCC:load_postfix>%?\t%0, %1"
12372 + [(set_attr "length" "4")
12373 + (set_attr "cc" "cmp_cond_insn")
12374 + (set_attr "type" "load")
12375 + (set_attr "predicable" "yes")]
12379 +(define_insn "st<mode>_predicable"
12380 + [(set (match_operand:MOVCC 0 "avr32_non_rmw_memory_operand" "=<MOVCC:pred_mem_constraint>")
12381 + (match_operand:MOVCC 1 "register_operand" "r"))]
12382 + "TARGET_V2_INSNS"
12383 + "st<MOVCC:store_postfix>%?\t%0, %1"
12384 + [(set_attr "length" "4")
12385 + (set_attr "cc" "cmp_cond_insn")
12386 + (set_attr "type" "store")
12387 + (set_attr "predicable" "yes")]
12390 +(define_insn "mov<mode>_predicable"
12391 + [(set (match_operand:MOVCC 0 "register_operand" "=r")
12392 + (match_operand:MOVCC 1 "avr32_cond_register_immediate_operand" "rKs08"))]
12395 + [(set_attr "length" "4")
12396 + (set_attr "cc" "cmp_cond_insn")
12397 + (set_attr "type" "alu")
12398 + (set_attr "predicable" "yes")]
12402 +;;=============================================================================
12403 +;; Move chunks of memory
12404 +;;=============================================================================
12406 +(define_expand "movmemsi"
12407 + [(match_operand:BLK 0 "general_operand" "")
12408 + (match_operand:BLK 1 "general_operand" "")
12409 + (match_operand:SI 2 "const_int_operand" "")
12410 + (match_operand:SI 3 "const_int_operand" "")]
12413 + if (avr32_gen_movmemsi (operands))
12422 +;;=============================================================================
12423 +;; Bit field instructions
12424 +;;-----------------------------------------------------------------------------
12425 +;; Instructions to insert or extract bit-fields
12426 +;;=============================================================================
12428 +(define_insn "insv"
12429 + [ (set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
12430 + (match_operand:SI 1 "immediate_operand" "Ku05")
12431 + (match_operand:SI 2 "immediate_operand" "Ku05"))
12432 + (match_operand 3 "register_operand" "r"))]
12434 + "bfins\t%0, %3, %2, %1"
12435 + [(set_attr "type" "alu")
12436 + (set_attr "length" "4")
12437 + (set_attr "cc" "set_ncz")])
12441 +(define_expand "extv"
12442 + [ (set (match_operand:SI 0 "register_operand" "")
12443 + (sign_extract:SI (match_operand:SI 1 "register_operand" "")
12444 + (match_operand:SI 2 "immediate_operand" "")
12445 + (match_operand:SI 3 "immediate_operand" "")))]
12448 + if ( INTVAL(operands[2]) >= 32 )
12453 +(define_expand "extzv"
12454 + [ (set (match_operand:SI 0 "register_operand" "")
12455 + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
12456 + (match_operand:SI 2 "immediate_operand" "")
12457 + (match_operand:SI 3 "immediate_operand" "")))]
12460 + if ( INTVAL(operands[2]) >= 32 )
12465 +(define_insn "extv_internal"
12466 + [ (set (match_operand:SI 0 "register_operand" "=r")
12467 + (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
12468 + (match_operand:SI 2 "immediate_operand" "Ku05")
12469 + (match_operand:SI 3 "immediate_operand" "Ku05")))]
12470 + "INTVAL(operands[2]) < 32"
12471 + "bfexts\t%0, %1, %3, %2"
12472 + [(set_attr "type" "alu")
12473 + (set_attr "length" "4")
12474 + (set_attr "cc" "set_ncz")])
12477 +(define_insn "extzv_internal"
12478 + [ (set (match_operand:SI 0 "register_operand" "=r")
12479 + (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
12480 + (match_operand:SI 2 "immediate_operand" "Ku05")
12481 + (match_operand:SI 3 "immediate_operand" "Ku05")))]
12482 + "INTVAL(operands[2]) < 32"
12483 + "bfextu\t%0, %1, %3, %2"
12484 + [(set_attr "type" "alu")
12485 + (set_attr "length" "4")
12486 + (set_attr "cc" "set_ncz")])
12490 +;;=============================================================================
12491 +;; Some peepholes for avoiding unnecessary cast instructions
12492 +;; followed by bfins.
12493 +;;-----------------------------------------------------------------------------
12496 + [(set (match_operand:SI 0 "register_operand" "")
12497 + (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
12498 + (set (zero_extract:SI (match_operand 2 "register_operand" "")
12499 + (match_operand:SI 3 "immediate_operand" "")
12500 + (match_operand:SI 4 "immediate_operand" ""))
12502 + "((peep2_reg_dead_p(2, operands[0]) &&
12503 + (INTVAL(operands[3]) <= 8)))"
12504 + [(set (zero_extract:SI (match_dup 2)
12511 + [(set (match_operand:SI 0 "register_operand" "")
12512 + (zero_extend:SI (match_operand:HI 1 "register_operand" "")))
12513 + (set (zero_extract:SI (match_operand 2 "register_operand" "")
12514 + (match_operand:SI 3 "immediate_operand" "")
12515 + (match_operand:SI 4 "immediate_operand" ""))
12517 + "((peep2_reg_dead_p(2, operands[0]) &&
12518 + (INTVAL(operands[3]) <= 16)))"
12519 + [(set (zero_extract:SI (match_dup 2)
12525 +;;=============================================================================
12527 +;;-----------------------------------------------------------------------------
12528 +;; Implements the push instruction
12529 +;;=============================================================================
12530 +(define_insn "pushm"
12531 + [(set (mem:BLK (pre_dec:BLK (reg:SI SP_REGNUM)))
12532 + (unspec:BLK [(match_operand 0 "const_int_operand" "")]
12536 + if (INTVAL(operands[0])) {
12537 + return "pushm\t%r0";
12542 + [(set_attr "type" "store")
12543 + (set_attr "length" "2")
12544 + (set_attr "cc" "none")])
12546 +(define_insn "stm"
12547 + [(unspec [(match_operand 0 "register_operand" "r")
12548 + (match_operand 1 "const_int_operand" "")
12549 + (match_operand 2 "const_int_operand" "")]
12553 + if (INTVAL(operands[1])) {
12554 + if (INTVAL(operands[2]) != 0)
12555 + return "stm\t--%0, %s1";
12557 + return "stm\t%0, %s1";
12562 + [(set_attr "type" "store")
12563 + (set_attr "length" "4")
12564 + (set_attr "cc" "none")])
12568 +(define_insn "popm"
12569 + [(unspec [(match_operand 0 "const_int_operand" "")]
12573 + if (INTVAL(operands[0])) {
12574 + return "popm %r0";
12579 + [(set_attr "type" "load")
12580 + (set_attr "length" "2")])
12584 +;;=============================================================================
12586 +;;-----------------------------------------------------------------------------
12587 +;; Adds reg1 with reg2 and puts the result in reg0.
12588 +;;=============================================================================
12589 +(define_insn "add<mode>3"
12590 + [(set (match_operand:INTM 0 "register_operand" "=r,r,r,r,r")
12591 + (plus:INTM (match_operand:INTM 1 "register_operand" "%0,r,0,r,0")
12592 + (match_operand:INTM 2 "avr32_add_operand" "r,r,Is08,Is16,Is21")))]
12601 + [(set_attr "length" "2,4,2,4,4")
12602 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12604 +(define_insn "add<mode>3_lsl"
12605 + [(set (match_operand:INTM 0 "register_operand" "=r")
12606 + (plus:INTM (ashift:INTM (match_operand:INTM 1 "register_operand" "r")
12607 + (match_operand:INTM 3 "avr32_add_shift_immediate_operand" "Ku02"))
12608 + (match_operand:INTM 2 "register_operand" "r")))]
12610 + "add %0, %2, %1 << %3"
12611 + [(set_attr "length" "4")
12612 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12614 +(define_insn "add<mode>3_lsl2"
12615 + [(set (match_operand:INTM 0 "register_operand" "=r")
12616 + (plus:INTM (match_operand:INTM 1 "register_operand" "r")
12617 + (ashift:INTM (match_operand:INTM 2 "register_operand" "r")
12618 + (match_operand:INTM 3 "avr32_add_shift_immediate_operand" "Ku02"))))]
12620 + "add %0, %1, %2 << %3"
12621 + [(set_attr "length" "4")
12622 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12625 +(define_insn "add<mode>3_mul"
12626 + [(set (match_operand:INTM 0 "register_operand" "=r")
12627 + (plus:INTM (mult:INTM (match_operand:INTM 1 "register_operand" "r")
12628 + (match_operand:INTM 3 "immediate_operand" "Ku04" ))
12629 + (match_operand:INTM 2 "register_operand" "r")))]
12630 + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) ||
12631 + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)"
12632 + "add %0, %2, %1 << %p3"
12633 + [(set_attr "length" "4")
12634 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12636 +(define_insn "add<mode>3_mul2"
12637 + [(set (match_operand:INTM 0 "register_operand" "=r")
12638 + (plus:INTM (match_operand:INTM 1 "register_operand" "r")
12639 + (mult:INTM (match_operand:INTM 2 "register_operand" "r")
12640 + (match_operand:INTM 3 "immediate_operand" "Ku04" ))))]
12641 + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) ||
12642 + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)"
12643 + "add %0, %1, %2 << %p3"
12644 + [(set_attr "length" "4")
12645 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12649 + [(set (match_operand:SI 0 "register_operand" "")
12650 + (ashift:SI (match_operand:SI 1 "register_operand" "")
12651 + (match_operand:SI 2 "immediate_operand" "")))
12652 + (set (match_operand:SI 3 "register_operand" "")
12653 + (plus:SI (match_dup 0)
12654 + (match_operand:SI 4 "register_operand" "")))]
12655 + "(peep2_reg_dead_p(2, operands[0]) &&
12656 + (INTVAL(operands[2]) < 4 && INTVAL(operands[2]) > 0))"
12657 + [(set (match_dup 3)
12658 + (plus:SI (ashift:SI (match_dup 1)
12664 + [(set (match_operand:SI 0 "register_operand" "")
12665 + (ashift:SI (match_operand:SI 1 "register_operand" "")
12666 + (match_operand:SI 2 "immediate_operand" "")))
12667 + (set (match_operand:SI 3 "register_operand" "")
12668 + (plus:SI (match_operand:SI 4 "register_operand" "")
12670 + "(peep2_reg_dead_p(2, operands[0]) &&
12671 + (INTVAL(operands[2]) < 4 && INTVAL(operands[2]) > 0))"
12672 + [(set (match_dup 3)
12673 + (plus:SI (ashift:SI (match_dup 1)
12678 +(define_insn "adddi3"
12679 + [(set (match_operand:DI 0 "register_operand" "=r,r")
12680 + (plus:DI (match_operand:DI 1 "register_operand" "%0,r")
12681 + (match_operand:DI 2 "register_operand" "r,r")))]
12684 + add %0, %2\;adc %m0, %m0, %m2
12685 + add %0, %1, %2\;adc %m0, %m1, %m2"
12686 + [(set_attr "length" "6,8")
12687 + (set_attr "type" "alu2")
12688 + (set_attr "cc" "set_vncz")])
12691 +(define_insn "add<mode>_imm_predicable"
12692 + [(set (match_operand:INTM 0 "register_operand" "+r")
12693 + (plus:INTM (match_dup 0)
12694 + (match_operand:INTM 1 "avr32_cond_immediate_operand" "%Is08")))]
12697 + [(set_attr "length" "4")
12698 + (set_attr "cc" "cmp_cond_insn")
12699 + (set_attr "predicable" "yes")]
12702 +;;=============================================================================
12704 +;;-----------------------------------------------------------------------------
12705 +;; Subtract reg2 or immediate value from reg0 and puts the result in reg0.
12706 +;;=============================================================================
12708 +(define_insn "sub<mode>3"
12709 + [(set (match_operand:INTM 0 "general_operand" "=r,r,r,r,r,r,r")
12710 + (minus:INTM (match_operand:INTM 1 "nonmemory_operand" "0,r,0,r,0,r,Ks08")
12711 + (match_operand:INTM 2 "nonmemory_operand" "r,r,Ks08,Ks16,Ks21,0,r")))]
12721 + [(set_attr "length" "2,4,2,4,4,2,4")
12722 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12724 +(define_insn "*sub<mode>3_mul"
12725 + [(set (match_operand:INTM 0 "register_operand" "=r")
12726 + (minus:INTM (match_operand:INTM 1 "register_operand" "r")
12727 + (mult:INTM (match_operand:INTM 2 "register_operand" "r")
12728 + (match_operand:SI 3 "immediate_operand" "Ku04" ))))]
12729 + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) ||
12730 + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)"
12731 + "sub %0, %1, %2 << %p3"
12732 + [(set_attr "length" "4")
12733 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12735 +(define_insn "*sub<mode>3_lsl"
12736 + [(set (match_operand:INTM 0 "register_operand" "=r")
12737 + (minus:INTM (match_operand:INTM 1 "register_operand" "r")
12738 + (ashift:INTM (match_operand:INTM 2 "register_operand" "r")
12739 + (match_operand:SI 3 "avr32_add_shift_immediate_operand" "Ku02"))))]
12741 + "sub %0, %1, %2 << %3"
12742 + [(set_attr "length" "4")
12743 + (set_attr "cc" "<INTM:alu_cc_attr>")])
12746 +(define_insn "subdi3"
12747 + [(set (match_operand:DI 0 "register_operand" "=r,r")
12748 + (minus:DI (match_operand:DI 1 "register_operand" "%0,r")
12749 + (match_operand:DI 2 "register_operand" "r,r")))]
12752 + sub %0, %2\;sbc %m0, %m0, %m2
12753 + sub %0, %1, %2\;sbc %m0, %m1, %m2"
12754 + [(set_attr "length" "6,8")
12755 + (set_attr "type" "alu2")
12756 + (set_attr "cc" "set_vncz")])
12759 +(define_insn "sub<mode>_imm_predicable"
12760 + [(set (match_operand:INTM 0 "register_operand" "+r")
12761 + (minus:INTM (match_dup 0)
12762 + (match_operand:INTM 1 "avr32_cond_immediate_operand" "Ks08")))]
12765 + [(set_attr "length" "4")
12766 + (set_attr "cc" "cmp_cond_insn")
12767 + (set_attr "predicable" "yes")])
12769 +(define_insn "rsub<mode>_imm_predicable"
12770 + [(set (match_operand:INTM 0 "register_operand" "+r")
12771 + (minus:INTM (match_operand:INTM 1 "avr32_cond_immediate_operand" "Ks08")
12775 + [(set_attr "length" "4")
12776 + (set_attr "cc" "cmp_cond_insn")
12777 + (set_attr "predicable" "yes")])
12779 +;;=============================================================================
12781 +;;-----------------------------------------------------------------------------
12782 +;; Multiply op1 and op2 and put the value in op0.
12783 +;;=============================================================================
12786 +(define_insn "mulqi3"
12787 + [(set (match_operand:QI 0 "register_operand" "=r,r,r")
12788 + (mult:QI (match_operand:QI 1 "register_operand" "%0,r,r")
12789 + (match_operand:QI 2 "avr32_mul_operand" "r,r,Ks08")))]
12790 + "!TARGET_NO_MUL_INSNS"
12792 + switch (which_alternative){
12794 + return "mul %0, %2";
12796 + return "mul %0, %1, %2";
12798 + return "mul %0, %1, %2";
12800 + gcc_unreachable();
12803 + [(set_attr "type" "mulww_w,mulww_w,mulwh")
12804 + (set_attr "length" "2,4,4")
12805 + (set_attr "cc" "none")])
12807 +(define_insn "mulsi3"
12808 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
12809 + (mult:SI (match_operand:SI 1 "register_operand" "%0,r,r")
12810 + (match_operand:SI 2 "avr32_mul_operand" "r,r,Ks08")))]
12811 + "!TARGET_NO_MUL_INSNS"
12813 + switch (which_alternative){
12815 + return "mul %0, %2";
12817 + return "mul %0, %1, %2";
12819 + return "mul %0, %1, %2";
12821 + gcc_unreachable();
12824 + [(set_attr "type" "mulww_w,mulww_w,mulwh")
12825 + (set_attr "length" "2,4,4")
12826 + (set_attr "cc" "none")])
12829 +(define_insn "mulhisi3"
12830 + [(set (match_operand:SI 0 "register_operand" "=r")
12832 + (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
12833 + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
12834 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
12835 + "mulhh.w %0, %1:b, %2:b"
12836 + [(set_attr "type" "mulhh")
12837 + (set_attr "length" "4")
12838 + (set_attr "cc" "none")])
12841 + [(match_scratch:DI 6 "r")
12842 + (set (match_operand:SI 0 "register_operand" "")
12844 + (sign_extend:SI (match_operand:HI 1 "register_operand" ""))
12845 + (sign_extend:SI (match_operand:HI 2 "register_operand" ""))))
12846 + (set (match_operand:SI 3 "register_operand" "")
12847 + (ashiftrt:SI (match_dup 0)
12848 + (const_int 16)))]
12849 + "!TARGET_NO_MUL_INSNS && TARGET_DSP
12850 + && (peep2_reg_dead_p(1, operands[0]) || (REGNO(operands[0]) == REGNO(operands[3])))"
12851 + [(set (match_dup 4) (sign_extend:SI (match_dup 1)))
12852 + (set (match_dup 6)
12853 + (ashift:DI (mult:DI (sign_extend:DI (match_dup 4))
12854 + (sign_extend:DI (match_dup 2)))
12856 + (set (match_dup 3) (match_dup 5))]
12859 + operands[4] = gen_rtx_REG(SImode, REGNO(operands[1]));
12860 + operands[5] = gen_highpart (SImode, operands[4]);
12864 +(define_insn "mulnhisi3"
12865 + [(set (match_operand:SI 0 "register_operand" "=r")
12867 + (sign_extend:SI (neg:HI (match_operand:HI 1 "register_operand" "r")))
12868 + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))]
12869 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
12870 + "mulnhh.w %0, %1:b, %2:b"
12871 + [(set_attr "type" "mulhh")
12872 + (set_attr "length" "4")
12873 + (set_attr "cc" "none")])
12875 +(define_insn "machisi3"
12876 + [(set (match_operand:SI 0 "register_operand" "+r")
12877 + (plus:SI (mult:SI
12878 + (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
12879 + (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))
12881 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
12882 + "machh.w %0, %1:b, %2:b"
12883 + [(set_attr "type" "machh_w")
12884 + (set_attr "length" "4")
12885 + (set_attr "cc" "none")])
12889 +(define_insn "mulsidi3"
12890 + [(set (match_operand:DI 0 "register_operand" "=r")
12892 + (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
12893 + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
12894 + "!TARGET_NO_MUL_INSNS"
12895 + "muls.d %0, %1, %2"
12896 + [(set_attr "type" "mulww_d")
12897 + (set_attr "length" "4")
12898 + (set_attr "cc" "none")])
12900 +(define_insn "umulsidi3"
12901 + [(set (match_operand:DI 0 "register_operand" "=r")
12903 + (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
12904 + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
12905 + "!TARGET_NO_MUL_INSNS"
12906 + "mulu.d %0, %1, %2"
12907 + [(set_attr "type" "mulww_d")
12908 + (set_attr "length" "4")
12909 + (set_attr "cc" "none")])
12911 +(define_insn "*mulaccsi3"
12912 + [(set (match_operand:SI 0 "register_operand" "+r")
12913 + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r")
12914 + (match_operand:SI 2 "register_operand" "r"))
12916 + "!TARGET_NO_MUL_INSNS"
12918 + [(set_attr "type" "macww_w")
12919 + (set_attr "length" "4")
12920 + (set_attr "cc" "none")])
12922 +(define_insn "*mulaccsidi3"
12923 + [(set (match_operand:DI 0 "register_operand" "+r")
12924 + (plus:DI (mult:DI
12925 + (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
12926 + (sign_extend:DI (match_operand:SI 2 "register_operand" "r")))
12928 + "!TARGET_NO_MUL_INSNS"
12929 + "macs.d %0, %1, %2"
12930 + [(set_attr "type" "macww_d")
12931 + (set_attr "length" "4")
12932 + (set_attr "cc" "none")])
12934 +(define_insn "*umulaccsidi3"
12935 + [(set (match_operand:DI 0 "register_operand" "+r")
12936 + (plus:DI (mult:DI
12937 + (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
12938 + (zero_extend:DI (match_operand:SI 2 "register_operand" "r")))
12940 + "!TARGET_NO_MUL_INSNS"
12941 + "macu.d %0, %1, %2"
12942 + [(set_attr "type" "macww_d")
12943 + (set_attr "length" "4")
12944 + (set_attr "cc" "none")])
12948 +;; Try to avoid Write-After-Write hazards for mul operations
12949 +;; if it can be done
12951 + [(set (match_operand:SI 0 "register_operand" "")
12953 + (sign_extend:SI (match_operand 1 "general_operand" ""))
12954 + (sign_extend:SI (match_operand 2 "general_operand" ""))))
12955 + (set (match_dup 0)
12956 + (match_operator:SI 3 "alu_operator" [(match_dup 0)
12957 + (match_operand 4 "general_operand" "")]))]
12958 + "peep2_reg_dead_p(1, operands[2])"
12959 + [(set (match_dup 5)
12961 + (sign_extend:SI (match_dup 1))
12962 + (sign_extend:SI (match_dup 2))))
12963 + (set (match_dup 0)
12964 + (match_op_dup 3 [(match_dup 5)
12965 + (match_dup 4)]))]
12966 + "{operands[5] = gen_rtx_REG(SImode, REGNO(operands[2]));}"
12971 +;;=============================================================================
12972 +;; DSP instructions
12973 +;;=============================================================================
12974 +(define_insn "mulsathh_h"
12975 + [(set (match_operand:HI 0 "register_operand" "=r")
12976 + (ss_truncate:HI (ashiftrt:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
12977 + (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))
12978 + (const_int 15))))]
12979 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
12980 + "mulsathh.h\t%0, %1:b, %2:b"
12981 + [(set_attr "length" "4")
12982 + (set_attr "cc" "none")
12983 + (set_attr "type" "mulhh")])
12985 +(define_insn "mulsatrndhh_h"
12986 + [(set (match_operand:HI 0 "register_operand" "=r")
12987 + (ss_truncate:HI (ashiftrt:SI
12988 + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r"))
12989 + (sign_extend:SI (match_operand:HI 2 "register_operand" "r")))
12990 + (const_int 1073741824))
12991 + (const_int 15))))]
12992 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
12993 + "mulsatrndhh.h\t%0, %1:b, %2:b"
12994 + [(set_attr "length" "4")
12995 + (set_attr "cc" "none")
12996 + (set_attr "type" "mulhh")])
12998 +(define_insn "mulsathh_w"
12999 + [(set (match_operand:SI 0 "register_operand" "=r")
13000 + (ss_truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r"))
13001 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13002 + (const_int 1))))]
13003 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13004 + "mulsathh.w\t%0, %1:b, %2:b"
13005 + [(set_attr "length" "4")
13006 + (set_attr "cc" "none")
13007 + (set_attr "type" "mulhh")])
13009 +(define_insn "mulsatwh_w"
13010 + [(set (match_operand:SI 0 "register_operand" "=r")
13011 + (ss_truncate:SI (ashiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
13012 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13013 + (const_int 15))))]
13014 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13015 + "mulsatwh.w\t%0, %1, %2:b"
13016 + [(set_attr "length" "4")
13017 + (set_attr "cc" "none")
13018 + (set_attr "type" "mulwh")])
13020 +(define_insn "mulsatrndwh_w"
13021 + [(set (match_operand:SI 0 "register_operand" "=r")
13022 + (ss_truncate:SI (ashiftrt:DI (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
13023 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13024 + (const_int 1073741824))
13025 + (const_int 15))))]
13026 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13027 + "mulsatrndwh.w\t%0, %1, %2:b"
13028 + [(set_attr "length" "4")
13029 + (set_attr "cc" "none")
13030 + (set_attr "type" "mulwh")])
13032 +(define_insn "macsathh_w"
13033 + [(set (match_operand:SI 0 "register_operand" "+r")
13034 + (plus:SI (match_dup 0)
13035 + (ss_truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r"))
13036 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13037 + (const_int 1)))))]
13038 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13039 + "macsathh.w\t%0, %1:b, %2:b"
13040 + [(set_attr "length" "4")
13041 + (set_attr "cc" "none")
13042 + (set_attr "type" "mulhh")])
13045 +(define_insn "mulwh_d"
13046 + [(set (match_operand:DI 0 "register_operand" "=r")
13047 + (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
13048 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13049 + (const_int 16)))]
13050 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13051 + "mulwh.d\t%0, %1, %2:b"
13052 + [(set_attr "length" "4")
13053 + (set_attr "cc" "none")
13054 + (set_attr "type" "mulwh")])
13057 +(define_insn "mulnwh_d"
13058 + [(set (match_operand:DI 0 "register_operand" "=r")
13059 + (ashift:DI (mult:DI (not:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))
13060 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13061 + (const_int 16)))]
13062 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13063 + "mulnwh.d\t%0, %1, %2:b"
13064 + [(set_attr "length" "4")
13065 + (set_attr "cc" "none")
13066 + (set_attr "type" "mulwh")])
13068 +(define_insn "macwh_d"
13069 + [(set (match_operand:DI 0 "register_operand" "+r")
13070 + (plus:DI (match_dup 0)
13071 + (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r"))
13072 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))
13073 + (const_int 16))))]
13074 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13075 + "macwh.d\t%0, %1, %2:b"
13076 + [(set_attr "length" "4")
13077 + (set_attr "cc" "none")
13078 + (set_attr "type" "mulwh")])
13080 +(define_insn "machh_d"
13081 + [(set (match_operand:DI 0 "register_operand" "+r")
13082 + (plus:DI (match_dup 0)
13083 + (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r"))
13084 + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))))]
13085 + "!TARGET_NO_MUL_INSNS && TARGET_DSP"
13086 + "machh.d\t%0, %1:b, %2:b"
13087 + [(set_attr "length" "4")
13088 + (set_attr "cc" "none")
13089 + (set_attr "type" "mulwh")])
13091 +(define_insn "satadd_w"
13092 + [(set (match_operand:SI 0 "register_operand" "=r")
13093 + (ss_plus:SI (match_operand:SI 1 "register_operand" "r")
13094 + (match_operand:SI 2 "register_operand" "r")))]
13096 + "satadd.w\t%0, %1, %2"
13097 + [(set_attr "length" "4")
13098 + (set_attr "cc" "none")
13099 + (set_attr "type" "alu_sat")])
13101 +(define_insn "satsub_w"
13102 + [(set (match_operand:SI 0 "register_operand" "=r")
13103 + (ss_minus:SI (match_operand:SI 1 "register_operand" "r")
13104 + (match_operand:SI 2 "register_operand" "r")))]
13106 + "satsub.w\t%0, %1, %2"
13107 + [(set_attr "length" "4")
13108 + (set_attr "cc" "none")
13109 + (set_attr "type" "alu_sat")])
13111 +(define_insn "satadd_h"
13112 + [(set (match_operand:HI 0 "register_operand" "=r")
13113 + (ss_plus:HI (match_operand:HI 1 "register_operand" "r")
13114 + (match_operand:HI 2 "register_operand" "r")))]
13116 + "satadd.h\t%0, %1, %2"
13117 + [(set_attr "length" "4")
13118 + (set_attr "cc" "none")
13119 + (set_attr "type" "alu_sat")])
13121 +(define_insn "satsub_h"
13122 + [(set (match_operand:HI 0 "register_operand" "=r")
13123 + (ss_minus:HI (match_operand:HI 1 "register_operand" "r")
13124 + (match_operand:HI 2 "register_operand" "r")))]
13126 + "satsub.h\t%0, %1, %2"
13127 + [(set_attr "length" "4")
13128 + (set_attr "cc" "none")
13129 + (set_attr "type" "alu_sat")])
13132 +;;=============================================================================
13134 +;;-----------------------------------------------------------------------------
13135 +;; Set reg0 to the smallest value of reg1 and reg2. It is used for signed
13136 +;; values in the registers.
13137 +;;=============================================================================
13138 +(define_insn "sminsi3"
13139 + [(set (match_operand:SI 0 "register_operand" "=r")
13140 + (smin:SI (match_operand:SI 1 "register_operand" "r")
13141 + (match_operand:SI 2 "register_operand" "r")))]
13144 + [(set_attr "length" "4")
13145 + (set_attr "cc" "none")])
13147 +;;=============================================================================
13149 +;;-----------------------------------------------------------------------------
13150 +;; Set reg0 to the largest value of reg1 and reg2. It is used for signed
13151 +;; values in the registers.
13152 +;;=============================================================================
13153 +(define_insn "smaxsi3"
13154 + [(set (match_operand:SI 0 "register_operand" "=r")
13155 + (smax:SI (match_operand:SI 1 "register_operand" "r")
13156 + (match_operand:SI 2 "register_operand" "r")))]
13159 + [(set_attr "length" "4")
13160 + (set_attr "cc" "none")])
13164 +;;=============================================================================
13165 +;; Logical operations
13166 +;;-----------------------------------------------------------------------------
13169 +;; Split up simple DImode logical operations. Simply perform the logical
13170 +;; operation on the upper and lower halves of the registers.
13172 + [(set (match_operand:DI 0 "register_operand" "")
13173 + (match_operator:DI 6 "logical_binary_operator"
13174 + [(match_operand:DI 1 "register_operand" "")
13175 + (match_operand:DI 2 "register_operand" "")]))]
13176 + "reload_completed"
13177 + [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
13178 + (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))]
13181 + operands[3] = gen_highpart (SImode, operands[0]);
13182 + operands[0] = gen_lowpart (SImode, operands[0]);
13183 + operands[4] = gen_highpart (SImode, operands[1]);
13184 + operands[1] = gen_lowpart (SImode, operands[1]);
13185 + operands[5] = gen_highpart (SImode, operands[2]);
13186 + operands[2] = gen_lowpart (SImode, operands[2]);
13190 +;;=============================================================================
13191 +;; Logical operations with shifted operand
13192 +;;=============================================================================
13193 +(define_insn "<code>si_lshift"
13194 + [(set (match_operand:SI 0 "register_operand" "=r")
13195 + (logical:SI (match_operator:SI 4 "logical_shift_operator"
13196 + [(match_operand:SI 2 "register_operand" "r")
13197 + (match_operand:SI 3 "immediate_operand" "Ku05")])
13198 + (match_operand:SI 1 "register_operand" "r")))]
13201 + if ( GET_CODE(operands[4]) == ASHIFT )
13202 + return "<logical_insn>\t%0, %1, %2 << %3";
13204 + return "<logical_insn>\t%0, %1, %2 >> %3";
13207 + [(set_attr "cc" "set_z")]
13211 +;;************************************************
13212 +;; Peepholes for detecting logical operantions
13213 +;; with shifted operands
13214 +;;************************************************
13217 + [(set (match_operand:SI 3 "register_operand" "")
13218 + (match_operator:SI 5 "logical_shift_operator"
13219 + [(match_operand:SI 1 "register_operand" "")
13220 + (match_operand:SI 2 "immediate_operand" "")]))
13221 + (set (match_operand:SI 0 "register_operand" "")
13222 + (logical:SI (match_operand:SI 4 "register_operand" "")
13224 + "(dead_or_set_p(insn, operands[3])) || (REGNO(operands[3]) == REGNO(operands[0]))"
13226 + if ( GET_CODE(operands[5]) == ASHIFT )
13227 + return "<logical_insn>\t%0, %4, %1 << %2";
13229 + return "<logical_insn>\t%0, %4, %1 >> %2";
13231 + [(set_attr "cc" "set_z")]
13235 + [(set (match_operand:SI 3 "register_operand" "")
13236 + (match_operator:SI 5 "logical_shift_operator"
13237 + [(match_operand:SI 1 "register_operand" "")
13238 + (match_operand:SI 2 "immediate_operand" "")]))
13239 + (set (match_operand:SI 0 "register_operand" "")
13240 + (logical:SI (match_dup 3)
13241 + (match_operand:SI 4 "register_operand" "")))]
13242 + "(dead_or_set_p(insn, operands[3])) || (REGNO(operands[3]) == REGNO(operands[0]))"
13244 + if ( GET_CODE(operands[5]) == ASHIFT )
13245 + return "<logical_insn>\t%0, %4, %1 << %2";
13247 + return "<logical_insn>\t%0, %4, %1 >> %2";
13249 + [(set_attr "cc" "set_z")]
13254 + [(set (match_operand:SI 0 "register_operand" "")
13255 + (match_operator:SI 5 "logical_shift_operator"
13256 + [(match_operand:SI 1 "register_operand" "")
13257 + (match_operand:SI 2 "immediate_operand" "")]))
13258 + (set (match_operand:SI 3 "register_operand" "")
13259 + (logical:SI (match_operand:SI 4 "register_operand" "")
13261 + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[3]) == REGNO(operands[0]))"
13263 + [(set (match_dup 3)
13264 + (logical:SI (match_op_dup:SI 5 [(match_dup 1) (match_dup 2)])
13271 + [(set (match_operand:SI 0 "register_operand" "")
13272 + (match_operator:SI 5 "logical_shift_operator"
13273 + [(match_operand:SI 1 "register_operand" "")
13274 + (match_operand:SI 2 "immediate_operand" "")]))
13275 + (set (match_operand:SI 3 "register_operand" "")
13276 + (logical:SI (match_dup 0)
13277 + (match_operand:SI 4 "register_operand" "")))]
13278 + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[3]) == REGNO(operands[0]))"
13280 + [(set (match_dup 3)
13281 + (logical:SI (match_op_dup:SI 5 [(match_dup 1) (match_dup 2)])
13288 +;;=============================================================================
13290 +;;-----------------------------------------------------------------------------
13291 +;; Store the result after a bitwise logical-and between reg0 and reg2 in reg0.
13292 +;;=============================================================================
13294 +(define_insn "andnsi"
13295 + [(set (match_operand:SI 0 "register_operand" "+r")
13296 + (and:SI (match_dup 0)
13297 + (not:SI (match_operand:SI 1 "register_operand" "r"))))]
13300 + [(set_attr "cc" "set_z")
13301 + (set_attr "length" "2")]
13305 +(define_insn "andsi3"
13306 + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r,r, r, r,r,r,r,r")
13307 + (and:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,r,0,0, 0, 0,0,0,0,r" )
13308 + (match_operand:SI 2 "nonmemory_operand" " N,M,N,Ku16,Ks17,J,L,r,i,r")))]
13312 + bfextu\t%0, %1, 0, %z2
13314 + andl\t%0, %2, COH
13316 + andh\t%0, hi(%2), COH
13319 + andh\t%0, hi(%2)\;andl\t%0, lo(%2)
13322 + [(set_attr "length" "4,4,2,4,4,4,4,2,8,4")
13323 + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z")])
13325 +(define_insn "anddi3"
13326 + [(set (match_operand:DI 0 "register_operand" "=&r,&r")
13327 + (and:DI (match_operand:DI 1 "register_operand" "%0,r")
13328 + (match_operand:DI 2 "register_operand" "r,r")))]
13331 + [(set_attr "length" "8")
13332 + (set_attr "cc" "clobber")]
13335 +;;=============================================================================
13337 +;;-----------------------------------------------------------------------------
13338 +;; Store the result after a bitwise inclusive-or between reg0 and reg2 in reg0.
13339 +;;=============================================================================
13341 +(define_insn "iorsi3"
13342 + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r, r,r,r,r")
13343 + (ior:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0,0, 0,0,0,r" )
13344 + (match_operand:SI 2 "nonmemory_operand" " O,O,Ku16,J,r,i,r")))]
13352 + orh\t%0, hi(%2)\;orl\t%0, lo(%2)
13355 + [(set_attr "length" "4,2,4,4,2,8,4")
13356 + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z")])
13359 +(define_insn "iordi3"
13360 + [(set (match_operand:DI 0 "register_operand" "=&r,&r")
13361 + (ior:DI (match_operand:DI 1 "register_operand" "%0,r")
13362 + (match_operand:DI 2 "register_operand" "r,r")))]
13365 + [(set_attr "length" "8")
13366 + (set_attr "cc" "clobber")]
13369 +;;=============================================================================
13371 +;;-----------------------------------------------------------------------------
13372 +;; Store the result after a bitwise exclusive-or between reg0 and reg2 in reg0.
13373 +;;=============================================================================
13375 +(define_insn "xorsi3"
13376 + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r, r,r,r,r")
13377 + (xor:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0, 0,0,0,r" )
13378 + (match_operand:SI 2 "nonmemory_operand" " O,Ku16,J,r,i,r")))]
13385 + eorh\t%0, hi(%2)\;eorl\t%0, lo(%2)
13388 + [(set_attr "length" "4,4,4,2,8,4")
13389 + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z")])
13392 +(define_insn "xordi3"
13393 + [(set (match_operand:DI 0 "register_operand" "=&r,&r")
13394 + (xor:DI (match_operand:DI 1 "register_operand" "%0,r")
13395 + (match_operand:DI 2 "register_operand" "r,r")))]
13398 + [(set_attr "length" "8")
13399 + (set_attr "cc" "clobber")]
13402 +;;=============================================================================
13403 +;; Three operand predicable insns
13404 +;;=============================================================================
13406 +(define_insn "<predicable_insn3><mode>_predicable"
13407 + [(set (match_operand:INTM 0 "register_operand" "=r")
13408 + (predicable_op3:INTM (match_operand:INTM 1 "register_operand" "<predicable_commutative3>r")
13409 + (match_operand:INTM 2 "register_operand" "r")))]
13410 + "TARGET_V2_INSNS"
13411 + "<predicable_insn3>%?\t%0, %1, %2"
13412 + [(set_attr "length" "4")
13413 + (set_attr "cc" "cmp_cond_insn")
13414 + (set_attr "predicable" "yes")]
13417 +(define_insn_and_split "<predicable_insn3><mode>_imm_clobber_predicable"
13419 + [(set (match_operand:INTM 0 "register_operand" "=r")
13420 + (predicable_op3:INTM (match_operand:INTM 1 "register_operand" "<predicable_commutative3>r")
13421 + (match_operand:INTM 2 "avr32_mov_immediate_operand" "JKs21")))
13422 + (clobber (match_operand:INTM 3 "register_operand" "=&r"))])]
13423 + "TARGET_V2_INSNS"
13425 + if ( current_insn_predicate != NULL_RTX )
13427 + if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks08") )
13428 + return "%! mov%?\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
13429 + else if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21") )
13430 + return "%! mov\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
13432 + return "%! movh\t%3, hi(%2)\;<predicable_insn3>%?\t%0, %1, %3";
13436 + if ( !avr32_cond_imm_clobber_splittable (insn, operands) )
13438 + if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks08") )
13439 + return "mov%?\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
13440 + else if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21") )
13441 + return "mov\t%3, %2\;<predicable_insn3>%?\t%0, %1, %3";
13443 + return "movh\t%3, hi(%2)\;<predicable_insn3>%?\t%0, %1, %3";
13449 + ;; If we find out that we could not actually do if-conversion on the block
13450 + ;; containing this insn we convert it back to normal immediate format
13451 + ;; to avoid outputing a redundant move insn
13452 + ;; Do not split until after we have checked if we can make the insn
13454 + "(GET_CODE (PATTERN (insn)) != COND_EXEC
13455 + && cfun->machine->ifcvt_after_reload
13456 + && avr32_cond_imm_clobber_splittable (insn, operands))"
13457 + [(set (match_dup 0)
13458 + (predicable_op3:INTM (match_dup 1)
13461 + [(set_attr "length" "8")
13462 + (set_attr "cc" "cmp_cond_insn")
13463 + (set_attr "predicable" "yes")]
13467 +;;=============================================================================
13468 +;; Zero extend predicable insns
13469 +;;=============================================================================
13470 +(define_insn_and_split "zero_extendhisi_clobber_predicable"
13472 + [(set (match_operand:SI 0 "register_operand" "=r")
13473 + (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
13474 + (clobber (match_operand:SI 2 "register_operand" "=&r"))])]
13475 + "TARGET_V2_INSNS"
13477 + if ( current_insn_predicate != NULL_RTX )
13479 + return "%! mov\t%2, 0xffff\;and%?\t%0, %1, %2";
13487 + ;; If we find out that we could not actually do if-conversion on the block
13488 + ;; containing this insn we convert it back to normal immediate format
13489 + ;; to avoid outputing a redundant move insn
13490 + ;; Do not split until after we have checked if we can make the insn
13492 + "(GET_CODE (PATTERN (insn)) != COND_EXEC
13493 + && cfun->machine->ifcvt_after_reload)"
13494 + [(set (match_dup 0)
13495 + (zero_extend:SI (match_dup 1)))]
13497 + [(set_attr "length" "8")
13498 + (set_attr "cc" "cmp_cond_insn")
13499 + (set_attr "predicable" "yes")]
13502 +(define_insn_and_split "zero_extendqisi_clobber_predicable"
13504 + [(set (match_operand:SI 0 "register_operand" "=r")
13505 + (zero_extend:SI (match_operand:QI 1 "register_operand" "r")))
13506 + (clobber (match_operand:SI 2 "register_operand" "=&r"))])]
13507 + "TARGET_V2_INSNS"
13509 + if ( current_insn_predicate != NULL_RTX )
13511 + return "%! mov\t%2, 0xff\;and%?\t%0, %1, %2";
13519 + ;; If we find out that we could not actually do if-conversion on the block
13520 + ;; containing this insn we convert it back to normal immediate format
13521 + ;; to avoid outputing a redundant move insn
13522 + ;; Do not split until after we have checked if we can make the insn
13524 + "(GET_CODE (PATTERN (insn)) != COND_EXEC
13525 + && cfun->machine->ifcvt_after_reload)"
13526 + [(set (match_dup 0)
13527 + (zero_extend:SI (match_dup 1)))]
13529 + [(set_attr "length" "8")
13530 + (set_attr "cc" "cmp_cond_insn")
13531 + (set_attr "predicable" "yes")]
13534 +(define_insn_and_split "zero_extendqihi_clobber_predicable"
13536 + [(set (match_operand:HI 0 "register_operand" "=r")
13537 + (zero_extend:HI (match_operand:QI 1 "register_operand" "r")))
13538 + (clobber (match_operand:SI 2 "register_operand" "=&r"))])]
13539 + "TARGET_V2_INSNS"
13541 + if ( current_insn_predicate != NULL_RTX )
13543 + return "%! mov\t%2, 0xff\;and%?\t%0, %1, %2";
13551 + ;; If we find out that we could not actually do if-conversion on the block
13552 + ;; containing this insn we convert it back to normal immediate format
13553 + ;; to avoid outputing a redundant move insn
13554 + ;; Do not split until after we have checked if we can make the insn
13556 + "(GET_CODE (PATTERN (insn)) != COND_EXEC
13557 + && cfun->machine->ifcvt_after_reload)"
13558 + [(set (match_dup 0)
13559 + (zero_extend:HI (match_dup 1)))]
13561 + [(set_attr "length" "8")
13562 + (set_attr "cc" "cmp_cond_insn")
13563 + (set_attr "predicable" "yes")]
13565 +;;=============================================================================
13567 +;;-----------------------------------------------------------------------------
13568 +;; Signed division that produces both a quotient and a remainder.
13569 +;;=============================================================================
13570 +(define_expand "divmodsi4"
13573 + (set (match_operand:SI 0 "register_operand" "=r")
13574 + (div:SI (match_operand:SI 1 "register_operand" "r")
13575 + (match_operand:SI 2 "register_operand" "r")))
13576 + (set (match_operand:SI 3 "register_operand" "=r")
13577 + (mod:SI (match_dup 1)
13578 + (match_dup 2)))])
13579 + (use (match_dup 4))])]
13582 + if (! no_new_pseudos) {
13583 + operands[4] = gen_reg_rtx (DImode);
13585 + emit_insn(gen_divmodsi4_internal(operands[4],operands[1],operands[2]));
13586 + emit_move_insn(operands[0], gen_rtx_SUBREG( SImode, operands[4], 4));
13587 + emit_move_insn(operands[3], gen_rtx_SUBREG( SImode, operands[4], 0));
13597 +(define_insn "divmodsi4_internal"
13598 + [(set (match_operand:DI 0 "register_operand" "=r")
13599 + (unspec:DI [(match_operand:SI 1 "register_operand" "r")
13600 + (match_operand:SI 2 "register_operand" "r")]
13601 + UNSPEC_DIVMODSI4_INTERNAL))]
13603 + "divs %0, %1, %2"
13604 + [(set_attr "type" "div")
13605 + (set_attr "cc" "none")])
13608 +;;=============================================================================
13610 +;;-----------------------------------------------------------------------------
13611 +;; Unsigned division that produces both a quotient and a remainder.
13612 +;;=============================================================================
13613 +(define_expand "udivmodsi4"
13616 + (set (match_operand:SI 0 "register_operand" "=r")
13617 + (udiv:SI (match_operand:SI 1 "register_operand" "r")
13618 + (match_operand:SI 2 "register_operand" "r")))
13619 + (set (match_operand:SI 3 "register_operand" "=r")
13620 + (umod:SI (match_dup 1)
13621 + (match_dup 2)))])
13622 + (use (match_dup 4))])]
13625 + if (! no_new_pseudos) {
13626 + operands[4] = gen_reg_rtx (DImode);
13628 + emit_insn(gen_udivmodsi4_internal(operands[4],operands[1],operands[2]));
13629 + emit_move_insn(operands[0], gen_rtx_SUBREG( SImode, operands[4], 4));
13630 + emit_move_insn(operands[3], gen_rtx_SUBREG( SImode, operands[4], 0));
13638 +(define_insn "udivmodsi4_internal"
13639 + [(set (match_operand:DI 0 "register_operand" "=r")
13640 + (unspec:DI [(match_operand:SI 1 "register_operand" "r")
13641 + (match_operand:SI 2 "register_operand" "r")]
13642 + UNSPEC_UDIVMODSI4_INTERNAL))]
13644 + "divu %0, %1, %2"
13645 + [(set_attr "type" "div")
13646 + (set_attr "cc" "none")])
13649 +;;=============================================================================
13650 +;; Arithmetic-shift left
13651 +;;-----------------------------------------------------------------------------
13652 +;; Arithmetic-shift reg0 left by reg2 or immediate value.
13653 +;;=============================================================================
13655 +(define_insn "ashlsi3"
13656 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
13657 + (ashift:SI (match_operand:SI 1 "register_operand" "r,0,r")
13658 + (match_operand:SI 2 "nonmemory_operand" "r,Ku05,Ku05")))]
13664 + [(set_attr "length" "4,2,4")
13665 + (set_attr "cc" "set_ncz")])
13667 +;;=============================================================================
13668 +;; Arithmetic-shift right
13669 +;;-----------------------------------------------------------------------------
13670 +;; Arithmetic-shift reg0 right by an immediate value.
13671 +;;=============================================================================
13673 +(define_insn "ashrsi3"
13674 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
13675 + (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,0,r")
13676 + (match_operand:SI 2 "nonmemory_operand" "r,Ku05,Ku05")))]
13682 + [(set_attr "length" "4,2,4")
13683 + (set_attr "cc" "set_ncz")])
13685 +;;=============================================================================
13686 +;; Logical shift right
13687 +;;-----------------------------------------------------------------------------
13688 +;; Logical shift reg0 right by an immediate value.
13689 +;;=============================================================================
13691 +(define_insn "lshrsi3"
13692 + [(set (match_operand:SI 0 "register_operand" "=r,r,r")
13693 + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0,r")
13694 + (match_operand:SI 2 "nonmemory_operand" "r,Ku05,Ku05")))]
13700 + [(set_attr "length" "4,2,4")
13701 + (set_attr "cc" "set_ncz")])
13704 +;;=============================================================================
13706 +;;-----------------------------------------------------------------------------
13707 +;; Negate operand 1 and store the result in operand 0.
13708 +;;=============================================================================
13709 +(define_insn "negsi2"
13710 + [(set (match_operand:SI 0 "register_operand" "=r,r")
13711 + (neg:SI (match_operand:SI 1 "register_operand" "0,r")))]
13716 + [(set_attr "length" "2,4")
13717 + (set_attr "cc" "set_vncz")])
13719 +(define_insn "negsi2_predicable"
13720 + [(set (match_operand:SI 0 "register_operand" "+r")
13721 + (neg:SI (match_dup 0)))]
13722 + "TARGET_V2_INSNS"
13724 + [(set_attr "length" "4")
13725 + (set_attr "cc" "cmp_cond_insn")
13726 + (set_attr "predicable" "yes")])
13728 +;;=============================================================================
13730 +;;-----------------------------------------------------------------------------
13731 +;; Store the absolute value of operand 1 into operand 0.
13732 +;;=============================================================================
13733 +(define_insn "abssi2"
13734 + [(set (match_operand:SI 0 "register_operand" "=r")
13735 + (abs:SI (match_operand:SI 1 "register_operand" "0")))]
13738 + [(set_attr "length" "2")
13739 + (set_attr "cc" "set_z")])
13742 +;;=============================================================================
13744 +;;-----------------------------------------------------------------------------
13745 +;; Store the bitwise-complement of operand 1 into operand 0.
13746 +;;=============================================================================
13748 +(define_insn "one_cmplsi2"
13749 + [(set (match_operand:SI 0 "register_operand" "=r,r")
13750 + (not:SI (match_operand:SI 1 "register_operand" "0,r")))]
13754 + rsub\t%0, %1, -1"
13755 + [(set_attr "length" "2,4")
13756 + (set_attr "cc" "set_z")])
13759 +(define_insn "one_cmplsi2_predicable"
13760 + [(set (match_operand:SI 0 "register_operand" "+r")
13761 + (not:SI (match_dup 0)))]
13762 + "TARGET_V2_INSNS"
13764 + [(set_attr "length" "4")
13765 + (set_attr "cc" "cmp_cond_insn")
13766 + (set_attr "predicable" "yes")])
13769 +;;=============================================================================
13771 +;;-----------------------------------------------------------------------------
13772 +;; Load a bit into Z and C flags
13773 +;;=============================================================================
13774 +(define_insn "bldsi"
13776 + (and:SI (match_operand:SI 0 "register_operand" "r")
13777 + (match_operand:SI 1 "one_bit_set_operand" "i")))]
13780 + [(set_attr "length" "4")
13781 + (set_attr "cc" "bld")]
13785 +;;=============================================================================
13787 +;;-----------------------------------------------------------------------------
13788 +;; Compare reg0 with reg1 or an immediate value.
13789 +;;=============================================================================
13791 +(define_expand "cmp<mode>"
13794 + (match_operand:CMP 0 "register_operand" "")
13795 + (match_operand:CMP 1 "<CMP:cmp_predicate>" "")))]
13798 + avr32_compare_op0 = operands[0];
13799 + avr32_compare_op1 = operands[1];
13803 +(define_insn "cmp<mode>_internal"
13806 + (match_operand:CMP 0 "register_operand" "r")
13807 + (match_operand:CMP 1 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")))]
13810 + set_next_insn_cond(insn,
13811 + avr32_output_cmp(get_next_insn_cond(insn), GET_MODE (operands[0]), operands[0], operands[1]));
13814 + [(set_attr "length" "4")
13815 + (set_attr "cc" "compare")])
13818 +;;;=============================================================================
13820 +;;-----------------------------------------------------------------------------
13821 +;; Compare reg against zero and set the condition codes.
13822 +;;=============================================================================
13825 +(define_expand "tstsi"
13827 + (match_operand:SI 0 "register_operand" ""))]
13830 + avr32_compare_op0 = operands[0];
13831 + avr32_compare_op1 = const0_rtx;
13835 +(define_insn "tstsi_internal"
13837 + (match_operand:SI 0 "register_operand" "r"))]
13840 + set_next_insn_cond(insn,
13841 + avr32_output_cmp(get_next_insn_cond(insn), SImode, operands[0], const0_rtx));
13845 + [(set_attr "length" "2")
13846 + (set_attr "cc" "compare")])
13849 +(define_expand "tstdi"
13851 + (match_operand:DI 0 "register_operand" ""))]
13854 + avr32_compare_op0 = operands[0];
13855 + avr32_compare_op1 = const0_rtx;
13859 +(define_insn "tstdi_internal"
13861 + (match_operand:DI 0 "register_operand" "r"))]
13864 + set_next_insn_cond(insn,
13865 + avr32_output_cmp(get_next_insn_cond(insn), DImode, operands[0], const0_rtx));
13868 + [(set_attr "length" "4")
13869 + (set_attr "type" "alu2")
13870 + (set_attr "cc" "compare")])
13874 +;;=============================================================================
13875 +;; Convert operands
13876 +;;-----------------------------------------------------------------------------
13878 +;;=============================================================================
13879 +(define_insn "truncdisi2"
13880 + [(set (match_operand:SI 0 "general_operand" "")
13881 + (truncate:SI (match_operand:DI 1 "general_operand" "")))]
13885 +;;=============================================================================
13887 +;;-----------------------------------------------------------------------------
13889 +;;=============================================================================
13892 +(define_insn "extendhisi2"
13893 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
13894 + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
13897 + switch ( which_alternative ){
13899 + return "casts.h\t%0";
13901 + return "bfexts\t%0, %1, 0, 16";
13904 + return "ld.sh\t%0, %1";
13909 + [(set_attr "length" "2,4,2,4")
13910 + (set_attr "cc" "set_ncz,set_ncz,none,none")
13911 + (set_attr "type" "alu,alu,load_rm,load_rm")])
13913 +(define_insn "extendqisi2"
13914 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
13915 + (sign_extend:SI (match_operand:QI 1 "extendqi_operand" "0,r,RKu00,m")))]
13918 + switch ( which_alternative ){
13920 + return "casts.b\t%0";
13922 + return "bfexts\t%0, %1, 0, 8";
13925 + return "ld.sb\t%0, %1";
13930 + [(set_attr "length" "2,4,2,4")
13931 + (set_attr "cc" "set_ncz,set_ncz,none,none")
13932 + (set_attr "type" "alu,alu,load_rm,load_rm")])
13934 +(define_insn "extendqihi2"
13935 + [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
13936 + (sign_extend:HI (match_operand:QI 1 "extendqi_operand" "0,r,RKu00,m")))]
13939 + switch ( which_alternative ){
13941 + return "casts.b\t%0";
13943 + return "bfexts\t%0, %1, 0, 8";
13946 + return "ld.sb\t%0, %1";
13951 + [(set_attr "length" "2,4,2,4")
13952 + (set_attr "cc" "set_ncz,set_ncz,none,none")
13953 + (set_attr "type" "alu,alu,load_rm,load_rm")])
13956 +;;=============================================================================
13958 +;;-----------------------------------------------------------------------------
13960 +;;=============================================================================
13962 +(define_insn "zero_extendhisi2"
13963 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
13964 + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
13967 + switch ( which_alternative ){
13969 + return "castu.h\t%0";
13971 + return "bfextu\t%0, %1, 0, 16";
13974 + return "ld.uh\t%0, %1";
13980 + [(set_attr "length" "2,4,2,4")
13981 + (set_attr "cc" "set_ncz,set_ncz,none,none")
13982 + (set_attr "type" "alu,alu,load_rm,load_rm")])
13984 +(define_insn "zero_extendqisi2"
13985 + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
13986 + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
13989 + switch ( which_alternative ){
13991 + return "castu.b\t%0";
13993 + return "bfextu\t%0, %1, 0, 8";
13996 + return "ld.ub\t%0, %1";
14001 + [(set_attr "length" "2,4,2,4")
14002 + (set_attr "cc" "set_ncz, set_ncz, none, none")
14003 + (set_attr "type" "alu, alu, load_rm, load_rm")])
14005 +(define_insn "zero_extendqihi2"
14006 + [(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
14007 + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,r,<RKu00>,m")))]
14010 + switch ( which_alternative ){
14012 + return "castu.b\t%0";
14014 + return "bfextu\t%0, %1, 0, 8";
14017 + return "ld.ub\t%0, %1";
14022 + [(set_attr "length" "2,4,2,4")
14023 + (set_attr "cc" "set_ncz, set_ncz, none, none")
14024 + (set_attr "type" "alu, alu, load_rm, load_rm")])
14027 +;;=============================================================================
14028 +;; Conditional load and extend insns
14029 +;;=============================================================================
14030 +(define_insn "ldsi<mode>_predicable_se"
14031 + [(set (match_operand:SI 0 "register_operand" "=r")
14033 + (match_operand:INTM 1 "memory_operand" "<INTM:pred_mem_constraint>")))]
14034 + "TARGET_V2_INSNS"
14035 + "ld<INTM:load_postfix_s>%?\t%0, %1"
14036 + [(set_attr "length" "4")
14037 + (set_attr "cc" "cmp_cond_insn")
14038 + (set_attr "type" "load")
14039 + (set_attr "predicable" "yes")]
14042 +(define_insn "ldsi<mode>_predicable_ze"
14043 + [(set (match_operand:SI 0 "register_operand" "=r")
14045 + (match_operand:INTM 1 "memory_operand" "<INTM:pred_mem_constraint>")))]
14046 + "TARGET_V2_INSNS"
14047 + "ld<INTM:load_postfix_u>%?\t%0, %1"
14048 + [(set_attr "length" "4")
14049 + (set_attr "cc" "cmp_cond_insn")
14050 + (set_attr "type" "load")
14051 + (set_attr "predicable" "yes")]
14054 +(define_insn "ldhi_predicable_ze"
14055 + [(set (match_operand:HI 0 "register_operand" "=r")
14057 + (match_operand:QI 1 "memory_operand" "RKs10")))]
14058 + "TARGET_V2_INSNS"
14059 + "ld.ub%?\t%0, %1"
14060 + [(set_attr "length" "4")
14061 + (set_attr "cc" "cmp_cond_insn")
14062 + (set_attr "type" "load")
14063 + (set_attr "predicable" "yes")]
14066 +(define_insn "ldhi_predicable_se"
14067 + [(set (match_operand:HI 0 "register_operand" "=r")
14069 + (match_operand:QI 1 "memory_operand" "RKs10")))]
14070 + "TARGET_V2_INSNS"
14071 + "ld.sb%?\t%0, %1"
14072 + [(set_attr "length" "4")
14073 + (set_attr "cc" "cmp_cond_insn")
14074 + (set_attr "type" "load")
14075 + (set_attr "predicable" "yes")]
14078 +;;=============================================================================
14079 +;; Conditional set register
14081 +;;-----------------------------------------------------------------------------
14083 +;;Because of the same issue as with conditional moves and adds we must
14084 +;;not separate the compare instrcution from the scc instruction as
14085 +;;they might be sheduled "badly".
14087 +(define_insn "s<code>"
14088 + [(set (match_operand:SI 0 "register_operand" "=r")
14089 + (any_cond:SI (cc0)
14093 + [(set_attr "length" "2")
14094 + (set_attr "cc" "none")])
14096 +(define_insn "smi"
14097 + [(set (match_operand:SI 0 "register_operand" "=r")
14098 + (unspec:SI [(cc0)
14099 + (const_int 0)] UNSPEC_COND_MI))]
14102 + [(set_attr "length" "2")
14103 + (set_attr "cc" "none")])
14105 +(define_insn "spl"
14106 + [(set (match_operand:SI 0 "register_operand" "=r")
14107 + (unspec:SI [(cc0)
14108 + (const_int 0)] UNSPEC_COND_PL))]
14111 + [(set_attr "length" "2")
14112 + (set_attr "cc" "none")])
14115 +;;=============================================================================
14116 +;; Conditional branch
14117 +;;-----------------------------------------------------------------------------
14118 +;; Branch to label if the specified condition codes are set.
14119 +;;=============================================================================
14120 +; branch if negative
14121 +(define_insn "bmi"
14123 + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_MI)
14124 + (label_ref (match_operand 0 "" ""))
14128 + [(set_attr "type" "branch")
14129 + (set (attr "length")
14130 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
14131 + (le (minus (pc) (match_dup 0)) (const_int 256)))
14132 + (const_int 2)] ; use compact branch
14133 + (const_int 4))) ; use extended branch
14134 + (set_attr "cc" "none")])
14136 +(define_insn "*bmi-reverse"
14138 + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_MI)
14140 + (label_ref (match_operand 0 "" ""))))]
14143 + [(set_attr "type" "branch")
14144 + (set (attr "length")
14145 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
14146 + (le (minus (pc) (match_dup 0)) (const_int 256)))
14147 + (const_int 2)] ; use compact branch
14148 + (const_int 4))) ; use extended branch
14149 + (set_attr "cc" "none")])
14151 +; branch if positive
14152 +(define_insn "bpl"
14154 + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_PL)
14155 + (label_ref (match_operand 0 "" ""))
14159 + [(set_attr "type" "branch")
14160 + (set (attr "length")
14161 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
14162 + (le (minus (pc) (match_dup 0)) (const_int 256)))
14163 + (const_int 2)] ; use compact branch
14164 + (const_int 4))) ; use extended branch
14165 + (set_attr "cc" "none")])
14167 +(define_insn "*bpl-reverse"
14169 + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_PL)
14171 + (label_ref (match_operand 0 "" ""))))]
14174 + [(set_attr "type" "branch")
14175 + (set (attr "length")
14176 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
14177 + (le (minus (pc) (match_dup 0)) (const_int 256)))
14178 + (const_int 2)] ; use compact branch
14179 + (const_int 4))) ; use extended branch
14180 + (set_attr "cc" "none")])
14183 +(define_insn "b<code>"
14185 + (if_then_else (any_cond:CC (cc0)
14187 + (label_ref (match_operand 0 "" ""))
14191 + [(set_attr "type" "branch")
14192 + (set (attr "length")
14193 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
14194 + (le (minus (pc) (match_dup 0)) (const_int 256)))
14195 + (const_int 2)] ; use compact branch
14196 + (const_int 4))) ; use extended branch
14197 + (set_attr "cc" "none")])
14200 +(define_insn "*b<code>-reverse"
14202 + (if_then_else (any_cond:CC (cc0)
14205 + (label_ref (match_operand 0 "" ""))))]
14207 + "br<invcond> %0 "
14208 + [(set_attr "type" "branch")
14209 + (set (attr "length")
14210 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254))
14211 + (le (minus (pc) (match_dup 0)) (const_int 256)))
14212 + (const_int 2)] ; use compact branch
14213 + (const_int 4))) ; use extended branch
14214 + (set_attr "cc" "none")])
14218 +;=============================================================================
14219 +; Conditional Add/Subtract
14220 +;-----------------------------------------------------------------------------
14221 +; sub{cond4} Rd, imm
14222 +;=============================================================================
14225 +(define_expand "add<mode>cc"
14226 + [(set (match_operand:ADDCC 0 "register_operand" "")
14227 + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator"
14230 + (match_operand:ADDCC 2 "register_operand" "")
14233 + (match_operand:ADDCC 3 "" ""))))]
14236 + if ( !(GET_CODE (operands[3]) == CONST_INT
14237 + || (TARGET_V2_INSNS && REG_P(operands[3]))) ){
14241 + /* Delete compare instruction as it is merged into this instruction */
14242 + remove_insn (get_last_insn_anywhere ());
14244 + operands[4] = avr32_compare_op0;
14245 + operands[5] = avr32_compare_op1;
14247 + if ( TARGET_V2_INSNS
14248 + && REG_P(operands[3])
14249 + && REGNO(operands[0]) != REGNO(operands[2]) ){
14250 + emit_move_insn (operands[0], operands[2]);
14251 + operands[2] = operands[0];
14256 +(define_insn "add<ADDCC:mode>cc_cmp<CMP:mode>_reg"
14257 + [(set (match_operand:ADDCC 0 "register_operand" "=r")
14258 + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator"
14259 + [(match_operand:CMP 4 "register_operand" "r")
14260 + (match_operand:CMP 5 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")])
14263 + (match_operand:ADDCC 2 "register_operand" "r")
14264 + (match_operand:ADDCC 3 "register_operand" "r"))))]
14265 + "TARGET_V2_INSNS"
14267 + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
14268 + return "add%i1\t%0, %2, %3";
14270 + [(set_attr "length" "8")
14271 + (set_attr "cc" "cmp_cond_insn")])
14273 +(define_insn "add<ADDCC:mode>cc_cmp<CMP:mode>"
14274 + [(set (match_operand:ADDCC 0 "register_operand" "=r")
14275 + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator"
14276 + [(match_operand:CMP 4 "register_operand" "r")
14277 + (match_operand:CMP 5 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>")])
14278 + (match_operand:ADDCC 2 "register_operand" "0")
14281 + (match_operand:ADDCC 3 "avr32_cond_immediate_operand" "Is08"))))]
14284 + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
14285 + return "sub%i1\t%0, -%3";
14287 + [(set_attr "length" "8")
14288 + (set_attr "cc" "cmp_cond_insn")])
14290 +;=============================================================================
14291 +; Conditional Move
14292 +;-----------------------------------------------------------------------------
14293 +; mov{cond4} Rd, (Rs/imm)
14294 +;=============================================================================
14295 +(define_expand "mov<mode>cc"
14296 + [(set (match_operand:MOVCC 0 "register_operand" "")
14297 + (if_then_else:MOVCC (match_operator 1 "avr32_comparison_operator"
14300 + (match_operand:MOVCC 2 "avr32_cond_register_immediate_operand" "")
14301 + (match_operand:MOVCC 3 "avr32_cond_register_immediate_operand" "")))]
14304 + /* Delete compare instruction as it is merged into this instruction */
14305 + remove_insn (get_last_insn_anywhere ());
14307 + operands[4] = avr32_compare_op0;
14308 + operands[5] = avr32_compare_op1;
14313 +(define_insn "mov<MOVCC:mode>cc_cmp<CMP:mode>"
14314 + [(set (match_operand:MOVCC 0 "register_operand" "=r,r,r")
14315 + (if_then_else:MOVCC (match_operator 1 "avr32_comparison_operator"
14316 + [(match_operand:CMP 4 "register_operand" "r,r,r")
14317 + (match_operand:CMP 5 "<CMP:cmp_predicate>" "<CMP:cmp_constraint>,<CMP:cmp_constraint>,<CMP:cmp_constraint>")])
14318 + (match_operand:MOVCC 2 "avr32_cond_register_immediate_operand" "0, rKs08,rKs08")
14319 + (match_operand:MOVCC 3 "avr32_cond_register_immediate_operand" "rKs08,0,rKs08")))]
14322 + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
14324 + switch( which_alternative ){
14326 + return "mov%i1 %0, %3";
14328 + return "mov%1 %0, %2";
14330 + return "mov%1 %0, %2\;mov%i1 %0, %3";
14336 + [(set_attr "length" "8,8,12")
14337 + (set_attr "cc" "cmp_cond_insn")])
14342 +;;=============================================================================
14344 +;;-----------------------------------------------------------------------------
14345 +;; Jump inside a function; an unconditional branch to a label.
14346 +;;=============================================================================
14347 +(define_insn "jump"
14349 + (label_ref (match_operand 0 "" "")))]
14352 + if (get_attr_length(insn) > 4)
14353 + return "Can't jump this far";
14354 + return (get_attr_length(insn) == 2 ?
14355 + "rjmp %0" : "bral %0");
14357 + [(set_attr "type" "branch")
14358 + (set (attr "length")
14359 + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 1022))
14360 + (le (minus (pc) (match_dup 0)) (const_int 1024)))
14361 + (const_int 2) ; use rjmp
14362 + (le (match_dup 0) (const_int 1048575))
14363 + (const_int 4)] ; use bral
14364 + (const_int 8))) ; do something else
14365 + (set_attr "cc" "none")])
14367 +;;=============================================================================
14369 +;;-----------------------------------------------------------------------------
14370 +;; Subroutine call instruction returning no value.
14371 +;;=============================================================================
14372 +(define_insn "call_internal"
14373 + [(parallel [(call (mem:SI (match_operand:SI 0 "avr32_call_operand" "r,U,T,W"))
14374 + (match_operand 1 "" ""))
14375 + (clobber (reg:SI LR_REGNUM))])]
14378 + switch (which_alternative){
14380 + return "icall\t%0";
14382 + return "rcall\t%0";
14384 + return "mcall\t%0";
14386 + if ( TARGET_HAS_ASM_ADDR_PSEUDOS )
14387 + return "call\t%0";
14389 + return "mcall\tr6[%0@got]";
14394 + [(set_attr "type" "call")
14395 + (set_attr "length" "2,4,4,10")
14396 + (set_attr "cc" "clobber")])
14399 +(define_expand "call"
14400 + [(parallel [(call (match_operand:SI 0 "" "")
14401 + (match_operand 1 "" ""))
14402 + (clobber (reg:SI LR_REGNUM))])]
14405 + rtx call_address;
14406 + if ( GET_CODE(operands[0]) != MEM )
14409 + call_address = XEXP(operands[0], 0);
14411 + /* If assembler supports call pseudo insn and the call
14412 + address is a symbol then nothing special needs to be done. */
14413 + if ( TARGET_HAS_ASM_ADDR_PSEUDOS
14414 + && (GET_CODE(call_address) == SYMBOL_REF) ){
14415 + /* We must however mark the function as using the GOT if
14416 + flag_pic is set, since the call insn might turn into
14417 + a mcall using the GOT ptr register. */
14419 + current_function_uses_pic_offset_table = 1;
14420 + emit_call_insn(gen_call_internal(call_address, operands[1]));
14425 + GET_CODE(call_address) == SYMBOL_REF ){
14426 + current_function_uses_pic_offset_table = 1;
14427 + emit_call_insn(gen_call_internal(call_address, operands[1]));
14431 + if ( !SYMBOL_REF_RCALL_FUNCTION_P(operands[0]) ){
14432 + if ( optimize_size &&
14433 + GET_CODE(call_address) == SYMBOL_REF ){
14434 + call_address = force_const_mem(SImode, call_address);
14436 + call_address = force_reg(SImode, call_address);
14440 + emit_call_insn(gen_call_internal(call_address, operands[1]));
14445 +;;=============================================================================
14447 +;;-----------------------------------------------------------------------------
14448 +;; Subrutine call instruction returning a value.
14449 +;;=============================================================================
14450 +(define_expand "call_value"
14451 + [(parallel [(set (match_operand:SI 0 "" "")
14452 + (call (match_operand:SI 1 "" "")
14453 + (match_operand 2 "" "")))
14454 + (clobber (reg:SI LR_REGNUM))])]
14457 + rtx call_address;
14458 + if ( GET_CODE(operands[1]) != MEM )
14461 + call_address = XEXP(operands[1], 0);
14463 + /* If assembler supports call pseudo insn and the call
14464 + address is a symbol then nothing special needs to be done. */
14465 + if ( TARGET_HAS_ASM_ADDR_PSEUDOS
14466 + && (GET_CODE(call_address) == SYMBOL_REF) ){
14467 + /* We must however mark the function as using the GOT if
14468 + flag_pic is set, since the call insn might turn into
14469 + a mcall using the GOT ptr register. */
14470 + if ( flag_pic ) {
14471 + current_function_uses_pic_offset_table = 1;
14472 + emit_call_insn(gen_call_value_internal(operands[0], call_address, operands[2]));
14477 + GET_CODE(call_address) == SYMBOL_REF ){
14478 + current_function_uses_pic_offset_table = 1;
14479 + emit_call_insn(gen_call_value_internal(operands[0], call_address, operands[2]));
14483 + if ( !SYMBOL_REF_RCALL_FUNCTION_P(operands[1]) ){
14484 + if ( optimize_size &&
14485 + GET_CODE(call_address) == SYMBOL_REF){
14486 + call_address = force_const_mem(SImode, call_address);
14488 + call_address = force_reg(SImode, call_address);
14492 + emit_call_insn(gen_call_value_internal(operands[0], call_address,
14498 +(define_insn "call_value_internal"
14499 + [(parallel [(set (match_operand 0 "register_operand" "=r,r,r,r")
14500 + (call (mem:SI (match_operand:SI 1 "avr32_call_operand" "r,U,T,W"))
14501 + (match_operand 2 "" "")))
14502 + (clobber (reg:SI LR_REGNUM))])]
14503 + ;; Operand 2 not used on the AVR32.
14506 + switch (which_alternative){
14508 + return "icall\t%1";
14510 + return "rcall\t%1";
14512 + return "mcall\t%1";
14514 + if ( TARGET_HAS_ASM_ADDR_PSEUDOS )
14515 + return "call\t%1";
14517 + return "mcall\tr6[%1@got]";
14522 + [(set_attr "type" "call")
14523 + (set_attr "length" "2,4,4,10")
14524 + (set_attr "cc" "call_set")])
14527 +;;=============================================================================
14529 +;;-----------------------------------------------------------------------------
14530 +;; Subrutine call instruction returning a value of any type.
14531 +;; The code is copied from m68k.md (except gen_blockage is removed)
14533 +;;=============================================================================
14534 +(define_expand "untyped_call"
14535 + [(parallel [(call (match_operand 0 "avr32_call_operand" "")
14537 + (match_operand 1 "" "")
14538 + (match_operand 2 "" "")])]
14543 + emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
14545 + for (i = 0; i < XVECLEN (operands[2], 0); i++) {
14546 + rtx set = XVECEXP (operands[2], 0, i);
14547 + emit_move_insn (SET_DEST (set), SET_SRC (set));
14550 + /* The optimizer does not know that the call sets the function value
14551 + registers we stored in the result block. We avoid problems by
14552 + claiming that all hard registers are used and clobbered at this
14554 + emit_insn (gen_blockage ());
14560 +;;=============================================================================
14562 +;;=============================================================================
14564 +(define_insn "return"
14566 + "USE_RETURN_INSN (FALSE)"
14568 + avr32_output_return_instruction(TRUE, FALSE, NULL, NULL);
14571 + [(set_attr "length" "4")
14572 + (set_attr "type" "call")]
14576 +(define_insn "return_cond"
14578 + (if_then_else (match_operand 0 "avr32_comparison_operand" "")
14581 + "USE_RETURN_INSN (TRUE)"
14583 + [(set_attr "type" "call")])
14585 +(define_insn "return_cond_predicable"
14587 + "USE_RETURN_INSN (TRUE)"
14589 + [(set_attr "type" "call")
14590 + (set_attr "predicable" "yes")])
14593 +(define_insn "return_imm"
14594 + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
14595 + (use (reg RETVAL_REGNUM))
14597 + "USE_RETURN_INSN (FALSE) &&
14598 + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
14600 + avr32_output_return_instruction(TRUE, FALSE, NULL, operands[0]);
14603 + [(set_attr "length" "4")
14604 + (set_attr "type" "call")]
14607 +(define_insn "return_imm_cond"
14608 + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
14609 + (use (reg RETVAL_REGNUM))
14611 + (if_then_else (match_operand 1 "avr32_comparison_operand" "")
14614 + "USE_RETURN_INSN (TRUE) &&
14615 + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
14617 + [(set_attr "type" "call")]
14620 +(define_insn "return_imm_predicable"
14621 + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
14622 + (use (reg RETVAL_REGNUM))
14624 + "USE_RETURN_INSN (TRUE) &&
14625 + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
14627 + [(set_attr "type" "call")
14628 + (set_attr "predicable" "yes")])
14630 +(define_insn "return_<mode>reg"
14631 + [(set (reg RETVAL_REGNUM) (match_operand:MOVM 0 "register_operand" "r"))
14632 + (use (reg RETVAL_REGNUM))
14634 + "USE_RETURN_INSN (TRUE)"
14636 + [(set_attr "type" "call")
14637 + (set_attr "predicable" "yes")])
14639 +(define_insn "return_<mode>reg_cond"
14640 + [(set (reg RETVAL_REGNUM) (match_operand:MOVM 0 "register_operand" "r"))
14641 + (use (reg RETVAL_REGNUM))
14643 + (if_then_else (match_operator 1 "avr32_comparison_operator"
14644 + [(cc0) (const_int 0)])
14647 + "USE_RETURN_INSN (TRUE)"
14649 + [(set_attr "type" "call")])
14651 +;;=============================================================================
14653 +;;-----------------------------------------------------------------------------
14654 +;; No-op instruction.
14655 +;;=============================================================================
14656 +(define_insn "nop"
14660 + [(set_attr "length" "2")
14661 + (set_attr "type" "alu")
14662 + (set_attr "cc" "none")])
14664 +;;=============================================================================
14665 +;; nonlocal_goto_receiver
14666 +;;-----------------------------------------------------------------------------
14667 +;; For targets with a return stack we must make sure to flush the return stack
14668 +;; since it will be corrupt after a nonlocal goto.
14669 +;;=============================================================================
14670 +(define_expand "nonlocal_goto_receiver"
14672 + "TARGET_RETURN_STACK"
14675 + emit_insn ( gen_frs() );
14682 +;;=============================================================================
14683 +;; builtin_setjmp_receiver
14684 +;;-----------------------------------------------------------------------------
14685 +;; For pic code we need to reload the pic register.
14686 +;; For targets with a return stack we must make sure to flush the return stack
14687 +;; since it will probably be corrupted.
14688 +;;=============================================================================
14689 +(define_expand "builtin_setjmp_receiver"
14690 + [(label_ref (match_operand 0 "" ""))]
14694 + if ( TARGET_RETURN_STACK )
14695 + emit_insn ( gen_frs() );
14697 + avr32_load_pic_register ();
14704 +;;=============================================================================
14706 +;;-----------------------------------------------------------------------------
14707 +;; Jump to an address in reg or memory.
14708 +;;=============================================================================
14709 +(define_expand "indirect_jump"
14711 + (match_operand:SI 0 "general_operand" ""))]
14714 + /* One of the ops has to be in a register. */
14715 + if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS )
14716 + && !avr32_legitimate_pic_operand_p(operands[0]) )
14717 + operands[0] = legitimize_pic_address (operands[0], SImode, 0);
14718 + else if ( flag_pic && avr32_address_operand(operands[0], GET_MODE(operands[0])) )
14719 + /* If we have an address operand then this function uses the pic register. */
14720 + current_function_uses_pic_offset_table = 1;
14724 +(define_insn "indirect_jump_internal"
14726 + (match_operand:SI 0 "avr32_non_rmw_general_operand" "r,m,W"))]
14729 + switch( which_alternative ){
14731 + return "mov\tpc, %0";
14733 + if ( avr32_const_pool_ref_operand(operands[0], GET_MODE(operands[0])) )
14734 + return "lddpc\tpc, %0";
14736 + return "ld.w\tpc, %0";
14739 + return "ld.w\tpc, r6[%0@got]";
14741 + return "lda.w\tpc, %0";
14746 + [(set_attr "length" "2,4,8")
14747 + (set_attr "type" "call,call,call")
14748 + (set_attr "cc" "none,none,clobber")])
14752 +;;=============================================================================
14753 +;; casesi and tablejump
14754 +;;=============================================================================
14755 +(define_insn "tablejump_add"
14757 + (plus:SI (match_operand:SI 0 "register_operand" "r")
14758 + (mult:SI (match_operand:SI 1 "register_operand" "r")
14759 + (match_operand:SI 2 "immediate_operand" "Ku04" ))))
14760 + (use (label_ref (match_operand 3 "" "")))]
14762 + ((INTVAL(operands[2]) == 0) || (INTVAL(operands[2]) == 2) ||
14763 + (INTVAL(operands[2]) == 4) || (INTVAL(operands[2]) == 8))"
14764 + "add\tpc, %0, %1 << %p2"
14765 + [(set_attr "length" "4")
14766 + (set_attr "cc" "clobber")])
14768 +(define_insn "tablejump_insn"
14769 + [(set (pc) (match_operand:SI 0 "memory_operand" "m"))
14770 + (use (label_ref (match_operand 1 "" "")))]
14773 + [(set_attr "length" "4")
14774 + (set_attr "type" "call")
14775 + (set_attr "cc" "none")])
14777 +(define_expand "casesi"
14778 + [(match_operand:SI 0 "register_operand" "") ; index to jump on
14779 + (match_operand:SI 1 "const_int_operand" "") ; lower bound
14780 + (match_operand:SI 2 "const_int_operand" "") ; total range
14781 + (match_operand:SI 3 "" "") ; table label
14782 + (match_operand:SI 4 "" "")] ; Out of range label
14787 + rtx index = operands[0];
14788 + rtx low_bound = operands[1];
14789 + rtx range = operands[2];
14790 + rtx table_label = operands[3];
14791 + rtx oor_label = operands[4];
14793 + index = force_reg ( SImode, index );
14794 + if (low_bound != const0_rtx)
14796 + if (!avr32_const_ok_for_constraint_p(INTVAL (low_bound), 'I', \"Is21\")){
14797 + reg = force_reg(SImode, GEN_INT (INTVAL (low_bound)));
14798 + emit_insn (gen_subsi3 (reg, index,
14801 + reg = gen_reg_rtx (SImode);
14802 + emit_insn (gen_addsi3 (reg, index,
14803 + GEN_INT (-INTVAL (low_bound))));
14808 + if (!avr32_const_ok_for_constraint_p (INTVAL (range), 'K', \"Ks21\"))
14809 + range = force_reg (SImode, range);
14811 + emit_cmp_and_jump_insns ( index, range, GTU, NULL_RTX, SImode, 1, oor_label );
14812 + reg = gen_reg_rtx (SImode);
14813 + emit_move_insn ( reg, gen_rtx_LABEL_REF (VOIDmode, table_label));
14816 + emit_jump_insn ( gen_tablejump_add ( reg, index, GEN_INT(4), table_label));
14819 + gen_tablejump_insn ( gen_rtx_MEM ( SImode,
14820 + gen_rtx_PLUS ( SImode,
14822 + gen_rtx_MULT ( SImode,
14832 +(define_insn "prefetch"
14833 + [(prefetch (match_operand:SI 0 "avr32_ks16_address_operand" "p")
14834 + (match_operand 1 "const_int_operand" "")
14835 + (match_operand 2 "const_int_operand" ""))]
14838 + return "pref\t%0";
14841 + [(set_attr "length" "4")
14842 + (set_attr "type" "load")
14843 + (set_attr "cc" "none")])
14847 +;;=============================================================================
14849 +;;-----------------------------------------------------------------------------
14850 +;; This pattern, if defined, emits RTL for entry to a function. The function
14851 +;; entry i responsible for setting up the stack frame, initializing the frame
14852 +;; pointer register, saving callee saved registers, etc.
14853 +;;=============================================================================
14854 +(define_expand "prologue"
14855 + [(clobber (const_int 0))]
14858 + avr32_expand_prologue();
14863 +;;=============================================================================
14865 +;;-----------------------------------------------------------------------------
14866 +;; This pattern, if defined, affects the way __builtin_eh_return, and
14867 +;; thence the call frame exception handling library routines, are
14868 +;; built. It is intended to handle non-trivial actions needed along
14869 +;; the abnormal return path.
14871 +;; The address of the exception handler to which the function should
14872 +;; return is passed as operand to this pattern. It will normally need
14873 +;; to copied by the pattern to some special register or memory
14874 +;; location. If the pattern needs to determine the location of the
14875 +;; target call frame in order to do so, it may use
14876 +;; EH_RETURN_STACKADJ_RTX, if defined; it will have already been
14879 +;; If this pattern is not defined, the default action will be to
14880 +;; simply copy the return address to EH_RETURN_HANDLER_RTX. Either
14881 +;; that macro or this pattern needs to be defined if call frame
14882 +;; exception handling is to be used.
14884 +;; We can't expand this before we know where the link register is stored.
14885 +(define_insn_and_split "eh_return"
14886 + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")]
14887 + VUNSPEC_EH_RETURN)
14888 + (clobber (match_scratch:SI 1 "=&r"))]
14891 + "reload_completed"
14895 + avr32_set_return_address (operands[0], operands[1]);
14901 +;;=============================================================================
14903 +;;-----------------------------------------------------------------------------
14904 +(define_insn "ffssi2"
14905 + [ (set (match_operand:SI 0 "register_operand" "=r")
14906 + (ffs:SI (match_operand:SI 1 "register_operand" "r"))) ]
14914 + [(set_attr "length" "18")
14915 + (set_attr "cc" "clobber")]
14920 +;;=============================================================================
14922 +;;-----------------------------------------------------------------------------
14923 +(define_insn "*swap_h"
14924 + [ (set (match_operand:SI 0 "register_operand" "=r")
14925 + (ior:SI (ashift:SI (match_dup 0) (const_int 16))
14926 + (lshiftrt:SI (match_dup 0) (const_int 16))))]
14929 + [(set_attr "length" "2")]
14932 +(define_insn_and_split "bswap_16"
14933 + [ (set (match_operand:HI 0 "avr32_bswap_operand" "=r,RKs13,r")
14934 + (ior:HI (and:HI (lshiftrt:HI (match_operand:HI 1 "avr32_bswap_operand" "r,r,RKs13")
14937 + (ashift:HI (and:HI (match_dup 1)
14939 + (const_int 8))))]
14942 + switch ( which_alternative ){
14944 + if ( REGNO(operands[0]) == REGNO(operands[1]))
14945 + return "swap.bh\t%0";
14947 + return "mov\t%0, %1\;swap.bh\t%0";
14949 + return "stswp.h\t%0, %1";
14951 + return "ldswp.sh\t%0, %1";
14957 + "(reload_completed &&
14958 + REG_P(operands[0]) && REG_P(operands[1])
14959 + && (REGNO(operands[0]) != REGNO(operands[1])))"
14960 + [(set (match_dup 0) (match_dup 1))
14961 + (set (match_dup 0)
14962 + (ior:HI (and:HI (lshiftrt:HI (match_dup 0)
14965 + (ashift:HI (and:HI (match_dup 0)
14967 + (const_int 8))))]
14970 + [(set_attr "length" "4,4,4")
14971 + (set_attr "type" "alu,store,load_rm")]
14974 +(define_insn_and_split "bswap_32"
14975 + [ (set (match_operand:SI 0 "avr32_bswap_operand" "=r,RKs14,r")
14976 + (ior:SI (ior:SI (lshiftrt:SI (and:SI (match_operand:SI 1 "avr32_bswap_operand" "r,r,RKs14")
14977 + (const_int -16777216))
14979 + (lshiftrt:SI (and:SI (match_dup 1)
14980 + (const_int 16711680))
14982 + (ior:SI (ashift:SI (and:SI (match_dup 1)
14983 + (const_int 65280))
14985 + (ashift:SI (and:SI (match_dup 1)
14987 + (const_int 24)))))]
14990 + switch ( which_alternative ){
14992 + if ( REGNO(operands[0]) == REGNO(operands[1]))
14993 + return "swap.b\t%0";
14997 + return "stswp.w\t%0, %1";
14999 + return "ldswp.w\t%0, %1";
15004 + "(reload_completed &&
15005 + REG_P(operands[0]) && REG_P(operands[1])
15006 + && (REGNO(operands[0]) != REGNO(operands[1])))"
15007 + [(set (match_dup 0) (match_dup 1))
15008 + (set (match_dup 0)
15009 + (ior:SI (ior:SI (lshiftrt:SI (and:SI (match_dup 0)
15010 + (const_int -16777216))
15012 + (lshiftrt:SI (and:SI (match_dup 0)
15013 + (const_int 16711680))
15015 + (ior:SI (ashift:SI (and:SI (match_dup 0)
15016 + (const_int 65280))
15018 + (ashift:SI (and:SI (match_dup 0)
15020 + (const_int 24)))))]
15023 + [(set_attr "length" "4,4,4")
15024 + (set_attr "type" "alu,store,load_rm")]
15028 +;;=============================================================================
15030 +;;-----------------------------------------------------------------------------
15031 +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
15032 +;; all of memory. This blocks insns from being moved across this point.
15034 +(define_insn "blockage"
15035 + [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)]
15038 + [(set_attr "length" "0")]
15041 +;;=============================================================================
15043 +;;-----------------------------------------------------------------------------
15044 +(define_insn "clzsi2"
15045 + [ (set (match_operand:SI 0 "register_operand" "=r")
15046 + (clz:SI (match_operand:SI 1 "register_operand" "r"))) ]
15049 + [(set_attr "length" "4")
15050 + (set_attr "cc" "set_z")]
15053 +;;=============================================================================
15055 +;;-----------------------------------------------------------------------------
15056 +(define_insn "ctzsi2"
15057 + [ (set (match_operand:SI 0 "register_operand" "=r,r")
15058 + (ctz:SI (match_operand:SI 1 "register_operand" "0,r"))) ]
15061 + brev\t%0\;clz\t%0, %0
15062 + mov\t%0, %1\;brev\t%0\;clz\t%0, %0"
15063 + [(set_attr "length" "8")
15064 + (set_attr "cc" "set_z")]
15067 +;;=============================================================================
15068 +;; cache instructions
15069 +;;-----------------------------------------------------------------------------
15070 +(define_insn "cache"
15071 + [ (unspec_volatile [(match_operand:SI 0 "avr32_ks11_address_operand" "p")
15072 + (match_operand:SI 1 "immediate_operand" "Ku05")] VUNSPEC_CACHE)]
15075 + [(set_attr "length" "4")]
15078 +(define_insn "sync"
15079 + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku08")] VUNSPEC_SYNC)]
15082 + [(set_attr "length" "4")]
15085 +;;=============================================================================
15086 +;; TLB instructions
15087 +;;-----------------------------------------------------------------------------
15088 +(define_insn "tlbr"
15089 + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBR)]
15092 + [(set_attr "length" "2")]
15095 +(define_insn "tlbw"
15096 + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBW)]
15099 + [(set_attr "length" "2")]
15102 +(define_insn "tlbs"
15103 + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBS)]
15106 + [(set_attr "length" "2")]
15109 +;;=============================================================================
15110 +;; Breakpoint instruction
15111 +;;-----------------------------------------------------------------------------
15112 +(define_insn "breakpoint"
15113 + [ (unspec_volatile [(const_int 0)] VUNSPEC_BREAKPOINT)]
15116 + [(set_attr "length" "2")]
15120 +;;=============================================================================
15121 +;; mtsr/mfsr instruction
15122 +;;-----------------------------------------------------------------------------
15123 +(define_insn "mtsr"
15124 + [ (unspec_volatile [(match_operand 0 "immediate_operand" "i")
15125 + (match_operand:SI 1 "register_operand" "r")] VUNSPEC_MTSR)]
15128 + [(set_attr "length" "4")]
15131 +(define_insn "mfsr"
15132 + [ (set (match_operand:SI 0 "register_operand" "=r")
15133 + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "i")] VUNSPEC_MFSR)) ]
15136 + [(set_attr "length" "4")]
15139 +;;=============================================================================
15140 +;; mtdr/mfdr instruction
15141 +;;-----------------------------------------------------------------------------
15142 +(define_insn "mtdr"
15143 + [ (unspec_volatile [(match_operand 0 "immediate_operand" "i")
15144 + (match_operand:SI 1 "register_operand" "r")] VUNSPEC_MTDR)]
15147 + [(set_attr "length" "4")]
15150 +(define_insn "mfdr"
15151 + [ (set (match_operand:SI 0 "register_operand" "=r")
15152 + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "i")] VUNSPEC_MFDR)) ]
15155 + [(set_attr "length" "4")]
15158 +;;=============================================================================
15160 +;;-----------------------------------------------------------------------------
15161 +(define_insn "musfr"
15162 + [ (unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_MUSFR)]
15165 + [(set_attr "length" "2")
15166 + (set_attr "cc" "clobber")]
15169 +(define_insn "mustr"
15170 + [ (set (match_operand:SI 0 "register_operand" "=r")
15171 + (unspec_volatile:SI [(const_int 0)] VUNSPEC_MUSTR)) ]
15174 + [(set_attr "length" "2")]
15177 +(define_insn "ssrf"
15178 + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku05")] VUNSPEC_SSRF)]
15181 + [(set_attr "length" "2")
15182 + (set_attr "cc" "clobber")]
15185 +(define_insn "csrf"
15186 + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku05")] VUNSPEC_CSRF)]
15189 + [(set_attr "length" "2")
15190 + (set_attr "cc" "clobber")]
15193 +;;=============================================================================
15194 +;; Flush Return Stack instruction
15195 +;;-----------------------------------------------------------------------------
15196 +(define_insn "frs"
15197 + [ (unspec_volatile [(const_int 0)] VUNSPEC_FRS)]
15200 + [(set_attr "length" "2")
15201 + (set_attr "cc" "none")]
15205 +;;=============================================================================
15206 +;; Saturation Round Scale instruction
15207 +;;-----------------------------------------------------------------------------
15208 +(define_insn "sats"
15209 + [ (set (match_operand:SI 0 "register_operand" "+r")
15210 + (unspec:SI [(match_dup 0)
15211 + (match_operand 1 "immediate_operand" "Ku05")
15212 + (match_operand 2 "immediate_operand" "Ku05")]
15215 + "sats\t%0 >> %1, %2"
15216 + [(set_attr "type" "alu_sat")
15217 + (set_attr "length" "4")]
15220 +(define_insn "satu"
15221 + [ (set (match_operand:SI 0 "register_operand" "+r")
15222 + (unspec:SI [(match_dup 0)
15223 + (match_operand 1 "immediate_operand" "Ku05")
15224 + (match_operand 2 "immediate_operand" "Ku05")]
15227 + "satu\t%0 >> %1, %2"
15228 + [(set_attr "type" "alu_sat")
15229 + (set_attr "length" "4")]
15232 +(define_insn "satrnds"
15233 + [ (set (match_operand:SI 0 "register_operand" "+r")
15234 + (unspec:SI [(match_dup 0)
15235 + (match_operand 1 "immediate_operand" "Ku05")
15236 + (match_operand 2 "immediate_operand" "Ku05")]
15237 + UNSPEC_SATRNDS)) ]
15239 + "satrnds\t%0 >> %1, %2"
15240 + [(set_attr "type" "alu_sat")
15241 + (set_attr "length" "4")]
15244 +(define_insn "satrndu"
15245 + [ (set (match_operand:SI 0 "register_operand" "+r")
15246 + (unspec:SI [(match_dup 0)
15247 + (match_operand 1 "immediate_operand" "Ku05")
15248 + (match_operand 2 "immediate_operand" "Ku05")]
15249 + UNSPEC_SATRNDU)) ]
15251 + "sats\t%0 >> %1, %2"
15252 + [(set_attr "type" "alu_sat")
15253 + (set_attr "length" "4")]
15256 +;; Special patterns for dealing with the constant pool
15258 +(define_insn "align_4"
15259 + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)]
15262 + assemble_align (32);
15265 + [(set_attr "length" "2")]
15268 +(define_insn "consttable_start"
15269 + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_START)]
15274 + [(set_attr "length" "0")]
15277 +(define_insn "consttable_end"
15278 + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)]
15281 + making_const_table = FALSE;
15284 + [(set_attr "length" "0")]
15288 +(define_insn "consttable_4"
15289 + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)]
15292 + making_const_table = TRUE;
15293 + switch (GET_MODE_CLASS (GET_MODE (operands[0])))
15297 + REAL_VALUE_TYPE r;
15298 + char real_string[1024];
15299 + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
15300 + real_to_decimal(real_string, &r, 1024, 0, 1);
15301 + asm_fprintf (asm_out_file, "\t.float\t%s\n", real_string);
15305 + assemble_integer (operands[0], 4, 0, 1);
15310 + [(set_attr "length" "4")]
15313 +(define_insn "consttable_8"
15314 + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)]
15317 + making_const_table = TRUE;
15318 + switch (GET_MODE_CLASS (GET_MODE (operands[0])))
15322 + REAL_VALUE_TYPE r;
15323 + char real_string[1024];
15324 + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]);
15325 + real_to_decimal(real_string, &r, 1024, 0, 1);
15326 + asm_fprintf (asm_out_file, "\t.double\t%s\n", real_string);
15330 + assemble_integer(operands[0], 8, 0, 1);
15335 + [(set_attr "length" "8")]
15338 +(define_insn "consttable_16"
15339 + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)]
15342 + making_const_table = TRUE;
15343 + assemble_integer(operands[0], 16, 0, 1);
15346 + [(set_attr "length" "16")]
15349 +;;=============================================================================
15350 +;; coprocessor instructions
15351 +;;-----------------------------------------------------------------------------
15352 +(define_insn "cop"
15353 + [ (unspec_volatile [(match_operand 0 "immediate_operand" "Ku03")
15354 + (match_operand 1 "immediate_operand" "Ku04")
15355 + (match_operand 2 "immediate_operand" "Ku04")
15356 + (match_operand 3 "immediate_operand" "Ku04")
15357 + (match_operand 4 "immediate_operand" "Ku07")] VUNSPEC_COP)]
15359 + "cop\tcp%0, cr%1, cr%2, cr%3, %4"
15360 + [(set_attr "length" "4")]
15363 +(define_insn "mvcrsi"
15364 + [ (set (match_operand:SI 0 "avr32_cop_move_operand" "=r,<,Z")
15365 + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "Ku03,Ku03,Ku03")
15366 + (match_operand 2 "immediate_operand" "Ku04,Ku04,Ku04")]
15370 + mvcr.w\tcp%1, %0, cr%2
15371 + stcm.w\tcp%1, %0, cr%2
15372 + stc.w\tcp%1, %0, cr%2"
15373 + [(set_attr "length" "4")]
15376 +(define_insn "mvcrdi"
15377 + [ (set (match_operand:DI 0 "avr32_cop_move_operand" "=r,<,Z")
15378 + (unspec_volatile:DI [(match_operand 1 "immediate_operand" "Ku03,Ku03,Ku03")
15379 + (match_operand 2 "immediate_operand" "Ku04,Ku04,Ku04")]
15383 + mvcr.d\tcp%1, %0, cr%2
15384 + stcm.d\tcp%1, %0, cr%2-cr%i2
15385 + stc.d\tcp%1, %0, cr%2"
15386 + [(set_attr "length" "4")]
15389 +(define_insn "mvrcsi"
15390 + [ (unspec_volatile:SI [(match_operand 0 "immediate_operand" "Ku03,Ku03,Ku03")
15391 + (match_operand 1 "immediate_operand" "Ku04,Ku04,Ku04")
15392 + (match_operand:SI 2 "avr32_cop_move_operand" "r,>,Z")]
15396 + switch (which_alternative){
15398 + return "mvrc.w\tcp%0, cr%1, %2";
15400 + return "ldcm.w\tcp%0, %2, cr%1";
15402 + return "ldc.w\tcp%0, cr%1, %2";
15407 + [(set_attr "length" "4")]
15410 +(define_insn "mvrcdi"
15411 + [ (unspec_volatile:DI [(match_operand 0 "immediate_operand" "Ku03,Ku03,Ku03")
15412 + (match_operand 1 "immediate_operand" "Ku04,Ku04,Ku04")
15413 + (match_operand:DI 2 "avr32_cop_move_operand" "r,>,Z")]
15417 + switch (which_alternative){
15419 + return "mvrc.d\tcp%0, cr%1, %2";
15421 + return "ldcm.d\tcp%0, %2, cr%1-cr%i1";
15423 + return "ldc.d\tcp%0, cr%1, %2";
15428 + [(set_attr "length" "4")]
15431 +;;=============================================================================
15433 +;;-----------------------------------------------------------------------------
15434 +;; This pattern emits RTL for exit from a function. The function exit is
15435 +;; responsible for deallocating the stack frame, restoring callee saved
15436 +;; registers and emitting the return instruction.
15437 +;; ToDo: using TARGET_ASM_FUNCTION_PROLOGUE instead.
15438 +;;=============================================================================
15439 +(define_expand "epilogue"
15440 + [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
15443 + if (USE_RETURN_INSN (FALSE)){
15444 + emit_jump_insn (gen_return ());
15447 + emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
15449 + gen_rtx_RETURN (VOIDmode)),
15450 + VUNSPEC_EPILOGUE));
15455 +(define_insn "*epilogue_insns"
15456 + [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
15459 + avr32_output_return_instruction (FALSE, FALSE, NULL, NULL);
15462 + ; Length is absolute worst case
15463 + [(set_attr "type" "branch")
15464 + (set_attr "length" "12")]
15467 +(define_insn "*epilogue_insns_ret_imm"
15468 + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
15469 + (use (reg RETVAL_REGNUM))
15470 + (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])]
15471 + "((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
15473 + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[0]);
15476 + ; Length is absolute worst case
15477 + [(set_attr "type" "branch")
15478 + (set_attr "length" "12")]
15481 +(define_insn "sibcall_epilogue"
15482 + [(unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)]
15485 + avr32_output_return_instruction (FALSE, FALSE, NULL, NULL);
15488 +;; Length is absolute worst case
15489 + [(set_attr "type" "branch")
15490 + (set_attr "length" "12")]
15493 +(define_insn "*sibcall_epilogue_insns_ret_imm"
15494 + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i"))
15495 + (use (reg RETVAL_REGNUM))
15496 + (unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)])]
15497 + "((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))"
15499 + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[0]);
15502 + ; Length is absolute worst case
15503 + [(set_attr "type" "branch")
15504 + (set_attr "length" "12")]
15507 +(define_insn "ldxi"
15508 + [(set (match_operand:SI 0 "register_operand" "=r")
15510 + (match_operand:SI 1 "register_operand" "r")
15511 + (mult:SI (zero_extract:SI (match_operand:SI 2 "register_operand" "r")
15513 + (match_operand:SI 3 "immediate_operand" "Ku05"))
15514 + (const_int 4)))))]
15515 + "(INTVAL(operands[3]) == 24 || INTVAL(operands[3]) == 16 || INTVAL(operands[3]) == 8
15516 + || INTVAL(operands[3]) == 0)"
15518 + switch ( INTVAL(operands[3]) ){
15520 + return "ld.w %0, %1[%2:b << 2]";
15522 + return "ld.w %0, %1[%2:l << 2]";
15524 + return "ld.w %0, %1[%2:u << 2]";
15526 + return "ld.w %0, %1[%2:t << 2]";
15528 + internal_error("illegal operand for ldxi");
15531 + [(set_attr "type" "load")
15532 + (set_attr "length" "4")
15533 + (set_attr "cc" "none")])
15540 +;;=============================================================================
15541 +;; Peephole optimizing
15542 +;;-----------------------------------------------------------------------------
15545 +;; st.w r8[0x0], r12
15548 +;; st.w r7[-0x8], r12
15549 +;;=============================================================================
15550 +; (set (reg:SI 9 r8)
15551 +; (plus:SI (reg/f:SI 6 r7)
15552 +; (const_int ...)))
15553 +; (set (mem:SI (reg:SI 9 r8))
15554 +; (reg:SI 12 r12))
15556 + [(set (match_operand:SI 0 "register_operand" "")
15557 + (plus:SI (match_operand:SI 1 "register_operand" "")
15558 + (match_operand:SI 2 "immediate_operand" "")))
15559 + (set (mem:SI (match_dup 0))
15560 + (match_operand:SI 3 "register_operand" ""))]
15561 + "REGNO(operands[0]) != REGNO(operands[1]) && avr32_const_ok_for_constraint_p(INTVAL(operands[2]), 'K', \"Ks16\")"
15562 + [(set (match_dup 0)
15563 + (plus:SI (match_dup 1)
15565 + (set (mem:SI (plus:SI (match_dup 1)
15570 +;;=============================================================================
15571 +;; Peephole optimizing
15572 +;;-----------------------------------------------------------------------------
15575 +;; ld.w r6, r6[0x0]
15578 +;; ld.w r6, r7[-0x4]
15579 +;;=============================================================================
15580 +; (set (reg:SI 7 r6)
15581 +; (plus:SI (reg/f:SI 6 r7)
15582 +; (const_int -4 [0xfffffffc])))
15583 +; (set (reg:SI 7 r6)
15584 +; (mem:SI (reg:SI 7 r6)))
15586 + [(set (match_operand:SI 0 "register_operand" "")
15587 + (plus:SI (match_operand:SI 1 "register_operand" "")
15588 + (match_operand:SI 2 "immediate_operand" "")))
15589 + (set (match_operand:SI 3 "register_operand" "")
15590 + (mem:SI (match_dup 0)))]
15591 + "REGNO(operands[0]) != REGNO(operands[1]) && avr32_const_ok_for_constraint_p(INTVAL(operands[2]), 'K', \"Ks16\")"
15592 + [(set (match_dup 0)
15593 + (plus:SI (match_dup 1)
15595 + (set (match_dup 3)
15596 + (mem:SI (plus:SI (match_dup 1)
15597 + (match_dup 2))))]
15600 +;;=============================================================================
15601 +;; Peephole optimizing
15602 +;;-----------------------------------------------------------------------------
15604 +;; ld.sb r0, r7[-0x6]
15607 +;; ld.sb r0, r7[-0x6]
15608 +;;=============================================================================
15610 + [(set (match_operand:QI 0 "register_operand" "")
15611 + (match_operand:QI 1 "load_sb_memory_operand" ""))
15612 + (set (match_operand:SI 2 "register_operand" "")
15613 + (sign_extend:SI (match_dup 0)))]
15614 + "(REGNO(operands[0]) == REGNO(operands[2]) || peep2_reg_dead_p(2, operands[0]))"
15615 + [(set (match_dup 2)
15616 + (sign_extend:SI (match_dup 1)))]
15619 +;;=============================================================================
15620 +;; Peephole optimizing
15621 +;;-----------------------------------------------------------------------------
15623 +;; ld.ub r0, r7[-0x6]
15626 +;; ld.ub r0, r7[-0x6]
15627 +;;=============================================================================
15629 + [(set (match_operand:QI 0 "register_operand" "")
15630 + (match_operand:QI 1 "memory_operand" ""))
15631 + (set (match_operand:SI 2 "register_operand" "")
15632 + (zero_extend:SI (match_dup 0)))]
15633 + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])"
15634 + [(set (match_dup 2)
15635 + (zero_extend:SI (match_dup 1)))]
15638 +;;=============================================================================
15639 +;; Peephole optimizing
15640 +;;-----------------------------------------------------------------------------
15642 +;; ld.sh r0, r7[-0x6]
15645 +;; ld.sh r0, r7[-0x6]
15646 +;;=============================================================================
15648 + [(set (match_operand:HI 0 "register_operand" "")
15649 + (match_operand:HI 1 "memory_operand" ""))
15650 + (set (match_operand:SI 2 "register_operand" "")
15651 + (sign_extend:SI (match_dup 0)))]
15652 + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])"
15653 + [(set (match_dup 2)
15654 + (sign_extend:SI (match_dup 1)))]
15657 +;;=============================================================================
15658 +;; Peephole optimizing
15659 +;;-----------------------------------------------------------------------------
15661 +;; ld.uh r0, r7[-0x6]
15664 +;; ld.uh r0, r7[-0x6]
15665 +;;=============================================================================
15667 + [(set (match_operand:HI 0 "register_operand" "")
15668 + (match_operand:HI 1 "memory_operand" ""))
15669 + (set (match_operand:SI 2 "register_operand" "")
15670 + (zero_extend:SI (match_dup 0)))]
15671 + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])"
15672 + [(set (match_dup 2)
15673 + (zero_extend:SI (match_dup 1)))]
15676 +;;=============================================================================
15677 +;; Peephole optimizing
15678 +;;-----------------------------------------------------------------------------
15683 +;; add rd2, rd, rd2
15685 +;; mac rd2, rx, ry
15686 +;;=============================================================================
15688 + [(set (match_operand:SI 0 "register_operand" "")
15689 + (mult:SI (match_operand:SI 1 "register_operand" "")
15690 + (match_operand:SI 2 "register_operand" "")))
15691 + (set (match_operand:SI 3 "register_operand" "")
15692 + (plus:SI (match_dup 3)
15694 + "peep2_reg_dead_p(2, operands[0])"
15695 + [(set (match_dup 3)
15696 + (plus:SI (mult:SI (match_dup 1)
15702 + [(set (match_operand:SI 0 "register_operand" "")
15703 + (mult:SI (match_operand:SI 1 "register_operand" "")
15704 + (match_operand:SI 2 "register_operand" "")))
15705 + (set (match_operand:SI 3 "register_operand" "")
15706 + (plus:SI (match_dup 0)
15708 + "peep2_reg_dead_p(2, operands[0])"
15709 + [(set (match_dup 3)
15710 + (plus:SI (mult:SI (match_dup 1)
15716 +;;=============================================================================
15717 +;; Peephole optimizing
15718 +;;-----------------------------------------------------------------------------
15720 +;; bfextu rd, rs, k5, 1 or and(h/l) rd, one_bit_set_mask
15724 +;; If rd is dead after the operation.
15725 +;;=============================================================================
15727 + [ (set (match_operand:SI 0 "register_operand" "")
15728 + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
15730 + (match_operand:SI 2 "immediate_operand" "")))
15733 + "peep2_reg_dead_p(2, operands[0])"
15735 + (and:SI (match_dup 1)
15737 + "operands[2] = GEN_INT(1 << INTVAL(operands[2]));")
15740 + [ (set (match_operand:SI 0 "register_operand" "")
15741 + (and:SI (match_operand:SI 1 "register_operand" "")
15742 + (match_operand:SI 2 "one_bit_set_operand" "")))
15745 + "peep2_reg_dead_p(2, operands[0])"
15747 + (and:SI (match_dup 1)
15751 +;;=============================================================================
15752 +;; Peephole optimizing
15753 +;;-----------------------------------------------------------------------------
15754 +;; Load with extracted index: ld.w Rd, Rb[Ri:{t/u/b/l} << 2]
15756 +;;=============================================================================
15760 + [(set (match_operand:SI 0 "register_operand" "")
15761 + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
15763 + (match_operand:SI 2 "avr32_extract_shift_operand" "")))
15764 + (set (match_operand:SI 3 "register_operand" "")
15765 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
15766 + (match_operand:SI 4 "register_operand" ""))))]
15768 + "(dead_or_set_p(insn, operands[0]))"
15770 + switch ( INTVAL(operands[2]) ){
15772 + return "ld.w %3, %4[%1:b << 2]";
15774 + return "ld.w %3, %4[%1:l << 2]";
15776 + return "ld.w %3, %4[%1:u << 2]";
15778 + return "ld.w %3, %4[%1:t << 2]";
15780 + internal_error("illegal operand for ldxi");
15783 + [(set_attr "type" "load")
15784 + (set_attr "length" "4")
15785 + (set_attr "cc" "clobber")]
15791 + [(set (match_operand:SI 0 "register_operand" "")
15792 + (and:SI (match_operand:SI 1 "register_operand" "") (const_int 255)))
15793 + (set (match_operand:SI 2 "register_operand" "")
15794 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
15795 + (match_operand:SI 3 "register_operand" ""))))]
15797 + "(dead_or_set_p(insn, operands[0]))"
15799 + "ld.w %2, %3[%1:b << 2]"
15800 + [(set_attr "type" "load")
15801 + (set_attr "length" "4")
15802 + (set_attr "cc" "clobber")]
15807 + [(set (match_operand:SI 0 "register_operand" "")
15808 + (zero_extract:SI (match_operand:SI 1 "register_operand" "")
15810 + (match_operand:SI 2 "avr32_extract_shift_operand" "")))
15811 + (set (match_operand:SI 3 "register_operand" "")
15812 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
15813 + (match_operand:SI 4 "register_operand" ""))))]
15815 + "(peep2_reg_dead_p(2, operands[0]))
15816 + || (REGNO(operands[0]) == REGNO(operands[3]))"
15817 + [(set (match_dup 3)
15820 + (mult:SI (zero_extract:SI (match_dup 1)
15823 + (const_int 4)))))]
15827 + [(set (match_operand:SI 0 "register_operand" "")
15828 + (zero_extend:SI (match_operand:QI 1 "register_operand" "")))
15829 + (set (match_operand:SI 2 "register_operand" "")
15830 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
15831 + (match_operand:SI 3 "register_operand" ""))))]
15833 + "(peep2_reg_dead_p(2, operands[0]))
15834 + || (REGNO(operands[0]) == REGNO(operands[2]))"
15835 + [(set (match_dup 2)
15838 + (mult:SI (zero_extract:SI (match_dup 1)
15841 + (const_int 4)))))]
15842 + "operands[1] = gen_rtx_REG(SImode, REGNO(operands[1]));"
15847 + [(set (match_operand:SI 0 "register_operand" "")
15848 + (and:SI (match_operand:SI 1 "register_operand" "")
15849 + (const_int 255)))
15850 + (set (match_operand:SI 2 "register_operand" "")
15851 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
15852 + (match_operand:SI 3 "register_operand" ""))))]
15854 + "(peep2_reg_dead_p(2, operands[0]))
15855 + || (REGNO(operands[0]) == REGNO(operands[2]))"
15856 + [(set (match_dup 2)
15859 + (mult:SI (zero_extract:SI (match_dup 1)
15862 + (const_int 4)))))]
15869 + [(set (match_operand:SI 0 "register_operand" "")
15870 + (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
15872 + (set (match_operand:SI 2 "register_operand" "")
15873 + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4))
15874 + (match_operand:SI 3 "register_operand" ""))))]
15876 + "(peep2_reg_dead_p(2, operands[0]))
15877 + || (REGNO(operands[0]) == REGNO(operands[2]))"
15878 + [(set (match_dup 2)
15881 + (mult:SI (zero_extract:SI (match_dup 1)
15884 + (const_int 4)))))]
15889 +;;************************************************
15892 +;;************************************************
15896 + [(set (match_operand:SI 0 "register_operand" "")
15897 + (not:SI (match_operand:SI 1 "register_operand" "")))
15898 + (set (match_operand:SI 2 "register_operand" "")
15899 + (and:SI (match_dup 2)
15901 + "peep2_reg_dead_p(2, operands[0])"
15903 + [(set (match_dup 2)
15904 + (and:SI (match_dup 2)
15905 + (not:SI (match_dup 1))
15911 + [(set (match_operand:SI 0 "register_operand" "")
15912 + (not:SI (match_operand:SI 1 "register_operand" "")))
15913 + (set (match_operand:SI 2 "register_operand" "")
15914 + (and:SI (match_dup 0)
15917 + "peep2_reg_dead_p(2, operands[0])"
15919 + [(set (match_dup 2)
15920 + (and:SI (match_dup 2)
15921 + (not:SI (match_dup 1))
15928 +;;=================================================================
15929 +;; Addabs peephole
15930 +;;=================================================================
15933 + [(set (match_operand:SI 2 "register_operand" "=r")
15934 + (abs:SI (match_operand:SI 1 "register_operand" "r")))
15935 + (set (match_operand:SI 0 "register_operand" "=r")
15936 + (plus:SI (match_operand:SI 3 "register_operand" "r")
15938 + "dead_or_set_p(insn, operands[2])"
15939 + "addabs %0, %3, %1"
15940 + [(set_attr "length" "4")
15941 + (set_attr "cc" "set_z")])
15944 + [(set (match_operand:SI 2 "register_operand" "=r")
15945 + (abs:SI (match_operand:SI 1 "register_operand" "r")))
15946 + (set (match_operand:SI 0 "register_operand" "=r")
15947 + (plus:SI (match_dup 2)
15948 + (match_operand:SI 3 "register_operand" "r")))]
15949 + "dead_or_set_p(insn, operands[2])"
15950 + "addabs %0, %3, %1"
15951 + [(set_attr "length" "4")
15952 + (set_attr "cc" "set_z")])
15955 +;;=================================================================
15956 +;; Detect roundings
15957 +;;=================================================================
15959 +(define_insn "*round"
15960 + [(set (match_operand:SI 0 "register_operand" "+r")
15961 + (ashiftrt:SI (plus:SI (match_dup 0)
15962 + (match_operand:SI 1 "immediate_operand" "i"))
15963 + (match_operand:SI 2 "immediate_operand" "i")))]
15964 + "avr32_rnd_operands(operands[1], operands[2])"
15966 + "satrnds %0 >> %2, 31"
15968 + [(set_attr "type" "alu_sat")
15969 + (set_attr "length" "4")]
15975 + [(set (match_operand:SI 0 "register_operand" "")
15976 + (plus:SI (match_dup 0)
15977 + (match_operand:SI 1 "immediate_operand" "")))
15978 + (set (match_dup 0)
15979 + (ashiftrt:SI (match_dup 0)
15980 + (match_operand:SI 2 "immediate_operand" "")))]
15981 + "avr32_rnd_operands(operands[1], operands[2])"
15983 + [(set (match_dup 0)
15984 + (ashiftrt:SI (plus:SI (match_dup 0)
15990 + [(set (match_operand:SI 0 "register_operand" "r")
15991 + (plus:SI (match_dup 0)
15992 + (match_operand:SI 1 "immediate_operand" "i")))
15993 + (set (match_dup 0)
15994 + (ashiftrt:SI (match_dup 0)
15995 + (match_operand:SI 2 "immediate_operand" "i")))]
15996 + "avr32_rnd_operands(operands[1], operands[2])"
15998 + "satrnds %0 >> %2, 31"
16000 + [(set_attr "type" "alu_sat")
16001 + (set_attr "length" "4")
16002 + (set_attr "cc" "clobber")]
16007 +;;=================================================================
16009 +;;=================================================================
16011 + [(set (match_operand:SI 0 "register_operand" "")
16012 + (match_operand 1 "avr32_const_pool_ref_operand" ""))
16013 + (parallel [(call (mem:SI (match_dup 0))
16014 + (match_operand 2 "" ""))
16015 + (clobber (reg:SI LR_REGNUM))])]
16016 + "dead_or_set_p(insn, operands[0])"
16018 + [(set_attr "type" "call")
16019 + (set_attr "length" "4")
16020 + (set_attr "cc" "clobber")]
16024 + [(set (match_operand:SI 2 "register_operand" "")
16025 + (match_operand 1 "avr32_const_pool_ref_operand" ""))
16026 + (parallel [(set (match_operand 0 "register_operand" "")
16027 + (call (mem:SI (match_dup 2))
16028 + (match_operand 3 "" "")))
16029 + (clobber (reg:SI LR_REGNUM))])]
16030 + "dead_or_set_p(insn, operands[2])"
16032 + [(set_attr "type" "call")
16033 + (set_attr "length" "4")
16034 + (set_attr "cc" "call_set")]
16039 + [(set (match_operand:SI 0 "register_operand" "")
16040 + (match_operand 1 "avr32_const_pool_ref_operand" ""))
16041 + (parallel [(call (mem:SI (match_dup 0))
16042 + (match_operand 2 "" ""))
16043 + (clobber (reg:SI LR_REGNUM))])]
16044 + "peep2_reg_dead_p(2, operands[0])"
16045 + [(parallel [(call (mem:SI (match_dup 1))
16047 + (clobber (reg:SI LR_REGNUM))])]
16052 + [(set (match_operand:SI 0 "register_operand" "")
16053 + (match_operand 1 "avr32_const_pool_ref_operand" ""))
16054 + (parallel [(set (match_operand 2 "register_operand" "")
16055 + (call (mem:SI (match_dup 0))
16056 + (match_operand 3 "" "")))
16057 + (clobber (reg:SI LR_REGNUM))])]
16058 + "(peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[2]) == REGNO(operands[0])))"
16059 + [(parallel [(set (match_dup 2)
16060 + (call (mem:SI (match_dup 1))
16062 + (clobber (reg:SI LR_REGNUM))])]
16066 +;;=================================================================
16067 +;; Returning a value
16068 +;;=================================================================
16072 + [(set (match_operand 0 "register_operand" "")
16073 + (match_operand 1 "register_operand" ""))
16075 + "USE_RETURN_INSN (TRUE) && (REGNO(operands[0]) == RETVAL_REGNUM)
16076 + && (REGNO(operands[1]) != LR_REGNUM)
16077 + && (REGNO_REG_CLASS(REGNO(operands[1])) == GENERAL_REGS)"
16079 + [(set_attr "type" "call")
16080 + (set_attr "length" "2")]
16085 + [(set (match_operand 0 "register_operand" "r")
16086 + (match_operand 1 "immediate_operand" "i"))
16088 + "(USE_RETURN_INSN (FALSE) && (REGNO(operands[0]) == RETVAL_REGNUM) &&
16089 + ((INTVAL(operands[1]) == -1) || (INTVAL(operands[1]) == 0) || (INTVAL(operands[1]) == 1)))"
16091 + avr32_output_return_instruction (TRUE, FALSE, NULL, operands[1]);
16094 + [(set_attr "type" "call")
16095 + (set_attr "length" "4")]
16099 + [(set (match_operand 0 "register_operand" "r")
16100 + (match_operand 1 "immediate_operand" "i"))
16101 + (unspec_volatile [(return)] VUNSPEC_EPILOGUE)]
16102 + "(REGNO(operands[0]) == RETVAL_REGNUM) &&
16103 + ((INTVAL(operands[1]) == -1) || (INTVAL(operands[1]) == 0) || (INTVAL(operands[1]) == 1))"
16105 + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[1]);
16108 + ; Length is absolute worst case
16109 + [(set_attr "type" "branch")
16110 + (set_attr "length" "12")]
16114 + [(set (match_operand 0 "register_operand" "=r")
16115 + (if_then_else (match_operator 1 "avr32_comparison_operator"
16116 + [(match_operand 4 "register_operand" "r")
16117 + (match_operand 5 "register_immediate_operand" "rKs21")])
16118 + (match_operand 2 "avr32_cond_register_immediate_operand" "rKs08")
16119 + (match_operand 3 "avr32_cond_register_immediate_operand" "rKs08")))
16121 + "USE_RETURN_INSN (TRUE) && (REGNO(operands[0]) == RETVAL_REGNUM)"
16123 + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]);
16125 + if ( GET_CODE(operands[2]) == REG
16126 + && GET_CODE(operands[3]) == REG
16127 + && REGNO(operands[2]) != LR_REGNUM
16128 + && REGNO(operands[3]) != LR_REGNUM ){
16129 + return "ret%1 %2\;ret%i1 %3";
16130 + } else if ( GET_CODE(operands[2]) == REG
16131 + && GET_CODE(operands[3]) == CONST_INT ){
16132 + if ( INTVAL(operands[3]) == -1
16133 + || INTVAL(operands[3]) == 0
16134 + || INTVAL(operands[3]) == 1 ){
16135 + return "ret%1 %2\;ret%i1 %d3";
16137 + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12";
16139 + } else if ( GET_CODE(operands[2]) == CONST_INT
16140 + && GET_CODE(operands[3]) == REG ){
16141 + if ( INTVAL(operands[2]) == -1
16142 + || INTVAL(operands[2]) == 0
16143 + || INTVAL(operands[2]) == 1 ){
16144 + return "ret%1 %d2\;ret%i1 %3";
16146 + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12";
16149 + if ( (INTVAL(operands[2]) == -1
16150 + || INTVAL(operands[2]) == 0
16151 + || INTVAL(operands[2]) == 1 )
16152 + && (INTVAL(operands[3]) == -1
16153 + || INTVAL(operands[3]) == 0
16154 + || INTVAL(operands[3]) == 1 )){
16155 + return "ret%1 %d2\;ret%i1 %d3";
16157 + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12";
16162 + [(set_attr "length" "10")
16163 + (set_attr "cc" "none")
16164 + (set_attr "type" "call")])
16168 +;;=================================================================
16170 +;;=================================================================
16173 + [(set (match_operand:HI 0 "register_operand" "")
16174 + (neg:HI (match_operand:HI 1 "register_operand" "")))
16175 + (set (match_operand:SI 2 "register_operand" "")
16177 + (sign_extend:SI (match_dup 0))
16178 + (sign_extend:SI (match_operand:HI 3 "register_operand" ""))))]
16179 + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[2]) == REGNO(operands[0]))"
16180 + [ (set (match_dup 2)
16182 + (sign_extend:SI (neg:HI (match_dup 1)))
16183 + (sign_extend:SI (match_dup 3))))]
16188 + [(set (match_operand:HI 0 "register_operand" "")
16189 + (neg:HI (match_operand:HI 1 "register_operand" "")))
16190 + (set (match_operand:SI 2 "register_operand" "")
16192 + (sign_extend:SI (match_operand:HI 3 "register_operand" ""))
16193 + (sign_extend:SI (match_dup 0))))]
16194 + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[2]) == REGNO(operands[0]))"
16195 + [ (set (match_dup 2)
16197 + (sign_extend:SI (neg:HI (match_dup 1)))
16198 + (sign_extend:SI (match_dup 3))))]
16204 +;;=================================================================
16205 +;; Vector set and extract operations
16206 +;;=================================================================
16207 +(define_insn "vec_setv2hi_hi"
16208 + [(set (match_operand:V2HI 0 "register_operand" "=r")
16211 + (vec_duplicate:V2HI
16212 + (match_operand:HI 1 "register_operand" "r"))
16215 + "bfins\t%0, %1, 16, 16"
16216 + [(set_attr "type" "alu")
16217 + (set_attr "length" "4")
16218 + (set_attr "cc" "clobber")])
16220 +(define_insn "vec_setv2hi_lo"
16221 + [(set (match_operand:V2HI 0 "register_operand" "+r")
16224 + (vec_duplicate:V2HI
16225 + (match_operand:HI 1 "register_operand" "r"))
16228 + "bfins\t%0, %1, 0, 16"
16229 + [(set_attr "type" "alu")
16230 + (set_attr "length" "4")
16231 + (set_attr "cc" "clobber")])
16233 +(define_expand "vec_setv2hi"
16234 + [(set (match_operand:V2HI 0 "register_operand" "")
16237 + (vec_duplicate:V2HI
16238 + (match_operand:HI 1 "register_operand" ""))
16239 + (match_operand 2 "immediate_operand" "")))]
16241 + { operands[2] = GEN_INT(INTVAL(operands[2]) + 1); }
16244 +(define_insn "vec_extractv2hi"
16245 + [(set (match_operand:HI 0 "register_operand" "=r")
16247 + (match_operand:V2HI 1 "register_operand" "r")
16248 + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
16251 + if ( INTVAL(operands[2]) == 0 )
16252 + return "bfextu\t%0, %1, 16, 16";
16254 + return "bfextu\t%0, %1, 0, 16";
16256 + [(set_attr "type" "alu")
16257 + (set_attr "length" "4")
16258 + (set_attr "cc" "clobber")])
16260 +(define_insn "vec_extractv4qi"
16261 + [(set (match_operand:QI 0 "register_operand" "=r")
16263 + (match_operand:V4QI 1 "register_operand" "r")
16264 + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))]
16267 + switch ( INTVAL(operands[2]) ){
16269 + return "bfextu\t%0, %1, 24, 8";
16271 + return "bfextu\t%0, %1, 16, 8";
16273 + return "bfextu\t%0, %1, 8, 8";
16275 + return "bfextu\t%0, %1, 0, 8";
16280 + [(set_attr "type" "alu")
16281 + (set_attr "length" "4")
16282 + (set_attr "cc" "clobber")])
16285 +(define_insn "concatv2hi"
16286 + [(set (match_operand:V2HI 0 "register_operand" "=r, r, r")
16288 + (match_operand:HI 1 "register_operand" "r, r, 0")
16289 + (match_operand:HI 2 "register_operand" "r, 0, r")))]
16292 + mov\t%0, %1\;bfins\t%0, %2, 0, 16
16293 + bfins\t%0, %2, 0, 16
16294 + bfins\t%0, %1, 16, 16"
16295 + [(set_attr "length" "6, 4, 4")
16296 + (set_attr "type" "alu")])
16299 +;; Load the atomic operation description
16300 +(include "sync.md")
16302 +;; Load the SIMD description
16303 +(include "simd.md")
16305 +;; Load the FP coprAocessor patterns
16306 +(include "fpcp.md")
16308 +++ b/gcc/config/avr32/avr32-modes.def
16310 +VECTOR_MODES (INT, 4); /* V4QI V2HI */
16312 +++ b/gcc/config/avr32/avr32.opt
16314 +; Options for the ATMEL AVR32 port of the compiler.
16316 +; Copyright 2007 Atmel Corporation.
16318 +; This file is part of GCC.
16320 +; GCC is free software; you can redistribute it and/or modify it under
16321 +; the terms of the GNU General Public License as published by the Free
16322 +; Software Foundation; either version 2, or (at your option) any later
16325 +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16326 +; WARRANTY; without even the implied warranty of MERCHANTABILITY or
16327 +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16328 +; for more details.
16330 +; You should have received a copy of the GNU General Public License
16331 +; along with GCC; see the file COPYING. If not, write to the Free
16332 +; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
16333 +; 02110-1301, USA.
16335 +muse-rodata-section
16336 +Target Report Mask(USE_RODATA_SECTION)
16337 +Use section .rodata for read-only data instead of .text.
16340 +Target Report Undocumented Mask(HARD_FLOAT)
16341 +Use floating point coprocessor instructions.
16344 +Target Report Undocumented InverseMask(HARD_FLOAT, SOFT_FLOAT)
16345 +Use software floating-point library for floating-point operations.
16347 +mforce-double-align
16348 +Target Report RejectNegative Mask(FORCE_DOUBLE_ALIGN)
16349 +Force double-word alignment for double-word memory accesses.
16352 +Target Report RejectNegative Mask(NO_INIT_GOT)
16353 +Do not initialize GOT register before using it when compiling PIC code.
16356 +Target Report Mask(RELAX)
16357 +Let invoked assembler and linker do relaxing (Enabled by default when optimization level is >1).
16360 +Target Report Undocumented Mask(MD_REORG_OPTIMIZATION)
16361 +Perform machine dependent optimizations in reorg stage.
16364 +Target Report Mask(HAS_ASM_ADDR_PSEUDOS)
16365 +Use assembler pseudo-instructions lda.w and call for handling direct addresses. (Enabled by default)
16368 +Target Report RejectNegative Joined Var(avr32_part_name)
16369 +Specify the AVR32 part name
16372 +Target Report RejectNegative Joined Undocumented Var(avr32_part_name)
16373 +Specify the AVR32 part name (deprecated)
16376 +Target Report RejectNegative Joined Var(avr32_arch_name)
16377 +Specify the AVR32 architecture name
16380 +Target Report Mask(FAST_FLOAT)
16381 +Enable fast floating-point library. Enabled by default if the -funsafe-math-optimizations switch is specified.
16383 +mimm-in-const-pool
16384 +Target Report Var(avr32_imm_in_const_pool) Init(-1)
16385 +Put large immediates in constant pool. This is enabled by default for archs with insn-cache.
16388 +Target Report RejectNegative Mask(NO_PIC)
16389 +Do not generate position-independent code. (deprecated, use -fno-pic instead)
16391 +mcond-exec-before-reload
16392 +Target Report Undocumented Mask(COND_EXEC_BEFORE_RELOAD)
16393 +Enable experimental conditional execution preparation before the reload stage.
16395 +mrmw-addressable-data
16396 +Target Report Mask(RMW_ADDRESSABLE_DATA)
16397 +Signal that all data is in range for the Atomic Read-Modify-Write memory instructions, and that
16398 +gcc can safely generate these whenever possible.
16401 +++ b/gcc/config/avr32/avr32-protos.h
16404 + Prototypes for exported functions defined in avr32.c
16405 + Copyright 2003-2006 Atmel Corporation.
16407 + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
16408 + Initial porting by Anders �dland.
16410 + This file is part of GCC.
16412 + This program is free software; you can redistribute it and/or modify
16413 + it under the terms of the GNU General Public License as published by
16414 + the Free Software Foundation; either version 2 of the License, or
16415 + (at your option) any later version.
16417 + This program is distributed in the hope that it will be useful,
16418 + but WITHOUT ANY WARRANTY; without even the implied warranty of
16419 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16420 + GNU General Public License for more details.
16422 + You should have received a copy of the GNU General Public License
16423 + along with this program; if not, write to the Free Software
16424 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
16427 +#ifndef AVR32_PROTOS_H
16428 +#define AVR32_PROTOS_H
16430 +extern const int swap_reg[];
16432 +extern int avr32_valid_macmac_bypass (rtx, rtx);
16433 +extern int avr32_valid_mulmac_bypass (rtx, rtx);
16435 +extern int avr32_decode_lcomm_symbol_offset (rtx, int *);
16436 +extern void avr32_encode_lcomm_symbol_offset (tree, char *, int);
16438 +extern const char *avr32_strip_name_encoding (const char *);
16440 +extern rtx avr32_get_note_reg_equiv (rtx insn);
16442 +extern int avr32_use_return_insn (int iscond);
16444 +extern void avr32_make_reglist16 (int reglist16_vect, char *reglist16_string);
16446 +extern void avr32_make_reglist8 (int reglist8_vect, char *reglist8_string);
16447 +extern void avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string);
16448 +extern void avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string);
16450 +extern void avr32_output_return_instruction (int single_ret_inst,
16451 + int iscond, rtx cond,
16453 +extern void avr32_expand_prologue (void);
16454 +extern void avr32_set_return_address (rtx source, rtx scratch);
16456 +extern int avr32_hard_regno_mode_ok (int regno, enum machine_mode mode);
16457 +extern int avr32_extra_constraint_s (rtx value, const int strict);
16458 +extern int avr32_eh_return_data_regno (const int n);
16459 +extern int avr32_initial_elimination_offset (const int from, const int to);
16460 +extern rtx avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode,
16461 + tree type, int named);
16462 +extern void avr32_init_cumulative_args (CUMULATIVE_ARGS * cum, tree fntype,
16463 + rtx libname, tree fndecl);
16464 +extern void avr32_function_arg_advance (CUMULATIVE_ARGS * cum,
16465 + enum machine_mode mode,
16466 + tree type, int named);
16467 +#ifdef ARGS_SIZE_RTX
16468 +/* expr.h defines ARGS_SIZE_RTX and `enum direction'. */
16469 +extern enum direction avr32_function_arg_padding (enum machine_mode mode,
16471 +#endif /* ARGS_SIZE_RTX */
16472 +extern rtx avr32_function_value (tree valtype, tree func, bool outgoing);
16473 +extern rtx avr32_libcall_value (enum machine_mode mode);
16474 +extern int avr32_sched_use_dfa_pipeline_interface (void);
16475 +extern bool avr32_return_in_memory (tree type, tree fntype);
16476 +extern void avr32_regs_to_save (char *operand);
16477 +extern void avr32_target_asm_function_prologue (FILE * file,
16478 + HOST_WIDE_INT size);
16479 +extern void avr32_target_asm_function_epilogue (FILE * file,
16480 + HOST_WIDE_INT size);
16481 +extern void avr32_trampoline_template (FILE * file);
16482 +extern void avr32_initialize_trampoline (rtx addr, rtx fnaddr,
16483 + rtx static_chain);
16484 +extern int avr32_legitimate_address (enum machine_mode mode, rtx x,
16486 +extern int avr32_legitimate_constant_p (rtx x);
16488 +extern int avr32_legitimate_pic_operand_p (rtx x);
16490 +extern rtx avr32_find_symbol (rtx x);
16491 +extern void avr32_select_section (rtx exp, int reloc, int align);
16492 +extern void avr32_encode_section_info (tree decl, rtx rtl, int first);
16493 +extern void avr32_asm_file_end (FILE * stream);
16494 +extern void avr32_asm_output_ascii (FILE * stream, char *ptr, int len);
16495 +extern void avr32_asm_output_common (FILE * stream, const char *name,
16496 + int size, int rounded);
16497 +extern void avr32_asm_output_label (FILE * stream, const char *name);
16498 +extern void avr32_asm_declare_object_name (FILE * stream, char *name,
16500 +extern void avr32_asm_globalize_label (FILE * stream, const char *name);
16501 +extern void avr32_asm_weaken_label (FILE * stream, const char *name);
16502 +extern void avr32_asm_output_external (FILE * stream, tree decl,
16503 + const char *name);
16504 +extern void avr32_asm_output_external_libcall (FILE * stream, rtx symref);
16505 +extern void avr32_asm_output_labelref (FILE * stream, const char *name);
16506 +extern void avr32_notice_update_cc (rtx exp, rtx insn);
16507 +extern void avr32_print_operand (FILE * stream, rtx x, int code);
16508 +extern void avr32_print_operand_address (FILE * stream, rtx x);
16510 +extern int avr32_symbol (rtx x);
16512 +extern void avr32_select_rtx_section (enum machine_mode mode, rtx x,
16513 + unsigned HOST_WIDE_INT align);
16515 +extern int avr32_load_multiple_operation (rtx op, enum machine_mode mode);
16516 +extern int avr32_store_multiple_operation (rtx op, enum machine_mode mode);
16518 +extern int avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c,
16519 + const char *str);
16521 +extern bool avr32_cannot_force_const_mem (rtx x);
16523 +extern void avr32_init_builtins (void);
16525 +extern rtx avr32_expand_builtin (tree exp, rtx target, rtx subtarget,
16526 + enum machine_mode mode, int ignore);
16528 +extern bool avr32_must_pass_in_stack (enum machine_mode mode, tree type);
16530 +extern bool avr32_strict_argument_naming (CUMULATIVE_ARGS * ca);
16532 +extern bool avr32_pass_by_reference (CUMULATIVE_ARGS * cum,
16533 + enum machine_mode mode,
16534 + tree type, bool named);
16536 +extern rtx avr32_gen_load_multiple (rtx * regs, int count, rtx from,
16537 + int write_back, int in_struct_p,
16539 +extern rtx avr32_gen_store_multiple (rtx * regs, int count, rtx to,
16540 + int in_struct_p, int scalar_p);
16541 +extern int avr32_gen_movmemsi (rtx * operands);
16543 +extern int avr32_rnd_operands (rtx add, rtx shift);
16544 +extern int avr32_adjust_insn_length (rtx insn, int length);
16546 +extern int symbol_mentioned_p (rtx x);
16547 +extern int label_mentioned_p (rtx x);
16548 +extern rtx legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg);
16549 +extern int avr32_address_register_rtx_p (rtx x, int strict_p);
16550 +extern int avr32_legitimate_index_p (enum machine_mode mode, rtx index,
16553 +extern int avr32_const_double_immediate (rtx value);
16554 +extern void avr32_init_expanders (void);
16555 +extern rtx avr32_return_addr (int count, rtx frame);
16556 +extern bool avr32_got_mentioned_p (rtx addr);
16558 +extern void avr32_final_prescan_insn (rtx insn, rtx * opvec, int noperands);
16560 +extern int avr32_expand_movcc (enum machine_mode mode, rtx operands[]);
16561 +extern int avr32_expand_addcc (enum machine_mode mode, rtx operands[]);
16563 +extern int avr32_expand_scc (RTX_CODE cond, rtx * operands);
16566 +extern int avr32_store_bypass (rtx insn_out, rtx insn_in);
16567 +extern int avr32_mul_waw_bypass (rtx insn_out, rtx insn_in);
16568 +extern int avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in);
16569 +extern int avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in);
16570 +extern rtx avr32_output_cmp (rtx cond, enum machine_mode mode,
16571 + rtx op0, rtx op1);
16573 +rtx get_next_insn_cond (rtx cur_insn);
16574 +int set_next_insn_cond (rtx cur_insn, rtx cond);
16575 +void avr32_override_options (void);
16576 +void avr32_load_pic_register (void);
16577 +#ifdef GCC_BASIC_BLOCK_H
16578 +rtx avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, rtx pattern, rtx insn,
16579 + int *num_true_changes);
16580 +rtx avr32_ifcvt_modify_test (ce_if_block_t *ce_info, rtx test );
16581 +void avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, int *num_true_changes);
16583 +void avr32_optimization_options (int level, int size);
16584 +int avr32_const_ok_for_move (HOST_WIDE_INT c);
16586 +void avr32_split_const_expr (enum machine_mode mode,
16587 + enum machine_mode new_mode,
16589 + rtx *split_expr);
16590 +void avr32_get_intval (enum machine_mode mode,
16592 + HOST_WIDE_INT *val);
16594 +int avr32_cond_imm_clobber_splittable (rtx insn,
16598 +#endif /* AVR32_PROTOS_H */
16600 +++ b/gcc/config/avr32/crti.asm
16603 + Init/fini stuff for AVR32.
16604 + Copyright 2003-2006 Atmel Corporation.
16606 + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
16608 + This file is part of GCC.
16610 + This program is free software; you can redistribute it and/or modify
16611 + it under the terms of the GNU General Public License as published by
16612 + the Free Software Foundation; either version 2 of the License, or
16613 + (at your option) any later version.
16615 + This program is distributed in the hope that it will be useful,
16616 + but WITHOUT ANY WARRANTY; without even the implied warranty of
16617 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16618 + GNU General Public License for more details.
16620 + You should have received a copy of the GNU General Public License
16621 + along with this program; if not, write to the Free Software
16622 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
16625 +/* The code in sections .init and .fini is supposed to be a single
16626 + regular function. The function in .init is called directly from
16627 + start in crt1.asm. The function in .fini is atexit()ed in crt1.asm
16630 + crti.asm contributes the prologue of a function to these sections,
16631 + and crtn.asm comes up the epilogue. STARTFILE_SPEC should list
16632 + crti.o before any other object files that might add code to .init
16633 + or .fini sections, and ENDFILE_SPEC should list crtn.o after any
16634 + such object files. */
16639 +/* Just load the GOT */
16649 +1: .long 0b - _GLOBAL_OFFSET_TABLE_
16653 +/* Just load the GOT */
16663 +1: .long 0b - _GLOBAL_OFFSET_TABLE_
16667 +++ b/gcc/config/avr32/crtn.asm
16669 +/* Copyright (C) 2001 Free Software Foundation, Inc.
16670 + Written By Nick Clifton
16672 + This file is free software; you can redistribute it and/or modify it
16673 + under the terms of the GNU General Public License as published by the
16674 + Free Software Foundation; either version 2, or (at your option) any
16677 + In addition to the permissions in the GNU General Public License, the
16678 + Free Software Foundation gives you unlimited permission to link the
16679 + compiled version of this file with other programs, and to distribute
16680 + those programs without any restriction coming from the use of this
16681 + file. (The General Public License restrictions do apply in other
16682 + respects; for example, they cover modification of the file, and
16683 + distribution when not linked into another program.)
16685 + This file is distributed in the hope that it will be useful, but
16686 + WITHOUT ANY WARRANTY; without even the implied warranty of
16687 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16688 + General Public License for more details.
16690 + You should have received a copy of the GNU General Public License
16691 + along with this program; see the file COPYING. If not, write to
16692 + the Free Software Foundation, 59 Temple Place - Suite 330,
16693 + Boston, MA 02111-1307, USA.
16695 + As a special exception, if you link this library with files
16696 + compiled with GCC to produce an executable, this does not cause
16697 + the resulting executable to be covered by the GNU General Public License.
16698 + This exception does not however invalidate any other reasons why
16699 + the executable file might be covered by the GNU General Public License.
16714 +++ b/gcc/config/avr32/fpcp.md
16716 +;; AVR32 machine description file for Floating-Point instructions.
16717 +;; Copyright 2003-2006 Atmel Corporation.
16719 +;; Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
16721 +;; This file is part of GCC.
16723 +;; This program is free software; you can redistribute it and/or modify
16724 +;; it under the terms of the GNU General Public License as published by
16725 +;; the Free Software Foundation; either version 2 of the License, or
16726 +;; (at your option) any later version.
16728 +;; This program is distributed in the hope that it will be useful,
16729 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16730 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16731 +;; GNU General Public License for more details.
16733 +;; You should have received a copy of the GNU General Public License
16734 +;; along with this program; if not, write to the Free Software
16735 +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16737 +;; -*- Mode: Scheme -*-
16739 +;;******************************************************************************
16740 +;; Automaton pipeline description for floating-point coprocessor insns
16741 +;;******************************************************************************
16742 +(define_cpu_unit "fid,fm1,fm2,fm3,fm4,fwb,fcmp,fcast" "avr32_ap")
16744 +(define_insn_reservation "fmv_op" 1
16745 + (and (eq_attr "pipeline" "ap")
16746 + (eq_attr "type" "fmv"))
16747 + "is,da,d,fid,fwb")
16749 +(define_insn_reservation "fmul_op" 5
16750 + (and (eq_attr "pipeline" "ap")
16751 + (eq_attr "type" "fmul"))
16752 + "is,da,d,fid,fm1,fm2,fm3,fm4,fwb")
16754 +(define_insn_reservation "fcmps_op" 1
16755 + (and (eq_attr "pipeline" "ap")
16756 + (eq_attr "type" "fcmps"))
16757 + "is,da,d,fid,fcmp")
16759 +(define_insn_reservation "fcmpd_op" 2
16760 + (and (eq_attr "pipeline" "ap")
16761 + (eq_attr "type" "fcmpd"))
16762 + "is,da,d,fid*2,fcmp")
16764 +(define_insn_reservation "fcast_op" 3
16765 + (and (eq_attr "pipeline" "ap")
16766 + (eq_attr "type" "fcast"))
16767 + "is,da,d,fid,fcmp,fcast,fwb")
16769 +(define_insn_reservation "fmvcpu_op" 2
16770 + (and (eq_attr "pipeline" "ap")
16771 + (eq_attr "type" "fmvcpu"))
16774 +(define_insn_reservation "fldd_op" 1
16775 + (and (eq_attr "pipeline" "ap")
16776 + (eq_attr "type" "fldd"))
16779 +(define_insn_reservation "flds_op" 1
16780 + (and (eq_attr "pipeline" "ap")
16781 + (eq_attr "type" "flds"))
16784 +(define_insn_reservation "fsts_op" 0
16785 + (and (eq_attr "pipeline" "ap")
16786 + (eq_attr "type" "fsts"))
16789 +(define_insn_reservation "fstd_op" 0
16790 + (and (eq_attr "pipeline" "ap")
16791 + (eq_attr "type" "fstd"))
16795 +(define_insn "*movsf_fpcp"
16796 + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,f,m,r,r,r,m")
16797 + (match_operand:SF 1 "general_operand" " f,r,f,m,f,r,G,m,r"))]
16798 + "TARGET_HARD_FLOAT"
16809 + [(set_attr "length" "4,4,4,4,4,2,4,4,4")
16810 + (set_attr "type" "fmv,flds,fmvcpu,flds,fsts,alu,alu,load,store")])
16812 +(define_insn_and_split "*movdf_fpcp"
16813 + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,f,m,r,r,m")
16814 + (match_operand:DF 1 "general_operand" " f,r,f,m,f,r,m,r"))]
16815 + "TARGET_HARD_FLOAT"
16822 + mov\t%0, %1\;mov\t%m0, %m1
16826 + "TARGET_HARD_FLOAT
16827 + && reload_completed
16828 + && (REG_P(operands[0]) && (REGNO_REG_CLASS(REGNO(operands[0])) == GENERAL_REGS))
16829 + && (REG_P(operands[1]) && (REGNO_REG_CLASS(REGNO(operands[1])) == GENERAL_REGS))"
16830 + [(set (match_dup 0) (match_dup 1))
16831 + (set (match_dup 2) (match_dup 3))]
16834 + operands[2] = gen_highpart (SImode, operands[0]);
16835 + operands[0] = gen_lowpart (SImode, operands[0]);
16836 + operands[3] = gen_highpart(SImode, operands[1]);
16837 + operands[1] = gen_lowpart(SImode, operands[1]);
16841 + [(set_attr "length" "4,4,4,4,4,4,4,4")
16842 + (set_attr "type" "fmv,fldd,fmvcpu,fldd,fstd,alu2,load2,store2")])
16845 +(define_insn "mulsf3"
16846 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16847 + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16848 + (match_operand:SF 2 "avr32_fp_register_operand" "f")))]
16849 + "TARGET_HARD_FLOAT"
16850 + "fmul.s\t%0, %1, %2"
16851 + [(set_attr "length" "4")
16852 + (set_attr "type" "fmul")])
16854 +(define_insn "nmulsf3"
16855 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16856 + (neg:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16857 + (match_operand:SF 2 "avr32_fp_register_operand" "f"))))]
16858 + "TARGET_HARD_FLOAT"
16859 + "fnmul.s\t%0, %1, %2"
16860 + [(set_attr "length" "4")
16861 + (set_attr "type" "fmul")])
16864 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "")
16865 + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "")
16866 + (match_operand:SF 2 "avr32_fp_register_operand" "")))
16867 + (set (match_operand:SF 3 "avr32_fp_register_operand" "")
16868 + (neg:SF (match_dup 0)))]
16869 + "TARGET_HARD_FLOAT &&
16870 + (peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[3]) == REGNO(operands[0])))"
16871 + [(set (match_dup 3)
16872 + (neg:SF (mult:SF (match_dup 1)
16873 + (match_dup 2))))]
16877 +(define_insn "macsf3"
16878 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16879 + (plus:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16880 + (match_operand:SF 2 "avr32_fp_register_operand" "f"))
16881 + (match_operand:SF 3 "avr32_fp_register_operand" "0")))]
16882 + "TARGET_HARD_FLOAT"
16883 + "fmac.s\t%0, %1, %2"
16884 + [(set_attr "length" "4")
16885 + (set_attr "type" "fmul")])
16887 +(define_insn "nmacsf3"
16888 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16889 + (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16890 + (match_operand:SF 2 "avr32_fp_register_operand" "f")))
16891 + (match_operand:SF 3 "avr32_fp_register_operand" "0")))]
16892 + "TARGET_HARD_FLOAT"
16893 + "fnmac.s\t%0, %1, %2"
16894 + [(set_attr "length" "4")
16895 + (set_attr "type" "fmul")])
16898 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "")
16899 + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "")
16900 + (match_operand:SF 2 "avr32_fp_register_operand" "")))
16901 + (set (match_operand:SF 3 "avr32_fp_register_operand" "")
16905 + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])"
16906 + [(set (match_dup 3)
16907 + (plus:SF (neg:SF (mult:SF (match_dup 1)
16913 +(define_insn "msubacsf3"
16914 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16915 + (minus:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16916 + (match_operand:SF 2 "avr32_fp_register_operand" "f"))
16917 + (match_operand:SF 3 "avr32_fp_register_operand" "0")))]
16918 + "TARGET_HARD_FLOAT"
16919 + "fmsc.s\t%0, %1, %2"
16920 + [(set_attr "length" "4")
16921 + (set_attr "type" "fmul")])
16924 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "")
16925 + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "")
16926 + (match_operand:SF 2 "avr32_fp_register_operand" "")))
16927 + (set (match_operand:SF 3 "avr32_fp_register_operand" "")
16931 + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])"
16932 + [(set (match_dup 3)
16933 + (minus:SF (mult:SF (match_dup 1)
16938 +(define_insn "nmsubacsf3"
16939 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16940 + (minus:SF (neg:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16941 + (match_operand:SF 2 "avr32_fp_register_operand" "f")))
16942 + (match_operand:SF 3 "avr32_fp_register_operand" "0")))]
16943 + "TARGET_HARD_FLOAT"
16944 + "fnmsc.s\t%0, %1, %2"
16945 + [(set_attr "length" "4")
16946 + (set_attr "type" "fmul")])
16950 +(define_insn "addsf3"
16951 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16952 + (plus:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16953 + (match_operand:SF 2 "avr32_fp_register_operand" "f")))]
16954 + "TARGET_HARD_FLOAT"
16955 + "fadd.s\t%0, %1, %2"
16956 + [(set_attr "length" "4")
16957 + (set_attr "type" "fmul")])
16959 +(define_insn "subsf3"
16960 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16961 + (minus:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")
16962 + (match_operand:SF 2 "avr32_fp_register_operand" "f")))]
16963 + "TARGET_HARD_FLOAT"
16964 + "fsub.s\t%0, %1, %2"
16965 + [(set_attr "length" "4")
16966 + (set_attr "type" "fmul")])
16969 +(define_insn "negsf2"
16970 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16971 + (neg:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")))]
16972 + "TARGET_HARD_FLOAT"
16974 + [(set_attr "length" "4")
16975 + (set_attr "type" "fmv")])
16977 +(define_insn "abssf2"
16978 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16979 + (abs:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")))]
16980 + "TARGET_HARD_FLOAT"
16982 + [(set_attr "length" "4")
16983 + (set_attr "type" "fmv")])
16985 +(define_insn "truncdfsf2"
16986 + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f")
16987 + (float_truncate:SF
16988 + (match_operand:DF 1 "avr32_fp_register_operand" "f")))]
16989 + "TARGET_HARD_FLOAT"
16990 + "fcastd.s\t%0, %1"
16991 + [(set_attr "length" "4")
16992 + (set_attr "type" "fcast")])
16994 +(define_insn "extendsfdf2"
16995 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
16997 + (match_operand:SF 1 "avr32_fp_register_operand" "f")))]
16998 + "TARGET_HARD_FLOAT"
16999 + "fcasts.d\t%0, %1"
17000 + [(set_attr "length" "4")
17001 + (set_attr "type" "fcast")])
17003 +(define_insn "muldf3"
17004 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17005 + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17006 + (match_operand:DF 2 "avr32_fp_register_operand" "f")))]
17007 + "TARGET_HARD_FLOAT"
17008 + "fmul.d\t%0, %1, %2"
17009 + [(set_attr "length" "4")
17010 + (set_attr "type" "fmul")])
17012 +(define_insn "nmuldf3"
17013 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17014 + (neg:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17015 + (match_operand:DF 2 "avr32_fp_register_operand" "f"))))]
17016 + "TARGET_HARD_FLOAT"
17017 + "fnmul.d\t%0, %1, %2"
17018 + [(set_attr "length" "4")
17019 + (set_attr "type" "fmul")])
17022 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "")
17023 + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "")
17024 + (match_operand:DF 2 "avr32_fp_register_operand" "")))
17025 + (set (match_operand:DF 3 "avr32_fp_register_operand" "")
17026 + (neg:DF (match_dup 0)))]
17027 + "TARGET_HARD_FLOAT &&
17028 + (peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[3]) == REGNO(operands[0])))"
17029 + [(set (match_dup 3)
17030 + (neg:DF (mult:DF (match_dup 1)
17031 + (match_dup 2))))]
17034 +(define_insn "macdf3"
17035 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17036 + (plus:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17037 + (match_operand:DF 2 "avr32_fp_register_operand" "f"))
17038 + (match_operand:DF 3 "avr32_fp_register_operand" "0")))]
17039 + "TARGET_HARD_FLOAT"
17040 + "fmac.d\t%0, %1, %2"
17041 + [(set_attr "length" "4")
17042 + (set_attr "type" "fmul")])
17044 +(define_insn "msubacdf3"
17045 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17046 + (minus:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17047 + (match_operand:DF 2 "avr32_fp_register_operand" "f"))
17048 + (match_operand:DF 3 "avr32_fp_register_operand" "0")))]
17049 + "TARGET_HARD_FLOAT"
17050 + "fmsc.d\t%0, %1, %2"
17051 + [(set_attr "length" "4")
17052 + (set_attr "type" "fmul")])
17055 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "")
17056 + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "")
17057 + (match_operand:DF 2 "avr32_fp_register_operand" "")))
17058 + (set (match_operand:DF 3 "avr32_fp_register_operand" "")
17062 + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])"
17063 + [(set (match_dup 3)
17064 + (minus:DF (mult:DF (match_dup 1)
17069 +(define_insn "nmsubacdf3"
17070 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17071 + (minus:DF (neg:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17072 + (match_operand:DF 2 "avr32_fp_register_operand" "f")))
17073 + (match_operand:DF 3 "avr32_fp_register_operand" "0")))]
17074 + "TARGET_HARD_FLOAT"
17075 + "fnmsc.d\t%0, %1, %2"
17076 + [(set_attr "length" "4")
17077 + (set_attr "type" "fmul")])
17079 +(define_insn "nmacdf3"
17080 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17081 + (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17082 + (match_operand:DF 2 "avr32_fp_register_operand" "f")))
17083 + (match_operand:DF 3 "avr32_fp_register_operand" "0")))]
17084 + "TARGET_HARD_FLOAT"
17085 + "fnmac.d\t%0, %1, %2"
17086 + [(set_attr "length" "4")
17087 + (set_attr "type" "fmul")])
17090 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "")
17091 + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "")
17092 + (match_operand:DF 2 "avr32_fp_register_operand" "")))
17093 + (set (match_operand:DF 3 "avr32_fp_register_operand" "")
17097 + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])"
17098 + [(set (match_dup 3)
17099 + (plus:DF (neg:DF (mult:DF (match_dup 1)
17104 +(define_insn "adddf3"
17105 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17106 + (plus:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17107 + (match_operand:DF 2 "avr32_fp_register_operand" "f")))]
17108 + "TARGET_HARD_FLOAT"
17109 + "fadd.d\t%0, %1, %2"
17110 + [(set_attr "length" "4")
17111 + (set_attr "type" "fmul")])
17113 +(define_insn "subdf3"
17114 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17115 + (minus:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")
17116 + (match_operand:DF 2 "avr32_fp_register_operand" "f")))]
17117 + "TARGET_HARD_FLOAT"
17118 + "fsub.d\t%0, %1, %2"
17119 + [(set_attr "length" "4")
17120 + (set_attr "type" "fmul")])
17122 +(define_insn "negdf2"
17123 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17124 + (neg:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")))]
17125 + "TARGET_HARD_FLOAT"
17127 + [(set_attr "length" "4")
17128 + (set_attr "type" "fmv")])
17130 +(define_insn "absdf2"
17131 + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f")
17132 + (abs:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")))]
17133 + "TARGET_HARD_FLOAT"
17135 + [(set_attr "length" "4")
17136 + (set_attr "type" "fmv")])
17139 +(define_expand "cmpdf"
17142 + (match_operand:DF 0 "general_operand" "")
17143 + (match_operand:DF 1 "general_operand" "")))]
17144 + "TARGET_HARD_FLOAT"
17147 + if ( !REG_P(operands[0]) )
17148 + operands[0] = force_reg(DFmode, operands[0]);
17150 + if ( !REG_P(operands[1]) )
17151 + operands[1] = force_reg(DFmode, operands[1]);
17153 + avr32_compare_op0 = operands[0];
17154 + avr32_compare_op1 = operands[1];
17156 + emit_insn(gen_cmpdf_internal(operands[0], operands[1]));
17158 + tmpreg = gen_reg_rtx(SImode);
17159 + emit_insn(gen_fpcc_to_reg(tmpreg));
17160 + emit_insn(gen_reg_to_cc(tmpreg));
17166 +(define_insn "cmpdf_internal"
17167 + [(set (reg:CC FPCC_REGNUM)
17169 + (match_operand:DF 0 "avr32_fp_register_operand" "f")
17170 + (match_operand:DF 1 "avr32_fp_register_operand" "f")))]
17171 + "TARGET_HARD_FLOAT"
17173 + if (!rtx_equal_p(cc_prev_status.mdep.fpvalue, SET_SRC(PATTERN (insn))) )
17174 + return "fcmp.d\t%0, %1";
17177 + [(set_attr "length" "4")
17178 + (set_attr "type" "fcmpd")
17179 + (set_attr "cc" "fpcompare")])
17181 +(define_expand "cmpsf"
17184 + (match_operand:SF 0 "general_operand" "")
17185 + (match_operand:SF 1 "general_operand" "")))]
17186 + "TARGET_HARD_FLOAT"
17189 + if ( !REG_P(operands[0]) )
17190 + operands[0] = force_reg(SFmode, operands[0]);
17192 + if ( !REG_P(operands[1]) )
17193 + operands[1] = force_reg(SFmode, operands[1]);
17195 + avr32_compare_op0 = operands[0];
17196 + avr32_compare_op1 = operands[1];
17198 + emit_insn(gen_cmpsf_internal(operands[0], operands[1]));
17200 + tmpreg = gen_reg_rtx(SImode);
17201 + emit_insn(gen_fpcc_to_reg(tmpreg));
17202 + emit_insn(gen_reg_to_cc(tmpreg));
17208 +(define_insn "cmpsf_internal"
17209 + [(set (reg:CC FPCC_REGNUM)
17211 + (match_operand:SF 0 "avr32_fp_register_operand" "f")
17212 + (match_operand:SF 1 "avr32_fp_register_operand" "f")))]
17213 + "TARGET_HARD_FLOAT"
17215 + if (!rtx_equal_p(cc_prev_status.mdep.fpvalue, SET_SRC(PATTERN (insn))) )
17216 + return "fcmp.s\t%0, %1";
17219 + [(set_attr "length" "4")
17220 + (set_attr "type" "fcmps")
17221 + (set_attr "cc" "fpcompare")])
17223 +(define_insn "fpcc_to_reg"
17224 + [(set (match_operand:SI 0 "register_operand" "=r")
17225 + (unspec:SI [(reg:CC FPCC_REGNUM)]
17226 + UNSPEC_FPCC_TO_REG))]
17227 + "TARGET_HARD_FLOAT"
17228 + "fmov.s\t%0, fsr"
17229 + [(set_attr "length" "4")
17230 + (set_attr "type" "fmvcpu")])
17232 +(define_insn "reg_to_cc"
17234 + (unspec:SI [(match_operand:SI 0 "register_operand" "r")]
17235 + UNSPEC_REG_TO_CC))]
17236 + "TARGET_HARD_FLOAT"
17238 + [(set_attr "length" "2")
17239 + (set_attr "type" "alu")
17240 + (set_attr "cc" "from_fpcc")])
17242 +(define_insn "stm_fp"
17243 + [(unspec [(match_operand 0 "register_operand" "r")
17244 + (match_operand 1 "const_int_operand" "")
17245 + (match_operand 2 "const_int_operand" "")]
17247 + "TARGET_HARD_FLOAT"
17249 + int cop_reglist = INTVAL(operands[1]);
17251 + if (INTVAL(operands[2]) != 0)
17252 + return "stcm.w\tcp0, --%0, %C1";
17254 + return "stcm.w\tcp0, %0, %C1";
17256 + if ( cop_reglist & ~0xff ){
17257 + operands[1] = GEN_INT(cop_reglist & ~0xff);
17258 + if (INTVAL(operands[2]) != 0)
17259 + return "stcm.d\tcp0, --%0, %D1";
17261 + return "stcm.d\tcp0, %0, %D1";
17264 + [(set_attr "type" "fstm")
17265 + (set_attr "length" "4")
17266 + (set_attr "cc" "none")])
17268 +++ b/gcc/config/avr32/lib1funcs.S
17270 +/* Macro for moving immediate value to register. */
17271 +.macro mov_imm reg, imm
17272 +.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm))
17274 +#if __AVR32_UC__ >= 2
17275 +.elseif ((\imm & 0xffff) == 0)
17276 + movh \reg, hi(\imm)
17280 + mov \reg, lo(\imm)
17281 + orh \reg, hi(\imm)
17287 +/* Adjust the unpacked double number if it is a subnormal number.
17288 + The exponent and mantissa pair are stored
17289 + in [mant_hi,mant_lo] and [exp]. A register with the correct sign bit in
17290 + the MSB is passed in [sign]. Needs two scratch
17291 + registers [scratch1] and [scratch2]. An adjusted and packed double float
17292 + is present in [mant_hi,mant_lo] after macro has executed */
17293 +.macro adjust_subnormal_df exp, mant_lo, mant_hi, sign, scratch1, scratch2
17294 + /* We have an exponent which is <=0 indicating a subnormal number
17295 + As it should be stored as if the exponent was 1 (although the
17296 + exponent field is all zeros to indicate a subnormal number)
17297 + we have to shift down the mantissa to its correct position. */
17299 + sub \exp,-1 /* amount to shift down */
17301 + brlo 50f /* if more than 53 shift steps, the
17302 + entire mantissa will disappear
17303 + without any rounding to occur */
17308 + sub \exp,-10 /* do the shift to position the
17309 + mantissa at the same time
17310 + note! this does not include the
17311 + final 1 step shift to add the sign */
17313 + /* when shifting, save all shifted out bits in [scratch2]. we may need to
17314 + look at them to make correct rounding. */
17316 + rsub \scratch1,\exp,32 /* get inverted shift count */
17317 + cp.w \exp,32 /* handle shifts >= 32 separately */
17320 + /* small (<32) shift amount, both words are part of the shift */
17321 + lsl \scratch2,\mant_lo,\scratch1 /* save bits to shift out from lsw*/
17322 + lsl \scratch1,\mant_hi,\scratch1 /* get bits from msw destined for lsw*/
17323 + lsr \mant_lo,\mant_lo,\exp /* shift down lsw */
17324 + lsr \mant_hi,\mant_hi,\exp /* shift down msw */
17325 + or \mant_hi,\scratch1 /* add bits from msw with prepared lsw */
17328 + /* large (>=32) shift amount, only lsw will have bits left after shift.
17329 + note that shift operations will use ((shift count) mod 32) so
17330 + we do not need to subtract 32 from shift count. */
17332 + lsl \scratch2,\mant_hi,\scratch1 /* save bits to shift out from msw */
17333 + or \scratch2,\mant_lo /* also save all bits from lsw */
17334 + mov \mant_lo,\mant_hi /* msw -> lsw (i.e. "shift 32 first") */
17335 + mov \mant_hi,0 /* clear msw */
17336 + lsr \mant_lo,\mant_lo,\exp /* make rest of shift inside lsw */
17339 + /* result is almost ready to return, except that least significant bit
17340 + and the part we already shifted out may cause the result to be
17342 + bld \mant_lo,0 /* get bit to be shifted out */
17343 + brcc 51f /* if bit was 0, no rounding */
17345 + /* msb of part to remove is 1, so rounding depends on rest of bits */
17346 + tst \scratch2,\scratch2 /* get shifted out tail */
17347 + brne 50f /* if rest > 0, do round */
17348 + bld \mant_lo,1 /* we have to look at lsb in result */
17349 + brcc 51f /* if lsb is 0, don't round */
17352 + /* subnormal result requires rounding
17353 + rounding may cause subnormal to become smallest normal number
17354 + luckily, smallest normal number has exactly the representation
17355 + we got by rippling a one bit up from mantissa into exponent field. */
17357 + subcc \mant_hi,-1
17360 + /* shift and return packed double with correct sign */
17368 +/* Adjust subnormal single float number with exponent [exp]
17369 + and mantissa [mant] and round. */
17370 +.macro adjust_subnormal_sf sf, exp, mant, sign, scratch
17371 + /* subnormal number */
17372 + rsub \exp,\exp, 1 /* shift amount */
17375 + brhs 90f /* Return zero */
17376 + rsub \scratch, \exp, 32
17377 + lsl \scratch, \mant,\scratch/* Check if there are any bits set
17378 + in the bits discarded in the mantissa */
17379 + srne \scratch /* If so set the lsb of the shifted mantissa */
17380 + lsr \mant,\mant,\exp /* Shift the mantissa */
17381 + or \mant, \scratch /* Round lsb if any bits were shifted out */
17382 + /* Rounding : For explaination, see round_sf. */
17383 + mov \scratch, 0x7f /* Set rounding constant */
17385 + subeq \scratch, -1 /* For odd numbers use rounding constant 0x80 */
17386 + add \mant, \scratch /* Add rounding constant to mantissa */
17387 + /* We can't overflow because mantissa is at least shifted one position
17388 + to the right so the implicit bit is zero. We can however get the implicit
17389 + bit set after rounding which means that we have the lowest normal number
17390 + but this is ok since this bit has the same position as the LSB of the
17392 + lsr \sf, \mant, 7
17393 + /* Rotate in sign */
17400 +/* Round the unpacked df number with exponent [exp] and
17401 + mantissa [mant_hi, mant_lo]. Uses scratch register
17403 +.macro round_df exp, mant_lo, mant_hi, scratch
17404 + mov \scratch, 0x3ff /* Rounding constant */
17405 + bld \mant_lo,11 /* Check if lsb in the final result is
17407 + subeq \scratch, -1 /* Adjust rounding constant to 0x400
17408 + if rounding 0.5 upwards */
17409 + add \mant_lo, \scratch /* Round */
17410 + acr \mant_hi /* If overflowing we know that
17411 + we have all zeros in the bits not
17412 + scaled out so we can leave them
17413 + but we must increase the exponent with
17414 + two since we had an implicit bit
17415 + which is lost + the extra overflow bit */
17416 + subcs \exp, -2 /* Update exponent */
17419 +/* Round single float number stored in [mant] and [exp] */
17420 +.macro round_sf exp, mant, scratch
17422 + For 0.5 we round to nearest even integer
17423 + for all other cases we round to nearest integer.
17424 + This means that if the digit left of the "point" (.)
17425 + is 1 we can add 0x80 to the mantissa since the
17426 + corner case 0x180 will round up to 0x200. If the
17427 + digit left of the "point" is 0 we will have to
17428 + add 0x7f since this will give 0xff and hence a
17429 + truncation/rounding downwards for the corner
17430 + case when the 9 lowest bits are 0x080 */
17431 + mov \scratch, 0x7f /* Set rounding constant */
17432 + /* Check if the mantissa is even or odd */
17434 + subeq \scratch, -1 /* Rounding constant should be 0x80 */
17435 + add \mant, \scratch
17436 + subcs \exp, -2 /* Adjust exponent if we overflowed */
17441 +/* Pack a single float number stored in [mant] and [exp]
17442 + into a single float number in [sf] */
17443 +.macro pack_sf sf, exp, mant
17444 + bld \mant,31 /* implicit bit to z */
17445 + subne \exp,1 /* if subnormal (implicit bit 0)
17446 + adjust exponent to storage format */
17448 + lsr \sf, \mant, 7
17449 + bfins \sf, \exp, 24, 8
17452 +/* Pack exponent [exp] and mantissa [mant_hi, mant_lo]
17453 + into [df_hi, df_lo]. [df_hi] is shifted
17454 + one bit up so the sign bit can be shifted into it */
17456 +.macro pack_df exp, mant_lo, mant_hi, df_lo, df_hi
17457 + bld \mant_hi,31 /* implicit bit to z */
17458 + subne \exp,1 /* if subnormal (implicit bit 0)
17459 + adjust exponent to storage format */
17461 + lsr \mant_lo,11 /* shift back lsw */
17462 + or \df_lo,\mant_lo,\mant_hi<<21 /* combine with low bits from msw */
17463 + lsl \mant_hi,1 /* get rid of implicit bit */
17464 + lsr \mant_hi,11 /* shift back msw except for one step*/
17465 + or \df_hi,\mant_hi,\exp<<21 /* combine msw with exponent */
17468 +/* Normalize single float number stored in [mant] and [exp]
17469 + using scratch register [scratch] */
17470 +.macro normalize_sf exp, mant, scratch
17471 + /* Adjust exponent and mantissa */
17472 + clz \scratch, \mant
17473 + sub \exp, \scratch
17474 + lsl \mant, \mant, \scratch
17477 +/* Normalize the exponent and mantissa pair stored
17478 + in [mant_hi,mant_lo] and [exp]. Needs two scratch
17479 + registers [scratch1] and [scratch2]. */
17480 +.macro normalize_df exp, mant_lo, mant_hi, scratch1, scratch2
17481 + clz \scratch1,\mant_hi /* Check if we have zeros in high bits */
17482 + breq 80f /* No need for scaling if no zeros in high bits */
17483 + brcs 81f /* Check for all zeros */
17485 + /* shift amount is smaller than 32, and involves both msw and lsw*/
17486 + rsub \scratch2,\scratch1,32 /* shift mantissa */
17487 + lsl \mant_hi,\mant_hi,\scratch1
17488 + lsr \scratch2,\mant_lo,\scratch2
17489 + or \mant_hi,\scratch2
17490 + lsl \mant_lo,\mant_lo,\scratch1
17491 + sub \exp,\scratch1 /* adjust exponent */
17492 + rjmp 80f /* Finished */
17494 + /* shift amount is greater than 32 */
17495 + clz \scratch1,\mant_lo /* shift mantissa */
17496 + movcs \scratch1, 0
17497 + subcc \scratch1,-32
17498 + lsl \mant_hi,\mant_lo,\scratch1
17500 + sub \exp,\scratch1 /* adjust exponent */
17505 +/* Fast but approximate multiply of two 64-bit numbers to give a 64 bit result.
17506 + The multiplication of [al]x[bl] is discarded.
17507 + Operands in [ah], [al], [bh], [bl].
17508 + Scratch registers in [sh], [sl].
17509 + Returns results in registers [rh], [rl].*/
17510 +.macro mul_approx_df ah, al, bh, bl, rh, rl, sh, sl
17511 + mulu.d \sl, \ah, \bl
17512 + macu.d \sl, \al, \bh
17513 + mulu.d \rl, \ah, \bh
17520 +#if defined(L_avr32_f64_mul) || defined(L_avr32_f64_mul_fast)
17522 +#if defined(L_avr32_f64_mul)
17523 + .global __avr32_f64_mul
17524 + .type __avr32_f64_mul,@function
17527 + .global __avr32_f64_mul_fast
17528 + .type __avr32_f64_mul_fast,@function
17529 +__avr32_f64_mul_fast:
17531 + or r12, r10, r11 << 1
17532 + breq __avr32_f64_mul_op1_zero
17534 +#if defined(L_avr32_f64_mul)
17537 + stm --sp, r5,r6,r7,lr
17540 +#define AVR32_F64_MUL_OP1_INT_BITS 1
17541 +#define AVR32_F64_MUL_OP2_INT_BITS 10
17542 +#define AVR32_F64_MUL_RES_INT_BITS 11
17544 + /* op1 in {r11,r10}*/
17545 + /* op2 in {r9,r8}*/
17546 + eor lr, r11, r9 /* MSB(lr) = Sign(op1) ^ Sign(op2) */
17548 + /* Unpack op1 to 1.63 format*/
17550 + /* sf: r11, r10 */
17551 + bfextu r7, r11, 20, 11 /* Extract exponent */
17555 + /* Check if normalization is needed */
17556 + breq __avr32_f64_mul_op1_subnormal /*If number is subnormal, normalize it */
17558 + lsl r11, (12-AVR32_F64_MUL_OP1_INT_BITS-1) /* Extract mantissa, leave room for implicit bit */
17559 + or r11, r11, r10>>(32-(12-AVR32_F64_MUL_OP1_INT_BITS-1))
17560 + lsl r10, (12-AVR32_F64_MUL_OP1_INT_BITS-1)
17561 + bfins r11, r5, 32 - (1 + AVR32_F64_MUL_OP1_INT_BITS), 1 + AVR32_F64_MUL_OP1_INT_BITS /* Insert implicit bit */
17565 + /* Unpack op2 to 10.54 format */
17568 + bfextu r6, r9, 20, 11 /* Extract exponent */
17570 + /* Check if normalization is needed */
17571 + breq __avr32_f64_mul_op2_subnormal /*If number is subnormal, normalize it */
17573 + lsl r8, 1 /* Extract mantissa, leave room for implicit bit */
17575 + bfins r9, r5, 32 - (1 + AVR32_F64_MUL_OP2_INT_BITS), 1 + AVR32_F64_MUL_OP2_INT_BITS /* Insert implicit bit */
17579 + /* Check if any operands are NaN or INF */
17581 + breq __avr32_f64_mul_op_nan_or_inf /* Check op1 for NaN or Inf */
17583 + breq __avr32_f64_mul_op_nan_or_inf /* Check op2 for NaN or Inf */
17586 + /* Calculate new exponent in r12*/
17588 + sub r12, (1023-1)
17590 +#if defined(L_avr32_f64_mul)
17591 + /* Do the multiplication.
17592 + Place result in [r11, r10, r7, r6]. The result is in 11.117 format. */
17593 + mulu.d r4, r11, r8
17594 + macu.d r4, r10, r9
17595 + mulu.d r6, r10, r8
17596 + mulu.d r10, r11, r9
17601 + /* Do the multiplication using approximate calculation. discard the al x bl
17603 + Place result in [r11, r10, r7]. The result is in 11.85 format. */
17605 + /* Do the multiplication using approximate calculation.
17606 + Place result in r11, r10. Use r7, r6 as scratch registers */
17607 + mulu.d r6, r11, r8
17608 + macu.d r6, r10, r9
17609 + mulu.d r10, r11, r9
17613 + /* Adjust exponent and mantissa */
17614 + /* [r12]:exp, [r11, r10]:mant [r7, r6]:sticky bits */
17615 + /* Mantissa may be of the format 00000000000.0xxx or 00000000000.1xxx. */
17616 + /* In the first case, shift one pos to left.*/
17617 + bld r11, 32-AVR32_F64_MUL_RES_INT_BITS-1
17625 + brle __avr32_f64_mul_res_subnormal /*Result was subnormal.*/
17627 + /* Check for Inf. */
17629 + brge __avr32_f64_mul_res_inf
17631 + /* Insert exponent. */
17632 + bfins r11, r12, 20, 11
17634 + /* Result was not subnormal. Perform rounding. */
17635 + /* For the fast version we discard the sticky bits and always round
17636 + the halfwaycase up. */
17638 +#if defined(L_avr32_f64_mul)
17639 + or r6, r6, r10 << 31 /* Or in parity bit into stickybits */
17640 + or r7, r7, r6 >> 1 /* Or together sticky and still make the msb
17641 + of r7 represent the halfway bit. */
17642 + eorh r7, 0x8000 /* Toggle halfway bit. */
17643 + /* We should now round up by adding one for the following cases:
17645 + halfway sticky|parity round-up
17650 + Since we have inverted the halfway bit we can use the satu instruction
17651 + by saturating to 1 bit to implement this.
17660 + /* Insert sign bit*/
17664 + /* Return result in [r11,r10] */
17665 +#if defined(L_avr32_f64_mul)
17668 + ldm sp++, r5, r6, r7,pc
17672 +__avr32_f64_mul_op1_subnormal:
17673 + andh r11, 0x000f /* Remove sign bit and exponent */
17674 + clz r12, r10 /* Count leading zeros in lsw */
17675 + clz r6, r11 /* Count leading zeros in msw */
17676 + subcs r12, -32 + AVR32_F64_MUL_OP1_INT_BITS
17678 + subcc r6, AVR32_F64_MUL_OP1_INT_BITS
17682 + /* shifting involves both msw and lsw*/
17683 + rsub r12, r6, 32 /* shift mantissa */
17685 + lsr r12, r10, r12
17688 + sub r6, 12-AVR32_F64_MUL_OP1_INT_BITS
17689 + sub r7, r6 /* adjust exponent */
17690 + rjmp 22b /* Finished */
17692 + /* msw is zero so only need to consider lsw */
17694 + breq __avr32_f64_mul_res_zero
17696 + sub r6, 12-AVR32_F64_MUL_OP1_INT_BITS
17697 + sub r7, r6 /* adjust exponent */
17701 +__avr32_f64_mul_op2_subnormal:
17702 + andh r9, 0x000f /* Remove sign bit and exponent */
17703 + clz r12, r8 /* Count leading zeros in lsw */
17704 + clz r5, r9 /* Count leading zeros in msw */
17705 + subcs r12, -32 + AVR32_F64_MUL_OP2_INT_BITS
17707 + subcc r5, AVR32_F64_MUL_OP2_INT_BITS
17711 + /* shifting involves both msw and lsw*/
17712 + rsub r12, r5, 32 /* shift mantissa */
17717 + sub r5, 12 - AVR32_F64_MUL_OP2_INT_BITS
17718 + sub r6, r5 /* adjust exponent */
17719 + rjmp 23b /* Finished */
17721 + /* msw is zero so only need to consider lsw */
17723 + breq __avr32_f64_mul_res_zero
17725 + sub r5, 12 - AVR32_F64_MUL_OP2_INT_BITS
17726 + sub r6, r5 /* adjust exponent */
17730 +__avr32_f64_mul_op_nan_or_inf:
17731 + /* Same code for OP1 and OP2*/
17732 + /* Since we are here, at least one of the OPs were NaN or INF*/
17733 + andh r9, 0x000f /* Remove sign bit and exponent */
17734 + andh r11, 0x000f /* Remove sign bit and exponent */
17735 + /* Merge the regs in each operand to check for zero*/
17736 + or r11, r10 /* op1 */
17737 + or r9, r8 /* op2 */
17738 + /* Check if op1 is NaN or INF */
17740 + brne __avr32_f64_mul_op1_not_naninf
17741 + /* op1 was NaN or INF.*/
17743 + brne __avr32_f64_mul_res_nan /* op1 was NaN. Result will be NaN*/
17744 + /*op1 was INF. check if op2 is NaN or INF*/
17746 + brne __avr32_f64_mul_res_inf /*op1 was INF, op2 was neither NaN nor INF*/
17747 + /* op1 is INF, op2 is either NaN or INF*/
17749 + breq __avr32_f64_mul_res_inf /*op2 was also INF*/
17750 + rjmp __avr32_f64_mul_res_nan /*op2 was NaN*/
17752 +__avr32_f64_mul_op1_not_naninf:
17753 + /* op1 was not NaN nor INF. Then op2 must be NaN or INF*/
17755 + breq __avr32_f64_mul_res_inf /*op2 was INF, return INF*/
17756 + rjmp __avr32_f64_mul_res_nan /*else return NaN*/
17758 +__avr32_f64_mul_res_subnormal:/* Multiply result was subnormal. */
17759 +#if defined(L_avr32_f64_mul)
17760 + /* Check how much we must scale down the mantissa. */
17762 + sub r12, -1 /* We do no longer have an implicit bit. */
17763 + satu r12 >> 0, 6 /* Saturate shift amount to max 63. */
17766 + /* Shift amount <32 */
17772 + lsr r10, r10, r12
17775 + lsr r11, r11, r12
17778 + /* Shift amount >=32 */
17785 + or r6, r6, r10 << 1
17786 + lsr r10, r10, r12
17788 + lsr r10, r11, r12
17792 + /* Flush to zero for the fast version. */
17793 + mov r11, lr /*Get correct sign*/
17794 + andh r11, 0x8000, COH
17796 + ldm sp++, r5, r6, r7,pc
17799 +__avr32_f64_mul_res_zero:/* Multiply result is zero. */
17800 + mov r11, lr /*Get correct sign*/
17801 + andh r11, 0x8000, COH
17803 +#if defined(L_avr32_f64_mul)
17806 + ldm sp++, r5, r6, r7,pc
17809 +__avr32_f64_mul_res_nan: /* Return NaN. */
17812 +#if defined(L_avr32_f64_mul)
17815 + ldm sp++, r5, r6, r7,pc
17818 +__avr32_f64_mul_res_inf: /* Return INF. */
17819 + mov r11, 0xfff00000
17823 +#if defined(L_avr32_f64_mul)
17826 + ldm sp++, r5, r6, r7,pc
17829 +__avr32_f64_mul_op1_zero:
17832 + andh r11, 0x8000, COH
17833 + /* Check if op2 is Inf or NaN. */
17834 + bfextu r12, r9, 20, 11
17836 + retne r12 /* Return 0.0 */
17847 +#if defined(L_avr32_f64_addsub) || defined(L_avr32_f64_addsub_fast)
17850 +__avr32_f64_sub_from_add:
17851 + /* Switch sign on op2 */
17854 +#if defined(L_avr32_f64_addsub_fast)
17855 + .global __avr32_f64_sub_fast
17856 + .type __avr32_f64_sub_fast,@function
17857 +__avr32_f64_sub_fast:
17859 + .global __avr32_f64_sub
17860 + .type __avr32_f64_sub,@function
17864 + /* op1 in {r11,r10}*/
17865 + /* op2 in {r9,r8}*/
17867 +#if defined(L_avr32_f64_addsub_fast)
17868 + /* If op2 is zero just return op1 */
17869 + or r12, r8, r9 << 1
17873 + /* Check signs */
17875 + /* Different signs, use addition. */
17876 + brmi __avr32_f64_add_from_sub
17878 + stm --sp, r5, r6, r7, lr
17880 + /* Get sign of op1 into r12 */
17882 + andh r12, 0x8000, COH
17884 + /* Remove sign from operands */
17888 + /* Put the largest number in [r11, r10]
17889 + and the smallest number in [r9, r8] */
17892 + brhs 1f /* Skip swap if operands already correctly ordered*/
17893 + /* Operands were not correctly ordered, swap them*/
17900 + eorh r12, 0x8000 /* Invert sign in r12*/
17902 + /* Unpack largest operand - opH */
17904 + /* sf: r11, r10 */
17905 + lsr r7, r11, 20 /* Extract exponent */
17906 + lsl r11, 11 /* Extract mantissa, leave room for implicit bit */
17907 + or r11, r11, r10>>21
17909 + sbr r11, 31 /* Insert implicit bit */
17912 + /* Unpack smallest operand - opL */
17915 + lsr r6, r9, 20 /* Extract exponent */
17916 + breq __avr32_f64_sub_opL_subnormal /* If either zero or subnormal */
17917 + lsl r9, 11 /* Extract mantissa, leave room for implicit bit */
17918 + or r9, r9, r8>>21
17920 + sbr r9, 31 /* Insert implicit bit */
17923 +__avr32_f64_sub_opL_subnormal_done:
17924 + /* opH is NaN or Inf. */
17926 + breq __avr32_f64_sub_opH_nan_or_inf
17928 + /* Get shift amount to scale mantissa of op2. */
17930 + breq __avr32_f64_sub_shift_done /* No need to shift, exponents are equal*/
17932 + /* Scale mantissa [r9, r8] with amount [r6].
17933 + Uses scratch registers [r5] and [lr].
17934 + In IEEE mode:Must not forget the sticky bits we intend to shift out. */
17936 + rsub r5,r6,32 /* get (32 - shift count)
17937 + (if shift count > 32 we get a
17938 + negative value, but that will
17939 + work as well in the code below.) */
17941 + cp.w r6,32 /* handle shifts >= 32 separately */
17942 + brhs __avr32_f64_sub_longshift
17944 + /* small (<32) shift amount, both words are part of the shift
17945 + first remember whether part that is lost contains any 1 bits ... */
17946 + lsl lr,r8,r5 /* shift away bits that are part of
17947 + final mantissa. only part that goes
17948 + to lr are bits that will be lost */
17950 + /* ... and now to the actual shift */
17951 + lsl r5,r9,r5 /* get bits from msw destined for lsw*/
17952 + lsr r8,r8,r6 /* shift down lsw of mantissa */
17953 + lsr r9,r9,r6 /* shift down msw of mantissa */
17954 + or r8,r5 /* combine these bits with prepared lsw*/
17955 +#if defined(L_avr32_f64_addsub)
17956 + cp.w lr,0 /* if any '1' bit in part we lost ...*/
17958 + or r8, lr /* ... we need to set sticky bit*/
17961 +__avr32_f64_sub_shift_done:
17962 + /* Now subtract the mantissas. */
17966 + /* Normalize the exponent and mantissa pair stored in
17967 + [r11,r10] and exponent in [r7]. Needs two scratch registers [r6] and [lr]. */
17968 + clz r6,r11 /* Check if we have zeros in high bits */
17969 + breq __avr32_f64_sub_longnormalize_done /* No need for scaling if no zeros in high bits */
17970 + brcs __avr32_f64_sub_longnormalize
17973 + /* shift amount is smaller than 32, and involves both msw and lsw*/
17974 + rsub lr,r6,32 /* shift mantissa */
17980 + sub r7,r6 /* adjust exponent */
17981 + brle __avr32_f64_sub_subnormal_result
17982 +__avr32_f64_sub_longnormalize_done:
17984 +#if defined(L_avr32_f64_addsub)
17985 + /* Insert the bits we will remove from the mantissa r9[31:21] */
17986 + lsl r9, r10, (32 - 11)
17988 + /* Keep the last bit shifted out. */
17989 + bfextu r9, r10, 10, 1
17992 + /* Pack final result*/
17993 + /* Input: [r7]:exp, [r11, r10]:mant, [r12]:sign in MSB */
17994 + /* Result in [r11,r10] */
17995 + /* Insert mantissa */
17997 + or r10, r10, r11<<21
17999 + /* Insert exponent and sign bit*/
18000 + bfins r11, r7, 20, 11
18004 +__avr32_f64_sub_round:
18005 +#if defined(L_avr32_f64_addsub)
18006 + mov_imm r7, 0x80000000
18016 + /* Return result in [r11,r10] */
18017 + ldm sp++, r5, r6, r7,pc
18021 +__avr32_f64_sub_opL_subnormal:
18022 + /* Extract the of mantissa */
18023 + lsl r9, 11 /* Extract mantissa, leave room for implicit bit */
18024 + or r9, r9, r8>>21
18027 + /* Set exponent to 1 if we do not have a zero. */
18031 + /* Check if opH is also subnormal. If so, clear implicit bit in r11*/
18036 + /* Check if op1 is zero, if so set exponent to 0. */
18040 + rjmp __avr32_f64_sub_opL_subnormal_done
18042 +__avr32_f64_sub_opH_nan_or_inf:
18043 + /* Check if opH is NaN, if so return NaN */
18046 + brne __avr32_f64_sub_return_nan
18048 + /* opH is Inf. */
18049 + /* Check if opL is Inf. or NaN */
18051 + breq __avr32_f64_sub_return_nan
18052 + /* Return infinity with correct sign. */
18053 + or r11, r12, r7 << 20
18054 + ldm sp++, r5, r6, r7, pc/* opL not Inf or NaN, return opH */
18055 +__avr32_f64_sub_return_nan:
18056 + mov r10, -1 /* Generate NaN in r11, r10 */
18058 + ldm sp++, r5, r6, r7, pc/* opL Inf or NaN, return NaN */
18061 +__avr32_f64_sub_subnormal_result:
18062 +#if defined(L_avr32_f64_addsub)
18063 + /* Check how much we must scale down the mantissa. */
18065 + sub r7, -1 /* We do no longer have an implicit bit. */
18066 + satu r7 >> 0, 6 /* Saturate shift amount to max 63. */
18069 + /* Shift amount <32 */
18074 + or r10, r6 /* Sticky bit from the
18075 + part that was shifted out. */
18079 + /* Set exponent */
18081 + rjmp __avr32_f64_sub_longnormalize_done
18083 + /* Shift amount >=32 */
18089 + or r10, r6 /* Sticky bit from the
18090 + part that was shifted out. */
18092 + /* Set exponent */
18094 + rjmp __avr32_f64_sub_longnormalize_done
18096 + /* Just flush subnormals to zero. */
18100 + ldm sp++, r5, r6, r7, pc
18102 +__avr32_f64_sub_longshift:
18103 + /* large (>=32) shift amount, only lsw will have bits left after shift.
18104 + note that shift operations will use ((shift count=r6) mod 32) so
18105 + we do not need to subtract 32 from shift count. */
18106 + /* Saturate the shift amount to 63. If the amount
18107 + is any larger op2 is insignificant. */
18110 +#if defined(L_avr32_f64_addsub)
18111 + /* first remember whether part that is lost contains any 1 bits ... */
18112 + moveq lr, r8 /* If shift amount is 32, no bits from msw are lost. */
18114 + lsl lr,r9,r5 /* save all lost bits from msw */
18115 + or lr,r8 /* also save lost bits (all) from lsw
18116 + now lr != 0 if we lose any bits */
18119 + /* ... and now to the actual shift */
18120 + lsr r8,r9,r6 /* Move msw to lsw and shift. */
18121 + mov r9,0 /* clear msw */
18122 +#if defined(L_avr32_f64_addsub)
18123 + cp.w lr,0 /* if any '1' bit in part we lost ...*/
18125 + or r8, lr /* ... we need to set sticky bit*/
18127 + rjmp __avr32_f64_sub_shift_done
18129 +__avr32_f64_sub_longnormalize:
18130 + /* shift amount is greater than 32 */
18131 + clz r6,r10 /* shift mantissa */
18132 + /* If the resulting mantissa is zero the result is
18133 + zero so force exponent to zero. */
18136 + movcs r12, 0 /* Also clear sign bit. A zero result from subtraction
18137 + always is +0.0 */
18141 + sub r7,r6 /* adjust exponent */
18142 + brle __avr32_f64_sub_subnormal_result
18143 + rjmp __avr32_f64_sub_longnormalize_done
18148 +__avr32_f64_add_from_sub:
18149 + /* Switch sign on op2 */
18152 +#if defined(L_avr32_f64_addsub_fast)
18153 + .global __avr32_f64_add_fast
18154 + .type __avr32_f64_add_fast,@function
18155 +__avr32_f64_add_fast:
18157 + .global __avr32_f64_add
18158 + .type __avr32_f64_add,@function
18162 + /* op1 in {r11,r10}*/
18163 + /* op2 in {r9,r8}*/
18165 +#if defined(L_avr32_f64_addsub_fast)
18166 + /* If op2 is zero just return op1 */
18167 + or r12, r8, r9 << 1
18171 + /* Check signs */
18173 + /* Different signs, use subtraction. */
18174 + brmi __avr32_f64_sub_from_add
18176 + stm --sp, r5, r6, r7, lr
18178 + /* Get sign of op1 into r12 */
18180 + andh r12, 0x8000, COH
18182 + /* Remove sign from operands */
18186 + /* Put the number with the largest exponent in [r11, r10]
18187 + and the number with the smallest exponent in [r9, r8] */
18189 + brhs 1f /* Skip swap if operands already correctly ordered */
18190 + /* Operands were not correctly ordered, swap them */
18198 + mov lr, 0 /* Set sticky bits to zero */
18199 + /* Unpack largest operand - opH */
18201 + /* sf: r11, r10 */
18202 + bfextu R7, R11, 20, 11 /* Extract exponent */
18203 + bfextu r11, r11, 0, 20 /* Extract mantissa */
18204 + sbr r11, 20 /* Insert implicit bit */
18206 + /* Unpack smallest operand - opL */
18209 + bfextu R6, R9, 20, 11 /* Extract exponent */
18210 + breq __avr32_f64_add_op2_subnormal
18211 + bfextu r9, r9, 0, 20 /* Extract mantissa */
18212 + sbr r9, 20 /* Insert implicit bit */
18215 + /* opH is NaN or Inf. */
18217 + breq __avr32_f64_add_opH_nan_or_inf
18219 + /* Get shift amount to scale mantissa of op2. */
18221 + breq __avr32_f64_add_shift_done /* No need to shift, exponents are equal*/
18223 + /* Scale mantissa [r9, r8] with amount [r6].
18224 + Uses scratch registers [r5] and [lr].
18225 + In IEEE mode:Must not forget the sticky bits we intend to shift out. */
18226 + rsub r5,r6,32 /* get (32 - shift count)
18227 + (if shift count > 32 we get a
18228 + negative value, but that will
18229 + work as well in the code below.) */
18231 + cp.w r6,32 /* handle shifts >= 32 separately */
18232 + brhs __avr32_f64_add_longshift
18234 + /* small (<32) shift amount, both words are part of the shift
18235 + first remember whether part that is lost contains any 1 bits ... */
18236 + lsl lr,r8,r5 /* shift away bits that are part of
18237 + final mantissa. only part that goes
18238 + to lr are bits that will be lost */
18240 + /* ... and now to the actual shift */
18241 + lsl r5,r9,r5 /* get bits from msw destined for lsw*/
18242 + lsr r8,r8,r6 /* shift down lsw of mantissa */
18243 + lsr r9,r9,r6 /* shift down msw of mantissa */
18244 + or r8,r5 /* combine these bits with prepared lsw*/
18246 +__avr32_f64_add_shift_done:
18247 + /* Now add the mantissas. */
18251 + /* Check if we overflowed. */
18253 + breq __avr32_f64_add_res_of:
18255 +__avr32_f64_add_res_of_done:
18257 + /* Pack final result*/
18258 + /* Input: [r7]:exp, [r11, r10]:mant, [r12]:sign in MSB */
18259 + /* Result in [r11,r10] */
18260 + /* Insert exponent and sign bit*/
18261 + bfins r11, r7, 20, 11
18265 +__avr32_f64_add_round:
18266 +#if defined(L_avr32_f64_addsub)
18267 + bfextu r12, r10, 0, 1 /* Extract parity bit.*/
18268 + or lr, r12 /* or it together with the sticky bits. */
18269 + eorh lr, 0x8000 /* Toggle round bit. */
18270 + /* We should now round up by adding one for the following cases:
18272 + halfway sticky|parity round-up
18277 + Since we have inverted the halfway bit we can use the satu instruction
18278 + by saturating to 1 bit to implement this.
18287 + /* Return result in [r11,r10] */
18288 + ldm sp++, r5, r6, r7,pc
18291 +__avr32_f64_add_opH_nan_or_inf:
18292 + /* Check if opH is NaN, if so return NaN */
18295 + brne __avr32_f64_add_return_nan
18297 + /* opH is Inf. */
18298 + /* Check if opL is Inf. or NaN */
18300 + breq __avr32_f64_add_opL_nan_or_inf
18301 + ldm sp++, r5, r6, r7, pc/* opL not Inf or NaN, return opH */
18302 +__avr32_f64_add_opL_nan_or_inf:
18305 + brne __avr32_f64_add_return_nan
18306 + mov r10, 0 /* Generate Inf in r11, r10 */
18307 + mov_imm r11, 0x7ff00000
18308 + ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */
18309 +__avr32_f64_add_return_nan:
18310 + mov r10, -1 /* Generate NaN in r11, r10 */
18312 + ldm sp++, r5, r6, r7, pc/* opL Inf or NaN, return NaN */
18315 +__avr32_f64_add_longshift:
18316 + /* large (>=32) shift amount, only lsw will have bits left after shift.
18317 + note that shift operations will use ((shift count=r6) mod 32) so
18318 + we do not need to subtract 32 from shift count. */
18319 + /* Saturate the shift amount to 63. If the amount
18320 + is any larger op2 is insignificant. */
18322 + /* If shift amount is 32 there are no bits from the msw that are lost. */
18325 + /* first remember whether part that is lost contains any 1 bits ... */
18326 + lsl lr,r9,r5 /* save all lost bits from msw */
18327 +#if defined(L_avr32_f64_addsub)
18330 + or lr,r8 /* also save lost bits (all) from lsw
18331 + now lr != 0 if we lose any bits */
18334 + /* ... and now to the actual shift */
18335 + lsr r8,r9,r6 /* msw -> lsw and make rest of shift inside lsw*/
18336 + mov r9,0 /* clear msw */
18337 + rjmp __avr32_f64_add_shift_done
18339 +__avr32_f64_add_res_of:
18340 + /* We overflowed. Scale down mantissa by shifting right one position. */
18341 + or lr, lr, lr << 1 /* Remember stickybits*/
18345 + sub r7, -1 /* Increment exponent */
18347 + /* Clear mantissa to set result to Inf if the exponent is 255. */
18352 + rjmp __avr32_f64_add_res_of_done
18354 +__avr32_f64_add_op2_subnormal:
18355 + /* Set epxponent to 1 */
18358 + /* Check if op2 is also subnormal. */
18363 + /* Both operands are subnormal. Just addd the mantissas
18364 + and the exponent will automatically be set to 1 if
18365 + we overflow into a normal number. */
18369 + /* Add sign bit */
18372 + /* Return result in [r11,r10] */
18373 + ldm sp++, r5, r6, r7,pc
18379 +#ifdef L_avr32_f64_to_u32
18380 + /* This goes into L_fixdfsi */
18384 +#ifdef L_avr32_f64_to_s32
18385 + .global __avr32_f64_to_u32
18386 + .type __avr32_f64_to_u32,@function
18387 +__avr32_f64_to_u32:
18389 + retmi 0 /* Negative returns 0 */
18391 + /* Fallthrough to df to signed si conversion */
18392 + .global __avr32_f64_to_s32
18393 + .type __avr32_f64_to_s32,@function
18394 +__avr32_f64_to_s32:
18396 + lsr r12,21 /* extract exponent*/
18397 + sub r12,1023 /* convert to unbiased exponent.*/
18398 + retlo 0 /* too small exponent implies zero. */
18401 + rsub r12,r12,31 /* shift count = 31 - exponent */
18402 + mov r9,r11 /* save sign for later...*/
18403 + lsl r11,11 /* remove exponent and sign*/
18404 + sbr r11,31 /* add implicit bit*/
18405 + or r11,r11,r10>>21 /* get rest of bits from lsw of double */
18406 + lsr r11,r11,r12 /* shift down mantissa to final place */
18407 + lsl r9,1 /* sign -> carry */
18408 + retcc r11 /* if positive, we are done */
18409 + neg r11 /* if negative float, negate result */
18412 +#endif /* L_fixdfsi*/
18414 +#ifdef L_avr32_f64_to_u64
18415 + /* Actual function is in L_fixdfdi */
18418 +#ifdef L_avr32_f64_to_s64
18419 + .global __avr32_f64_to_u64
18420 + .type __avr32_f64_to_u64,@function
18421 +__avr32_f64_to_u64:
18423 + /* Negative numbers return zero */
18430 + /* Fallthrough */
18431 + .global __avr32_f64_to_s64
18432 + .type __avr32_f64_to_s64,@function
18433 +__avr32_f64_to_s64:
18435 + lsr r9,21 /* get exponent*/
18436 + sub r9,1023 /* convert to correct range*/
18437 + /* Return zero if exponent to small */
18442 + mov r8,r11 /* save sign for later...*/
18444 + lsl r11,11 /* remove exponent */
18445 + sbr r11,31 /* add implicit bit*/
18446 + or r11,r11,r10>>21 /* get rest of bits from lsw of double*/
18447 + lsl r10,11 /* align lsw correctly as well */
18448 + rsub r9,r9,63 /* shift count = 63 - exponent */
18451 + cp.w r9,32 /* is shift count more than one reg? */
18454 + mov r12,r11 /* save msw */
18455 + lsr r10,r10,r9 /* small shift count, shift down lsw */
18456 + lsr r11,r11,r9 /* small shift count, shift down msw */
18457 + rsub r9,r9,32 /* get 32-size of shifted out tail */
18458 + lsl r12,r12,r9 /* align part to move from msw to lsw */
18459 + or r10,r12 /* combine to get new lsw */
18463 + lsr r10,r11,r9 /* large shift count,only lsw get bits
18464 + note that shift count is modulo 32*/
18465 + mov r11,0 /* msw will be 0 */
18468 + lsl r8,1 /* sign -> carry */
18469 + retcc r11 /* if positive, we are done */
18471 + neg r11 /* if negative float, negate result */
18478 +#ifdef L_avr32_u32_to_f64
18479 + /* Code located in L_floatsidf */
18482 +#ifdef L_avr32_s32_to_f64
18483 + .global __avr32_u32_to_f64
18484 + .type __avr32_u32_to_f64,@function
18485 +__avr32_u32_to_f64:
18486 + sub r11, r12, 0 /* Move to r11 and force Z flag to be updated */
18487 + mov r12, 0 /* always positive */
18488 + rjmp 0f /* Jump to common code for floatsidf */
18490 + .global __avr32_s32_to_f64
18491 + .type __avr32_s32_to_f64,@function
18492 +__avr32_s32_to_f64:
18493 + mov r11, r12 /* Keep original value in r12 for sign */
18494 + abs r11 /* Absolute value if r12 */
18496 + mov r10,0 /* let remaining bits be zero */
18497 + reteq r11 /* zero long will return zero float */
18500 + mov r9,31+1023 /* set exponent */
18502 + normalize_df r9 /*exp*/, r10, r11 /* mantissa */, r8, lr /* scratch */
18504 + /* Check if a subnormal result was created */
18508 + adjust_subnormal_df r9 /* exp */, r10, r11 /* Mantissa */, r12 /*sign*/, r8, lr /* scratch */
18512 + /* Round result */
18513 + round_df r9 /*exp*/, r10, r11 /* Mantissa */, r8 /*scratch*/
18516 + /*Return infinity */
18518 + mov_imm r11, 0xffe00000
18519 + rjmp __floatsidf_return_op1
18524 + pack_df r9 /*exp*/, r10, r11 /* mantissa */, r10, r11 /* Output df number*/
18525 +__floatsidf_return_op1:
18526 + lsl r12,1 /* shift in sign bit */
18533 +#ifdef L_avr32_f32_cmp_eq
18534 + .global __avr32_f32_cmp_eq
18535 + .type __avr32_f32_cmp_eq,@function
18536 +__avr32_f32_cmp_eq:
18539 + /* If not equal check for +/-0 */
18540 + /* Or together the two values and shift out the sign bit.
18541 + If the result is zero, then the two values are both zero. */
18547 + /* Numbers were equal. Check for NaN or Inf */
18548 + mov_imm r11, 0xff000000
18551 + retls 1 /* 0 if NaN, 1 otherwise */
18555 +#if defined(L_avr32_f32_cmp_ge) || defined(L_avr32_f32_cmp_lt)
18556 +#ifdef L_avr32_f32_cmp_ge
18557 + .global __avr32_f32_cmp_ge
18558 + .type __avr32_f32_cmp_ge,@function
18559 +__avr32_f32_cmp_ge:
18561 +#ifdef L_avr32_f32_cmp_lt
18562 + .global __avr32_f32_cmp_lt
18563 + .type __avr32_f32_cmp_lt,@function
18564 +__avr32_f32_cmp_lt:
18566 + lsl r10, r12, 1 /* Remove sign bits */
18569 +#ifdef L_avr32_f32_cmp_ge
18570 + reteq 1 /* Both number are zero. Return true. */
18572 +#ifdef L_avr32_f32_cmp_lt
18573 + reteq 0 /* Both number are zero. Return false. */
18575 + mov_imm r8, 0xff000000
18577 + rethi 0 /* Op0 is NaN */
18579 + rethi 0 /* Op1 is Nan */
18583 +#ifdef L_avr32_f32_cmp_ge
18584 + srcc r8 /* Set result to true if op0 is positive*/
18586 +#ifdef L_avr32_f32_cmp_lt
18587 + srcs r8 /* Set result to true if op0 is negative*/
18589 + retmi r8 /* Return if signs are different */
18590 + brcs 0f /* Both signs negative? */
18592 + /* Both signs positive */
18594 +#ifdef L_avr32_f32_cmp_ge
18598 +#ifdef L_avr32_f32_cmp_lt
18603 + /* Both signs negative */
18605 +#ifdef L_avr32_f32_cmp_ge
18609 +#ifdef L_avr32_f32_cmp_lt
18616 +#ifdef L_avr32_f64_cmp_eq
18617 + .global __avr32_f64_cmp_eq
18618 + .type __avr32_f64_cmp_eq,@function
18619 +__avr32_f64_cmp_eq:
18624 + /* Args were not equal*/
18625 + /* Both args could be zero with different sign bits */
18626 + lsl r11,1 /* get rid of sign bits */
18628 + or r11,r10 /* Check if all bits are zero */
18631 + reteq 1 /* If all zeros the arguments are equal
18632 + so return 1 else return 0 */
18635 + /* check for NaN */
18637 + mov_imm r12, 0xffe00000
18639 + cpc r11,r12 /* check if nan or inf */
18640 + retls 1 /* If Arg is NaN return 0 else 1*/
18641 + ret 0 /* Return */
18646 +#if defined(L_avr32_f64_cmp_ge) || defined(L_avr32_f64_cmp_lt)
18648 +#ifdef L_avr32_f64_cmp_ge
18649 + .global __avr32_f64_cmp_ge
18650 + .type __avr32_f64_cmp_ge,@function
18651 +__avr32_f64_cmp_ge:
18653 +#ifdef L_avr32_f64_cmp_lt
18654 + .global __avr32_f64_cmp_lt
18655 + .type __avr32_f64_cmp_lt,@function
18656 +__avr32_f64_cmp_lt:
18659 + /* compare magnitude of op1 and op2 */
18660 + lsl r11,1 /* Remove sign bit of op1 */
18661 + srcs r12 /* Sign op1 to lsb of r12*/
18663 + breq 3f /* op1 zero */
18664 + lsl r9,1 /* Remove sign bit of op2 */
18665 + rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/
18668 + /* Check for Nan */
18670 + mov_imm lr, 0xffe00000
18673 + brhi 0f /* We have NaN */
18676 + brhi 0f /* We have NaN */
18679 + cp.w r12,3 /* both operands negative ?*/
18682 + cp.w r12,1 /* both operands positive? */
18685 + /* Different signs. If sign of op1 is negative the difference
18686 + between op1 and op2 will always be negative, and if op1 is
18687 + positive the difference will always be positive */
18688 +#ifdef L_avr32_f64_cmp_ge
18692 +#ifdef L_avr32_f64_cmp_lt
18698 + /* Both operands positive. Just compute the difference */
18701 +#ifdef L_avr32_f64_cmp_ge
18705 +#ifdef L_avr32_f64_cmp_lt
18711 + /* Both operands negative. Compute the difference with operands switched */
18714 +#ifdef L_avr32_f64_cmp_ge
18718 +#ifdef L_avr32_f64_cmp_lt
18728 + lsl r9,1 /* Remove sign bit of op1 */
18729 +#ifdef L_avr32_f64_cmp_ge
18730 + srcs r12 /* If op2 is negative then op1 >= op2. */
18732 +#ifdef L_avr32_f64_cmp_lt
18733 + srcc r12 /* If op2 is positve then op1 <= op2. */
18736 +#ifdef L_avr32_f64_cmp_ge
18737 + reteq 1 /* Both operands are zero. Return true. */
18739 +#ifdef L_avr32_f64_cmp_lt
18740 + reteq 0 /* Both operands are zero. Return false. */
18745 +#if defined(L_avr32_f64_div) || defined(L_avr32_f64_div_fast)
18748 +#if defined(L_avr32_f64_div_fast)
18749 + .global __avr32_f64_div_fast
18750 + .type __avr32_f64_div_fast,@function
18751 +__avr32_f64_div_fast:
18753 + .global __avr32_f64_div
18754 + .type __avr32_f64_div,@function
18757 + stm --sp, r0, r1, r2, r3, r4, r5, r6, r7,lr
18758 + /* op1 in {r11,r10}*/
18759 + /* op2 in {r9,r8}*/
18760 + eor lr, r11, r9 /* MSB(lr) = Sign(op1) ^ Sign(op2) */
18763 + /* Unpack op1 to 2.62 format*/
18765 + /* sf: r11, r10 */
18766 + lsr r7, r11, 20 /* Extract exponent */
18768 + lsl r11, 9 /* Extract mantissa, leave room for implicit bit */
18769 + or r11, r11, r10>>23
18771 + sbr r11, 29 /* Insert implicit bit */
18772 + andh r11, 0x3fff /*Mask last part of exponent since we use 2.62 format*/
18774 + cbr r7, 11 /* Clear sign bit */
18775 + /* Check if normalization is needed */
18776 + breq 11f /*If number is subnormal, normalize it */
18779 + brge 2f /* Check op1 for NaN or Inf */
18781 + /* Unpack op2 to 2.62 format*/
18784 + lsr r6, r9, 20 /* Extract exponent */
18786 + lsl r9, 9 /* Extract mantissa, leave room for implicit bit */
18787 + or r9, r9, r8>>23
18789 + sbr r9, 29 /* Insert implicit bit */
18790 + andh r9, 0x3fff /*Mask last part of exponent since we use 2.62 format*/
18792 + cbr r6, 11 /* Clear sign bit */
18793 + /* Check if normalization is needed */
18794 + breq 13f /*If number is subnormal, normalize it */
18797 + brge 3f /* Check op2 for NaN or Inf */
18799 + /* Calculate new exponent */
18804 + /* Approximating 1/d with the following recurrence: */
18805 + /* R[j+1] = R[j]*(2-R[j]*d) */
18806 + /* Using 2.62 format */
18808 + /* d = op2 = divisor (2.62 format): r9,r8 */
18809 + /* Multiply result : r5, r4 */
18810 + /* Initial guess : r3, r2 */
18811 + /* New approximations : r3, r2 */
18812 + /* op1 = Dividend (2.62 format) : r11, r10 */
18814 + mov_imm r12, 0x80000000
18816 + /* Load initial guess, using look-up table */
18817 + /* Initial guess is of format 01.XY, where XY is constructed as follows: */
18818 + /* Let d be of following format: 00.1xy....., then XY=~xy */
18819 + /* For d=00.100 = 0,5 -> initial guess=01.11 = 1,75 */
18820 + /* For d=00.101 = 0,625 -> initial guess=01.11 = 1,5 */
18821 + /* For d=00.110 = 0,75 -> initial guess=01.11 = 1,25 */
18822 + /* For d=00.111 = 0,875 -> initial guess=01.11 = 1,0 */
18823 + /* r2 is also part of the reg pair forming initial guess, but it*/
18824 + /* is kept uninitialized to save one cycle since it has so low significance*/
18827 + bfextu r4, r9, 27, 2
18829 + bfins r3, r4, 28, 2
18831 + /* First approximation */
18832 + /* Approximating to 32 bits */
18833 + /* r5 = R[j]*d */
18834 + mulu.d r4, r3, r9
18835 + /* r5 = 2-R[j]*d */
18836 + sub r5, r12, r5<<2
18837 + /* r3 = R[j]*(2-R[j]*d) */
18838 + mulu.d r4, r3, r5
18841 + /* Second approximation */
18842 + /* Approximating to 32 bits */
18843 + /* r5 = R[j]*d */
18844 + mulu.d r4, r3, r9
18845 + /* r5 = 2-R[j]*d */
18846 + sub r5, r12, r5<<2
18847 + /* r3 = R[j]*(2-R[j]*d) */
18848 + mulu.d r4, r3, r5
18851 + /* Third approximation */
18852 + /* Approximating to 32 bits */
18853 + /* r5 = R[j]*d */
18854 + mulu.d r4, r3, r9
18855 + /* r5 = 2-R[j]*d */
18856 + sub r5, r12, r5<<2
18857 + /* r3 = R[j]*(2-R[j]*d) */
18858 + mulu.d r4, r3, r5
18861 + /* Fourth approximation */
18862 + /* Approximating to 64 bits */
18863 + /* r5,r4 = R[j]*d */
18864 + mul_approx_df r3 /*ah*/, r2 /*al*/, r9 /*bh*/, r8 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
18866 + or r5, r5, r4>>30
18868 + /* r5,r4 = 2-R[j]*d */
18871 + /* r3,r2 = R[j]*(2-R[j]*d) */
18872 + mul_approx_df r3 /*ah*/, r2 /*al*/, r5 /*bh*/, r4 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
18874 + or r3, r3, r4>>30
18878 + /* Fifth approximation */
18879 + /* Approximating to 64 bits */
18880 + /* r5,r4 = R[j]*d */
18881 + mul_approx_df r3 /*ah*/, r2 /*al*/, r9 /*bh*/, r8 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
18883 + or r5, r5, r4>>30
18885 + /* r5,r4 = 2-R[j]*d */
18888 + /* r3,r2 = R[j]*(2-R[j]*d) */
18889 + mul_approx_df r3 /*ah*/, r2 /*al*/, r5 /*bh*/, r4 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/
18891 + or r3, r3, r4>>30
18895 + /* Multiply with dividend to get quotient */
18896 + mul_approx_df r3 /*ah*/, r2 /*al*/, r11 /*bh*/, r10 /*bl*/, r3 /*rh*/, r2 /*rl*/, r1 /*sh*/, r0 /*sl*/
18899 + /* To increase speed, this result is not corrected before final rounding.*/
18900 + /* This may give a difference to IEEE compliant code of 1 ULP.*/
18903 + /* Adjust exponent and mantissa */
18904 + /* r7:exp, [r3, r2]:mant, [r5, r4]:scratch*/
18905 + /* Mantissa may be of the format 0.xxxx or 1.xxxx. */
18906 + /* In the first case, shift one pos to left.*/
18912 +#if defined(L_avr32_f64_div)
18913 + /* We must scale down the dividend to 5.59 format. */
18915 + or r10, r10, r11 << 29
18920 +#if defined(L_avr32_f64_div)
18921 + /* We must scale down the dividend to 6.58 format. */
18923 + or r10, r10, r11 << 28
18928 + brle __avr32_f64_div_res_subnormal /* Result was subnormal. */
18931 +#if defined(L_avr32_f64_div)
18932 + /* In order to round correctly we calculate the remainder:
18933 + Remainder = dividend[11:r10] - divisor[r9:r8]*quotient[r3:r2]
18934 + for the case when the quotient is halfway between the round-up
18935 + value and the round down value. If the remainder then is negative
18936 + it means that the quotient was to big and that it should not be
18937 + rounded up, if the remainder is positive the quotient was to small
18938 + and we need to round up. If the remainder is zero it means that the
18939 + quotient is exact but since we need to remove the guard bit we should
18940 + round to even. */
18942 + /* Truncate and add guard bit. */
18947 + /* Now do the multiplication. The quotient has the format 4.60
18948 + while the divisor has the format 2.62 which gives a result
18950 + mulu.d r0, r3, r8
18951 + macu.d r0, r2, r9
18952 + mulu.d r4, r2, r8
18953 + mulu.d r8, r3, r9
18959 + /* Check if remainder is positive, negative or equal. */
18960 + bfextu r12, r2, 8, 1 /* Get parity bit into bit 0 of r0 */
18963 +__avr32_f64_div_round_subnormal:
18966 + srlo r6 /* Remainder positive: we need to round up.*/
18967 + moveq r6, r12 /* Remainder zero: round up if mantissa odd. */
18969 + bfextu r6, r2, 7, 1 /* Get guard bit */
18971 + /* Final packing, scale down mantissa. */
18973 + or r10, r10, r3<<24
18975 + /* Insert exponent and sign bit*/
18976 + bfins r11, r7, 20, 11
18980 + /* Final rounding */
18984 + /* Return result in [r11,r10] */
18985 + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
18989 + /* Op1 is NaN or inf */
18990 + andh r11, 0x000f /* Extract mantissa */
18992 + brne 16f /* Return NaN if op1 is NaN */
18993 + /* Op1 is inf check op2 */
18994 + lsr r6, r9, 20 /* Extract exponent */
18995 + cbr r6, 8 /* Clear sign bit */
18997 + brne 17f /* Inf/number gives inf, return inf */
18998 + rjmp 16f /* The rest gives NaN*/
19001 + /* Op1 is a valid number. Op 2 is NaN or inf */
19002 + andh r9, 0x000f /* Extract mantissa */
19004 + brne 16f /* Return NaN if op2 is NaN */
19005 + rjmp 15f /* Op2 was inf, return zero*/
19007 +11: /* Op1 was denormal. Fix it. */
19009 + or r11, r11, r10 >> 29
19011 + /* Check if op1 is zero. */
19013 + breq __avr32_f64_div_op1_zero
19014 + normalize_df r7 /*exp*/, r10, r11 /*Mantissa*/, r4, r5 /*scratch*/
19016 + or r10, r10, r11 << 30
19021 +13: /* Op2 was denormal. Fix it */
19023 + or r9, r9, r8 >> 29
19025 + /* Check if op2 is zero. */
19027 + breq 17f /* Divisor is zero -> return Inf */
19028 + normalize_df r6 /*exp*/, r8, r9 /*Mantissa*/, r4, r5 /*scratch*/
19030 + or r8, r8, r9 << 30
19035 +__avr32_f64_div_res_subnormal:/* Divide result was subnormal. */
19036 +#if defined(L_avr32_f64_div)
19037 + /* Check how much we must scale down the mantissa. */
19039 + sub r7, -1 /* We do no longer have an implicit bit. */
19040 + satu r7 >> 0, 6 /* Saturate shift amount to max 63. */
19043 + /* Shift amount <32 */
19044 + /* Scale down quotient */
19050 + /* Scale down the dividend to match the scaling of the quotient. */
19059 + /* Shift amount >=32 */
19069 + /* Scale down the dividend to match the scaling of the quotient. */
19075 + /* Start performing the same rounding as done for normal numbers
19076 + but this time we have scaled the quotient and dividend and hence
19077 + need a little different comparison. */
19078 + /* Truncate and add guard bit. */
19082 + /* Now do the multiplication. */
19083 + mulu.d r6, r3, r8
19084 + macu.d r6, r2, r9
19085 + mulu.d r4, r2, r8
19086 + mulu.d r8, r3, r9
19091 + /* Set exponent to 0 */
19094 + /* Check if remainder is positive, negative or equal. */
19095 + bfextu r12, r2, 8, 1 /* Get parity bit into bit 0 of r0 */
19098 + /* Now the rest of the rounding is the same as for normals. */
19099 + rjmp __avr32_f64_div_round_subnormal
19103 + /* Flush to zero for the fast version. */
19104 + mov r11, lr /*Get correct sign*/
19105 + andh r11, 0x8000, COH
19107 + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
19109 +16: /* Return NaN. */
19112 + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
19114 +17: /* Return INF. */
19115 + mov r11, lr /*Get correct sign*/
19116 + andh r11, 0x8000, COH
19119 + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc
19121 +__avr32_f64_div_op1_zero:
19122 + or r5, r8, r9 << 1
19123 + breq 16b /* 0.0/0.0 -> NaN */
19124 + bfextu r4, r9, 20, 11
19126 + brne 15b /* Return zero */
19127 + /* Check if divisor is Inf or NaN */
19128 + or r5, r8, r9 << 12
19129 + breq 15b /* Divisor is inf -> return zero */
19130 + rjmp 16b /* Return NaN */
19137 +#if defined(L_avr32_f32_addsub) || defined(L_avr32_f32_addsub_fast)
19140 +__avr32_f32_sub_from_add:
19141 + /* Switch sign on op2 */
19144 +#if defined(L_avr32_f32_addsub_fast)
19145 + .global __avr32_f32_sub_fast
19146 + .type __avr32_f32_sub_fast,@function
19147 +__avr32_f32_sub_fast:
19149 + .global __avr32_f32_sub
19150 + .type __avr32_f32_sub,@function
19154 + /* Check signs */
19156 + /* Different signs, use subtraction. */
19157 + brmi __avr32_f32_add_from_sub
19159 + /* Get sign of op1 */
19161 + andh r12, 0x8000, COH
19163 + /* Remove sign from operands */
19165 +#if defined(L_avr32_f32_addsub_fast)
19166 + reteq r8 /* If op2 is zero return op1 */
19170 + /* Put the number with the largest exponent in r10
19171 + and the number with the smallest exponent in r9 */
19174 + cp r10, r8 /*If largest operand (in R10) is not equal to op1*/
19175 + subne r12, 1 /* Subtract 1 from sign, which will invert MSB of r12*/
19176 + andh r12, 0x8000, COH /*Mask all but MSB*/
19178 + /* Unpack exponent and mantissa of op1 */
19180 + sbr r8, 31 /* Set implicit bit. */
19183 + /* op1 is NaN or Inf. */
19185 + breq __avr32_f32_sub_op1_nan_or_inf
19187 + /* Unpack exponent and mantissa of op2 */
19189 + sbr r11, 31 /* Set implicit bit. */
19192 +#if defined(L_avr32_f32_addsub)
19193 + /* Keep sticky bit for correct IEEE rounding */
19196 + /* op2 is either zero or subnormal. */
19197 + breq __avr32_f32_sub_op2_subnormal
19199 + /* Get shift amount to scale mantissa of op2. */
19202 + breq __avr32_f32_sub_shift_done
19204 + /* Saturate the shift amount to 31. If the amount
19205 + is any larger op2 is insignificant. */
19208 + /* Put the remaining bits into r9.*/
19212 + /* If the remaining bits are non-zero then we must subtract one
19213 + more from opL. */
19215 + srne r9 /* LSB of r9 represents sticky bits. */
19217 + /* Shift mantissa of op2 to same decimal point as the mantissa
19219 + lsr r11, r11, r12
19222 +__avr32_f32_sub_shift_done:
19223 + /* Now subtract the mantissas. */
19228 + /* Normalize resulting mantissa. */
19234 + brle __avr32_f32_sub_subnormal_result
19236 + /* Insert the bits we will remove from the mantissa into r9[31:24] */
19237 + or r9, r9, r8 << 24
19239 + /* Ignore sticky bit to simplify and speed up rounding */
19240 + /* op2 is either zero or subnormal. */
19241 + breq __avr32_f32_sub_op2_subnormal
19243 + /* Get shift amount to scale mantissa of op2. */
19246 + /* Saturate the shift amount to 31. If the amount
19247 + is any larger op2 is insignificant. */
19250 + /* Shift mantissa of op2 to same decimal point as the mantissa
19254 + /* Now subtract the mantissas. */
19257 + /* Normalize resulting mantissa. */
19262 + brle __avr32_f32_sub_subnormal_result
19265 + /* Pack result. */
19266 + or r12, r12, r8 >> 8
19267 + bfins r12, r10, 23, 8
19270 +__avr32_f32_sub_round:
19271 +#if defined(L_avr32_f32_addsub)
19272 + mov_imm r10, 0x80000000
19285 +__avr32_f32_sub_op2_subnormal:
19286 + /* Fix implicit bit and adjust exponent of subnormals. */
19288 + /* Set exponent to 1 if we do not have a zero. */
19291 + /* Check if op1 is also subnormal. */
19296 + /* If op1 is not zero set exponent to 1. */
19301 +__avr32_f32_sub_op1_nan_or_inf:
19302 + /* Check if op1 is NaN, if so return NaN */
19306 + /* op1 is Inf. */
19307 + bfins r12, r10, 23, 8 /* Generate Inf in r12 */
19309 + /* Check if op2 is Inf. or NaN */
19312 + retne r12 /* op2 not Inf or NaN, return op1 */
19314 + ret -1 /* op2 Inf or NaN, return NaN */
19316 +__avr32_f32_sub_subnormal_result:
19317 + /* Check if the number is so small that
19318 + it will be represented with zero. */
19320 + rsub r11, r10, 32
19323 + /* Shift the mantissa into the correct position.*/
19325 + /* Add sign bit. */
19328 + /* Put the shifted out bits in the most significant part
19332 +#if defined(L_avr32_f32_addsub)
19333 + /* Add all the remainder bits used for rounding into r9 */
19338 + rjmp __avr32_f32_sub_round
19343 +__avr32_f32_add_from_sub:
19344 + /* Switch sign on op2 */
19347 +#if defined(L_avr32_f32_addsub_fast)
19348 + .global __avr32_f32_add_fast
19349 + .type __avr32_f32_add_fast,@function
19350 +__avr32_f32_add_fast:
19352 + .global __avr32_f32_add
19353 + .type __avr32_f32_add,@function
19357 + /* Check signs */
19359 + /* Different signs, use subtraction. */
19360 + brmi __avr32_f32_sub_from_add
19362 + /* Get sign of op1 */
19364 + andh r12, 0x8000, COH
19366 + /* Remove sign from operands */
19368 +#if defined(L_avr32_f32_addsub_fast)
19369 + reteq r8 /* If op2 is zero return op1 */
19373 + /* Put the number with the largest exponent in r10
19374 + and the number with the smallest exponent in r9 */
19378 + /* Unpack exponent and mantissa of op1 */
19380 + sbr r8, 31 /* Set implicit bit. */
19383 + /* op1 is NaN or Inf. */
19385 + breq __avr32_f32_add_op1_nan_or_inf
19387 + /* Unpack exponent and mantissa of op2 */
19389 + sbr r11, 31 /* Set implicit bit. */
19392 +#if defined(L_avr32_f32_addsub)
19393 + /* op2 is either zero or subnormal. */
19394 + breq __avr32_f32_add_op2_subnormal
19396 + /* Keep sticky bit for correct IEEE rounding */
19399 + /* Get shift amount to scale mantissa of op2. */
19402 + /* Saturate the shift amount to 31. If the amount
19403 + is any larger op2 is insignificant. */
19406 + /* Shift mantissa of op2 to same decimal point as the mantissa
19410 + /* Put the remainding bits into r11[23:..].*/
19411 + rsub r9, r9, (32-8)
19413 + /* Insert the bits we will remove from the mantissa into r11[31:24] */
19414 + bfins r11, r12, 24, 8
19416 + /* Now add the mantissas. */
19421 + /* Ignore sticky bit to simplify and speed up rounding */
19422 + /* op2 is either zero or subnormal. */
19423 + breq __avr32_f32_add_op2_subnormal
19425 + /* Get shift amount to scale mantissa of op2. */
19428 + /* Saturate the shift amount to 31. If the amount
19429 + is any larger op2 is insignificant. */
19432 + /* Shift mantissa of op2 to same decimal point as the mantissa
19436 + /* Now add the mantissas. */
19440 + /* Check if we overflowed. */
19441 + brcs __avr32_f32_add_res_of
19443 + /* Pack result. */
19444 + or r12, r12, r8 >> 8
19445 + bfins r12, r10, 23, 8
19448 +#if defined(L_avr32_f32_addsub)
19449 + mov_imm r10, 0x80000000
19461 +__avr32_f32_add_op2_subnormal:
19462 + /* Fix implicit bit and adjust exponent of subnormals. */
19464 + /* Set exponent to 1 if we do not have a zero. */
19467 + /* Check if op1 is also subnormal. */
19470 + /* Both operands subnormal, just add the mantissas and
19471 + pack. If the addition of the subnormal numbers results
19472 + in a normal number then the exponent will automatically
19473 + be set to 1 by the addition. */
19476 + or r12, r12, r11 >> 8
19479 +__avr32_f32_add_op1_nan_or_inf:
19480 + /* Check if op1 is NaN, if so return NaN */
19484 + /* op1 is Inf. */
19485 + bfins r12, r10, 23, 8 /* Generate Inf in r12 */
19487 + /* Check if op2 is Inf. or NaN */
19490 + retne r12 /* op2 not Inf or NaN, return op1 */
19493 + reteq r12 /* op2 Inf return op1 */
19494 + ret -1 /* op2 is NaN, return NaN */
19496 +__avr32_f32_add_res_of:
19497 + /* We overflowed. Increase exponent and shift mantissa.*/
19501 + /* Clear mantissa to set result to Inf if the exponent is 255. */
19511 +#if defined(L_avr32_f32_div) || defined(L_avr32_f32_div_fast)
19514 +#if defined(L_avr32_f32_div_fast)
19515 + .global __avr32_f32_div_fast
19516 + .type __avr32_f32_div_fast,@function
19517 +__avr32_f32_div_fast:
19519 + .global __avr32_f32_div
19520 + .type __avr32_f32_div,@function
19524 + eor r8, r11, r12 /* MSB(r8) = Sign(op1) ^ Sign(op2) */
19528 + reteq 0 /* Return zero if op1 is zero */
19530 + breq 4f /* Check op2 for zero */
19536 + breq 11f /*If number is subnormal*/
19538 + brhs 2f /* Check op1 for NaN or Inf */
19540 + sbr r12, 31 /*Implicit bit*/
19547 + breq 13f /*If number is subnormal*/
19549 + brhs 3f /* Check op2 for NaN or Inf */
19552 + sbr r11, 31 /*Implicit bit*/
19555 + /* For UC3, store with predecrement is faster than stm */
19559 + /* Calculate new exponent */
19564 + /* Approximating 1/d with the following recurrence: */
19565 + /* R[j+1] = R[j]*(2-R[j]*d) */
19566 + /* Using 2.30 format */
19569 + /* Multiply result : r6, r7 */
19570 + /* Initial guess : r11 */
19571 + /* New approximations : r11 */
19572 + /* Dividend : r12 */
19575 + mov_imm r10, 0x80000000
19577 + lsr r12, 2 /* Get significand of Op1 in 2.30 format */
19578 + lsr r5, r11, 2 /* Get significand of Op2 (=d) in 2.30 format */
19580 + /* Load initial guess, using look-up table */
19581 + /* Initial guess is of format 01.XY, where XY is constructed as follows: */
19582 + /* Let d be of following format: 00.1xy....., then XY=~xy */
19583 + /* For d=00.100 = 0,5 -> initial guess=01.11 = 1,75 */
19584 + /* For d=00.101 = 0,625 -> initial guess=01.11 = 1,5 */
19585 + /* For d=00.110 = 0,75 -> initial guess=01.11 = 1,25 */
19586 + /* For d=00.111 = 0,875 -> initial guess=01.11 = 1,0 */
19589 + bfextu r6, r5, 27, 2
19591 + bfins r11, r6, 28, 2
19593 + /* First approximation */
19594 + /* r7 = R[j]*d */
19595 + mulu.d r6, r11, r5
19596 + /* r7 = 2-R[j]*d */
19597 + sub r7, r10, r7<<2
19598 + /* r11 = R[j]*(2-R[j]*d) */
19599 + mulu.d r6, r11, r7
19602 + /* Second approximation */
19603 + /* r7 = R[j]*d */
19604 + mulu.d r6, r11, r5
19605 + /* r7 = 2-R[j]*d */
19606 + sub r7, r10, r7<<2
19607 + /* r11 = R[j]*(2-R[j]*d) */
19608 + mulu.d r6, r11, r7
19611 + /* Third approximation */
19612 + /* r7 = R[j]*d */
19613 + mulu.d r6, r11, r5
19614 + /* r7 = 2-R[j]*d */
19615 + sub r7, r10, r7<<2
19616 + /* r11 = R[j]*(2-R[j]*d) */
19617 + mulu.d r6, r11, r7
19620 + /* Fourth approximation */
19621 + /* r7 = R[j]*d */
19622 + mulu.d r6, r11, r5
19623 + /* r7 = 2-R[j]*d */
19624 + sub r7, r10, r7<<2
19625 + /* r11 = R[j]*(2-R[j]*d) */
19626 + mulu.d r6, r11, r7
19630 + /* Multiply with dividend to get quotient, r7 = sf(op1)/sf(op2) */
19631 + mulu.d r6, r11, r12
19633 + /* Shift by 3 to get result in 1.31 format, as required by the exponent. */
19634 + /* Note that 1.31 format is already used by the exponent in r9, since */
19635 + /* a bias of 127 was added to the result exponent, even though the implicit */
19636 + /* bit was inserted. This gives the exponent an additional bias of 1, which */
19637 + /* supports 1.31 format. */
19640 + /* Adjust exponent and mantissa in case the result is of format
19641 + 0000.1xxx to 0001.xxx*/
19642 +#if defined(L_avr32_f32_div)
19643 + lsr r12, 4 /* Scale dividend to 6.26 format to match the
19644 + result of the multiplication of the divisor and
19645 + quotient to get the remainder. */
19651 +#if defined(L_avr32_f32_div)
19652 + lsl r12, 1 /* Scale dividend to 5.27 format to match the
19653 + result of the multiplication of the divisor and
19654 + quotient to get the remainder. */
19658 + brle __avr32_f32_div_res_subnormal /* Result was subnormal. */
19661 +#if defined(L_avr32_f32_div)
19662 + /* In order to round correctly we calculate the remainder:
19663 + Remainder = dividend[r12] - divisor[r5]*quotient[r7]
19664 + for the case when the quotient is halfway between the round-up
19665 + value and the round down value. If the remainder then is negative
19666 + it means that the quotient was to big and that it should not be
19667 + rounded up, if the remainder is positive the quotient was to small
19668 + and we need to round up. If the remainder is zero it means that the
19669 + quotient is exact but since we need to remove the guard bit we should
19670 + round to even. */
19674 + /* Now do the multiplication. The quotient has the format 4.28
19675 + while the divisor has the format 2.30 which gives a result
19677 + mulu.d r10, r5, r7
19679 + /* Check if remainder is positive, negative or equal. */
19680 + bfextu r5, r7, 5, 1 /* Get parity bit into bit 0 of r5 */
19682 +__avr32_f32_div_round_subnormal:
19684 + srlo r11 /* Remainder positive: we need to round up.*/
19685 + moveq r11, r5 /* Remainder zero: round up if mantissa odd. */
19687 + bfextu r11, r7, 4, 1 /* Get guard bit */
19690 + /* Pack final result*/
19692 + bfins r12, r9, 23, 8
19693 + /* For UC3, load with postincrement is faster than ldm */
19698 + /* Rounding add. */
19702 +__divsf_return_op1:
19709 + /* Op1 is NaN or inf */
19710 + retne -1 /* Return NaN if op1 is NaN */
19711 + /* Op1 is inf check op2 */
19712 + mov_imm r9, 0xff000000
19714 + brlo __divsf_return_op1 /* inf/number gives inf */
19715 + ret -1 /* The rest gives NaN*/
19717 + /* Op2 is NaN or inf */
19718 + reteq 0 /* Return zero if number/inf*/
19719 + ret -1 /* Return NaN*/
19721 + /* Op2 is zero ? */
19723 + reteq -1 /* 0.0/0.0 is NaN */
19724 + /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/
19725 + mov_imm r12, 0xff000000
19726 + rjmp __divsf_return_op1
19728 +11: /* Op1 was denormal. Fix it. */
19735 +13: /* Op2 was denormal. Fix it. */
19743 +__avr32_f32_div_res_subnormal: /* Divide result was subnormal */
19744 +#if defined(L_avr32_f32_div)
19745 + /* Check how much we must scale down the mantissa. */
19747 + sub r9, -1 /* We do no longer have an implicit bit. */
19748 + satu r9 >> 0, 5 /* Saturate shift amount to max 32. */
19749 + /* Scale down quotient */
19752 + /* Scale down the dividend to match the scaling of the quotient. */
19753 + lsl r6, r12, r10 /* Make the divident 64-bit and put the lsw in r6 */
19756 + /* Start performing the same rounding as done for normal numbers
19757 + but this time we have scaled the quotient and dividend and hence
19758 + need a little different comparison. */
19762 + /* Now do the multiplication. The quotient has the format 4.28
19763 + while the divisor has the format 2.30 which gives a result
19765 + mulu.d r10, r5, r7
19767 + /* Set exponent to 0 */
19770 + /* Check if remainder is positive, negative or equal. */
19771 + bfextu r5, r7, 5, 1 /* Get parity bit into bit 0 of r5 */
19773 + rjmp __avr32_f32_div_round_subnormal
19778 + /*Flush to zero*/
19783 +#ifdef L_avr32_f32_mul
19784 + .global __avr32_f32_mul
19785 + .type __avr32_f32_mul,@function
19790 + eor r12, r11 /* MSB(r8) = Sign(op1) ^ Sign(op2) */
19791 + andh r12, 0x8000, COH
19793 + /* arrange operands so that that op1 >= op2 */
19795 + breq __avr32_f32_mul_op1_zero
19798 + /* Put the number with the largest exponent in r10
19799 + and the number with the smallest exponent in r9 */
19803 + /* Unpack exponent and mantissa of op1 */
19805 + sbr r8, 31 /* Set implicit bit. */
19808 + /* op1 is NaN or Inf. */
19810 + breq __avr32_f32_mul_op1_nan_or_inf
19812 + /* Unpack exponent and mantissa of op2 */
19814 + sbr r11, 31 /* Set implicit bit. */
19817 + /* op2 is either zero or subnormal. */
19818 + breq __avr32_f32_mul_op2_subnormal
19820 + /* Calculate new exponent */
19823 + /* Do the multiplication */
19824 + mulu.d r10,r8,r11
19826 + /* We might need to scale up by two if the MSB of the result is
19832 + /* Put the shifted out bits of the mantissa into r10 */
19834 + bfins r10, r11, 24, 8
19836 + sub r9,(127-1) /* remove extra exponent bias */
19837 + brle __avr32_f32_mul_res_subnormal
19839 + /* Check for Inf. */
19843 + /* Pack result. */
19844 + or r12, r12, r11 >> 8
19845 + bfins r12, r9, 23, 8
19848 +__avr32_f32_mul_round:
19849 + mov_imm r8, 0x80000000
19863 +__avr32_f32_mul_op2_subnormal:
19866 + retcs 0 /* op2 is zero. Return 0 */
19870 + /* Check if op2 is subnormal. */
19874 + /* op2 is subnormal */
19877 + retcs 0 /* op1 is zero. Return 0 */
19884 +__avr32_f32_mul_op1_nan_or_inf:
19885 + /* Check if op1 is NaN, if so return NaN */
19889 + /* op1 is Inf. */
19891 + reteq -1 /* Inf * 0 -> NaN */
19893 + bfins r12, r10, 23, 8 /* Generate Inf in r12 */
19895 + /* Check if op2 is Inf. or NaN */
19898 + retne r12 /* op2 not Inf or NaN, return Info */
19901 + reteq r12 /* op2 Inf return Inf */
19902 + ret -1 /* op2 is NaN, return NaN */
19904 +__avr32_f32_mul_res_subnormal:
19905 + /* Check if the number is so small that
19906 + it will be represented with zero. */
19911 + /* Shift the mantissa into the correct position.*/
19913 + /* Add sign bit. */
19915 + /* Put the shifted out bits in the most significant part
19919 + /* Add all the remainder bits used for rounding into r11 */
19922 + rjmp __avr32_f32_mul_round
19924 +__avr32_f32_mul_op1_zero:
19925 + bfextu r10, r11, 23, 8
19933 +#ifdef L_avr32_s32_to_f32
19934 + .global __avr32_s32_to_f32
19935 + .type __avr32_s32_to_f32,@function
19936 +__avr32_s32_to_f32:
19938 + reteq r12 /* If zero then return zero float */
19939 + mov r11, r12 /* Keep the sign */
19940 + abs r12 /* Compute the absolute value */
19941 + mov r10, 31 + 127 /* Set the correct exponent */
19944 + normalize_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
19946 + /* Check for subnormal result */
19948 + brle __avr32_s32_to_f32_subnormal
19950 + round_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
19951 + pack_sf r12 /*sf*/, r10 /*exp*/, r12 /*mant*/
19956 +__avr32_s32_to_f32_subnormal:
19957 + /* Adjust a subnormal result */
19958 + adjust_subnormal_sf r12/*sf*/, r10 /*exp*/, r12 /*mant*/, r11/*sign*/, r9 /*scratch*/
19963 +#ifdef L_avr32_u32_to_f32
19964 + .global __avr32_u32_to_f32
19965 + .type __avr32_u32_to_f32,@function
19966 +__avr32_u32_to_f32:
19968 + reteq r12 /* If zero then return zero float */
19969 + mov r10, 31 + 127 /* Set the correct exponent */
19972 + normalize_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
19974 + /* Check for subnormal result */
19976 + brle __avr32_u32_to_f32_subnormal
19978 + round_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/
19979 + pack_sf r12 /*sf*/, r10 /*exp*/, r12 /*mant*/
19980 + lsr r12,1 /* Sign bit is 0 for unsigned int */
19983 +__avr32_u32_to_f32_subnormal:
19984 + /* Adjust a subnormal result */
19986 + adjust_subnormal_sf r12/*sf*/,r10 /*exp*/, r12 /*mant*/,r8/*sign*/, r9 /*scratch*/
19993 +#ifdef L_avr32_f32_to_s32
19994 + .global __avr32_f32_to_s32
19995 + .type __avr32_f32_to_s32,@function
19996 +__avr32_f32_to_s32:
19997 + bfextu r11, r12, 23, 8
19998 + sub r11,127 /* Fix bias */
19999 + retlo 0 /* Negative exponent yields zero integer */
20001 + /* Shift mantissa into correct position */
20002 + rsub r11,r11,31 /* Shift amount */
20003 + lsl r10,r12,8 /* Get mantissa */
20004 + sbr r10,31 /* Add implicit bit */
20005 + lsr r10,r10,r11 /* Perform shift */
20006 + lsl r12,1 /* Check sign */
20007 + retcc r10 /* if positive, we are done */
20008 + neg r10 /* if negative float, negate result */
20013 +#ifdef L_avr32_f32_to_u32
20014 + .global __avr32_f32_to_u32
20015 + .type __avr32_f32_to_u32,@function
20016 +__avr32_f32_to_u32:
20018 + retmi 0 /* Negative numbers gives 0 */
20019 + bfextu r11, r12, 23, 8 /* Extract exponent */
20020 + sub r11,127 /* Fix bias */
20021 + retlo 0 /* Negative exponent yields zero integer */
20023 + /* Shift mantissa into correct position */
20024 + rsub r11,r11,31 /* Shift amount */
20025 + lsl r12,8 /* Get mantissa */
20026 + sbr r12,31 /* Add implicit bit */
20027 + lsr r12,r12,r11 /* Perform shift */
20032 +#ifdef L_avr32_f32_to_f64
20033 + .global __avr32_f32_to_f64
20034 + .type __avr32_f32_to_f64,@function
20036 +__avr32_f32_to_f64:
20037 + lsl r11,r12,1 /* Remove sign bit, keep original value in r12*/
20039 + reteq r11 /* Return zero if input is zero */
20041 + bfextu r9,r11,24,8 /* Get exponent */
20042 + cp.w r9,0xff /* check for NaN or inf */
20045 + lsl r11,7 /* Convert sf mantissa to df format */
20048 + /* Check if implicit bit should be set */
20050 + subeq r9,-1 /* Adjust exponent if it was 0 */
20052 + or r11, r11, r8 << 31 /* Set implicit bit if needed */
20053 + sub r9,(127-0x3ff) /* Convert exponent to df format exponent */
20055 + /*We know that low register of mantissa is 0, and will be unaffected by normalization.*/
20056 + /*We can therefore use the faster normalize_sf function instead of normalize_df.*/
20057 + normalize_sf r9 /*exp*/, r11 /*mantissa*/, r8 /*scratch*/
20058 + pack_df r9 /*exp*/, r10, r11 /*mantissa*/, r10, r11 /*df*/
20060 +__extendsfdf_return_op1:
20061 + /* Rotate in sign bit */
20068 + mov_imm r10, 0xffe00000
20069 + lsl r11,8 /* check mantissa */
20070 + movne r11, -1 /* Return NaN */
20071 + moveq r11, r10 /* Return inf */
20072 + rjmp __extendsfdf_return_op1
20076 +#ifdef L_avr32_f64_to_f32
20077 + .global __avr32_f64_to_f32
20078 + .type __avr32_f64_to_f32,@function
20080 +__avr32_f64_to_f32:
20082 + lsl r9,r11,1 /* Unpack exponent */
20085 + reteq 0 /* If exponent is 0 the number is so small
20086 + that the conversion to single float gives
20089 + lsl r8,r11,10 /* Adjust mantissa */
20090 + or r12,r8,r10>>22
20092 + lsl r10,10 /* Check if there are any remaining bits
20093 + in the low part of the mantissa.*/
20095 + rol r12 /* If there were remaining bits then set lsb
20096 + of mantissa to 1 */
20099 + breq 2f /* Check for NaN or inf */
20101 + sub r9,(0x3ff-127) /* Adjust bias of exponent */
20102 + sbr r12,31 /* set the implicit bit.*/
20104 + cp.w r9, 0 /* Check for subnormal number */
20107 + round_sf r9 /*exp*/, r12 /*mant*/, r10 /*scratch*/
20108 + pack_sf r12 /*sf*/, r9 /*exp*/, r12 /*mant*/
20109 +__truncdfsf_return_op1:
20110 + /* Rotate in sign bit */
20117 + cbr r12,31 /* clear implicit bit */
20118 + retne -1 /* Return NaN if mantissa not zero */
20119 + mov_imm r12, 0xff000000
20120 + ret r12 /* Return inf */
20122 +3: /* Result is subnormal. Adjust it.*/
20123 + adjust_subnormal_sf r12/*sf*/,r9 /*exp*/, r12 /*mant*/, r11/*sign*/, r10 /*scratch*/
20129 +#if defined(L_mulsi3) && (__AVR32_UC__ == 3)
20131 + .type __mulsi3,@function
20137 + addcs r9, r9, r12
20145 +++ b/gcc/config/avr32/lib2funcs.S
20148 + .global __nonlocal_goto
20149 + .type __nonlocal_goto,@function
20151 +/* __nonlocal_goto: This function handles nonlocal_goto's in gcc.
20153 + parameter 0 (r12) = New Frame Pointer
20154 + parameter 1 (r11) = Address to goto
20155 + parameter 2 (r10) = New Stack Pointer
20157 + This function invalidates the return stack, since it returns from a
20158 + function without using a return instruction.
20163 + frs # Flush return stack
20169 +++ b/gcc/config/avr32/linux-elf.h
20172 + Linux/Elf specific definitions.
20173 + Copyright 2003-2006 Atmel Corporation.
20175 + Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
20176 + and H�vard Skinnemoen, Atmel Norway, <hskinnemoen@atmel.com>
20178 + This file is part of GCC.
20180 + This program is free software; you can redistribute it and/or modify
20181 + it under the terms of the GNU General Public License as published by
20182 + the Free Software Foundation; either version 2 of the License, or
20183 + (at your option) any later version.
20185 + This program is distributed in the hope that it will be useful,
20186 + but WITHOUT ANY WARRANTY; without even the implied warranty of
20187 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20188 + GNU General Public License for more details.
20190 + You should have received a copy of the GNU General Public License
20191 + along with this program; if not, write to the Free Software
20192 + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
20196 +/* elfos.h should have already been included. Now just override
20197 + any conflicting definitions and add any extras. */
20199 +/* Run-time Target Specification. */
20200 +#undef TARGET_VERSION
20201 +#define TARGET_VERSION fputs (" (AVR32 GNU/Linux with ELF)", stderr);
20203 +/* Do not assume anything about header files. */
20204 +#define NO_IMPLICIT_EXTERN_C
20206 +/* The GNU C++ standard library requires that these macros be defined. */
20207 +#undef CPLUSPLUS_CPP_SPEC
20208 +#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)"
20210 +/* Now we define the strings used to build the spec file. */
20212 +#define LIB_SPEC \
20213 + "%{pthread:-lpthread} \
20215 + %{!shared:%{profile:-lc_p}%{!profile:-lc}}"
20217 +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add
20218 + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which
20219 + provides part of the support for getting C++ file-scope static
20220 + object constructed before entering `main'. */
20222 +#undef STARTFILE_SPEC
20223 +#define STARTFILE_SPEC \
20225 + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \
20226 + %{!p:%{profile:gcrt1.o%s} \
20227 + %{!profile:crt1.o%s}}}} \
20228 + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}"
20230 +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on
20231 + the GNU/Linux magical crtend.o file (see crtstuff.c) which
20232 + provides part of the support for getting C++ file-scope static
20233 + object constructed before entering `main', followed by a normal
20234 + GNU/Linux "finalizer" file, `crtn.o'. */
20236 +#undef ENDFILE_SPEC
20237 +#define ENDFILE_SPEC \
20238 + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s"
20241 +#define ASM_SPEC "%{!mno-pic:%{!fno-pic:--pic}} %{mrelax|O*:%{mno-relax|O0|O1: ;:--linkrelax}} %{mcpu=*:-mcpu=%*}"
20244 +#define LINK_SPEC "%{version:-v} \
20245 + %{static:-Bstatic} \
20246 + %{shared:-shared} \
20247 + %{symbolic:-Bsymbolic} \
20248 + %{rdynamic:-export-dynamic} \
20249 + %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0} \
20250 + %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}}"
20252 +#define TARGET_OS_CPP_BUILTINS() LINUX_TARGET_OS_CPP_BUILTINS()
20254 +/* This is how we tell the assembler that two symbols have the same value. */
20255 +#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \
20258 + assemble_name (FILE, NAME1); \
20259 + fputs (" = ", FILE); \
20260 + assemble_name (FILE, NAME2); \
20261 + fputc ('\n', FILE); \
20268 +#define CC1_SPEC "%{profile:-p}"
20270 +/* Target CPU builtins. */
20271 +#define TARGET_CPU_CPP_BUILTINS() \
20274 + builtin_define ("__avr32__"); \
20275 + builtin_define ("__AVR32__"); \
20276 + builtin_define ("__AVR32_LINUX__"); \
20277 + builtin_define (avr32_part->macro); \
20278 + builtin_define (avr32_arch->macro); \
20279 + if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \
20280 + builtin_define ("__AVR32_AVR32A__"); \
20282 + builtin_define ("__AVR32_AVR32B__"); \
20283 + if (TARGET_UNALIGNED_WORD) \
20284 + builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \
20285 + if (TARGET_SIMD) \
20286 + builtin_define ("__AVR32_HAS_SIMD__"); \
20287 + if (TARGET_DSP) \
20288 + builtin_define ("__AVR32_HAS_DSP__"); \
20289 + if (TARGET_RMW) \
20290 + builtin_define ("__AVR32_HAS_RMW__"); \
20291 + if (TARGET_BRANCH_PRED) \
20292 + builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \
20293 + if (TARGET_FAST_FLOAT) \
20294 + builtin_define ("__AVR32_FAST_FLOAT__"); \
20300 +/* Call the function profiler with a given profile label. */
20301 +#undef FUNCTION_PROFILER
20302 +#define FUNCTION_PROFILER(STREAM, LABELNO) \
20305 + fprintf (STREAM, "\tmov\tlr, lo(mcount)\n\torh\tlr, hi(mcount)\n"); \
20306 + fprintf (STREAM, "\ticall lr\n"); \
20310 +#define NO_PROFILE_COUNTERS 1
20312 +/* For dynamic libraries to work */
20313 +/* #define PLT_REG_CALL_CLOBBERED 1 */
20314 +#define AVR32_ALWAYS_PIC 1
20316 +/* uclibc does not implement sinf, cosf etc. */
20317 +#undef TARGET_C99_FUNCTIONS
20318 +#define TARGET_C99_FUNCTIONS 0
20320 +#define LINK_GCC_C_SEQUENCE_SPEC \
20321 + "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
20323 +++ b/gcc/config/avr32/predicates.md
20325 +;; AVR32 predicates file.
20326 +;; Copyright 2003-2006 Atmel Corporation.
20328 +;; Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
20330 +;; This file is part of GCC.
20332 +;; This program is free software; you can redistribute it and/or modify
20333 +;; it under the terms of the GNU General Public License as published by
20334 +;; the Free Software Foundation; either version 2 of the License, or
20335 +;; (at your option) any later version.
20337 +;; This program is distributed in the hope that it will be useful,
20338 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
20339 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20340 +;; GNU General Public License for more details.
20342 +;; You should have received a copy of the GNU General Public License
20343 +;; along with this program; if not, write to the Free Software
20344 +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20347 +;; True if the operand is a memory reference which contains an
20348 +;; Address consisting of a single pointer register
20349 +(define_predicate "avr32_indirect_register_operand"
20350 + (and (match_code "mem")
20351 + (match_test "register_operand(XEXP(op, 0), SImode)")))
20355 +;; Address expression with a base pointer offset with
20356 +;; a register displacement
20357 +(define_predicate "avr32_indexed_memory_operand"
20358 + (and (match_code "mem")
20359 + (match_test "GET_CODE(XEXP(op, 0)) == PLUS"))
20362 + rtx op0 = XEXP(XEXP(op, 0), 0);
20363 + rtx op1 = XEXP(XEXP(op, 0), 1);
20365 + return ((avr32_address_register_rtx_p (op0, 0)
20366 + && avr32_legitimate_index_p (GET_MODE(op), op1, 0))
20367 + || (avr32_address_register_rtx_p (op1, 0)
20368 + && avr32_legitimate_index_p (GET_MODE(op), op0, 0)));
20372 +;; Operand suitable for the ld.sb instruction
20373 +(define_predicate "load_sb_memory_operand"
20374 + (ior (match_operand 0 "avr32_indirect_register_operand")
20375 + (match_operand 0 "avr32_indexed_memory_operand")))
20378 +;; Operand suitable as operand to insns sign extending QI values
20379 +(define_predicate "extendqi_operand"
20380 + (ior (match_operand 0 "load_sb_memory_operand")
20381 + (match_operand 0 "register_operand")))
20383 +(define_predicate "post_inc_memory_operand"
20384 + (and (match_code "mem")
20385 + (match_test "(GET_CODE(XEXP(op, 0)) == POST_INC)
20386 + && REG_P(XEXP(XEXP(op, 0), 0))")))
20388 +(define_predicate "pre_dec_memory_operand"
20389 + (and (match_code "mem")
20390 + (match_test "(GET_CODE(XEXP(op, 0)) == PRE_DEC)
20391 + && REG_P(XEXP(XEXP(op, 0), 0))")))
20393 +;; Operand suitable for add instructions
20394 +(define_predicate "avr32_add_operand"
20395 + (ior (match_operand 0 "register_operand")
20396 + (and (match_operand 0 "immediate_operand")
20397 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'I', \"Is21\")"))))
20399 +;; Operand is a power of two immediate
20400 +(define_predicate "power_of_two_operand"
20401 + (match_code "const_int")
20403 + HOST_WIDE_INT value = INTVAL (op);
20405 + return value != 0 && (value & (value - 1)) == 0;
20408 +;; Operand is a multiple of 8 immediate
20409 +(define_predicate "multiple_of_8_operand"
20410 + (match_code "const_int")
20412 + HOST_WIDE_INT value = INTVAL (op);
20414 + return (value & 0x7) == 0 ;
20417 +;; Operand is a multiple of 16 immediate
20418 +(define_predicate "multiple_of_16_operand"
20419 + (match_code "const_int")
20421 + HOST_WIDE_INT value = INTVAL (op);
20423 + return (value & 0xf) == 0 ;
20426 +;; Operand is a mask used for masking away upper bits of a reg
20427 +(define_predicate "avr32_mask_upper_bits_operand"
20428 + (match_code "const_int")
20430 + HOST_WIDE_INT value = INTVAL (op) + 1;
20432 + return value != 1 && value != 0 && (value & (value - 1)) == 0;
20436 +;; Operand suitable for mul instructions
20437 +(define_predicate "avr32_mul_operand"
20438 + (ior (match_operand 0 "register_operand")
20439 + (and (match_operand 0 "immediate_operand")
20440 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")"))))
20442 +;; True for logical binary operators.
20443 +(define_predicate "logical_binary_operator"
20444 + (match_code "ior,xor,and"))
20446 +;; True for logical shift operators
20447 +(define_predicate "logical_shift_operator"
20448 + (match_code "ashift,lshiftrt"))
20450 +;; True for shift operand for logical and, or and eor insns
20451 +(define_predicate "avr32_logical_shift_operand"
20452 + (and (match_code "ashift,lshiftrt")
20453 + (ior (and (match_test "GET_CODE(XEXP(op, 1)) == CONST_INT")
20454 + (match_test "register_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))"))
20455 + (and (match_test "GET_CODE(XEXP(op, 0)) == CONST_INT")
20456 + (match_test "register_operand(XEXP(op, 1), GET_MODE(XEXP(op, 1)))"))))
20460 +;; Predicate for second operand to and, ior and xor insn patterns
20461 +(define_predicate "avr32_logical_insn_operand"
20462 + (ior (match_operand 0 "register_operand")
20463 + (match_operand 0 "avr32_logical_shift_operand"))
20467 +;; True for avr32 comparison operators
20468 +(define_predicate "avr32_comparison_operator"
20469 + (ior (match_code "eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu")
20470 + (and (match_code "unspec")
20471 + (match_test "(XINT(op, 1) == UNSPEC_COND_MI)
20472 + || (XINT(op, 1) == UNSPEC_COND_PL)"))))
20474 +(define_predicate "avr32_cond3_comparison_operator"
20475 + (ior (match_code "eq, ne, ge, lt, geu, ltu")
20476 + (and (match_code "unspec")
20477 + (match_test "(XINT(op, 1) == UNSPEC_COND_MI)
20478 + || (XINT(op, 1) == UNSPEC_COND_PL)"))))
20480 +;; True for avr32 comparison operand
20481 +(define_predicate "avr32_comparison_operand"
20482 + (ior (and (match_code "eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu")
20483 + (match_test "(CC0_P (XEXP(op,0)) && rtx_equal_p (XEXP(op,1), const0_rtx))"))
20484 + (and (match_code "unspec")
20485 + (match_test "(XINT(op, 1) == UNSPEC_COND_MI)
20486 + || (XINT(op, 1) == UNSPEC_COND_PL)"))))
20488 +;; True if this is a const_int with one bit set
20489 +(define_predicate "one_bit_set_operand"
20490 + (match_code "const_int")
20496 + value = INTVAL(op);
20497 + for ( i = 0 ; i < 32; i++ ){
20498 + if ( value & ( 1 << i ) ){
20503 + return ( ones == 1 );
20507 +;; True if this is a const_int with one bit cleared
20508 +(define_predicate "one_bit_cleared_operand"
20509 + (match_code "const_int")
20515 + value = INTVAL(op);
20516 + for ( i = 0 ; i < 32; i++ ){
20517 + if ( !(value & ( 1 << i )) ){
20522 + return ( zeroes == 1 );
20526 +;; Immediate all the low 16-bits cleared
20527 +(define_predicate "avr32_hi16_immediate_operand"
20528 + (match_code "const_int")
20530 + /* If the low 16-bits are zero then this
20531 + is a hi16 immediate. */
20532 + return ((INTVAL(op) & 0xffff) == 0);
20536 +;; True if this is a register or immediate operand
20537 +(define_predicate "register_immediate_operand"
20538 + (ior (match_operand 0 "register_operand")
20539 + (match_operand 0 "immediate_operand")))
20541 +;; True if this is a register or const_int operand
20542 +(define_predicate "register_const_int_operand"
20543 + (ior (match_operand 0 "register_operand")
20544 + (and (match_operand 0 "const_int_operand")
20545 + (match_operand 0 "immediate_operand"))))
20547 +;; True if this is a register or const_double operand
20548 +(define_predicate "register_const_double_operand"
20549 + (ior (match_operand 0 "register_operand")
20550 + (match_operand 0 "const_double_operand")))
20552 +;; True is this is an operand containing a label_ref
20553 +(define_predicate "avr32_label_ref_operand"
20554 + (and (match_code "mem")
20555 + (match_test "avr32_find_symbol(op)
20556 + && (GET_CODE(avr32_find_symbol(op)) == LABEL_REF)")))
20558 +;; True is this is a valid symbol pointing to the constant pool
20559 +(define_predicate "avr32_const_pool_operand"
20560 + (and (match_code "symbol_ref")
20561 + (match_test "CONSTANT_POOL_ADDRESS_P(op)"))
20563 + return (flag_pic ? (!(symbol_mentioned_p (get_pool_constant (op))
20564 + || label_mentioned_p (get_pool_constant (op)))
20565 + || avr32_got_mentioned_p(get_pool_constant (op)))
20570 +;; True is this is a memory reference to the constant or mini pool
20571 +(define_predicate "avr32_const_pool_ref_operand"
20572 + (ior (match_operand 0 "avr32_label_ref_operand")
20573 + (and (match_code "mem")
20574 + (match_test "avr32_const_pool_operand(XEXP(op,0), GET_MODE(XEXP(op,0)))"))))
20577 +;; Legal source operand for movti insns
20578 +(define_predicate "avr32_movti_src_operand"
20579 + (ior (match_operand 0 "avr32_const_pool_ref_operand")
20580 + (ior (ior (match_operand 0 "register_immediate_operand")
20581 + (match_operand 0 "avr32_indirect_register_operand"))
20582 + (match_operand 0 "post_inc_memory_operand"))))
20584 +;; Legal destination operand for movti insns
20585 +(define_predicate "avr32_movti_dst_operand"
20586 + (ior (ior (match_operand 0 "register_operand")
20587 + (match_operand 0 "avr32_indirect_register_operand"))
20588 + (match_operand 0 "pre_dec_memory_operand")))
20591 +;; True is this is a k12 offseted memory operand
20592 +(define_predicate "avr32_k12_memory_operand"
20593 + (and (match_code "mem")
20594 + (ior (match_test "REG_P(XEXP(op, 0))")
20595 + (match_test "GET_CODE(XEXP(op, 0)) == PLUS
20596 + && REG_P(XEXP(XEXP(op, 0), 0))
20597 + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)
20598 + && (CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(XEXP(op, 0), 0)),
20599 + 'K', (mode == SImode) ? \"Ks14\" : ((mode == HImode) ? \"Ks13\" : \"Ks12\")))"))))
20601 +;; True is this is a memory operand with an immediate displacement
20602 +(define_predicate "avr32_imm_disp_memory_operand"
20603 + (and (match_code "mem")
20604 + (match_test "GET_CODE(XEXP(op, 0)) == PLUS
20605 + && REG_P(XEXP(XEXP(op, 0), 0))
20606 + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)")))
20608 +;; True is this is a bswap operand
20609 +(define_predicate "avr32_bswap_operand"
20610 + (ior (match_operand 0 "avr32_k12_memory_operand")
20611 + (match_operand 0 "register_operand")))
20613 +;; True is this is a valid coprocessor insn memory operand
20614 +(define_predicate "avr32_cop_memory_operand"
20615 + (and (match_operand 0 "memory_operand")
20616 + (not (match_test "GET_CODE(XEXP(op, 0)) == PLUS
20617 + && REG_P(XEXP(XEXP(op, 0), 0))
20618 + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)
20619 + && !(CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(XEXP(op, 0), 0)), 'K', \"Ku10\"))"))))
20621 +;; True is this is a valid source/destination operand
20622 +;; for moving values to/from a coprocessor
20623 +(define_predicate "avr32_cop_move_operand"
20624 + (ior (match_operand 0 "register_operand")
20625 + (match_operand 0 "avr32_cop_memory_operand")))
20628 +;; True is this is a valid extract byte offset for use in
20629 +;; load extracted index insns
20630 +(define_predicate "avr32_extract_shift_operand"
20631 + (and (match_operand 0 "const_int_operand")
20632 + (match_test "(INTVAL(op) == 0) || (INTVAL(op) == 8)
20633 + || (INTVAL(op) == 16) || (INTVAL(op) == 24)")))
20635 +;; True is this is a floating-point register
20636 +(define_predicate "avr32_fp_register_operand"
20637 + (and (match_operand 0 "register_operand")
20638 + (match_test "REGNO_REG_CLASS(REGNO(op)) == FP_REGS")))
20640 +;; True is this is valid avr32 symbol operand
20641 +(define_predicate "avr32_symbol_operand"
20642 + (and (match_code "label_ref, symbol_ref, const")
20643 + (match_test "avr32_find_symbol(op)")))
20645 +;; True is this is valid operand for the lda.w and call pseudo insns
20646 +(define_predicate "avr32_address_operand"
20647 + (and (and (match_code "label_ref, symbol_ref")
20648 + (match_test "avr32_find_symbol(op)"))
20649 + (ior (match_test "TARGET_HAS_ASM_ADDR_PSEUDOS")
20650 + (match_test "flag_pic")) ))
20652 +;; An immediate k16 address operand
20653 +(define_predicate "avr32_ks16_address_operand"
20654 + (and (match_operand 0 "address_operand")
20655 + (ior (match_test "REG_P(op)")
20656 + (match_test "GET_CODE(op) == PLUS
20657 + && ((GET_CODE(XEXP(op,0)) == CONST_INT)
20658 + || (GET_CODE(XEXP(op,1)) == CONST_INT))")) ))
20660 +;; An offset k16 memory operand
20661 +(define_predicate "avr32_ks16_memory_operand"
20662 + (and (match_code "mem")
20663 + (match_test "avr32_ks16_address_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))")))
20665 +;; An immediate k11 address operand
20666 +(define_predicate "avr32_ks11_address_operand"
20667 + (and (match_operand 0 "address_operand")
20668 + (ior (match_test "REG_P(op)")
20669 + (match_test "GET_CODE(op) == PLUS
20670 + && (((GET_CODE(XEXP(op,0)) == CONST_INT)
20671 + && avr32_const_ok_for_constraint_p(INTVAL(XEXP(op,0)), 'K', \"Ks11\"))
20672 + || ((GET_CODE(XEXP(op,1)) == CONST_INT)
20673 + && avr32_const_ok_for_constraint_p(INTVAL(XEXP(op,1)), 'K', \"Ks11\")))")) ))
20675 +;; True if this is a avr32 call operand
20676 +(define_predicate "avr32_call_operand"
20677 + (ior (ior (match_operand 0 "register_operand")
20678 + (ior (match_operand 0 "avr32_const_pool_ref_operand")
20679 + (match_operand 0 "avr32_address_operand")))
20680 + (match_test "SYMBOL_REF_RCALL_FUNCTION_P(op)")))
20682 +;; Return true for operators performing ALU operations
20684 +(define_predicate "alu_operator"
20685 + (match_code "ior, xor, and, plus, minus, ashift, lshiftrt, ashiftrt"))
20687 +(define_predicate "avr32_add_shift_immediate_operand"
20688 + (and (match_operand 0 "immediate_operand")
20689 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ku02\")")))
20691 +(define_predicate "avr32_cond_register_immediate_operand"
20692 + (ior (match_operand 0 "register_operand")
20693 + (and (match_operand 0 "immediate_operand")
20694 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")"))))
20696 +(define_predicate "avr32_cond_immediate_operand"
20697 + (and (match_operand 0 "immediate_operand")
20698 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'I', \"Is08\")")))
20701 +(define_predicate "avr32_cond_move_operand"
20702 + (ior (ior (match_operand 0 "register_operand")
20703 + (and (match_operand 0 "immediate_operand")
20704 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")")))
20705 + (and (match_test "TARGET_V2_INSNS")
20706 + (match_operand 0 "memory_operand"))))
20708 +(define_predicate "avr32_mov_immediate_operand"
20709 + (and (match_operand 0 "immediate_operand")
20710 + (match_test "avr32_const_ok_for_move(INTVAL(op))")))
20713 +(define_predicate "avr32_rmw_address_operand"
20714 + (ior (and (match_code "symbol_ref")
20715 + (match_test "({rtx symbol = avr32_find_symbol(op); \
20716 + symbol && (GET_CODE (symbol) == SYMBOL_REF) && SYMBOL_REF_RMW_ADDR(symbol);})"))
20717 + (and (match_operand 0 "immediate_operand")
20718 + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks17\")")))
20720 + return TARGET_RMW && !flag_pic;
20724 +(define_predicate "avr32_rmw_memory_operand"
20725 + (and (match_code "mem")
20726 + (match_test "(GET_MODE(op) == SImode) &&
20727 + avr32_rmw_address_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))")))
20729 +(define_predicate "avr32_rmw_memory_or_register_operand"
20730 + (ior (match_operand 0 "avr32_rmw_memory_operand")
20731 + (match_operand 0 "register_operand")))
20733 +(define_predicate "avr32_non_rmw_memory_operand"
20734 + (and (not (match_operand 0 "avr32_rmw_memory_operand"))
20735 + (match_operand 0 "memory_operand")))
20737 +(define_predicate "avr32_non_rmw_general_operand"
20738 + (and (not (match_operand 0 "avr32_rmw_memory_operand"))
20739 + (match_operand 0 "general_operand")))
20741 +(define_predicate "avr32_non_rmw_nonimmediate_operand"
20742 + (and (not (match_operand 0 "avr32_rmw_memory_operand"))
20743 + (match_operand 0 "nonimmediate_operand")))
20745 +++ b/gcc/config/avr32/simd.md
20747 +;; AVR32 machine description file for SIMD instructions.
20748 +;; Copyright 2003-2006 Atmel Corporation.
20750 +;; Written by Ronny Pedersen, Atmel Norway, <rpedersen@atmel.com>
20752 +;; This file is part of GCC.
20754 +;; This program is free software; you can redistribute it and/or modify
20755 +;; it under the terms of the GNU General Public License as published by
20756 +;; the Free Software Foundation; either version 2 of the License, or
20757 +;; (at your option) any later version.
20759 +;; This program is distributed in the hope that it will be useful,
20760 +;; but WITHOUT ANY WARRANTY; without even the implied warranty of
20761 +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20762 +;; GNU General Public License for more details.
20764 +;; You should have received a copy of the GNU General Public License
20765 +;; along with this program; if not, write to the Free Software
20766 +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20768 +;; -*- Mode: Scheme -*-
20772 +(define_mode_macro VECM [V2HI V4QI])
20773 +(define_mode_attr size [(V2HI "h") (V4QI "b")])
20775 +(define_insn "add<mode>3"
20776 + [(set (match_operand:VECM 0 "register_operand" "=r")
20777 + (plus:VECM (match_operand:VECM 1 "register_operand" "r")
20778 + (match_operand:VECM 2 "register_operand" "r")))]
20780 + "padd.<size>\t%0, %1, %2"
20781 + [(set_attr "length" "4")
20782 + (set_attr "type" "alu")])
20785 +(define_insn "sub<mode>3"
20786 + [(set (match_operand:VECM 0 "register_operand" "=r")
20787 + (minus:VECM (match_operand:VECM 1 "register_operand" "r")
20788 + (match_operand:VECM 2 "register_operand" "r")))]
20790 + "psub.<size>\t%0, %1, %2"
20791 + [(set_attr "length" "4")
20792 + (set_attr "type" "alu")])
20795 +(define_insn "abs<mode>2"
20796 + [(set (match_operand:VECM 0 "register_operand" "=r")
20797 + (abs:VECM (match_operand:VECM 1 "register_operand" "r")))]
20799 + "pabs.s<size>\t%0, %1"
20800 + [(set_attr "length" "4")
20801 + (set_attr "type" "alu")])
20803 +(define_insn "ashl<mode>3"
20804 + [(set (match_operand:VECM 0 "register_operand" "=r")
20805 + (ashift:VECM (match_operand:VECM 1 "register_operand" "r")
20806 + (match_operand:SI 2 "immediate_operand" "Ku04")))]
20808 + "plsl.<size>\t%0, %1, %2"
20809 + [(set_attr "length" "4")
20810 + (set_attr "type" "alu")])
20812 +(define_insn "ashr<mode>3"
20813 + [(set (match_operand:VECM 0 "register_operand" "=r")
20814 + (ashiftrt:VECM (match_operand:VECM 1 "register_operand" "r")
20815 + (match_operand:SI 2 "immediate_operand" "Ku04")))]
20817 + "pasr.<size>\t%0, %1, %2"
20818 + [(set_attr "length" "4")
20819 + (set_attr "type" "alu")])
20821 +(define_insn "lshr<mode>3"
20822 + [(set (match_operand:VECM 0 "register_operand" "=r")
20823 + (lshiftrt:VECM (match_operand:VECM 1 "register_operand" "r")
20824 + (match_operand:SI 2 "immediate_operand" "Ku04")))]
20826 + "plsr.<size>\t%0, %1, %2"
20827 + [(set_attr "length" "4")
20828 + (set_attr "type" "alu")])
20830 +(define_insn "smaxv2hi3"
20831 + [(set (match_operand:V2HI 0 "register_operand" "=r")
20832 + (smax:V2HI (match_operand:V2HI 1 "register_operand" "r")
20833 + (match_operand:V2HI 2 "register_operand" "r")))]
20836 + "pmax.sh\t%0, %1, %2"
20837 + [(set_attr "length" "4")
20838 + (set_attr "type" "alu")])
20840 +(define_insn "sminv2hi3"
20841 + [(set (match_operand:V2HI 0 "register_operand" "=r")
20842 + (smin:V2HI (match_operand:V2HI 1 "register_operand" "r")
20843 + (match_operand:V2HI 2 "register_operand" "r")))]
20846 + "pmin.sh\t%0, %1, %2"
20847 + [(set_attr "length" "4")
20848 + (set_attr "type" "alu")])
20850 +(define_insn "umaxv4qi3"
20851 + [(set (match_operand:V4QI 0 "register_operand" "=r")
20852 + (umax:V4QI (match_operand:V4QI 1 "register_operand" "r")
20853 + (match_operand:V4QI 2 "register_operand" "r")))]
20856 + "pmax.ub\t%0, %1, %2"
20857 + [(set_attr "length" "4")
20858 + (set_attr "type" "alu")])
20860 +(define_insn "uminv4qi3"
20861 + [(set (match_operand:V4QI 0 "register_operand" "=r")
20862 + (umin:V4QI (match_operand:V4QI 1 "register_operand" "r")
20863 + (match_operand:V4QI 2 "register_operand" "r")))]
20866 + "pmin.ub\t%0, %1, %2"
20867 + [(set_attr "length" "4")
20868 + (set_attr "type" "alu")])
20871 +(define_insn "addsubv2hi"
20872 + [(set (match_operand:V2HI 0 "register_operand" "=r")
20874 + (plus:HI (match_operand:HI 1 "register_operand" "r")
20875 + (match_operand:HI 2 "register_operand" "r"))
20876 + (minus:HI (match_dup 1) (match_dup 2))))]
20878 + "paddsub.h\t%0, %1:b, %2:b"
20879 + [(set_attr "length" "4")
20880 + (set_attr "type" "alu")])
20882 +(define_insn "subaddv2hi"
20883 + [(set (match_operand:V2HI 0 "register_operand" "=r")
20885 + (minus:HI (match_operand:HI 1 "register_operand" "r")
20886 + (match_operand:HI 2 "register_operand" "r"))
20887 + (plus:HI (match_dup 1) (match_dup 2))))]
20889 + "psubadd.h\t%0, %1:b, %2:b"
20890 + [(set_attr "length" "4")
20891 + (set_attr "type" "alu")])
20893 +++ b/gcc/config/avr32/sync.md
20895 +;;=================================================================
20896 +;; Atomic operations
20897 +;;=================================================================
20900 +(define_insn "sync_compare_and_swapsi"
20901 + [(set (match_operand:SI 0 "register_operand" "=&r,&r")
20902 + (match_operand:SI 1 "memory_operand" "+RKs16,+RKs16"))
20903 + (set (match_dup 1)
20904 + (unspec_volatile:SI
20906 + (match_operand:SI 2 "register_immediate_operand" "r,Ks21")
20907 + (match_operand:SI 3 "register_operand" "r,r")]
20908 + VUNSPEC_SYNC_CMPXCHG)) ]
20919 + [(set_attr "length" "16,18")
20920 + (set_attr "cc" "clobber")]
20924 +(define_code_macro atomic_op [plus minus and ior xor])
20925 +(define_code_attr atomic_asm_insn [(plus "add") (minus "sub") (and "and") (ior "or") (xor "eor")])
20926 +(define_code_attr atomic_insn [(plus "add") (minus "sub") (and "and") (ior "ior") (xor "xor")])
20928 +(define_insn "sync_loadsi"
20929 + ; NB! Put an early clobber on the destination operand to
20930 + ; avoid gcc using the same register in the source and
20931 + ; destination. This is done in order to avoid gcc to
20932 + ; clobber the source operand since these instructions
20933 + ; are actually inside a "loop".
20934 + [(set (match_operand:SI 0 "register_operand" "=&r")
20935 + (unspec_volatile:SI
20936 + [(match_operand:SI 1 "avr32_ks16_memory_operand" "RKs16")
20937 + (label_ref (match_operand 2 "" ""))]
20938 + VUNSPEC_SYNC_SET_LOCK_AND_LOAD) )]
20943 + [(set_attr "length" "6")
20944 + (set_attr "cc" "clobber")]
20947 +(define_insn "sync_store_if_lock"
20948 + [(set (match_operand:SI 0 "avr32_ks16_memory_operand" "=RKs16")
20949 + (unspec_volatile:SI
20950 + [(match_operand:SI 1 "register_operand" "r")
20951 + (label_ref (match_operand 2 "" ""))]
20952 + VUNSPEC_SYNC_STORE_IF_LOCK) )]
20956 + [(set_attr "length" "6")
20957 + (set_attr "cc" "clobber")]
20961 +(define_expand "sync_<atomic_insn>si"
20962 + [(set (match_dup 2)
20963 + (unspec_volatile:SI
20964 + [(match_operand:SI 0 "avr32_ks16_memory_operand" "")
20966 + VUNSPEC_SYNC_SET_LOCK_AND_LOAD))
20967 + (set (match_dup 2)
20968 + (atomic_op:SI (match_dup 2)
20969 + (match_operand:SI 1 "register_immediate_operand" "")))
20970 + (set (match_dup 0)
20971 + (unspec_volatile:SI
20974 + VUNSPEC_SYNC_STORE_IF_LOCK) )
20975 + (use (match_dup 1))
20976 + (use (match_dup 4))]
20979 + rtx *mem_expr = &operands[0];
20981 + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) )
20983 + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0));
20984 + XEXP (*mem_expr, 0) = ptr_reg;
20988 + rtx address = XEXP (*mem_expr, 0);
20989 + if ( REG_P (address) )
20990 + ptr_reg = address;
20991 + else if ( REG_P (XEXP (address, 0)) )
20992 + ptr_reg = XEXP (address, 0);
20994 + ptr_reg = XEXP (address, 1);
20997 + operands[2] = gen_reg_rtx (SImode);
20998 + operands[3] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ());
20999 + operands[4] = ptr_reg;
21006 +(define_expand "sync_old_<atomic_insn>si"
21007 + [(set (match_operand:SI 0 "register_operand" "")
21008 + (unspec_volatile:SI
21009 + [(match_operand:SI 1 "avr32_ks16_memory_operand" "")
21011 + VUNSPEC_SYNC_SET_LOCK_AND_LOAD))
21012 + (set (match_dup 3)
21013 + (atomic_op:SI (match_dup 0)
21014 + (match_operand:SI 2 "register_immediate_operand" "")))
21015 + (set (match_dup 1)
21016 + (unspec_volatile:SI
21019 + VUNSPEC_SYNC_STORE_IF_LOCK) )
21020 + (use (match_dup 2))
21021 + (use (match_dup 5))]
21024 + rtx *mem_expr = &operands[1];
21026 + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) )
21028 + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0));
21029 + XEXP (*mem_expr, 0) = ptr_reg;
21033 + rtx address = XEXP (*mem_expr, 0);
21034 + if ( REG_P (address) )
21035 + ptr_reg = address;
21036 + else if ( REG_P (XEXP (address, 0)) )
21037 + ptr_reg = XEXP (address, 0);
21039 + ptr_reg = XEXP (address, 1);
21042 + operands[3] = gen_reg_rtx (SImode);
21043 + operands[4] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ());
21044 + operands[5] = ptr_reg;
21048 +(define_expand "sync_new_<atomic_insn>si"
21049 + [(set (match_operand:SI 0 "register_operand" "")
21050 + (unspec_volatile:SI
21051 + [(match_operand:SI 1 "avr32_ks16_memory_operand" "")
21053 + VUNSPEC_SYNC_SET_LOCK_AND_LOAD))
21054 + (set (match_dup 0)
21055 + (atomic_op:SI (match_dup 0)
21056 + (match_operand:SI 2 "register_immediate_operand" "")))
21057 + (set (match_dup 1)
21058 + (unspec_volatile:SI
21061 + VUNSPEC_SYNC_STORE_IF_LOCK) )
21062 + (use (match_dup 2))
21063 + (use (match_dup 4))]
21066 + rtx *mem_expr = &operands[1];
21068 + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) )
21070 + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0));
21071 + XEXP (*mem_expr, 0) = ptr_reg;
21075 + rtx address = XEXP (*mem_expr, 0);
21076 + if ( REG_P (address) )
21077 + ptr_reg = address;
21078 + else if ( REG_P (XEXP (address, 0)) )
21079 + ptr_reg = XEXP (address, 0);
21081 + ptr_reg = XEXP (address, 1);
21084 + operands[3] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ());
21085 + operands[4] = ptr_reg;
21090 +;(define_insn "sync_<atomic_insn>si"
21091 +; [(set (match_operand:SI 0 "memory_operand" "+RKs16")
21092 +; (unspec_volatile:SI
21093 +; [(atomic_op:SI (match_dup 0)
21094 +; (match_operand:SI 1 "register_operand" "r"))]
21095 +; VUNSPEC_SYNC_CMPXCHG))
21096 +; (clobber (match_scratch:SI 2 "=&r"))]
21101 +; <atomic_asm_insn>\t%2,%1
21105 +; [(set_attr "length" "14")
21106 +; (set_attr "cc" "clobber")]
21109 +;(define_insn "sync_new_<atomic_insn>si"
21110 +; [(set (match_operand:SI 1 "memory_operand" "+RKs16")
21111 +; (unspec_volatile:SI
21112 +; [(atomic_op:SI (match_dup 1)
21113 +; (match_operand:SI 2 "register_operand" "r"))]
21114 +; VUNSPEC_SYNC_CMPXCHG))
21115 +; (set (match_operand:SI 0 "register_operand" "=&r")
21116 +; (atomic_op:SI (match_dup 1)
21117 +; (match_dup 2)))]
21122 +; <atomic_asm_insn>\t%0,%2
21126 +; [(set_attr "length" "14")
21127 +; (set_attr "cc" "clobber")]
21130 +(define_insn "sync_lock_test_and_setsi"
21131 + [ (set (match_operand:SI 0 "register_operand" "=&r")
21132 + (match_operand:SI 1 "memory_operand" "+RKu00"))
21133 + (set (match_dup 1)
21134 + (match_operand:SI 2 "register_operand" "r")) ]
21136 + "xchg\t%0, %p1, %2"
21137 + [(set_attr "length" "4")]
21140 +++ b/gcc/config/avr32/t-avr32
21143 +MD_INCLUDES= $(srcdir)/config/avr32/avr32.md \
21144 + $(srcdir)/config/avr32/sync.md \
21145 + $(srcdir)/config/avr32/fpcp.md \
21146 + $(srcdir)/config/avr32/simd.md \
21147 + $(srcdir)/config/avr32/predicates.md
21149 +s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
21150 + s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
21152 +# We want fine grained libraries, so use the new code
21153 +# to build the floating point emulation libraries.
21157 +LIB1ASMSRC = avr32/lib1funcs.S
21158 +LIB1ASMFUNCS = _avr32_f64_mul _avr32_f64_mul_fast _avr32_f64_addsub _avr32_f64_addsub_fast _avr32_f64_to_u32 \
21159 + _avr32_f64_to_s32 _avr32_f64_to_u64 _avr32_f64_to_s64 _avr32_u32_to_f64 \
21160 + _avr32_s32_to_f64 _avr32_f64_cmp_eq _avr32_f64_cmp_ge _avr32_f64_cmp_lt \
21161 + _avr32_f32_cmp_eq _avr32_f32_cmp_ge _avr32_f32_cmp_lt _avr32_f64_div _avr32_f64_div_fast \
21162 + _avr32_f32_div _avr32_f32_div_fast _avr32_f32_addsub _avr32_f32_addsub_fast \
21163 + _avr32_f32_mul _avr32_s32_to_f32 _avr32_u32_to_f32 _avr32_f32_to_s32 \
21164 + _avr32_f32_to_u32 _avr32_f32_to_f64 _avr32_f64_to_f32 _mulsi3
21166 +#LIB2FUNCS_EXTRA += $(srcdir)/config/avr32/lib2funcs.S
21168 +MULTILIB_OPTIONS = march=ap/march=ucr1/march=ucr2/march=ucr2nomul
21169 +MULTILIB_DIRNAMES = ap ucr1 ucr2 ucr2nomul
21170 +MULTILIB_EXCEPTIONS =
21171 +MULTILIB_MATCHES += march?ap=mpart?ap7000
21172 +MULTILIB_MATCHES += march?ap=mpart?ap7001
21173 +MULTILIB_MATCHES += march?ap=mpart?ap7002
21174 +MULTILIB_MATCHES += march?ap=mpart?ap7200
21175 +MULTILIB_MATCHES += march?ucr1=march?uc
21176 +MULTILIB_MATCHES += march?ucr1=mpart?uc3a0512es
21177 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0128
21178 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0256
21179 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0512
21180 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1128
21181 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1256
21182 +MULTILIB_MATCHES += march?ucr1=mpart?uc3a1512es
21183 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1512
21184 +MULTILIB_MATCHES += march?ucr2nomul=mpart?uc3a3revd
21185 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364
21186 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364s
21187 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128
21188 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128s
21189 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256
21190 +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256s
21191 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b064
21192 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0128
21193 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256es
21194 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256
21195 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b164
21196 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1128
21197 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256es
21198 +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256
21201 +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o crti.o crtn.o
21203 +CRTSTUFF_T_CFLAGS = -mrelax
21204 +CRTSTUFF_T_CFLAGS_S = -mrelax -fPIC
21205 +TARGET_LIBGCC2_CFLAGS += -mrelax
21207 +LIBGCC = stmp-multilib
21208 +INSTALL_LIBGCC = install-multilib
21210 +fp-bit.c: $(srcdir)/config/fp-bit.c
21211 + echo '#define FLOAT' > fp-bit.c
21212 + cat $(srcdir)/config/fp-bit.c >> fp-bit.c
21214 +dp-bit.c: $(srcdir)/config/fp-bit.c
21215 + cat $(srcdir)/config/fp-bit.c > dp-bit.c
21220 +++ b/gcc/config/avr32/t-elf
21223 +# Assemble startup files.
21224 +$(T)crti.o: $(srcdir)/config/avr32/crti.asm $(GCC_PASSES)
21225 + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) $(INCLUDES) \
21226 + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/avr32/crti.asm
21228 +$(T)crtn.o: $(srcdir)/config/avr32/crtn.asm $(GCC_PASSES)
21229 + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) $(INCLUDES) \
21230 + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/avr32/crtn.asm
21233 +# Build the libraries for both hard and soft floating point
21234 +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o crti.o crtn.o
21236 +LIBGCC = stmp-multilib
21237 +INSTALL_LIBGCC = install-multilib
21239 +++ b/gcc/config/avr32/uclinux-elf.h
21242 +/* Run-time Target Specification. */
21243 +#undef TARGET_VERSION
21244 +#define TARGET_VERSION fputs (" (AVR32 uClinux with ELF)", stderr)
21246 +/* We don't want a .jcr section on uClinux. As if this makes a difference... */
21247 +#define TARGET_USE_JCR_SECTION 0
21249 +/* Here we go. Drop the crtbegin/crtend stuff completely. */
21250 +#undef STARTFILE_SPEC
21251 +#define STARTFILE_SPEC \
21252 + "%{!shared: %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s}" \
21253 + " %{!p:%{profile:gcrt1.o%s}" \
21254 + " %{!profile:crt1.o%s}}}} crti.o%s"
21256 +#undef ENDFILE_SPEC
21257 +#define ENDFILE_SPEC "crtn.o%s"
21259 +#undef TARGET_DEFAULT
21260 +#define TARGET_DEFAULT (AVR32_FLAG_NO_INIT_GOT)
21261 --- a/gcc/config/host-linux.c
21262 +++ b/gcc/config/host-linux.c
21264 #include "hosthooks.h"
21265 #include "hosthooks-def.h"
21268 +#define SSIZE_MAX LONG_MAX
21271 /* Linux has a feature called exec-shield-randomize that perturbs the
21272 address of non-fixed mapped segments by a (relatively) small amount.
21273 --- a/gcc/config.gcc
21274 +++ b/gcc/config.gcc
21275 @@ -781,6 +781,24 @@ avr-*-*)
21276 tm_file="avr/avr.h dbxelf.h"
21280 + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h "
21281 + tmake_file="t-linux avr32/t-avr32 avr32/t-elf"
21282 + extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o"
21283 + extra_modes=avr32/avr32-modes.def
21286 +avr32*-*-uclinux*)
21287 + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/uclinux-elf.h avr32/avr32.h"
21288 + tmake_file="t-linux avr32/t-avr32 avr32/t-elf"
21289 + extra_modes=avr32/avr32-modes.def
21293 + tm_file="dbxelf.h elfos.h avr32/avr32.h avr32/avr32-elf.h"
21294 + tmake_file="avr32/t-avr32 avr32/t-elf"
21295 + extra_modes=avr32/avr32-modes.def
21298 tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h"
21299 tmake_file=bfin/t-bfin-elf
21300 @@ -1681,6 +1699,9 @@ pdp11-*-bsd)
21307 # port not yet contributed
21308 #powerpc-*-openbsd*)
21309 # tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-fprules-fpbit "
21310 @@ -2717,6 +2738,32 @@ case "${target}" in
21315 + supported_defaults="part arch"
21317 + case "$with_part" in
21319 + | "ap7000" | "ap7010" | "ap7020" | "uc3a0256" | "uc3a0512" | "uc3a1128" | "uc3a1256" | "uc3a1512" )
21323 + echo "Unknown part used in --with-part=$with_part" 1>&2
21328 + case "$with_arch" in
21334 + echo "Unknown arch used in --with-arch=$with_arch" 1>&2
21341 supported_defaults=cpu
21342 case "$with_cpu" in
21343 --- a/gcc/doc/extend.texi
21344 +++ b/gcc/doc/extend.texi
21345 @@ -1981,7 +1981,7 @@ this attribute to work correctly.
21348 @cindex interrupt handler functions
21349 -Use this attribute on the ARM, AVR, C4x, CRX, M32C, M32R/D, MS1, and Xstormy16
21350 +Use this attribute on the ARM, AVR, AVR32, C4x, CRX, M32C, M32R/D, MS1, and Xstormy16
21351 ports to indicate that the specified function is an interrupt handler.
21352 The compiler will generate function entry and exit sequences suitable
21353 for use in an interrupt handler when this attribute is present.
21354 @@ -2000,6 +2000,15 @@ void f () __attribute__ ((interrupt ("IR
21356 Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@.
21358 +Note, for the AVR32, you can specify which banking scheme is used for
21359 +the interrupt mode this interrupt handler is used in like this:
21362 +void f () __attribute__ ((interrupt ("FULL")));
21365 +Permissible values for this parameter are: FULL, HALF, NONE and UNDEF.
21367 @item interrupt_handler
21368 @cindex interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors
21369 Use this attribute on the Blackfin, m68k, H8/300, H8/300H, H8S, and SH to
21370 @@ -3460,6 +3469,23 @@ placed in either the @code{.bss_below100
21374 +@subsection AVR32 Variable Attributes
21376 +One attribute is currently defined for AVR32 configurations:
21377 +@code{rmw_addressable}
21380 +@item rmw_addressable
21381 +@cindex @code{rmw_addressable} attribute
21383 +This attribute can be used to signal that a variable can be accessed
21384 +with the addressing mode of the AVR32 Atomic Read-Modify-Write memory
21385 +instructions and hence make it possible for gcc to generate these
21386 +instructions without using built-in functions or inline assembly statements.
21387 +Variables used within the AVR32 Atomic Read-Modify-Write built-in
21388 +functions will automatically get the @code{rmw_addressable} attribute.
21391 @node Type Attributes
21392 @section Specifying Attributes of Types
21393 @cindex attribute of types
21394 @@ -6167,6 +6193,7 @@ instructions, but allow the compiler to
21396 * Alpha Built-in Functions::
21397 * ARM Built-in Functions::
21398 +* AVR32 Built-in Functions::
21399 * Blackfin Built-in Functions::
21400 * FR-V Built-in Functions::
21401 * X86 Built-in Functions::
21402 @@ -6405,6 +6432,76 @@ long long __builtin_arm_wxor (long long,
21403 long long __builtin_arm_wzero ()
21406 +@node AVR32 Built-in Functions
21407 +@subsection AVR32 Built-in Functions
21411 +Built-in functions for atomic memory (RMW) instructions. Note that these
21412 +built-ins will fail for targets where the RMW instructions are not
21413 +implemented. Also note that these instructions only that a Ks15 << 2
21414 +memory address and will therefor not work with any runtime computed
21415 +memory addresses. The user is responsible for making sure that any
21416 +pointers used within these functions points to a valid memory address.
21419 +void __builtin_mems(int */*ptr*/, int /*bit*/)
21420 +void __builtin_memc(int */*ptr*/, int /*bit*/)
21421 +void __builtin_memt(int */*ptr*/, int /*bit*/)
21424 +Built-in functions for DSP instructions. Note that these built-ins will
21425 +fail for targets where the DSP instructions are not implemented.
21428 +int __builtin_sats (int /*Rd*/,int /*sa*/, int /*bn*/)
21429 +int __builtin_satu (int /*Rd*/,int /*sa*/, int /*bn*/)
21430 +int __builtin_satrnds (int /*Rd*/,int /*sa*/, int /*bn*/)
21431 +int __builtin_satrndu (int /*Rd*/,int /*sa*/, int /*bn*/)
21432 +short __builtin_mulsathh_h (short, short)
21433 +int __builtin_mulsathh_w (short, short)
21434 +short __builtin_mulsatrndhh_h (short, short)
21435 +int __builtin_mulsatrndwh_w (int, short)
21436 +int __builtin_mulsatwh_w (int, short)
21437 +int __builtin_macsathh_w (int, short, short)
21438 +short __builtin_satadd_h (short, short)
21439 +short __builtin_satsub_h (short, short)
21440 +int __builtin_satadd_w (int, int)
21441 +int __builtin_satsub_w (int, int)
21442 +long long __builtin_mulwh_d(int, short)
21443 +long long __builtin_mulnwh_d(int, short)
21444 +long long __builtin_macwh_d(long long, int, short)
21445 +long long __builtin_machh_d(long long, short, short)
21448 +Other built-in functions for instructions that cannot easily be
21449 +generated by the compiler.
21452 +void __builtin_ssrf(int);
21453 +void __builtin_csrf(int);
21454 +void __builtin_musfr(int);
21455 +int __builtin_mustr(void);
21456 +int __builtin_mfsr(int /*Status Register Address*/)
21457 +void __builtin_mtsr(int /*Status Register Address*/, int /*Value*/)
21458 +int __builtin_mfdr(int /*Debug Register Address*/)
21459 +void __builtin_mtdr(int /*Debug Register Address*/, int /*Value*/)
21460 +void __builtin_cache(void * /*Address*/, int /*Cache Operation*/)
21461 +void __builtin_sync(int /*Sync Operation*/)
21462 +void __builtin_tlbr(void)
21463 +void __builtin_tlbs(void)
21464 +void __builtin_tlbw(void)
21465 +void __builtin_breakpoint(void)
21466 +int __builtin_xchg(void * /*Address*/, int /*Value*/ )
21467 +short __builtin_bswap_16(short)
21468 +int __builtin_bswap_32(int)
21469 +void __builtin_cop(int/*cpnr*/, int/*crd*/, int/*crx*/, int/*cry*/, int/*op*/)
21470 +int __builtin_mvcr_w(int/*cpnr*/, int/*crs*/)
21471 +void __builtin_mvrc_w(int/*cpnr*/, int/*crd*/, int/*value*/)
21472 +long long __builtin_mvcr_d(int/*cpnr*/, int/*crs*/)
21473 +void __builtin_mvrc_d(int/*cpnr*/, int/*crd*/, long long/*value*/)
21476 @node Blackfin Built-in Functions
21477 @subsection Blackfin Built-in Functions
21479 --- a/gcc/doc/invoke.texi
21480 +++ b/gcc/doc/invoke.texi
21481 @@ -190,7 +190,7 @@ in the following sections.
21482 -fno-default-inline -fvisibility-inlines-hidden @gol
21483 -Wabi -Wctor-dtor-privacy @gol
21484 -Wnon-virtual-dtor -Wreorder @gol
21485 --Weffc++ -Wno-deprecated -Wstrict-null-sentinel @gol
21486 +-Weffc++ -Wno-deprecated @gol
21487 -Wno-non-template-friend -Wold-style-cast @gol
21488 -Woverloaded-virtual -Wno-pmf-conversions @gol
21490 @@ -588,6 +588,12 @@ Objective-C and Objective-C++ Dialects}.
21491 -mauto-incdec -minmax -mlong-calls -mshort @gol
21492 -msoft-reg-count=@var{count}}
21494 +@emph{AVR32 Options}
21495 +@gccoptlist{-muse-rodata-section -mhard-float -msoft-float -mrelax @gol
21496 +-mforce-double-align -mno-init-got -mrelax -mmd-reorg-opt -masm-addr-pseudos @gol
21497 +-mpart=@var{part} -mcpu=@var{cpu} -march=@var{arch} @gol
21498 +-mfast-float -mimm-in-const-pool}
21500 @emph{MCore Options}
21501 @gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol
21502 -mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol
21503 @@ -1868,14 +1874,6 @@ to filter out those warnings.
21504 @opindex Wno-deprecated
21505 Do not warn about usage of deprecated features. @xref{Deprecated Features}.
21507 -@item -Wstrict-null-sentinel @r{(C++ only)}
21508 -@opindex Wstrict-null-sentinel
21509 -Warn also about the use of an uncasted @code{NULL} as sentinel. When
21510 -compiling only with GCC this is a valid sentinel, as @code{NULL} is defined
21511 -to @code{__null}. Although it is a null pointer constant not a null pointer,
21512 -it is guaranteed to of the same size as a pointer. But this use is
21513 -not portable across different compilers.
21515 @item -Wno-non-template-friend @r{(C++ only)}
21516 @opindex Wno-non-template-friend
21517 Disable warnings when non-templatized friend functions are declared
21518 @@ -2732,13 +2730,11 @@ requiring @option{-O}.
21519 If you want to warn about code which uses the uninitialized value of the
21520 variable in its own initializer, use the @option{-Winit-self} option.
21522 -These warnings occur for individual uninitialized or clobbered
21523 -elements of structure, union or array variables as well as for
21524 -variables which are uninitialized or clobbered as a whole. They do
21525 -not occur for variables or elements declared @code{volatile}. Because
21526 -these warnings depend on optimization, the exact variables or elements
21527 -for which there are warnings will depend on the precise optimization
21528 -options and version of GCC used.
21529 +These warnings occur only for variables that are candidates for
21530 +register allocation. Therefore, they do not occur for a variable that
21531 +is declared @code{volatile}, or whose address is taken, or whose size
21532 +is other than 1, 2, 4 or 8 bytes. Also, they do not occur for
21533 +structures, unions or arrays, even when they are in registers.
21535 Note that there may be no warning about a variable that is used only
21536 to compute a value that itself is never used, because such
21537 @@ -6201,10 +6197,6 @@ If number of candidates in the set is sm
21538 we always try to remove unnecessary ivs from the set during its
21539 optimization when a new iv is added to the set.
21541 -@item scev-max-expr-size
21542 -Bound on size of expressions used in the scalar evolutions analyzer.
21543 -Large expressions slow the analyzer.
21545 @item vect-max-version-checks
21546 The maximum number of runtime checks that can be performed when doing
21547 loop versioning in the vectorizer. See option ftree-vect-loop-version
21548 @@ -7402,7 +7394,7 @@ platform.
21552 -* Blackfin Options::
21557 @@ -7867,81 +7859,80 @@ comply to the C standards, but it will p
21561 -@node Blackfin Options
21562 -@subsection Blackfin Options
21563 -@cindex Blackfin Options
21564 +@node AVR32 Options
21565 +@subsection AVR32 Options
21566 +@cindex AVR32 Options
21568 +These options are defined for AVR32 implementations:
21571 -@item -momit-leaf-frame-pointer
21572 -@opindex momit-leaf-frame-pointer
21573 -Don't keep the frame pointer in a register for leaf functions. This
21574 -avoids the instructions to save, set up and restore frame pointers and
21575 -makes an extra register available in leaf functions. The option
21576 -@option{-fomit-frame-pointer} removes the frame pointer for all functions
21577 -which might make debugging harder.
21578 +@item -muse-rodata-section
21579 +@opindex muse-rodata-section
21580 +Use section @samp{.rodata} for read-only data instead of @samp{.text}.
21582 -@item -mspecld-anomaly
21583 -@opindex mspecld-anomaly
21584 -When enabled, the compiler will ensure that the generated code does not
21585 -contain speculative loads after jump instructions. This option is enabled
21588 -@item -mno-specld-anomaly
21589 -@opindex mno-specld-anomaly
21590 -Don't generate extra code to prevent speculative loads from occurring.
21592 -@item -mcsync-anomaly
21593 -@opindex mcsync-anomaly
21594 -When enabled, the compiler will ensure that the generated code does not
21595 -contain CSYNC or SSYNC instructions too soon after conditional branches.
21596 -This option is enabled by default.
21598 -@item -mno-csync-anomaly
21599 -@opindex mno-csync-anomaly
21600 -Don't generate extra code to prevent CSYNC or SSYNC instructions from
21601 -occurring too soon after a conditional branch.
21605 -When enabled, the compiler is free to take advantage of the knowledge that
21606 -the entire program fits into the low 64k of memory.
21608 -@item -mno-low-64k
21609 -@opindex mno-low-64k
21610 -Assume that the program is arbitrarily large. This is the default.
21611 +@item -mhard-float
21612 +@opindex mhard-float
21613 +Use floating point coprocessor instructions.
21615 -@item -mid-shared-library
21616 -@opindex mid-shared-library
21617 -Generate code that supports shared libraries via the library ID method.
21618 -This allows for execute in place and shared libraries in an environment
21619 -without virtual memory management. This option implies @option{-fPIC}.
21620 +@item -msoft-float
21621 +@opindex msoft-float
21622 +Use software floating-point library for floating-point operations.
21624 -@item -mno-id-shared-library
21625 -@opindex mno-id-shared-library
21626 -Generate code that doesn't assume ID based shared libraries are being used.
21627 -This is the default.
21628 +@item -mforce-double-align
21629 +@opindex mforce-double-align
21630 +Force double-word alignment for double-word memory accesses.
21632 +@item -mno-init-got
21633 +@opindex mno-init-got
21634 +Do not initialize the GOT register before using it when compiling PIC
21637 -@item -mshared-library-id=n
21638 -@opindex mshared-library-id
21639 -Specified the identification number of the ID based shared library being
21640 -compiled. Specifying a value of 0 will generate more compact code, specifying
21641 -other values will force the allocation of that number to the current
21642 -library but is no more space or time efficient than omitting this option.
21645 +Let invoked assembler and linker do relaxing
21646 +(Enabled by default when optimization level is >1).
21647 +This means that when the address of symbols are known at link time,
21648 +the linker can optimize @samp{icall} and @samp{mcall}
21649 +instructions into a @samp{rcall} instruction if possible.
21650 +Loading the address of a symbol can also be optimized.
21652 +@item -mmd-reorg-opt
21653 +@opindex mmd-reorg-opt
21654 +Perform machine dependent optimizations in reorg stage.
21656 +@item -masm-addr-pseudos
21657 +@opindex masm-addr-pseudos
21658 +Use assembler pseudo-instructions lda.w and call for handling direct
21659 +addresses. (Enabled by default)
21661 +@item -mpart=@var{part}
21663 +Generate code for the specified part. Permissible parts are:
21664 +@samp{ap7000}, @samp{ap7010},@samp{ap7020},
21665 +@samp{uc3a0128}, @samp{uc3a0256}, @samp{uc3a0512},
21666 +@samp{uc3a1128}, @samp{uc3a1256}, @samp{uc3a1512},
21667 +@samp{uc3b064}, @samp{uc3b0128}, @samp{uc3b0256},
21668 +@samp{uc3b164}, @samp{uc3b1128}, @samp{uc3b1256}.
21670 -@item -mlong-calls
21671 -@itemx -mno-long-calls
21672 -@opindex mlong-calls
21673 -@opindex mno-long-calls
21674 -Tells the compiler to perform function calls by first loading the
21675 -address of the function into a register and then performing a subroutine
21676 -call on this register. This switch is needed if the target function
21677 -will lie outside of the 24 bit addressing range of the offset based
21678 -version of subroutine call instruction.
21679 +@item -mcpu=@var{cpu-type}
21681 +Same as -mpart. Obsolete.
21683 +@item -march=@var{arch}
21685 +Generate code for the specified architecture. Permissible architectures are:
21686 +@samp{ap} and @samp{uc}.
21688 +@item -mfast-float
21689 +@opindex mfast-float
21690 +Enable fast floating-point library that does not conform to ieee but is still good enough
21691 +for most applications. The fast floating-point library does not round to the nearest even
21692 +but away from zero. Enabled by default if the -funsafe-math-optimizations switch is specified.
21694 +@item -mimm-in-const-pool
21695 +@opindex mimm-in-const-pool
21696 +Put large immediates in constant pool. This is enabled by default for archs with insn-cache.
21698 -This feature is not enabled by default. Specifying
21699 -@option{-mno-long-calls} will restore the default behavior. Note these
21700 -switches have no effect on how the compiler generates code to handle
21701 -function calls via function pointers.
21705 --- a/gcc/doc/md.texi
21706 +++ b/gcc/doc/md.texi
21707 @@ -1681,6 +1681,80 @@ A memory reference suitable for iWMMXt l
21708 A memory reference suitable for the ARMv4 ldrsb instruction.
21711 +@item AVR32 family---@file{avr32.h}
21714 +Floating-point registers (f0 to f15) (Reserved for future use)
21716 +@item Ku@var{bits}
21717 +Unsigned constant representable with @var{bits} number of bits (Must be
21718 +two digits). I.e: An unsigned 8-bit constant is written as @samp{Ku08}
21720 +@item Ks@var{bits}
21721 +Signed constant representable with @var{bits} number of bits (Must be
21722 +two digits). I.e: A signed 12-bit constant is written as @samp{Ks12}
21724 +@item Is@var{bits}
21725 +The negated range of a signed constant representable with @var{bits}
21726 +number of bits. The same as @samp{Ks@var{bits}} with a negated range.
21727 +This means that the constant must be in the range @math{-2^{bits-1}-1} to @math{2^{bits-1}}
21730 +A single/double precision floating-point immediate or 64-bit integer
21731 +immediate where the least and most significant words both can be
21732 +loaded with a move instruction. That is the the integer form of the
21733 +values in the least and most significant words both are in the range
21734 +@math{-2^{20}} to @math{2^{20}-1}.
21737 +Any 32-bit immediate with the most significant bits set to zero and the
21738 +remaining least significant bits set to one.
21741 +A 32-bit immediate where all the lower 16-bits are zero.
21744 +A 32-bit immediate with one bit set and the rest of the bits cleared.
21747 +A 32-bit immediate with one bit cleared and the rest of the bits set.
21750 +A 32-bit immediate where all the lower 16-bits are set.
21753 +Any AVR32 memory reference except for reference used for the atomic memory (RMW) instructions.
21755 +@item RKs@var{bits}
21756 +A memory reference where the address consists of a base register
21757 +plus a signed immediate displacement with range given by @samp{Ks@var{bits}}
21758 +which has the same format as for the signed immediate integer constraint
21761 +@item RKu@var{bits}
21762 +A memory reference where the address consists of a base register
21763 +plus an unsigned immediate displacement with range given by @samp{Ku@var{bits}}
21764 +which has the same format as for the unsigned immediate integer constraint
21768 +A memory reference with an immediate or register offset
21771 +A memory reference to a constant pool entry
21774 +A valid operand for use in the @samp{lda.w} instruction macro when
21775 +relaxing is enabled
21778 +A memory reference suitable for the atomic memory (RMW) instructions.
21781 +A memory reference valid for coprocessor memory instructions
21785 @item AVR family---@file{config/avr/constraints.md}
21790 @@ -36,6 +36,7 @@ along with GCC; see the file COPYING3.
21793 #include "langhooks.h"
21794 +#include "target.h"
21796 static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT,
21797 unsigned HOST_WIDE_INT,
21798 @@ -454,9 +455,19 @@ store_bit_field (rtx str_rtx, unsigned H
21799 ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD
21800 || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode))
21801 && byte_offset % GET_MODE_SIZE (fieldmode) == 0)
21802 - : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
21803 - || (offset * BITS_PER_UNIT % bitsize == 0
21804 - && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))
21807 + /* NB! Added for AVR32, and I think this should be true for
21808 + all targets not using narrow volatile bitfields. If the
21809 + bitfield is volatile then we need to perform an access
21810 + consistent with the container type. */
21811 + !(MEM_VOLATILE_P (op0)
21812 + && GET_MODE_BITSIZE (GET_MODE (op0)) != bitsize
21813 + && bitsize < BITS_PER_WORD
21814 + && !targetm.narrow_volatile_bitfield ())
21815 + && (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0))
21816 + || (offset * BITS_PER_UNIT % bitsize == 0
21817 + && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0)))))
21820 op0 = adjust_address (op0, fieldmode, offset);
21821 @@ -1256,6 +1267,13 @@ extract_bit_field (rtx str_rtx, unsigned
21822 && GET_MODE_SIZE (mode1) != 0
21823 && byte_offset % GET_MODE_SIZE (mode1) == 0)
21825 + /* NB! Added for AVR32, and I think this should be true for
21826 + all targets not using narrow volatile bitfields. If the
21827 + bitfield is volatile then we need to perform an access
21828 + consistent with the container type. */
21829 + && !(MEM_VOLATILE_P (op0)
21830 + && GET_MODE_BITSIZE (GET_MODE (op0)) != bitsize
21831 + && !targetm.narrow_volatile_bitfield ())
21832 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0))
21833 || (offset * BITS_PER_UNIT % bitsize == 0
21834 && MEM_ALIGN (op0) % bitsize == 0)))))
21837 @@ -3519,18 +3519,19 @@ emit_single_push_insn (enum machine_mode
21841 + emit_move_insn (stack_pointer_rtx,
21842 + expand_binop (Pmode,
21843 #ifdef STACK_GROWS_DOWNWARD
21844 - /* ??? This seems wrong if STACK_PUSH_CODE == POST_DEC. */
21845 - dest_addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21846 - GEN_INT (-(HOST_WIDE_INT) rounded_size));
21849 - /* ??? This seems wrong if STACK_PUSH_CODE == POST_INC. */
21850 - dest_addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx,
21851 - GEN_INT (rounded_size));
21854 - dest_addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, dest_addr);
21855 + stack_pointer_rtx,
21856 + GEN_INT (rounded_size),
21857 + NULL_RTX, 0, OPTAB_LIB_WIDEN));
21858 + dest_addr = stack_pointer_rtx;
21862 dest = gen_rtx_MEM (mode, dest_addr);
21865 @@ -5509,7 +5510,21 @@ store_field (rtx target, HOST_WIDE_INT b
21866 is a bit field, we cannot use addressing to access it.
21867 Use bit-field techniques or SUBREG to store in it. */
21869 - if (mode == VOIDmode
21871 + /* NB! Added for AVR32, and I think this should be true for
21872 + all targets not using narrow volatile bitfields. If the
21873 + bitfield is volatile then we need to perform an access
21874 + consistent with the container type. */
21876 + && MEM_VOLATILE_P (target)
21877 + && ((GET_MODE (target) != BLKmode
21878 + && GET_MODE_BITSIZE (GET_MODE (target)) > bitsize )
21879 + /* If BLKmode, check if this is a record. Do not know
21880 + if this is really necesarry though...*/
21881 + || (GET_MODE (target) == BLKmode
21882 + && TREE_CODE (type) == RECORD_TYPE))
21883 + && !targetm.narrow_volatile_bitfield ())
21884 + || mode == VOIDmode
21885 || (mode != BLKmode && ! direct_store[(int) mode]
21886 && GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
21887 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
21888 @@ -7560,7 +7575,21 @@ expand_expr_real_1 (tree exp, rtx target
21889 by doing the extract into an object as wide as the field
21890 (which we know to be the width of a basic mode), then
21891 storing into memory, and changing the mode to BLKmode. */
21892 - if (mode1 == VOIDmode
21894 + /* NB! Added for AVR32, and I think this should be true for
21895 + all targets not using narrow volatile bitfields. If the
21896 + bitfield is volatile then we need to perform an access
21897 + consistent with the container type. */
21899 + && MEM_VOLATILE_P (op0)
21900 + && ((GET_MODE (op0) != BLKmode
21901 + && GET_MODE_BITSIZE (GET_MODE (op0)) > bitsize )
21902 + /* If BLKmode, check if this is a record. Do not know
21903 + if this is really necesarry though...*/
21904 + || (GET_MODE (op0) == BLKmode
21905 + && TREE_CODE (type) == RECORD_TYPE))
21906 + && !targetm.narrow_volatile_bitfield ())
21907 + || mode1 == VOIDmode
21908 || REG_P (op0) || GET_CODE (op0) == SUBREG
21909 || (mode1 != BLKmode && ! direct_load[(int) mode1]
21910 && GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
21913 @@ -3327,12 +3327,12 @@ not_reg_cond (rtx x)
21914 if (GET_CODE (x) == NOT)
21915 return XEXP (x, 0);
21916 if (COMPARISON_P (x)
21917 - && REG_P (XEXP (x, 0)))
21918 + /* && REG_P (XEXP (x, 0))*/)
21920 - gcc_assert (XEXP (x, 1) == const0_rtx);
21921 + /*gcc_assert (XEXP (x, 1) == const0_rtx);*/
21923 return gen_rtx_fmt_ee (reversed_comparison_code (x, NULL),
21924 - VOIDmode, XEXP (x, 0), const0_rtx);
21925 + VOIDmode, XEXP (x, 0), XEXP (x, 0) /*const0_rtx*/);
21927 return gen_rtx_NOT (0, x);
21929 --- a/gcc/function.c
21930 +++ b/gcc/function.c
21931 @@ -2676,8 +2676,12 @@ assign_parm_setup_reg (struct assign_par
21932 SET_DECL_RTL (parm, parmreg);
21934 /* Copy the value into the register. */
21935 - if (data->nominal_mode != data->passed_mode
21936 - || promoted_nominal_mode != data->promoted_mode)
21937 + if ( (data->nominal_mode != data->passed_mode
21938 + /* Added for AVR32: If passed_mode is equal
21939 + to promoted nominal mode why should be convert?
21940 + The conversion should make no difference. */
21941 + && data->passed_mode != promoted_nominal_mode)
21942 + || promoted_nominal_mode != data->promoted_mode)
21944 int save_tree_used;
21946 --- a/gcc/genemit.c
21947 +++ b/gcc/genemit.c
21948 @@ -121,6 +121,24 @@ max_operand_vec (rtx insn, int arg)
21952 +gen_vararg_prologue(int operands)
21956 + if (operands > 1)
21958 + for (i = 1; i < operands; i++)
21959 + printf(" rtx operand%d ATTRIBUTE_UNUSED;\n", i);
21961 + printf(" va_list args;\n\n");
21962 + printf(" va_start(args, operand0);\n");
21963 + for (i = 1; i < operands; i++)
21964 + printf(" operand%d = va_arg(args, rtx);\n", i);
21965 + printf(" va_end(args);\n\n");
21970 print_code (RTX_CODE code)
21973 @@ -405,18 +423,16 @@ gen_insn (rtx insn, int lineno)
21974 fatal ("match_dup operand number has no match_operand");
21976 /* Output the function name and argument declarations. */
21977 - printf ("rtx\ngen_%s (", XSTR (insn, 0));
21978 + printf ("rtx\ngen_%s ", XSTR (insn, 0));
21981 - for (i = 0; i < operands; i++)
21983 - printf (",\n\trtx operand%d ATTRIBUTE_UNUSED", i);
21985 - printf ("rtx operand%d ATTRIBUTE_UNUSED", i);
21986 + printf("(rtx operand0 ATTRIBUTE_UNUSED, ...)\n");
21990 + printf("(void)\n");
21993 + gen_vararg_prologue(operands);
21995 /* Output code to construct and return the rtl for the instruction body. */
21997 if (XVECLEN (insn, 1) == 1)
21998 @@ -456,16 +472,12 @@ gen_expand (rtx expand)
21999 operands = max_operand_vec (expand, 1);
22001 /* Output the function name and argument declarations. */
22002 - printf ("rtx\ngen_%s (", XSTR (expand, 0));
22003 + printf ("rtx\ngen_%s ", XSTR (expand, 0));
22005 - for (i = 0; i < operands; i++)
22007 - printf (",\n\trtx operand%d", i);
22009 - printf ("rtx operand%d", i);
22010 + printf("(rtx operand0 ATTRIBUTE_UNUSED, ...)\n");
22014 + printf("(void)\n");
22018 /* If we don't have any C code to write, only one insn is being written,
22019 @@ -475,6 +487,8 @@ gen_expand (rtx expand)
22020 && operands > max_dup_opno
22021 && XVECLEN (expand, 1) == 1)
22023 + gen_vararg_prologue(operands);
22025 printf (" return ");
22026 gen_exp (XVECEXP (expand, 1, 0), DEFINE_EXPAND, NULL);
22027 printf (";\n}\n\n");
22028 @@ -488,6 +502,7 @@ gen_expand (rtx expand)
22029 for (; i <= max_scratch_opno; i++)
22030 printf (" rtx operand%d ATTRIBUTE_UNUSED;\n", i);
22031 printf (" rtx _val = 0;\n");
22032 + gen_vararg_prologue(operands);
22033 printf (" start_sequence ();\n");
22035 /* The fourth operand of DEFINE_EXPAND is some code to be executed
22036 --- a/gcc/genflags.c
22037 +++ b/gcc/genflags.c
22038 @@ -127,7 +127,6 @@ static void
22039 gen_proto (rtx insn)
22041 int num = num_operands (insn);
22043 const char *name = XSTR (insn, 0);
22044 int truth = maybe_eval_c_test (XSTR (insn, 2));
22046 @@ -158,12 +157,7 @@ gen_proto (rtx insn)
22048 fputs ("void", stdout);
22051 - for (i = 1; i < num; i++)
22052 - fputs ("rtx, ", stdout);
22054 - fputs ("rtx", stdout);
22056 + fputs("rtx, ...", stdout);
22060 @@ -173,12 +167,7 @@ gen_proto (rtx insn)
22062 printf ("static inline rtx\ngen_%s", name);
22066 - for (i = 0; i < num-1; i++)
22067 - printf ("rtx ARG_UNUSED (%c), ", 'a' + i);
22068 - printf ("rtx ARG_UNUSED (%c))\n", 'a' + i);
22070 + puts("(rtx ARG_UNUSED(a), ...)");
22073 puts ("{\n return 0;\n}");
22074 --- a/gcc/genoutput.c
22075 +++ b/gcc/genoutput.c
22076 @@ -386,7 +386,7 @@ output_insn_data (void)
22079 if (d->name && d->name[0] != '*')
22080 - printf (" (insn_gen_fn) gen_%s,\n", d->name);
22081 + printf (" gen_%s,\n", d->name);
22087 @@ -77,7 +77,7 @@ static int num_possible_if_blocks;
22088 static int num_updated_if_blocks;
22090 /* # of changes made which require life information to be updated. */
22091 -static int num_true_changes;
22092 +int num_true_changes;
22094 /* Whether conditional execution changes were made. */
22095 static int cond_exec_changed_p;
22096 @@ -287,12 +287,15 @@ cond_exec_process_insns (ce_if_block_t *
22100 - if (modified_in_p (test, insn))
22104 - must_be_last = TRUE;
22106 +#ifdef IFCVT_ALLOW_MODIFY_TEST_IN_INSN
22107 + if ( !IFCVT_ALLOW_MODIFY_TEST_IN_INSN )
22109 + if (modified_in_p (test, insn))
22113 + must_be_last = TRUE;
22116 /* Now build the conditional form of the instruction. */
22117 pattern = PATTERN (insn);
22118 @@ -566,16 +569,19 @@ cond_exec_process_if_block (ce_if_block_
22119 /* Do any machine dependent final modifications. */
22120 IFCVT_MODIFY_FINAL (ce_info);
22123 - /* Conversion succeeded. */
22125 - fprintf (dump_file, "%d insn%s converted to conditional execution.\n",
22126 - n_insns, (n_insns == 1) ? " was" : "s were");
22129 /* Merge the blocks! */
22130 - merge_if_block (ce_info);
22131 - cond_exec_changed_p = TRUE;
22133 + if ( reload_completed ){
22134 + /* Conversion succeeded. */
22136 + fprintf (dump_file, "%d insn%s converted to conditional execution.\n",
22137 + n_insns, (n_insns == 1) ? " was" : "s were");
22139 + merge_if_block (ce_info);
22140 + cond_exec_changed_p = TRUE;
22146 #ifdef IFCVT_MODIFY_CANCEL
22147 @@ -1050,7 +1056,11 @@ noce_try_addcc (struct noce_if_info *if_
22150 rtx cond = if_info->cond;
22151 - enum rtx_code code = reversed_comparison_code (cond, if_info->jump);
22152 + /* This generates wrong code for AVR32. The cond code need not be reversed
22153 + since the addmodecc patterns add if the condition is NOT met. */
22154 + /* enum rtx_code code = reversed_comparison_code (cond, if_info->jump);*/
22155 + enum rtx_code code = GET_CODE(cond);
22158 /* First try to use addcc pattern. */
22159 if (general_operand (XEXP (cond, 0), VOIDmode)
22160 @@ -2651,7 +2661,12 @@ process_if_block (struct ce_if_block * c
22161 && cond_move_process_if_block (ce_info))
22164 - if (HAVE_conditional_execution && reload_completed)
22165 + if (HAVE_conditional_execution &&
22166 +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD
22167 + (reload_completed || IFCVT_COND_EXEC_BEFORE_RELOAD))
22169 + reload_completed)
22172 /* If we have && and || tests, try to first handle combining the && and
22173 || tests into the conditional code, and if that fails, go back and
22174 @@ -4036,6 +4051,15 @@ rest_of_handle_if_after_reload (void)
22175 cleanup_cfg (CLEANUP_EXPENSIVE
22176 | CLEANUP_UPDATE_LIFE
22177 | (flag_crossjumping ? CLEANUP_CROSSJUMP : 0));
22179 + /* Hack for the AVR32 experimental ifcvt processing before reload.
22180 + The AVR32 specific ifcvt code needs to know when ifcvt after reload
22182 +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD
22183 + if ( IFCVT_COND_EXEC_BEFORE_RELOAD )
22184 + cfun->machine->ifcvt_after_reload = 1;
22187 if (flag_if_conversion2)
22190 --- a/gcc/longlong.h
22191 +++ b/gcc/longlong.h
22192 @@ -226,6 +226,41 @@ UDItype __umulsidi3 (USItype, USItype);
22193 #define UDIV_TIME 100
22194 #endif /* __arm__ */
22196 +#if defined (__avr32__) && W_TYPE_SIZE == 32
22197 +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
22198 + __asm__ ("add\t%1, %4, %5\n\tadc\t%0, %2, %3" \
22199 + : "=r" ((USItype) (sh)), \
22200 + "=&r" ((USItype) (sl)) \
22201 + : "r" ((USItype) (ah)), \
22202 + "r" ((USItype) (bh)), \
22203 + "r" ((USItype) (al)), \
22204 + "r" ((USItype) (bl)) __CLOBBER_CC)
22205 +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
22206 + __asm__ ("sub\t%1, %4, %5\n\tsbc\t%0, %2, %3" \
22207 + : "=r" ((USItype) (sh)), \
22208 + "=&r" ((USItype) (sl)) \
22209 + : "r" ((USItype) (ah)), \
22210 + "r" ((USItype) (bh)), \
22211 + "r" ((USItype) (al)), \
22212 + "r" ((USItype) (bl)) __CLOBBER_CC)
22214 +#if !defined (__AVR32_UC__) || __AVR32_UC__ != 3
22215 +#define __umulsidi3(a,b) ((UDItype)(a) * (UDItype)(b))
22217 +#define umul_ppmm(w1, w0, u, v) \
22220 + __w.ll = __umulsidi3 (u, v); \
22221 + w1 = __w.s.high; \
22222 + w0 = __w.s.low; \
22226 +#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X))
22227 +#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X))
22228 +#define COUNT_LEADING_ZEROS_0 32
22231 #if defined (__hppa) && W_TYPE_SIZE == 32
22232 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
22233 __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \
22236 @@ -431,7 +431,7 @@ extern enum insn_code reload_out_optab[N
22237 extern GTY(()) optab code_to_optab[NUM_RTX_CODE + 1];
22240 -typedef rtx (*rtxfun) (rtx);
22241 +typedef rtx (*rtxfun) (rtx, ...);
22243 /* Indexed by the rtx-code for a conditional (e.g. EQ, LT,...)
22244 gives the gen_function to make a branch to test that condition. */
22245 --- a/gcc/regrename.c
22246 +++ b/gcc/regrename.c
22247 @@ -1592,6 +1592,9 @@ copyprop_hardreg_forward_1 (basic_block
22248 bool changed = false;
22251 + rtx prev_pred_test;
22252 + int prev_pred_insn_skipped = 0;
22254 for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn))
22256 int n_ops, i, alt, predicated;
22257 @@ -1630,7 +1633,60 @@ copyprop_hardreg_forward_1 (basic_block
22258 || (predicated && recog_data.operand_type[i] == OP_OUT))
22259 recog_data.operand_type[i] = OP_INOUT;
22263 + /* Added for targets (AVR32) which supports test operands to be modified
22264 + in cond_exec instruction. For these targets we cannot make a change to
22265 + the test operands if one of the test operands is an output operand This beacuse
22266 + changing the test operands might cause the need for inserting a new test
22267 + insns in the middle of a sequence of cond_exec insns and if the test operands
22268 + are modified these tests will fail.
22271 + if ( IFCVT_ALLOW_MODIFY_TEST_IN_INSN
22274 + int insn_skipped = 0;
22275 + rtx test = COND_EXEC_TEST (PATTERN (insn));
22277 + /* Check if the previous insn was a skipped predicated insn with the same
22278 + test as this predicated insns. If so we cannot do any modification to
22279 + this insn either since we cannot emit the test insn because the operands
22280 + are clobbered. */
22281 + if ( prev_pred_insn_skipped
22282 + && (rtx_equal_p (test, prev_pred_test)
22283 + || rtx_equal_p (test, reversed_condition (prev_pred_test))) )
22285 + insn_skipped = 1;
22289 + /* Check if the output operand is used in the test expression. */
22290 + for (i = 0; i < n_ops; ++i)
22291 + if ( recog_data.operand_type[i] == OP_INOUT
22292 + && reg_mentioned_p (recog_data.operand[i], test) )
22294 + insn_skipped = 1;
22300 + prev_pred_test = test;
22301 + prev_pred_insn_skipped = insn_skipped;
22302 + if ( insn_skipped )
22304 + if (insn == BB_END (bb))
22312 + prev_pred_insn_skipped = 0;
22315 /* For each earlyclobber operand, zap the value data. */
22316 for (i = 0; i < n_ops; i++)
22317 if (recog_op_alt[i][alt].earlyclobber)
22320 @@ -4574,7 +4574,7 @@ find_reloads_toplev (rtx x, int opnum, e
22322 i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0),
22323 opnum, type, ind_levels, insn);
22325 + if (!rtx_equal_p (x, mem))
22326 push_reg_equiv_alt_mem (regno, x);
22327 if (address_reloaded)
22328 *address_reloaded = i;
22329 --- a/gcc/sched-deps.c
22330 +++ b/gcc/sched-deps.c
22331 @@ -649,7 +649,14 @@ fixup_sched_groups (rtx insn)
22333 prev_nonnote = prev_nonnote_insn (insn);
22334 if (BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (prev_nonnote)
22335 - && ! sched_insns_conditions_mutex_p (insn, prev_nonnote))
22336 + /* Modification for AVR32 by RP: Why is this here, this will
22337 + cause instruction to be without any dependencies which might
22338 + cause it to be moved anywhere. For the AVR32 we try to keep
22339 + a group of conditionals together even if they are mutual exclusive.
22341 + && (! sched_insns_conditions_mutex_p (insn, prev_nonnote)
22342 + || GET_CODE (PATTERN (insn)) == COND_EXEC )
22344 add_dependence (insn, prev_nonnote, REG_DEP_ANTI);
22347 @@ -1123,8 +1130,29 @@ sched_analyze_insn (struct deps *deps, r
22349 if (code == COND_EXEC)
22351 +#ifdef IFCVT_ALLOW_MODIFY_TEST_IN_INSN
22352 + if (IFCVT_ALLOW_MODIFY_TEST_IN_INSN)
22354 + /* Check if we have a group og conditional instructions with the same test.
22355 + If so we must make sure that they are not scheduled apart in order to
22356 + avoid unnecesarry tests and if one of the registers in the test is modified
22357 + in the instruction this is needed to ensure correct code. */
22358 + if ( prev_nonnote_insn (insn)
22359 + && INSN_P (prev_nonnote_insn (insn))
22360 + && GET_CODE (PATTERN (prev_nonnote_insn (insn))) == COND_EXEC
22361 + && rtx_equal_p (XEXP(COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn))), 0), XEXP (COND_EXEC_TEST (x), 0))
22362 + && rtx_equal_p (XEXP(COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn))), 1), XEXP (COND_EXEC_TEST (x), 1))
22363 + && ( GET_CODE (COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn)))) == GET_CODE (COND_EXEC_TEST (x))
22364 + || GET_CODE (COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn)))) == reversed_comparison_code (COND_EXEC_TEST (x), insn)))
22366 + SCHED_GROUP_P (insn) = 1;
22367 + //CANT_MOVE (prev_nonnote_insn (insn)) = 1;
22371 sched_analyze_2 (deps, COND_EXEC_TEST (x), insn);
22374 /* ??? Should be recording conditions so we reduce the number of
22375 false dependencies. */
22376 x = COND_EXEC_CODE (x);
22377 --- a/gcc/testsuite/gcc.dg/sibcall-3.c
22378 +++ b/gcc/testsuite/gcc.dg/sibcall-3.c
22380 Copyright (C) 2002 Free Software Foundation Inc.
22381 Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
22383 -/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
22384 +/* { dg-do run { xfail arc-*-* avr-*-* avr32-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
22385 /* { dg-options "-O2 -foptimize-sibling-calls" } */
22387 /* The option -foptimize-sibling-calls is the default, but serves as
22388 --- a/gcc/testsuite/gcc.dg/sibcall-4.c
22389 +++ b/gcc/testsuite/gcc.dg/sibcall-4.c
22391 Copyright (C) 2002 Free Software Foundation Inc.
22392 Contributed by Hans-Peter Nilsson <hp@bitrange.com> */
22394 -/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
22395 +/* { dg-do run { xfail arc-*-* avr-*-* avr32-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */
22396 /* { dg-options "-O2 -foptimize-sibling-calls" } */
22398 /* The option -foptimize-sibling-calls is the default, but serves as
22399 --- a/gcc/testsuite/gcc.dg/trampoline-1.c
22400 +++ b/gcc/testsuite/gcc.dg/trampoline-1.c
22401 @@ -46,6 +46,8 @@ void foo (void)
22405 +#ifndef NO_TRAMPOLINES
22410 --- a/gcc/testsuite/g++.old-deja/g++.pt/static11.C
22411 +++ b/gcc/testsuite/g++.old-deja/g++.pt/static11.C
22413 // in their dejagnu baseboard description) require that the status is
22414 // final when exit is entered (or main returns), and not "overruled" by a
22415 // destructor calling _exit. It's not really worth it to handle that.
22416 -// { dg-do run { xfail mmix-knuth-mmixware xtensa-*-elf* arm*-*-elf arm*-*-eabi m68k-*-elf } }
22417 +// { dg-do run { xfail mmix-knuth-mmixware xtensa-*-elf* avr32-*-elf arm*-*-elf arm*-*-eabi m68k-*-elf } }
22419 // Bug: g++ was failing to destroy C<int>::a because it was using two
22420 // different sentry variables for construction and destruction.
22421 --- a/gcc/version.c
22422 +++ b/gcc/version.c
22424 in parentheses. You may also wish to include a number indicating
22425 the revision of your modified compiler. */
22427 -#define VERSUFFIX ""
22428 +#define VERSUFFIX "-atmel.1.1.3.avr32linux.1"
22430 /* This is the location of the online document giving instructions for
22431 reporting bugs. If you distribute a modified version of GCC,
22433 forward us bugs reported to you, if you determine that they are
22434 not bugs in your modifications.) */
22436 -const char bug_report_url[] = "<URL:http://gcc.gnu.org/bugs.html>";
22437 +const char bug_report_url[] = "<URL:http://www.atmel.com/avr32/>";
22439 /* The complete version string, assembled from several pieces.
22440 BASEVER, DATESTAMP, and DEVPHASE are defined by the Makefile. */
22442 -const char version_string[] = BASEVER DATESTAMP DEVPHASE VERSUFFIX;
22443 +const char version_string[] = BASEVER VERSUFFIX DATESTAMP DEVPHASE;
22444 --- a/libstdc++-v3/acinclude.m4
22445 +++ b/libstdc++-v3/acinclude.m4
22446 @@ -125,15 +125,6 @@ AC_DEFUN([GLIBCXX_CONFIGURE], [
22447 ## other macros from doing the same. This should be automated.) -pme
22450 - # Check for uClibc since Linux platforms use different configuration
22451 - # directories depending on the C library in use.
22452 - AC_EGREP_CPP([_using_uclibc], [
22453 - #include <stdio.h>
22457 - ], uclibc=yes, uclibc=no)
22459 # Find platform-specific directories containing configuration info.
22460 # Also possibly modify flags used elsewhere, as needed by the platform.
22462 @@ -1389,8 +1380,8 @@ AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [
22466 - const char __one[] = "Äuglein Augmen";
22467 - const char __two[] = "Äuglein";
22468 + const char __one[] = "Äuglein Augmen";
22469 + const char __two[] = "Äuglein";
22473 --- a/libstdc++-v3/config/os/gnu-linux/ctype_base.h
22474 +++ b/libstdc++-v3/config/os/gnu-linux/ctype_base.h
22477 // ISO C++ 14882: 22.1 Locales
22479 +#include <features.h>
22480 +#include <ctype.h>
22482 /** @file ctype_base.h
22483 * This is an internal header file, included by other library headers.
22484 @@ -45,8 +47,12 @@ _GLIBCXX_BEGIN_NAMESPACE(std)
22487 // Non-standard typedefs.
22488 - typedef const int* __to_type;
22491 + typedef const __ctype_touplow_t* __to_type;
22493 + typedef const int* __to_type;
22496 // NB: Offsets into ctype<char>::_M_table force a particular size
22497 // on the mask type. Because of this, we don't use an enum.
22498 typedef unsigned short mask;
22499 --- a/libstdc++-v3/include/Makefile.in
22500 +++ b/libstdc++-v3/include/Makefile.in
22501 @@ -36,6 +36,7 @@ POST_UNINSTALL = :
22502 build_triplet = @build@
22503 host_triplet = @host@
22504 target_triplet = @target@
22506 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
22507 $(top_srcdir)/fragment.am
22509 --- a/libstdc++-v3/libmath/Makefile.in
22510 +++ b/libstdc++-v3/libmath/Makefile.in
22511 @@ -37,6 +37,7 @@ POST_UNINSTALL = :
22512 build_triplet = @build@
22513 host_triplet = @host@
22514 target_triplet = @target@
22517 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in
22518 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
22519 --- a/libstdc++-v3/libsupc++/Makefile.in
22520 +++ b/libstdc++-v3/libsupc++/Makefile.in
22521 @@ -38,6 +38,7 @@ POST_UNINSTALL = :
22522 build_triplet = @build@
22523 host_triplet = @host@
22524 target_triplet = @target@
22526 DIST_COMMON = $(glibcxxinstall_HEADERS) $(srcdir)/Makefile.am \
22527 $(srcdir)/Makefile.in $(top_srcdir)/fragment.am
22529 --- a/libstdc++-v3/Makefile.in
22530 +++ b/libstdc++-v3/Makefile.in
22531 @@ -36,6 +36,7 @@ POST_UNINSTALL = :
22532 build_triplet = @build@
22533 host_triplet = @host@
22534 target_triplet = @target@
22536 DIST_COMMON = README $(am__configure_deps) $(srcdir)/../config.guess \
22537 $(srcdir)/../config.sub $(srcdir)/../install-sh \
22538 $(srcdir)/../ltmain.sh $(srcdir)/../missing \
22539 --- a/libstdc++-v3/po/Makefile.in
22540 +++ b/libstdc++-v3/po/Makefile.in
22541 @@ -36,6 +36,7 @@ POST_UNINSTALL = :
22542 build_triplet = @build@
22543 host_triplet = @host@
22544 target_triplet = @target@
22546 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
22547 $(top_srcdir)/fragment.am
22549 --- a/libstdc++-v3/src/Makefile.in
22550 +++ b/libstdc++-v3/src/Makefile.in
22551 @@ -36,6 +36,7 @@ POST_UNINSTALL = :
22552 build_triplet = @build@
22553 host_triplet = @host@
22554 target_triplet = @target@
22556 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \
22557 $(top_srcdir)/fragment.am
22561 @@ -481,7 +481,7 @@ lang_env_dependencies = { module=rda; };
22562 lang_env_dependencies = { module=winsup; };
22563 lang_env_dependencies = { module=qthreads; };
22565 -dependencies = { module=all-target-libgloss; on=configure-target-newlib; };
22566 +dependencies = { module=all-target-libgloss; on=all-target-newlib; };
22567 dependencies = { module=all-target-winsup; on=all-target-libiberty; };
22568 dependencies = { module=all-target-winsup; on=all-target-libtermcap; };
22572 @@ -43791,7 +43791,7 @@ all-target-libobjc: maybe-all-target-boe
22573 all-target-libstdc++-v3: maybe-all-target-libiberty
22574 install-target-libssp: maybe-install-gcc
22575 install-target-libgomp: maybe-install-gcc
22576 -all-target-libgloss: maybe-configure-target-newlib
22577 +all-target-libgloss: maybe-all-target-newlib
22578 all-target-winsup: maybe-all-target-libiberty
22579 all-target-winsup: maybe-all-target-libtermcap
22581 --- a/gcc/configure.ac
22582 +++ b/gcc/configure.ac
22583 @@ -2158,7 +2158,7 @@ L2:],
22584 as_ver=`$gcc_cv_as --version 2>/dev/null | sed 1q`
22585 if echo "$as_ver" | grep GNU > /dev/null; then
22587 - as_ver=`echo $as_ver | sed -e 's/GNU assembler \([0-9.][0-9.]*\).*/\1/'`
22588 + as_ver=`echo $as_ver | sed -e 's/GNU assembler\( (GNU Binutils)\)\? \([0-9.][0-9.]*\).*/\2/'`
22589 as_major=`echo $as_ver | sed 's/\..*//'`
22590 as_minor=`echo $as_ver | sed 's/[^.]*\.\([0-9]*\).*/\1/'`
22591 changequote([,])dnl
22592 @@ -2971,7 +2971,7 @@ esac
22594 i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \
22595 | x86_64*-*-* | hppa*-*-* | arm*-*-* | strongarm*-*-* | xscale*-*-* \
22596 - | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-*)
22597 + | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-* | avr32-*-*)
22600 ia64*-*-* | s390*-*-*)
22601 --- a/gcc/configure
22602 +++ b/gcc/configure
22603 @@ -14023,7 +14023,7 @@ L2:' > conftest.s
22604 # arbitrary sections are supported and try the test.
22605 as_ver=`$gcc_cv_as --version 2>/dev/null | sed 1q`
22606 if echo "$as_ver" | grep GNU > /dev/null; then
22607 - as_ver=`echo $as_ver | sed -e 's/GNU assembler \([0-9.][0-9.]*\).*/\1/'`
22608 + as_ver=`echo $as_ver | sed -e 's/GNU assembler\( (GNU Binutils)\)\? \([0-9.][0-9.]*\).*/\2/'`
22609 as_major=`echo $as_ver | sed 's/\..*//'`
22610 as_minor=`echo $as_ver | sed 's/[^.]*\.\([0-9]*\).*/\1/'`
22611 if test $as_major -eq 2 && test $as_minor -lt 11
22612 @@ -15610,7 +15610,7 @@ esac
22614 i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \
22615 | x86_64*-*-* | hppa*-*-* | arm*-*-* | strongarm*-*-* | xscale*-*-* \
22616 - | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-*)
22617 + | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-* | avr32-*-*)
22620 ia64*-*-* | s390*-*-*)