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patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
author "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>
Sun Jul 17 22:46:47 2011 +0200 (2011-07-17)
changeset 2892 aa934ec4b4ee
parent 746 b150d6f590fc
permissions -rw-r--r--
cc/gcc: add the backend/frontend infra for final gcc

Currently, we issue the bare-metal compiler from the pass_1 & pass_2
core compilers, because the final gcc breaks while doing so.

This implies we have to build some libces during the start_files step,
instead of the standard libc step. This is the case for newlib.

By adding a backend/frontend infra to the final gcc, we can abstract
what backend to call: the standard backend for non-bare-metal gcc,
and the core backend for bare-metal.

This patch is just an no-op, it just adds the final backend and
frontend without changing the way bare-metal is built, to come in a
subsequent patch.

Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr> 
     1 diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c

     2 --- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200

     3 +++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200

     4 @@ -4572,6 +4572,10 @@

     5  int

     6  adjacent_mem_locations (rtx a, rtx b)

     7  {

     8 +  /* We don't guarantee to preserve the order of these memory refs.  */

     9 +  if (volatile_refs_p (a) || volatile_refs_p (b))

    10 +    return 0;

    11 +

    12    if ((GET_CODE (XEXP (a, 0)) == REG

    13         || (GET_CODE (XEXP (a, 0)) == PLUS

    14  	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))

    15 @@ -4611,6 +4615,17 @@

    16  	return 0;

    17  

    18        val_diff = val1 - val0;

    19 +

    20 +      if (arm_ld_sched)

    21 +	{

    22 +	  /* If the target has load delay slots, then there's no benefit

    23 +	     to using an ldm instruction unless the offset is zero and

    24 +	     we are optimizing for size.  */

    25 +	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))

    26 +		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)

    27 +		  && (val_diff == 4 || val_diff == -4));

    28 +	}

    29 +

    30        return ((REGNO (reg0) == REGNO (reg1))

    31  	      && (val_diff == 4 || val_diff == -4));

    32      }
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