crosstool-ng: patches/glibc/2.6.1/160-use_short_for

arch: add softfp support

Some architectures support a mixed hard/soft floating point, where
the compiler emits hardware floating point instructions, but passes
the operands in core (aka integer) registers.

For example, ARM supports this mode (to come in the next changeset).

Add support for softfp cross compilers to the GCC and GLIBC
configuration. Needed for Ubuntu and other distros that are softfp.

Signed-off-by: Michael Hope <michael.hope@linaro.org>
[yann.morin.1998@anciens.enib.fr: split the original patch]
Signed-off-by: "Yann E. MORIN" <yann.morin.1998@anciens.enib.fr>

     1 Original patch from H.J. Lu, as reported there:

     2 http://www.nabble.com/PATCH:-Use-short-for-fnstsw-td14775171.html

     4 fnstsw stores 16bit into %ax. The upper 16bit of %eax is unchanged.

     5 The new assembler (binutils-2.18.50.0.4 and up) will disallow "fnstsw %eax".

     7 diff -dur glibc-2.6.1.orig/sysdeps/i386/fpu/ftestexcept.c glibc-2.6.1/sysdeps/i386/fpu/ftestexcept.c

     8 --- glibc-2.6.1.orig/sysdeps/i386/fpu/ftestexcept.c	2004-03-05 11:14:48.000000000 +0100

     9 +++ glibc-2.6.1/sysdeps/i386/fpu/ftestexcept.c	2008-06-24 10:56:14.000000000 +0200

    10 @@ -26,7 +26,7 @@

    11  int

    12  fetestexcept (int excepts)

    13  {

    14 -  int temp;

    15 +  short temp;

    16    int xtemp = 0;

    18    /* Get current exceptions.  */

author	Michael Hope <michael.hope@linaro.org>
	Wed Oct 19 15:27:32 2011 +1300 (2011-10-19)
changeset 2739	f320e22f2cba
parent 607	aaf7ae5cb11a
permissions	-rw-r--r--