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patches/eglibc/2_9/100-powerpc-8xx-CPU15-errata.patch
author Johannes Stezenbach <js@sig21.net>
Thu Jul 29 19:47:16 2010 +0200 (2010-07-29)
changeset 2045 fdaa6c7f6dea
permissions -rw-r--r--
cc/gcc: add option to compile against static libstdc++, for gcc-4.4 and newer

Idea and know-how taken from CodeSourcery build script.

Normal build:
$ ldd arm-unknown-linux-uclibcgnueabi-gcc
linux-gate.so.1 => (0xb77f3000)
libstdc++.so.6 => /usr/lib/libstdc++.so.6 (0xb76e8000)
libc.so.6 => /lib/i686/cmov/libc.so.6 (0xb75a1000)
libm.so.6 => /lib/i686/cmov/libm.so.6 (0xb757a000)
/lib/ld-linux.so.2 (0xb77f4000)
libgcc_s.so.1 => /lib/libgcc_s.so.1 (0xb755c000)

CC_STATIC_LIBSTDCXX=y:
$ ldd arm-unknown-linux-uclibcgnueabi-gcc
linux-gate.so.1 => (0xb7843000)
libc.so.6 => /lib/i686/cmov/libc.so.6 (0xb76e6000)
/lib/ld-linux.so.2 (0xb7844000)

I made CC_STATIC_LIBSTDCXX default=y since I think
it is always desirable.

Signed-off-by: Johannes Stezenbach <js@sig21.net> 
     1 diff -ru eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S

     2 --- eglibc-2_9_orig/sysdeps/powerpc/powerpc32/memset.S	2007-04-13 08:35:45.000000000 -0700

     3 +++ eglibc-2_9/sysdeps/powerpc/powerpc32/memset.S	2009-05-06 16:52:04.000000000 -0700

     4 @@ -112,11 +112,13 @@

     5  	clrrwi.	rALIGN, rLEN, 5

     6  	mtcrf	0x01, rLEN	/* 40th instruction from .align */

     7  

     8 +#ifndef BROKEN_PPC_8xx_CPU15

     9  /* Check if we can use the special case for clearing memory using dcbz.

    10     This requires that we know the correct cache line size for this

    11     processor.  Getting the __cache_line_size may require establishing GOT

    12     addressability, so branch out of line to set this up.  */

    13  	beq	cr1, L(checklinesize)

    14 +#endif

    15  

    16  /* Store blocks of 32-bytes (256-bits) starting on a 32-byte boundary.

    17     Can't assume that rCHR is zero or that the cache line size is either

    18 @@ -158,6 +160,7 @@

    19  	add	rMEMP, rMEMP, rALIGN

    20  	b	L(medium_tail2)	/* 72nd instruction from .align */

    21  

    22 +#ifndef BROKEN_PPC_8xx_CPU15

    23  	.align	5

    24  	nop

    25  /* Clear cache lines of memory in 128-byte chunks.

    26 @@ -191,6 +194,7 @@

    27  	bdnz	L(zloop)

    28  	beqlr	cr5

    29  	b	L(medium_tail2)

    30 +#endif /* ! BROKEN_PPC_8xx_CPU15 */

    31  

    32  	.align	5

    33  L(small):

    34 @@ -248,6 +252,7 @@

    35  	stw	rCHR, -8(rMEMP)

    36  	blr

    37  

    38 +#ifndef BROKEN_PPC_8xx_CPU15

    39  L(checklinesize):

    40  #ifdef SHARED

    41  	mflr	rTMP

    42 @@ -329,6 +334,7 @@

    43  L(handletail32):

    44  	clrrwi.	rALIGN, rLEN, 5

    45  	b	L(nondcbz)

    46 +#endif /* ! BROKEN_PPC_8xx_CPU15 */

    47  

    48  END (BP_SYM (memset))

    49  libc_hidden_builtin_def (memset)
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