yann@339: diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
yann@339: --- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
yann@339: +++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
yann@339: @@ -4572,6 +4572,10 @@
yann@339:  int
yann@339:  adjacent_mem_locations (rtx a, rtx b)
yann@339:  {
yann@339: +  /* We don't guarantee to preserve the order of these memory refs.  */
yann@339: +  if (volatile_refs_p (a) || volatile_refs_p (b))
yann@339: +    return 0;
yann@339: +
yann@339:    if ((GET_CODE (XEXP (a, 0)) == REG
yann@339:         || (GET_CODE (XEXP (a, 0)) == PLUS
yann@339:  	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
yann@339: @@ -4611,6 +4615,17 @@
yann@339:  	return 0;
yann@339:  
yann@339:        val_diff = val1 - val0;
yann@339: +
yann@339: +      if (arm_ld_sched)
yann@339: +	{
yann@339: +	  /* If the target has load delay slots, then there's no benefit
yann@339: +	     to using an ldm instruction unless the offset is zero and
yann@339: +	     we are optimizing for size.  */
yann@339: +	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
yann@339: +		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
yann@339: +		  && (val_diff == 4 || val_diff == -4));
yann@339: +	}
yann@339: +
yann@339:        return ((REGNO (reg0) == REGNO (reg1))
yann@339:  	      && (val_diff == 4 || val_diff == -4));
yann@339:      }