mgl@1371: --- a/configure.in mgl@1371: +++ b/configure.in mgl@1371: @@ -503,6 +503,9 @@ case "${target}" in mgl@1371: arm-*-riscix*) mgl@1371: noconfigdirs="$noconfigdirs ld target-libgloss ${libgcj}" mgl@1371: ;; mgl@1371: + avr32-*-*) mgl@1371: + noconfigdirs="$noconfigdirs target-libiberty target-libmudflap target-libffi ${libgcj}" mgl@1371: + ;; mgl@1371: avr-*-*) mgl@1371: noconfigdirs="$noconfigdirs target-libiberty target-libstdc++-v3 ${libgcj}" mgl@1371: ;; mgl@1371: --- a/gcc/builtins.c mgl@1371: +++ b/gcc/builtins.c mgl@1371: @@ -9223,7 +9223,7 @@ validate_arglist (tree arglist, ...) mgl@1371: mgl@1371: do mgl@1371: { mgl@1371: - code = va_arg (ap, enum tree_code); mgl@1371: + code = va_arg (ap, int); mgl@1371: switch (code) mgl@1371: { mgl@1371: case 0: mgl@1371: --- a/gcc/calls.c mgl@1371: +++ b/gcc/calls.c mgl@1371: @@ -3447,7 +3447,7 @@ emit_library_call_value_1 (int retval, r mgl@1371: for (; count < nargs; count++) mgl@1371: { mgl@1371: rtx val = va_arg (p, rtx); mgl@1371: - enum machine_mode mode = va_arg (p, enum machine_mode); mgl@1371: + enum machine_mode mode = va_arg (p, int); mgl@1371: mgl@1371: /* We cannot convert the arg value to the mode the library wants here; mgl@1371: must do it earlier where we know the signedness of the arg. */ mgl@1371: --- a/gcc/c-incpath.c mgl@1371: +++ b/gcc/c-incpath.c mgl@1371: @@ -347,6 +347,18 @@ add_path (char *path, int chain, int cxx mgl@1371: char* c; mgl@1371: for (c = path; *c; c++) mgl@1371: if (*c == '\\') *c = '/'; mgl@1371: + /* Remove unnecessary trailing slashes. On some versions of MS mgl@1371: + Windows, trailing _forward_ slashes cause no problems for stat(). mgl@1371: + On newer versions, stat() does not recognise a directory that ends mgl@1371: + in a '\\' or '/', unless it is a drive root dir, such as "c:/", mgl@1371: + where it is obligatory. */ mgl@1371: + int pathlen = strlen (path); mgl@1371: + char* end = path + pathlen - 1; mgl@1371: + /* Preserve the lead '/' or lead "c:/". */ mgl@1371: + char* start = path + (pathlen > 2 && path[1] == ':' ? 3 : 1); mgl@1371: + mgl@1371: + for (; end > start && IS_DIR_SEPARATOR (*end); end--) mgl@1371: + *end = 0; mgl@1371: #endif mgl@1371: mgl@1371: p = XNEW (cpp_dir); mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32.c mgl@1371: @@ -0,0 +1,7915 @@ mgl@1371: +/* mgl@1371: + Target hooks and helper functions for AVR32. mgl@1371: + Copyright 2003-2006 Atmel Corporation. mgl@1371: + mgl@1371: + Written by Ronny Pedersen, Atmel Norway, mgl@1371: + Initial porting by Anders �dland. mgl@1371: + mgl@1371: + This file is part of GCC. mgl@1371: + mgl@1371: + This program is free software; you can redistribute it and/or modify mgl@1371: + it under the terms of the GNU General Public License as published by mgl@1371: + the Free Software Foundation; either version 2 of the License, or mgl@1371: + (at your option) any later version. mgl@1371: + mgl@1371: + This program is distributed in the hope that it will be useful, mgl@1371: + but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: + GNU General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; if not, write to the Free Software mgl@1371: + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ mgl@1371: + mgl@1371: +#include "config.h" mgl@1371: +#include "system.h" mgl@1371: +#include "coretypes.h" mgl@1371: +#include "tm.h" mgl@1371: +#include "rtl.h" mgl@1371: +#include "tree.h" mgl@1371: +#include "obstack.h" mgl@1371: +#include "regs.h" mgl@1371: +#include "hard-reg-set.h" mgl@1371: +#include "real.h" mgl@1371: +#include "insn-config.h" mgl@1371: +#include "conditions.h" mgl@1371: +#include "output.h" mgl@1371: +#include "insn-attr.h" mgl@1371: +#include "flags.h" mgl@1371: +#include "reload.h" mgl@1371: +#include "function.h" mgl@1371: +#include "expr.h" mgl@1371: +#include "optabs.h" mgl@1371: +#include "toplev.h" mgl@1371: +#include "recog.h" mgl@1371: +#include "ggc.h" mgl@1371: +#include "except.h" mgl@1371: +#include "c-pragma.h" mgl@1371: +#include "integrate.h" mgl@1371: +#include "tm_p.h" mgl@1371: +#include "langhooks.h" mgl@1371: + mgl@1371: +#include "target.h" mgl@1371: +#include "target-def.h" mgl@1371: + mgl@1371: +#include mgl@1371: + mgl@1371: +/* Forward definitions of types. */ mgl@1371: +typedef struct minipool_node Mnode; mgl@1371: +typedef struct minipool_fixup Mfix; mgl@1371: + mgl@1371: +/* Obstack for minipool constant handling. */ mgl@1371: +static struct obstack minipool_obstack; mgl@1371: +static char *minipool_startobj; mgl@1371: +static rtx minipool_vector_label; mgl@1371: + mgl@1371: +/* True if we are currently building a constant table. */ mgl@1371: +int making_const_table; mgl@1371: + mgl@1371: +/* Some forward function declarations */ mgl@1371: +static unsigned long avr32_isr_value (tree); mgl@1371: +static unsigned long avr32_compute_func_type (void); mgl@1371: +static tree avr32_handle_isr_attribute (tree *, tree, tree, int, bool *); mgl@1371: +static tree avr32_handle_acall_attribute (tree *, tree, tree, int, bool *); mgl@1371: +static tree avr32_handle_fndecl_attribute (tree * node, tree name, tree args, mgl@1371: + int flags, bool * no_add_attrs); mgl@1371: +static void avr32_reorg (void); mgl@1371: +bool avr32_return_in_msb (tree type); mgl@1371: +bool avr32_vector_mode_supported (enum machine_mode mode); mgl@1371: +static void avr32_init_libfuncs (void); mgl@1371: + mgl@1371: + mgl@1371: +static void mgl@1371: +avr32_add_gc_roots (void) mgl@1371: +{ mgl@1371: + gcc_obstack_init (&minipool_obstack); mgl@1371: + minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* List of all known AVR32 parts */ mgl@1371: +static const struct part_type_s avr32_part_types[] = { mgl@1371: + /* name, part_type, architecture type, macro */ mgl@1371: + {"none", PART_TYPE_AVR32_NONE, ARCH_TYPE_AVR32_AP, "__AVR32__"}, mgl@1371: + {"ap7000", PART_TYPE_AVR32_AP7000, ARCH_TYPE_AVR32_AP, "__AVR32_AP7000__"}, mgl@1371: + {"ap7001", PART_TYPE_AVR32_AP7001, ARCH_TYPE_AVR32_AP, "__AVR32_AP7001__"}, mgl@1371: + {"ap7002", PART_TYPE_AVR32_AP7002, ARCH_TYPE_AVR32_AP, "__AVR32_AP7002__"}, mgl@1371: + {"ap7200", PART_TYPE_AVR32_AP7200, ARCH_TYPE_AVR32_AP, "__AVR32_AP7200__"}, mgl@1371: + {"uc3a0128", PART_TYPE_AVR32_UC3A0128, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A0128__"}, mgl@1371: + {"uc3a0256", PART_TYPE_AVR32_UC3A0256, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A0256__"}, mgl@1371: + {"uc3a0512", PART_TYPE_AVR32_UC3A0512, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A0512__"}, mgl@1371: + {"uc3a0512es", PART_TYPE_AVR32_UC3A0512ES, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3A0512ES__"}, mgl@1371: + {"uc3a1128", PART_TYPE_AVR32_UC3A1128, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A1128__"}, mgl@1371: + {"uc3a1256", PART_TYPE_AVR32_UC3A1256, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A1256__"}, mgl@1371: + {"uc3a1512", PART_TYPE_AVR32_UC3A1512, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A1512__"}, mgl@1371: + {"uc3a1512es", PART_TYPE_AVR32_UC3A1512ES, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3A1512ES__"}, mgl@1371: + {"uc3a3revd", PART_TYPE_AVR32_UC3A3REVD, ARCH_TYPE_AVR32_UCR2NOMUL, mgl@1371: + "__AVR32_UC3A3256S__"}, mgl@1371: + {"uc3a364", PART_TYPE_AVR32_UC3A364, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A364__"}, mgl@1371: + {"uc3a364s", PART_TYPE_AVR32_UC3A364S, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A364S__"}, mgl@1371: + {"uc3a3128", PART_TYPE_AVR32_UC3A3128, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A3128__"}, mgl@1371: + {"uc3a3128s", PART_TYPE_AVR32_UC3A3128S, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A3128S__"}, mgl@1371: + {"uc3a3256", PART_TYPE_AVR32_UC3A3256, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A3256__"}, mgl@1371: + {"uc3a3256s", PART_TYPE_AVR32_UC3A3256S, ARCH_TYPE_AVR32_UCR2, mgl@1371: + "__AVR32_UC3A3256S__"}, mgl@1371: + {"uc3b064", PART_TYPE_AVR32_UC3B064, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B064__"}, mgl@1371: + {"uc3b0128", PART_TYPE_AVR32_UC3B0128, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B0128__"}, mgl@1371: + {"uc3b0256", PART_TYPE_AVR32_UC3B0256, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B0256__"}, mgl@1371: + {"uc3b0256es", PART_TYPE_AVR32_UC3B0256ES, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B0256ES__"}, mgl@1371: + {"uc3b164", PART_TYPE_AVR32_UC3B164, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B164__"}, mgl@1371: + {"uc3b1128", PART_TYPE_AVR32_UC3B1128, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B1128__"}, mgl@1371: + {"uc3b1256", PART_TYPE_AVR32_UC3B1256, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B1256__"}, mgl@1371: + {"uc3b1256es", PART_TYPE_AVR32_UC3B1256ES, ARCH_TYPE_AVR32_UCR1, mgl@1371: + "__AVR32_UC3B1256ES__"}, mgl@1371: + {NULL, 0, 0, NULL} mgl@1371: +}; mgl@1371: + mgl@1371: +/* List of all known AVR32 architectures */ mgl@1371: +static const struct arch_type_s avr32_arch_types[] = { mgl@1371: + /* name, architecture type, microarchitecture type, feature flags, macro */ mgl@1371: + {"ap", ARCH_TYPE_AVR32_AP, UARCH_TYPE_AVR32B, mgl@1371: + (FLAG_AVR32_HAS_DSP mgl@1371: + | FLAG_AVR32_HAS_SIMD mgl@1371: + | FLAG_AVR32_HAS_UNALIGNED_WORD mgl@1371: + | FLAG_AVR32_HAS_BRANCH_PRED | FLAG_AVR32_HAS_RETURN_STACK mgl@1371: + | FLAG_AVR32_HAS_CACHES), mgl@1371: + "__AVR32_AP__"}, mgl@1371: + {"ucr1", ARCH_TYPE_AVR32_UCR1, UARCH_TYPE_AVR32A, mgl@1371: + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW), mgl@1371: + "__AVR32_UC__=1"}, mgl@1371: + {"ucr2", ARCH_TYPE_AVR32_UCR2, UARCH_TYPE_AVR32A, mgl@1371: + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW mgl@1371: + | FLAG_AVR32_HAS_V2_INSNS), mgl@1371: + "__AVR32_UC__=2"}, mgl@1371: + {"ucr2nomul", ARCH_TYPE_AVR32_UCR2NOMUL, UARCH_TYPE_AVR32A, mgl@1371: + (FLAG_AVR32_HAS_DSP | FLAG_AVR32_HAS_RMW mgl@1371: + | FLAG_AVR32_HAS_V2_INSNS | FLAG_AVR32_HAS_NO_MUL_INSNS), mgl@1371: + "__AVR32_UC__=3"}, mgl@1371: + {NULL, 0, 0, 0, NULL} mgl@1371: +}; mgl@1371: + mgl@1371: +/* Default arch name */ mgl@1371: +const char *avr32_arch_name = "none"; mgl@1371: +const char *avr32_part_name = "none"; mgl@1371: + mgl@1371: +const struct part_type_s *avr32_part; mgl@1371: +const struct arch_type_s *avr32_arch; mgl@1371: + mgl@1371: + mgl@1371: +/* Set default target_flags. */ mgl@1371: +#undef TARGET_DEFAULT_TARGET_FLAGS mgl@1371: +#define TARGET_DEFAULT_TARGET_FLAGS \ mgl@1371: + (MASK_HAS_ASM_ADDR_PSEUDOS | MASK_MD_REORG_OPTIMIZATION | MASK_COND_EXEC_BEFORE_RELOAD) mgl@1371: + mgl@1371: +void mgl@1371: +avr32_optimization_options (int level, mgl@1371: + int size){ mgl@1371: + if (AVR32_ALWAYS_PIC) mgl@1371: + flag_pic = 1; mgl@1371: + mgl@1371: + /* Enable section anchors if optimization is enabled. */ mgl@1371: + if (level > 0 || size) mgl@1371: + flag_section_anchors = 1; mgl@1371: +} mgl@1371: + mgl@1371: +/* Override command line options */ mgl@1371: +void mgl@1371: +avr32_override_options (void) mgl@1371: +{ mgl@1371: + const struct part_type_s *part; mgl@1371: + const struct arch_type_s *arch; mgl@1371: + mgl@1371: + /*Add backward compability*/ mgl@1371: + if (strcmp ("uc", avr32_arch_name)== 0) mgl@1371: + { mgl@1371: + fprintf (stderr, "Warning: Deprecated arch `%s' specified. " mgl@1371: + "Please use '-march=ucr1' instead. " mgl@1371: + "Converting to arch 'ucr1'\n", mgl@1371: + avr32_arch_name); mgl@1371: + avr32_arch_name="ucr1"; mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if arch type is set. */ mgl@1371: + for (arch = avr32_arch_types; arch->name; arch++) mgl@1371: + { mgl@1371: + if (strcmp (arch->name, avr32_arch_name) == 0) mgl@1371: + break; mgl@1371: + } mgl@1371: + avr32_arch = arch; mgl@1371: + mgl@1371: + if (!arch->name && strcmp("none", avr32_arch_name) != 0) mgl@1371: + { mgl@1371: + fprintf (stderr, "Unknown arch `%s' specified\n" mgl@1371: + "Known arch names:\n" mgl@1371: + "\tuc (deprecated)\n", mgl@1371: + avr32_arch_name); mgl@1371: + for (arch = avr32_arch_types; arch->name; arch++) mgl@1371: + fprintf (stderr, "\t%s\n", arch->name); mgl@1371: + avr32_arch = &avr32_arch_types[ARCH_TYPE_AVR32_AP]; mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if part type is set. */ mgl@1371: + for (part = avr32_part_types; part->name; part++) mgl@1371: + if (strcmp (part->name, avr32_part_name) == 0) mgl@1371: + break; mgl@1371: + mgl@1371: + avr32_part = part; mgl@1371: + if (!part->name) mgl@1371: + { mgl@1371: + fprintf (stderr, "Unknown part `%s' specified\nKnown part names:\n", mgl@1371: + avr32_part_name); mgl@1371: + for (part = avr32_part_types; part->name; part++) mgl@1371: + { mgl@1371: + if (strcmp("none", part->name) != 0) mgl@1371: + fprintf (stderr, "\t%s\n", part->name); mgl@1371: + } mgl@1371: + /* Set default to NONE*/ mgl@1371: + avr32_part = &avr32_part_types[PART_TYPE_AVR32_NONE]; mgl@1371: + } mgl@1371: + mgl@1371: + /* NB! option -march= overrides option -mpart mgl@1371: + * if both are used at the same time */ mgl@1371: + if (!arch->name) mgl@1371: + avr32_arch = &avr32_arch_types[avr32_part->arch_type]; mgl@1371: + mgl@1371: + /* If optimization level is two or greater, then align start of loops to a mgl@1371: + word boundary since this will allow folding the first insn of the loop. mgl@1371: + Do this only for targets supporting branch prediction. */ mgl@1371: + if (optimize >= 2 && TARGET_BRANCH_PRED) mgl@1371: + align_loops = 2; mgl@1371: + mgl@1371: + mgl@1371: + /* Enable fast-float library if unsafe math optimizations mgl@1371: + are used. */ mgl@1371: + if (flag_unsafe_math_optimizations) mgl@1371: + target_flags |= MASK_FAST_FLOAT; mgl@1371: + mgl@1371: + /* Check if we should set avr32_imm_in_const_pool mgl@1371: + based on if caches are present or not. */ mgl@1371: + if ( avr32_imm_in_const_pool == -1 ) mgl@1371: + { mgl@1371: + if ( TARGET_CACHES ) mgl@1371: + avr32_imm_in_const_pool = 1; mgl@1371: + else mgl@1371: + avr32_imm_in_const_pool = 0; mgl@1371: + } mgl@1371: + mgl@1371: + if (TARGET_NO_PIC) mgl@1371: + flag_pic = 0; mgl@1371: + mgl@1371: + avr32_add_gc_roots (); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a function that outputs the assembler code for entry to a mgl@1371: +function. The prologue is responsible for setting up the stack frame, mgl@1371: +initializing the frame pointer register, saving registers that must be mgl@1371: +saved, and allocating size additional bytes of storage for the mgl@1371: +local variables. size is an integer. file is a stdio mgl@1371: +stream to which the assembler code should be output. mgl@1371: + mgl@1371: +The label for the beginning of the function need not be output by this mgl@1371: +macro. That has already been done when the macro is run. mgl@1371: + mgl@1371: +To determine which registers to save, the macro can refer to the array mgl@1371: +regs_ever_live: element r is nonzero if hard register mgl@1371: +r is used anywhere within the function. This implies the function mgl@1371: +prologue should save register r, provided it is not one of the mgl@1371: +call-used registers. (TARGET_ASM_FUNCTION_EPILOGUE must likewise use mgl@1371: +regs_ever_live.) mgl@1371: + mgl@1371: +On machines that have ``register windows'', the function entry code does mgl@1371: +not save on the stack the registers that are in the windows, even if mgl@1371: +they are supposed to be preserved by function calls; instead it takes mgl@1371: +appropriate steps to ``push'' the register stack, if any non-call-used mgl@1371: +registers are used in the function. mgl@1371: + mgl@1371: +On machines where functions may or may not have frame-pointers, the mgl@1371: +function entry code must vary accordingly; it must set up the frame mgl@1371: +pointer if one is wanted, and not otherwise. To determine whether a mgl@1371: +frame pointer is in wanted, the macro can refer to the variable mgl@1371: +frame_pointer_needed. The variable's value will be 1 at run mgl@1371: +time in a function that needs a frame pointer. (see Elimination). mgl@1371: + mgl@1371: +The function entry code is responsible for allocating any stack space mgl@1371: +required for the function. This stack space consists of the regions mgl@1371: +listed below. In most cases, these regions are allocated in the mgl@1371: +order listed, with the last listed region closest to the top of the mgl@1371: +stack (the lowest address if STACK_GROWS_DOWNWARD is defined, and mgl@1371: +the highest address if it is not defined). You can use a different order mgl@1371: +for a machine if doing so is more convenient or required for mgl@1371: +compatibility reasons. Except in cases where required by standard mgl@1371: +or by a debugger, there is no reason why the stack layout used by GCC mgl@1371: +need agree with that used by other compilers for a machine. mgl@1371: +*/ mgl@1371: + mgl@1371: +#undef TARGET_ASM_FUNCTION_PROLOGUE mgl@1371: +#define TARGET_ASM_FUNCTION_PROLOGUE avr32_target_asm_function_prologue mgl@1371: + mgl@1371: + mgl@1371: +#undef TARGET_DEFAULT_SHORT_ENUMS mgl@1371: +#define TARGET_DEFAULT_SHORT_ENUMS hook_bool_void_false mgl@1371: + mgl@1371: +#undef TARGET_PROMOTE_FUNCTION_ARGS mgl@1371: +#define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true mgl@1371: + mgl@1371: +#undef TARGET_PROMOTE_FUNCTION_RETURN mgl@1371: +#define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true mgl@1371: + mgl@1371: +#undef TARGET_PROMOTE_PROTOTYPES mgl@1371: +#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true mgl@1371: + mgl@1371: +#undef TARGET_MUST_PASS_IN_STACK mgl@1371: +#define TARGET_MUST_PASS_IN_STACK avr32_must_pass_in_stack mgl@1371: + mgl@1371: +#undef TARGET_PASS_BY_REFERENCE mgl@1371: +#define TARGET_PASS_BY_REFERENCE avr32_pass_by_reference mgl@1371: + mgl@1371: +#undef TARGET_STRICT_ARGUMENT_NAMING mgl@1371: +#define TARGET_STRICT_ARGUMENT_NAMING avr32_strict_argument_naming mgl@1371: + mgl@1371: +#undef TARGET_VECTOR_MODE_SUPPORTED_P mgl@1371: +#define TARGET_VECTOR_MODE_SUPPORTED_P avr32_vector_mode_supported mgl@1371: + mgl@1371: +#undef TARGET_RETURN_IN_MEMORY mgl@1371: +#define TARGET_RETURN_IN_MEMORY avr32_return_in_memory mgl@1371: + mgl@1371: +#undef TARGET_RETURN_IN_MSB mgl@1371: +#define TARGET_RETURN_IN_MSB avr32_return_in_msb mgl@1371: + mgl@1371: +#undef TARGET_ENCODE_SECTION_INFO mgl@1371: +#define TARGET_ENCODE_SECTION_INFO avr32_encode_section_info mgl@1371: + mgl@1371: +#undef TARGET_ARG_PARTIAL_BYTES mgl@1371: +#define TARGET_ARG_PARTIAL_BYTES avr32_arg_partial_bytes mgl@1371: + mgl@1371: +#undef TARGET_STRIP_NAME_ENCODING mgl@1371: +#define TARGET_STRIP_NAME_ENCODING avr32_strip_name_encoding mgl@1371: + mgl@1371: +#define streq(string1, string2) (strcmp (string1, string2) == 0) mgl@1371: + mgl@1371: +#undef TARGET_NARROW_VOLATILE_BITFIELD mgl@1371: +#define TARGET_NARROW_VOLATILE_BITFIELD hook_bool_void_false mgl@1371: + mgl@1371: +#undef TARGET_ATTRIBUTE_TABLE mgl@1371: +#define TARGET_ATTRIBUTE_TABLE avr32_attribute_table mgl@1371: + mgl@1371: +#undef TARGET_COMP_TYPE_ATTRIBUTES mgl@1371: +#define TARGET_COMP_TYPE_ATTRIBUTES avr32_comp_type_attributes mgl@1371: + mgl@1371: + mgl@1371: +#undef TARGET_RTX_COSTS mgl@1371: +#define TARGET_RTX_COSTS avr32_rtx_costs mgl@1371: + mgl@1371: +#undef TARGET_CANNOT_FORCE_CONST_MEM mgl@1371: +#define TARGET_CANNOT_FORCE_CONST_MEM avr32_cannot_force_const_mem mgl@1371: + mgl@1371: +#undef TARGET_ASM_INTEGER mgl@1371: +#define TARGET_ASM_INTEGER avr32_assemble_integer mgl@1371: + mgl@1371: +#undef TARGET_FUNCTION_VALUE mgl@1371: +#define TARGET_FUNCTION_VALUE avr32_function_value mgl@1371: + mgl@1371: +#undef TARGET_MIN_ANCHOR_OFFSET mgl@1371: +#define TARGET_MIN_ANCHOR_OFFSET (0) mgl@1371: + mgl@1371: +#undef TARGET_MAX_ANCHOR_OFFSET mgl@1371: +#define TARGET_MAX_ANCHOR_OFFSET ((1 << 15) - 1) mgl@1371: + mgl@1371: +#undef TARGET_SECONDARY_RELOAD mgl@1371: +#define TARGET_SECONDARY_RELOAD avr32_secondary_reload mgl@1371: + mgl@1371: +enum reg_class mgl@1371: +avr32_secondary_reload (bool in_p, rtx x, enum reg_class class ATTRIBUTE_UNUSED, mgl@1371: + enum machine_mode mode, secondary_reload_info *sri) mgl@1371: +{ mgl@1371: + mgl@1371: + if ( avr32_rmw_memory_operand (x, mode) ) mgl@1371: + { mgl@1371: + if (!in_p) mgl@1371: + sri->icode = CODE_FOR_reload_out_rmw_memory_operand; mgl@1371: + else mgl@1371: + sri->icode = CODE_FOR_reload_in_rmw_memory_operand; mgl@1371: + } mgl@1371: + return NO_REGS; mgl@1371: + mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + * Switches to the appropriate section for output of constant pool mgl@1371: + * entry x in mode. You can assume that x is some kind of constant in mgl@1371: + * RTL. The argument mode is redundant except in the case of a mgl@1371: + * const_int rtx. Select the section by calling readonly_data_ section mgl@1371: + * or one of the alternatives for other sections. align is the mgl@1371: + * constant alignment in bits. mgl@1371: + * mgl@1371: + * The default version of this function takes care of putting symbolic mgl@1371: + * constants in flag_ pic mode in data_section and everything else in mgl@1371: + * readonly_data_section. mgl@1371: + */ mgl@1371: +//#undef TARGET_ASM_SELECT_RTX_SECTION mgl@1371: +//#define TARGET_ASM_SELECT_RTX_SECTION avr32_select_rtx_section mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + * If non-null, this hook performs a target-specific pass over the mgl@1371: + * instruction stream. The compiler will run it at all optimization mgl@1371: + * levels, just before the point at which it normally does mgl@1371: + * delayed-branch scheduling. mgl@1371: + * mgl@1371: + * The exact purpose of the hook varies from target to target. Some mgl@1371: + * use it to do transformations that are necessary for correctness, mgl@1371: + * such as laying out in-function constant pools or avoiding hardware mgl@1371: + * hazards. Others use it as an opportunity to do some mgl@1371: + * machine-dependent optimizations. mgl@1371: + * mgl@1371: + * You need not implement the hook if it has nothing to do. The mgl@1371: + * default definition is null. mgl@1371: + */ mgl@1371: +#undef TARGET_MACHINE_DEPENDENT_REORG mgl@1371: +#define TARGET_MACHINE_DEPENDENT_REORG avr32_reorg mgl@1371: + mgl@1371: +/* Target hook for assembling integer objects. mgl@1371: + Need to handle integer vectors */ mgl@1371: +static bool mgl@1371: +avr32_assemble_integer (rtx x, unsigned int size, int aligned_p) mgl@1371: +{ mgl@1371: + if (avr32_vector_mode_supported (GET_MODE (x))) mgl@1371: + { mgl@1371: + int i, units; mgl@1371: + mgl@1371: + if (GET_CODE (x) != CONST_VECTOR) mgl@1371: + abort (); mgl@1371: + mgl@1371: + units = CONST_VECTOR_NUNITS (x); mgl@1371: + mgl@1371: + switch (GET_MODE (x)) mgl@1371: + { mgl@1371: + case V2HImode: mgl@1371: + size = 2; mgl@1371: + break; mgl@1371: + case V4QImode: mgl@1371: + size = 1; mgl@1371: + break; mgl@1371: + default: mgl@1371: + abort (); mgl@1371: + } mgl@1371: + mgl@1371: + for (i = 0; i < units; i++) mgl@1371: + { mgl@1371: + rtx elt; mgl@1371: + mgl@1371: + elt = CONST_VECTOR_ELT (x, i); mgl@1371: + assemble_integer (elt, size, i == 0 ? 32 : size * BITS_PER_UNIT, 1); mgl@1371: + } mgl@1371: + mgl@1371: + return true; mgl@1371: + } mgl@1371: + mgl@1371: + return default_assemble_integer (x, size, aligned_p); mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + * This target hook describes the relative costs of RTL expressions. mgl@1371: + * mgl@1371: + * The cost may depend on the precise form of the expression, which is mgl@1371: + * available for examination in x, and the rtx code of the expression mgl@1371: + * in which it is contained, found in outer_code. code is the mgl@1371: + * expression code--redundant, since it can be obtained with GET_CODE mgl@1371: + * (x). mgl@1371: + * mgl@1371: + * In implementing this hook, you can use the construct COSTS_N_INSNS mgl@1371: + * (n) to specify a cost equal to n fast instructions. mgl@1371: + * mgl@1371: + * On entry to the hook, *total contains a default estimate for the mgl@1371: + * cost of the expression. The hook should modify this value as mgl@1371: + * necessary. Traditionally, the default costs are COSTS_N_INSNS (5) mgl@1371: + * for multiplications, COSTS_N_INSNS (7) for division and modulus mgl@1371: + * operations, and COSTS_N_INSNS (1) for all other operations. mgl@1371: + * mgl@1371: + * When optimizing for code size, i.e. when optimize_size is non-zero, mgl@1371: + * this target hook should be used to estimate the relative size cost mgl@1371: + * of an expression, again relative to COSTS_N_INSNS. mgl@1371: + * mgl@1371: + * The hook returns true when all subexpressions of x have been mgl@1371: + * processed, and false when rtx_cost should recurse. mgl@1371: + */ mgl@1371: + mgl@1371: +/* Worker routine for avr32_rtx_costs. */ mgl@1371: +static inline int mgl@1371: +avr32_rtx_costs_1 (rtx x, enum rtx_code code ATTRIBUTE_UNUSED, mgl@1371: + enum rtx_code outer ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + enum machine_mode mode = GET_MODE (x); mgl@1371: + mgl@1371: + switch (GET_CODE (x)) mgl@1371: + { mgl@1371: + case MEM: mgl@1371: + /* Using pre decrement / post increment memory operations on the mgl@1371: + avr32_uc architecture means that two writebacks must be performed mgl@1371: + and hence two cycles are needed. */ mgl@1371: + if (!optimize_size mgl@1371: + && GET_MODE_SIZE (mode) <= 2 * UNITS_PER_WORD mgl@1371: + && TARGET_ARCH_UC mgl@1371: + && (GET_CODE (XEXP (x, 0)) == PRE_DEC mgl@1371: + || GET_CODE (XEXP (x, 0)) == POST_INC)) mgl@1371: + return COSTS_N_INSNS (5); mgl@1371: + mgl@1371: + /* Memory costs quite a lot for the first word, but subsequent words mgl@1371: + load at the equivalent of a single insn each. */ mgl@1371: + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) mgl@1371: + return COSTS_N_INSNS (3 + (GET_MODE_SIZE (mode) / UNITS_PER_WORD)); mgl@1371: + mgl@1371: + return COSTS_N_INSNS (4); mgl@1371: + case SYMBOL_REF: mgl@1371: + case CONST: mgl@1371: + /* These are valid for the pseudo insns: lda.w and call which operates mgl@1371: + on direct addresses. We assume that the cost of a lda.w is the same mgl@1371: + as the cost of a ld.w insn. */ mgl@1371: + return (outer == SET) ? COSTS_N_INSNS (4) : COSTS_N_INSNS (1); mgl@1371: + case DIV: mgl@1371: + case MOD: mgl@1371: + case UDIV: mgl@1371: + case UMOD: mgl@1371: + return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16); mgl@1371: + mgl@1371: + case ROTATE: mgl@1371: + case ROTATERT: mgl@1371: + if (mode == TImode) mgl@1371: + return COSTS_N_INSNS (100); mgl@1371: + mgl@1371: + if (mode == DImode) mgl@1371: + return COSTS_N_INSNS (10); mgl@1371: + return COSTS_N_INSNS (4); mgl@1371: + case ASHIFT: mgl@1371: + case LSHIFTRT: mgl@1371: + case ASHIFTRT: mgl@1371: + case NOT: mgl@1371: + if (mode == TImode) mgl@1371: + return COSTS_N_INSNS (10); mgl@1371: + mgl@1371: + if (mode == DImode) mgl@1371: + return COSTS_N_INSNS (4); mgl@1371: + return COSTS_N_INSNS (1); mgl@1371: + case PLUS: mgl@1371: + case MINUS: mgl@1371: + case NEG: mgl@1371: + case COMPARE: mgl@1371: + case ABS: mgl@1371: + if (GET_MODE_CLASS (mode) == MODE_FLOAT) mgl@1371: + return COSTS_N_INSNS (100); mgl@1371: + mgl@1371: + if (mode == TImode) mgl@1371: + return COSTS_N_INSNS (50); mgl@1371: + mgl@1371: + if (mode == DImode) mgl@1371: + return COSTS_N_INSNS (2); mgl@1371: + return COSTS_N_INSNS (1); mgl@1371: + mgl@1371: + case MULT: mgl@1371: + { mgl@1371: + if (GET_MODE_CLASS (mode) == MODE_FLOAT) mgl@1371: + return COSTS_N_INSNS (300); mgl@1371: + mgl@1371: + if (mode == TImode) mgl@1371: + return COSTS_N_INSNS (16); mgl@1371: + mgl@1371: + if (mode == DImode) mgl@1371: + return COSTS_N_INSNS (4); mgl@1371: + mgl@1371: + if (mode == HImode) mgl@1371: + return COSTS_N_INSNS (2); mgl@1371: + mgl@1371: + return COSTS_N_INSNS (3); mgl@1371: + } mgl@1371: + case IF_THEN_ELSE: mgl@1371: + if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) mgl@1371: + return COSTS_N_INSNS (4); mgl@1371: + return COSTS_N_INSNS (1); mgl@1371: + case SIGN_EXTEND: mgl@1371: + case ZERO_EXTEND: mgl@1371: + /* Sign/Zero extensions of registers cost quite much since these mgl@1371: + instrcutions only take one register operand which means that gcc mgl@1371: + often must insert some move instrcutions */ mgl@1371: + if (mode == QImode || mode == HImode) mgl@1371: + return (COSTS_N_INSNS (GET_CODE (XEXP (x, 0)) == MEM ? 0 : 1)); mgl@1371: + return COSTS_N_INSNS (4); mgl@1371: + case UNSPEC: mgl@1371: + /* divmod operations */ mgl@1371: + if (XINT (x, 1) == UNSPEC_UDIVMODSI4_INTERNAL mgl@1371: + || XINT (x, 1) == UNSPEC_DIVMODSI4_INTERNAL) mgl@1371: + { mgl@1371: + return optimize_size ? COSTS_N_INSNS (1) : COSTS_N_INSNS (16); mgl@1371: + } mgl@1371: + /* Fallthrough */ mgl@1371: + default: mgl@1371: + return COSTS_N_INSNS (1); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +static bool mgl@1371: +avr32_rtx_costs (rtx x, int code, int outer_code, int *total) mgl@1371: +{ mgl@1371: + *total = avr32_rtx_costs_1 (x, code, outer_code); mgl@1371: + return true; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +bool mgl@1371: +avr32_cannot_force_const_mem (rtx x ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + /* Do not want symbols in the constant pool when compiling pic or if using mgl@1371: + address pseudo instructions. */ mgl@1371: + return ((flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS) mgl@1371: + && avr32_find_symbol (x) != NULL_RTX); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Table of machine attributes. */ mgl@1371: +const struct attribute_spec avr32_attribute_table[] = { mgl@1371: + /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ mgl@1371: + /* Interrupt Service Routines have special prologue and epilogue mgl@1371: + requirements. */ mgl@1371: + {"isr", 0, 1, false, false, false, avr32_handle_isr_attribute}, mgl@1371: + {"interrupt", 0, 1, false, false, false, avr32_handle_isr_attribute}, mgl@1371: + {"acall", 0, 1, false, true, true, avr32_handle_acall_attribute}, mgl@1371: + {"naked", 0, 0, true, false, false, avr32_handle_fndecl_attribute}, mgl@1371: + {"rmw_addressable", 0, 0, true, false, false, NULL}, mgl@1371: + {NULL, 0, 0, false, false, false, NULL} mgl@1371: +}; mgl@1371: + mgl@1371: + mgl@1371: +typedef struct mgl@1371: +{ mgl@1371: + const char *const arg; mgl@1371: + const unsigned long return_value; mgl@1371: +} mgl@1371: +isr_attribute_arg; mgl@1371: + mgl@1371: +static const isr_attribute_arg isr_attribute_args[] = { mgl@1371: + {"FULL", AVR32_FT_ISR_FULL}, mgl@1371: + {"full", AVR32_FT_ISR_FULL}, mgl@1371: + {"HALF", AVR32_FT_ISR_HALF}, mgl@1371: + {"half", AVR32_FT_ISR_HALF}, mgl@1371: + {"NONE", AVR32_FT_ISR_NONE}, mgl@1371: + {"none", AVR32_FT_ISR_NONE}, mgl@1371: + {"UNDEF", AVR32_FT_ISR_NONE}, mgl@1371: + {"undef", AVR32_FT_ISR_NONE}, mgl@1371: + {"SWI", AVR32_FT_ISR_NONE}, mgl@1371: + {"swi", AVR32_FT_ISR_NONE}, mgl@1371: + {NULL, AVR32_FT_ISR_NONE} mgl@1371: +}; mgl@1371: + mgl@1371: +/* Returns the (interrupt) function type of the current mgl@1371: + function, or AVR32_FT_UNKNOWN if the type cannot be determined. */ mgl@1371: + mgl@1371: +static unsigned long mgl@1371: +avr32_isr_value (tree argument) mgl@1371: +{ mgl@1371: + const isr_attribute_arg *ptr; mgl@1371: + const char *arg; mgl@1371: + mgl@1371: + /* No argument - default to ISR_NONE. */ mgl@1371: + if (argument == NULL_TREE) mgl@1371: + return AVR32_FT_ISR_NONE; mgl@1371: + mgl@1371: + /* Get the value of the argument. */ mgl@1371: + if (TREE_VALUE (argument) == NULL_TREE mgl@1371: + || TREE_CODE (TREE_VALUE (argument)) != STRING_CST) mgl@1371: + return AVR32_FT_UNKNOWN; mgl@1371: + mgl@1371: + arg = TREE_STRING_POINTER (TREE_VALUE (argument)); mgl@1371: + mgl@1371: + /* Check it against the list of known arguments. */ mgl@1371: + for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) mgl@1371: + if (streq (arg, ptr->arg)) mgl@1371: + return ptr->return_value; mgl@1371: + mgl@1371: + /* An unrecognized interrupt type. */ mgl@1371: + return AVR32_FT_UNKNOWN; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +These hooks specify assembly directives for creating certain kinds mgl@1371: +of integer object. The TARGET_ASM_BYTE_OP directive creates a mgl@1371: +byte-sized object, the TARGET_ASM_ALIGNED_HI_OP one creates an mgl@1371: +aligned two-byte object, and so on. Any of the hooks may be mgl@1371: +NULL, indicating that no suitable directive is available. mgl@1371: + mgl@1371: +The compiler will print these strings at the start of a new line, mgl@1371: +followed immediately by the object's initial value. In most cases, mgl@1371: +the string should contain a tab, a pseudo-op, and then another tab. mgl@1371: +*/ mgl@1371: +#undef TARGET_ASM_BYTE_OP mgl@1371: +#define TARGET_ASM_BYTE_OP "\t.byte\t" mgl@1371: +#undef TARGET_ASM_ALIGNED_HI_OP mgl@1371: +#define TARGET_ASM_ALIGNED_HI_OP "\t.align 1\n\t.short\t" mgl@1371: +#undef TARGET_ASM_ALIGNED_SI_OP mgl@1371: +#define TARGET_ASM_ALIGNED_SI_OP "\t.align 2\n\t.int\t" mgl@1371: +#undef TARGET_ASM_ALIGNED_DI_OP mgl@1371: +#define TARGET_ASM_ALIGNED_DI_OP NULL mgl@1371: +#undef TARGET_ASM_ALIGNED_TI_OP mgl@1371: +#define TARGET_ASM_ALIGNED_TI_OP NULL mgl@1371: +#undef TARGET_ASM_UNALIGNED_HI_OP mgl@1371: +#define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t" mgl@1371: +#undef TARGET_ASM_UNALIGNED_SI_OP mgl@1371: +#define TARGET_ASM_UNALIGNED_SI_OP "\t.int\t" mgl@1371: +#undef TARGET_ASM_UNALIGNED_DI_OP mgl@1371: +#define TARGET_ASM_UNALIGNED_DI_OP NULL mgl@1371: +#undef TARGET_ASM_UNALIGNED_TI_OP mgl@1371: +#define TARGET_ASM_UNALIGNED_TI_OP NULL mgl@1371: + mgl@1371: +#undef TARGET_ASM_OUTPUT_MI_THUNK mgl@1371: +#define TARGET_ASM_OUTPUT_MI_THUNK avr32_output_mi_thunk mgl@1371: + mgl@1371: +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK mgl@1371: +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true mgl@1371: + mgl@1371: +static void mgl@1371: +avr32_output_mi_thunk (FILE * file, mgl@1371: + tree thunk ATTRIBUTE_UNUSED, mgl@1371: + HOST_WIDE_INT delta, mgl@1371: + HOST_WIDE_INT vcall_offset, tree function) mgl@1371: + { mgl@1371: + int mi_delta = delta; mgl@1371: + int this_regno = mgl@1371: + (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) ? mgl@1371: + INTERNAL_REGNUM (11) : INTERNAL_REGNUM (12)); mgl@1371: + mgl@1371: + mgl@1371: + if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21") mgl@1371: + || vcall_offset) mgl@1371: + { mgl@1371: + fputs ("\tpushm\tlr\n", file); mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + if (mi_delta != 0) mgl@1371: + { mgl@1371: + if (avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21")) mgl@1371: + { mgl@1371: + fprintf (file, "\tsub\t%s, %d\n", reg_names[this_regno], -mi_delta); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Immediate is larger than k21 we must make us a temp register by mgl@1371: + pushing a register to the stack. */ mgl@1371: + fprintf (file, "\tmov\tlr, lo(%d)\n", mi_delta); mgl@1371: + fprintf (file, "\torh\tlr, hi(%d)\n", mi_delta); mgl@1371: + fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + if (vcall_offset != 0) mgl@1371: + { mgl@1371: + fprintf (file, "\tld.w\tlr, %s[0]\n", reg_names[this_regno]); mgl@1371: + fprintf (file, "\tld.w\tlr, lr[%i]\n", (int) vcall_offset); mgl@1371: + fprintf (file, "\tadd\t%s, lr\n", reg_names[this_regno]); mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + if (!avr32_const_ok_for_constraint_p (mi_delta, 'I', "Is21") mgl@1371: + || vcall_offset) mgl@1371: + { mgl@1371: + fputs ("\tpopm\tlr\n", file); mgl@1371: + } mgl@1371: + mgl@1371: + /* Jump to the function. We assume that we can use an rjmp since the mgl@1371: + function to jump to is local and probably not too far away from mgl@1371: + the thunk. If this assumption proves to be wrong we could implement mgl@1371: + this jump by calculating the offset between the jump source and destination mgl@1371: + and put this in the constant pool and then perform an add to pc. mgl@1371: + This would also be legitimate PIC code. But for now we hope that an rjmp mgl@1371: + will be sufficient... mgl@1371: + */ mgl@1371: + fputs ("\trjmp\t", file); mgl@1371: + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); mgl@1371: + fputc ('\n', file); mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: +/* Implements target hook vector_mode_supported. */ mgl@1371: +bool mgl@1371: +avr32_vector_mode_supported (enum machine_mode mode) mgl@1371: +{ mgl@1371: + if ((mode == V2HImode) || (mode == V4QImode)) mgl@1371: + return true; mgl@1371: + mgl@1371: + return false; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +#undef TARGET_INIT_LIBFUNCS mgl@1371: +#define TARGET_INIT_LIBFUNCS avr32_init_libfuncs mgl@1371: + mgl@1371: +#undef TARGET_INIT_BUILTINS mgl@1371: +#define TARGET_INIT_BUILTINS avr32_init_builtins mgl@1371: + mgl@1371: +#undef TARGET_EXPAND_BUILTIN mgl@1371: +#define TARGET_EXPAND_BUILTIN avr32_expand_builtin mgl@1371: + mgl@1371: +tree int_ftype_int, int_ftype_void, short_ftype_short, void_ftype_int_int, mgl@1371: + void_ftype_ptr_int; mgl@1371: +tree void_ftype_int, void_ftype_void, int_ftype_ptr_int; mgl@1371: +tree short_ftype_short, int_ftype_int_short, int_ftype_short_short, mgl@1371: + short_ftype_short_short; mgl@1371: +tree int_ftype_int_int, longlong_ftype_int_short, longlong_ftype_short_short; mgl@1371: +tree void_ftype_int_int_int_int_int, void_ftype_int_int_int; mgl@1371: +tree longlong_ftype_int_int, void_ftype_int_int_longlong; mgl@1371: +tree int_ftype_int_int_int, longlong_ftype_longlong_int_short; mgl@1371: +tree longlong_ftype_longlong_short_short, int_ftype_int_short_short; mgl@1371: + mgl@1371: +#define def_builtin(NAME, TYPE, CODE) \ mgl@1371: + lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \ mgl@1371: + BUILT_IN_MD, NULL, NULL_TREE) mgl@1371: + mgl@1371: +#define def_mbuiltin(MASK, NAME, TYPE, CODE) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if ((MASK)) \ mgl@1371: + lang_hooks.builtin_function ((NAME), (TYPE), (CODE), \ mgl@1371: + BUILT_IN_MD, NULL, NULL_TREE); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: +struct builtin_description mgl@1371: +{ mgl@1371: + const unsigned int mask; mgl@1371: + const enum insn_code icode; mgl@1371: + const char *const name; mgl@1371: + const int code; mgl@1371: + const enum rtx_code comparison; mgl@1371: + const unsigned int flag; mgl@1371: + const tree *ftype; mgl@1371: +}; mgl@1371: + mgl@1371: +static const struct builtin_description bdesc_2arg[] = { mgl@1371: +#define DSP_BUILTIN(code, builtin, ftype) \ mgl@1371: + { 1, CODE_FOR_##code, "__builtin_" #code , \ mgl@1371: + AVR32_BUILTIN_##builtin, 0, 0, ftype } mgl@1371: + mgl@1371: + DSP_BUILTIN (mulsathh_h, MULSATHH_H, &short_ftype_short_short), mgl@1371: + DSP_BUILTIN (mulsathh_w, MULSATHH_W, &int_ftype_short_short), mgl@1371: + DSP_BUILTIN (mulsatrndhh_h, MULSATRNDHH_H, &short_ftype_short_short), mgl@1371: + DSP_BUILTIN (mulsatrndwh_w, MULSATRNDWH_W, &int_ftype_int_short), mgl@1371: + DSP_BUILTIN (mulsatwh_w, MULSATWH_W, &int_ftype_int_short), mgl@1371: + DSP_BUILTIN (satadd_h, SATADD_H, &short_ftype_short_short), mgl@1371: + DSP_BUILTIN (satsub_h, SATSUB_H, &short_ftype_short_short), mgl@1371: + DSP_BUILTIN (satadd_w, SATADD_W, &int_ftype_int_int), mgl@1371: + DSP_BUILTIN (satsub_w, SATSUB_W, &int_ftype_int_int), mgl@1371: + DSP_BUILTIN (mulwh_d, MULWH_D, &longlong_ftype_int_short), mgl@1371: + DSP_BUILTIN (mulnwh_d, MULNWH_D, &longlong_ftype_int_short) mgl@1371: +}; mgl@1371: + mgl@1371: + mgl@1371: +void mgl@1371: +avr32_init_builtins (void) mgl@1371: +{ mgl@1371: + unsigned int i; mgl@1371: + const struct builtin_description *d; mgl@1371: + tree endlink = void_list_node; mgl@1371: + tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink); mgl@1371: + tree longlong_endlink = mgl@1371: + tree_cons (NULL_TREE, long_long_integer_type_node, endlink); mgl@1371: + tree short_endlink = mgl@1371: + tree_cons (NULL_TREE, short_integer_type_node, endlink); mgl@1371: + tree void_endlink = tree_cons (NULL_TREE, void_type_node, endlink); mgl@1371: + mgl@1371: + /* int func (int) */ mgl@1371: + int_ftype_int = build_function_type (integer_type_node, int_endlink); mgl@1371: + mgl@1371: + /* short func (short) */ mgl@1371: + short_ftype_short mgl@1371: + = build_function_type (short_integer_type_node, short_endlink); mgl@1371: + mgl@1371: + /* short func (short, short) */ mgl@1371: + short_ftype_short_short mgl@1371: + = build_function_type (short_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, short_integer_type_node, mgl@1371: + short_endlink)); mgl@1371: + mgl@1371: + /* long long func (long long, short, short) */ mgl@1371: + longlong_ftype_longlong_short_short mgl@1371: + = build_function_type (long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, mgl@1371: + short_integer_type_node, mgl@1371: + short_endlink))); mgl@1371: + mgl@1371: + /* long long func (short, short) */ mgl@1371: + longlong_ftype_short_short mgl@1371: + = build_function_type (long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, short_integer_type_node, mgl@1371: + short_endlink)); mgl@1371: + mgl@1371: + /* int func (int, int) */ mgl@1371: + int_ftype_int_int mgl@1371: + = build_function_type (integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + int_endlink)); mgl@1371: + mgl@1371: + /* long long func (int, int) */ mgl@1371: + longlong_ftype_int_int mgl@1371: + = build_function_type (long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + int_endlink)); mgl@1371: + mgl@1371: + /* long long int func (long long, int, short) */ mgl@1371: + longlong_ftype_longlong_int_short mgl@1371: + = build_function_type (long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + short_endlink))); mgl@1371: + mgl@1371: + /* long long int func (int, short) */ mgl@1371: + longlong_ftype_int_short mgl@1371: + = build_function_type (long_long_integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + short_endlink)); mgl@1371: + mgl@1371: + /* int func (int, short, short) */ mgl@1371: + int_ftype_int_short_short mgl@1371: + = build_function_type (integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + tree_cons (NULL_TREE, mgl@1371: + short_integer_type_node, mgl@1371: + short_endlink))); mgl@1371: + mgl@1371: + /* int func (short, short) */ mgl@1371: + int_ftype_short_short mgl@1371: + = build_function_type (integer_type_node, mgl@1371: + tree_cons (NULL_TREE, short_integer_type_node, mgl@1371: + short_endlink)); mgl@1371: + mgl@1371: + /* int func (int, short) */ mgl@1371: + int_ftype_int_short mgl@1371: + = build_function_type (integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + short_endlink)); mgl@1371: + mgl@1371: + /* void func (int, int) */ mgl@1371: + void_ftype_int_int mgl@1371: + = build_function_type (void_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + int_endlink)); mgl@1371: + mgl@1371: + /* void func (int, int, int) */ mgl@1371: + void_ftype_int_int_int mgl@1371: + = build_function_type (void_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + int_endlink))); mgl@1371: + mgl@1371: + /* void func (int, int, long long) */ mgl@1371: + void_ftype_int_int_longlong mgl@1371: + = build_function_type (void_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + longlong_endlink))); mgl@1371: + mgl@1371: + /* void func (int, int, int, int, int) */ mgl@1371: + void_ftype_int_int_int_int_int mgl@1371: + = build_function_type (void_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + tree_cons (NULL_TREE, mgl@1371: + integer_type_node, mgl@1371: + tree_cons mgl@1371: + (NULL_TREE, mgl@1371: + integer_type_node, mgl@1371: + int_endlink))))); mgl@1371: + mgl@1371: + /* void func (void *, int) */ mgl@1371: + void_ftype_ptr_int mgl@1371: + = build_function_type (void_type_node, mgl@1371: + tree_cons (NULL_TREE, ptr_type_node, int_endlink)); mgl@1371: + mgl@1371: + /* void func (int) */ mgl@1371: + void_ftype_int = build_function_type (void_type_node, int_endlink); mgl@1371: + mgl@1371: + /* void func (void) */ mgl@1371: + void_ftype_void = build_function_type (void_type_node, void_endlink); mgl@1371: + mgl@1371: + /* int func (void) */ mgl@1371: + int_ftype_void = build_function_type (integer_type_node, void_endlink); mgl@1371: + mgl@1371: + /* int func (void *, int) */ mgl@1371: + int_ftype_ptr_int mgl@1371: + = build_function_type (integer_type_node, mgl@1371: + tree_cons (NULL_TREE, ptr_type_node, int_endlink)); mgl@1371: + mgl@1371: + /* int func (int, int, int) */ mgl@1371: + int_ftype_int_int_int mgl@1371: + = build_function_type (integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + tree_cons (NULL_TREE, integer_type_node, mgl@1371: + int_endlink))); mgl@1371: + mgl@1371: + /* Initialize avr32 builtins. */ mgl@1371: + def_builtin ("__builtin_mfsr", int_ftype_int, AVR32_BUILTIN_MFSR); mgl@1371: + def_builtin ("__builtin_mtsr", void_ftype_int_int, AVR32_BUILTIN_MTSR); mgl@1371: + def_builtin ("__builtin_mfdr", int_ftype_int, AVR32_BUILTIN_MFDR); mgl@1371: + def_builtin ("__builtin_mtdr", void_ftype_int_int, AVR32_BUILTIN_MTDR); mgl@1371: + def_builtin ("__builtin_cache", void_ftype_ptr_int, AVR32_BUILTIN_CACHE); mgl@1371: + def_builtin ("__builtin_sync", void_ftype_int, AVR32_BUILTIN_SYNC); mgl@1371: + def_builtin ("__builtin_ssrf", void_ftype_int, AVR32_BUILTIN_SSRF); mgl@1371: + def_builtin ("__builtin_csrf", void_ftype_int, AVR32_BUILTIN_CSRF); mgl@1371: + def_builtin ("__builtin_tlbr", void_ftype_void, AVR32_BUILTIN_TLBR); mgl@1371: + def_builtin ("__builtin_tlbs", void_ftype_void, AVR32_BUILTIN_TLBS); mgl@1371: + def_builtin ("__builtin_tlbw", void_ftype_void, AVR32_BUILTIN_TLBW); mgl@1371: + def_builtin ("__builtin_breakpoint", void_ftype_void, mgl@1371: + AVR32_BUILTIN_BREAKPOINT); mgl@1371: + def_builtin ("__builtin_xchg", int_ftype_ptr_int, AVR32_BUILTIN_XCHG); mgl@1371: + def_builtin ("__builtin_ldxi", int_ftype_ptr_int, AVR32_BUILTIN_LDXI); mgl@1371: + def_builtin ("__builtin_bswap_16", short_ftype_short, mgl@1371: + AVR32_BUILTIN_BSWAP16); mgl@1371: + def_builtin ("__builtin_bswap_32", int_ftype_int, AVR32_BUILTIN_BSWAP32); mgl@1371: + def_builtin ("__builtin_cop", void_ftype_int_int_int_int_int, mgl@1371: + AVR32_BUILTIN_COP); mgl@1371: + def_builtin ("__builtin_mvcr_w", int_ftype_int_int, AVR32_BUILTIN_MVCR_W); mgl@1371: + def_builtin ("__builtin_mvrc_w", void_ftype_int_int_int, mgl@1371: + AVR32_BUILTIN_MVRC_W); mgl@1371: + def_builtin ("__builtin_mvcr_d", longlong_ftype_int_int, mgl@1371: + AVR32_BUILTIN_MVCR_D); mgl@1371: + def_builtin ("__builtin_mvrc_d", void_ftype_int_int_longlong, mgl@1371: + AVR32_BUILTIN_MVRC_D); mgl@1371: + def_builtin ("__builtin_sats", int_ftype_int_int_int, AVR32_BUILTIN_SATS); mgl@1371: + def_builtin ("__builtin_satu", int_ftype_int_int_int, AVR32_BUILTIN_SATU); mgl@1371: + def_builtin ("__builtin_satrnds", int_ftype_int_int_int, mgl@1371: + AVR32_BUILTIN_SATRNDS); mgl@1371: + def_builtin ("__builtin_satrndu", int_ftype_int_int_int, mgl@1371: + AVR32_BUILTIN_SATRNDU); mgl@1371: + def_builtin ("__builtin_musfr", void_ftype_int, AVR32_BUILTIN_MUSFR); mgl@1371: + def_builtin ("__builtin_mustr", int_ftype_void, AVR32_BUILTIN_MUSTR); mgl@1371: + def_builtin ("__builtin_macsathh_w", int_ftype_int_short_short, mgl@1371: + AVR32_BUILTIN_MACSATHH_W); mgl@1371: + def_builtin ("__builtin_macwh_d", longlong_ftype_longlong_int_short, mgl@1371: + AVR32_BUILTIN_MACWH_D); mgl@1371: + def_builtin ("__builtin_machh_d", longlong_ftype_longlong_short_short, mgl@1371: + AVR32_BUILTIN_MACHH_D); mgl@1371: + def_builtin ("__builtin_mems", void_ftype_ptr_int, AVR32_BUILTIN_MEMS); mgl@1371: + def_builtin ("__builtin_memt", void_ftype_ptr_int, AVR32_BUILTIN_MEMT); mgl@1371: + def_builtin ("__builtin_memc", void_ftype_ptr_int, AVR32_BUILTIN_MEMC); mgl@1371: + mgl@1371: + /* Add all builtins that are more or less simple operations on two mgl@1371: + operands. */ mgl@1371: + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) mgl@1371: + { mgl@1371: + /* Use one of the operands; the target can have a different mode for mgl@1371: + mask-generating compares. */ mgl@1371: + mgl@1371: + if (d->name == 0) mgl@1371: + continue; mgl@1371: + mgl@1371: + def_mbuiltin (d->mask, d->name, *(d->ftype), d->code); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Subroutine of avr32_expand_builtin to take care of binop insns. */ mgl@1371: + mgl@1371: +static rtx mgl@1371: +avr32_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) mgl@1371: +{ mgl@1371: + rtx pat; mgl@1371: + tree arg0 = TREE_VALUE (arglist); mgl@1371: + tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + enum machine_mode tmode = insn_data[icode].operand[0].mode; mgl@1371: + enum machine_mode mode0 = insn_data[icode].operand[1].mode; mgl@1371: + enum machine_mode mode1 = insn_data[icode].operand[2].mode; mgl@1371: + mgl@1371: + if (!target mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + mgl@1371: + /* In case the insn wants input operands in modes different from the mgl@1371: + result, abort. */ mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + /* If op0 is already a reg we must cast it to the correct mode. */ mgl@1371: + if (REG_P (op0)) mgl@1371: + op0 = convert_to_mode (mode0, op0, 1); mgl@1371: + else mgl@1371: + op0 = copy_to_mode_reg (mode0, op0); mgl@1371: + } mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) mgl@1371: + { mgl@1371: + /* If op1 is already a reg we must cast it to the correct mode. */ mgl@1371: + if (REG_P (op1)) mgl@1371: + op1 = convert_to_mode (mode1, op1, 1); mgl@1371: + else mgl@1371: + op1 = copy_to_mode_reg (mode1, op1); mgl@1371: + } mgl@1371: + pat = GEN_FCN (icode) (target, op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: +} mgl@1371: + mgl@1371: +/* Expand an expression EXP that calls a built-in function, mgl@1371: + with result going to TARGET if that's convenient mgl@1371: + (and in mode MODE if that's convenient). mgl@1371: + SUBTARGET may be used as the target for computing one of EXP's operands. mgl@1371: + IGNORE is nonzero if the value is to be ignored. */ mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_expand_builtin (tree exp, mgl@1371: + rtx target, mgl@1371: + rtx subtarget ATTRIBUTE_UNUSED, mgl@1371: + enum machine_mode mode ATTRIBUTE_UNUSED, mgl@1371: + int ignore ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + const struct builtin_description *d; mgl@1371: + unsigned int i; mgl@1371: + enum insn_code icode = 0; mgl@1371: + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); mgl@1371: + tree arglist = TREE_OPERAND (exp, 1); mgl@1371: + tree arg0, arg1, arg2; mgl@1371: + rtx op0, op1, op2, pat; mgl@1371: + enum machine_mode tmode, mode0, mode1; mgl@1371: + enum machine_mode arg0_mode; mgl@1371: + int fcode = DECL_FUNCTION_CODE (fndecl); mgl@1371: + mgl@1371: + switch (fcode) mgl@1371: + { mgl@1371: + default: mgl@1371: + break; mgl@1371: + mgl@1371: + case AVR32_BUILTIN_SATS: mgl@1371: + case AVR32_BUILTIN_SATU: mgl@1371: + case AVR32_BUILTIN_SATRNDS: mgl@1371: + case AVR32_BUILTIN_SATRNDU: mgl@1371: + { mgl@1371: + const char *fname; mgl@1371: + switch (fcode) mgl@1371: + { mgl@1371: + default: mgl@1371: + case AVR32_BUILTIN_SATS: mgl@1371: + icode = CODE_FOR_sats; mgl@1371: + fname = "sats"; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_SATU: mgl@1371: + icode = CODE_FOR_satu; mgl@1371: + fname = "satu"; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_SATRNDS: mgl@1371: + icode = CODE_FOR_satrnds; mgl@1371: + fname = "satrnds"; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_SATRNDU: mgl@1371: + icode = CODE_FOR_satrndu; mgl@1371: + fname = "satrndu"; mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); mgl@1371: + mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, GET_MODE (op0))) mgl@1371: + { mgl@1371: + op0 = copy_to_mode_reg (insn_data[icode].operand[0].mode, op0); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) mgl@1371: + { mgl@1371: + error ("Parameter 2 to __builtin_%s should be a constant number.", mgl@1371: + fname); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op2, SImode)) mgl@1371: + { mgl@1371: + error ("Parameter 3 to __builtin_%s should be a constant number.", mgl@1371: + fname); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + emit_move_insn (target, op0); mgl@1371: + pat = GEN_FCN (icode) (target, op1, op2); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + mgl@1371: + return target; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_MUSTR: mgl@1371: + icode = CODE_FOR_mustr; mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + pat = GEN_FCN (icode) (target); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: + mgl@1371: + case AVR32_BUILTIN_MFSR: mgl@1371: + icode = CODE_FOR_mfsr; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + error ("Parameter 1 to __builtin_mfsr must be a constant number"); mgl@1371: + } mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + pat = GEN_FCN (icode) (target, op0); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: + case AVR32_BUILTIN_MTSR: mgl@1371: + icode = CODE_FOR_mtsr; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + mode0 = insn_data[icode].operand[0].mode; mgl@1371: + mode1 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + error ("Parameter 1 to __builtin_mtsr must be a constant number"); mgl@1371: + return gen_reg_rtx (mode0); mgl@1371: + } mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) mgl@1371: + op1 = copy_to_mode_reg (mode1, op1); mgl@1371: + pat = GEN_FCN (icode) (op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_MFDR: mgl@1371: + icode = CODE_FOR_mfdr; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + error ("Parameter 1 to __builtin_mfdr must be a constant number"); mgl@1371: + } mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + pat = GEN_FCN (icode) (target, op0); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: + case AVR32_BUILTIN_MTDR: mgl@1371: + icode = CODE_FOR_mtdr; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + mode0 = insn_data[icode].operand[0].mode; mgl@1371: + mode1 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + error ("Parameter 1 to __builtin_mtdr must be a constant number"); mgl@1371: + return gen_reg_rtx (mode0); mgl@1371: + } mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) mgl@1371: + op1 = copy_to_mode_reg (mode1, op1); mgl@1371: + pat = GEN_FCN (icode) (op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_CACHE: mgl@1371: + icode = CODE_FOR_cache; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + mode0 = insn_data[icode].operand[0].mode; mgl@1371: + mode1 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, mode1)) mgl@1371: + { mgl@1371: + error ("Parameter 2 to __builtin_cache must be a constant number"); mgl@1371: + return gen_reg_rtx (mode1); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) mgl@1371: + op0 = copy_to_mode_reg (mode0, op0); mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_SYNC: mgl@1371: + case AVR32_BUILTIN_MUSFR: mgl@1371: + case AVR32_BUILTIN_SSRF: mgl@1371: + case AVR32_BUILTIN_CSRF: mgl@1371: + { mgl@1371: + const char *fname; mgl@1371: + switch (fcode) mgl@1371: + { mgl@1371: + default: mgl@1371: + case AVR32_BUILTIN_SYNC: mgl@1371: + icode = CODE_FOR_sync; mgl@1371: + fname = "sync"; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_MUSFR: mgl@1371: + icode = CODE_FOR_musfr; mgl@1371: + fname = "musfr"; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_SSRF: mgl@1371: + icode = CODE_FOR_ssrf; mgl@1371: + fname = "ssrf"; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_CSRF: mgl@1371: + icode = CODE_FOR_csrf; mgl@1371: + fname = "csrf"; mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + mode0 = insn_data[icode].operand[0].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + if (icode == CODE_FOR_musfr) mgl@1371: + op0 = copy_to_mode_reg (mode0, op0); mgl@1371: + else mgl@1371: + { mgl@1371: + error ("Parameter to __builtin_%s is illegal.", fname); mgl@1371: + return gen_reg_rtx (mode0); mgl@1371: + } mgl@1371: + } mgl@1371: + pat = GEN_FCN (icode) (op0); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_TLBR: mgl@1371: + icode = CODE_FOR_tlbr; mgl@1371: + pat = GEN_FCN (icode) (NULL_RTX); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_TLBS: mgl@1371: + icode = CODE_FOR_tlbs; mgl@1371: + pat = GEN_FCN (icode) (NULL_RTX); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_TLBW: mgl@1371: + icode = CODE_FOR_tlbw; mgl@1371: + pat = GEN_FCN (icode) (NULL_RTX); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_BREAKPOINT: mgl@1371: + icode = CODE_FOR_breakpoint; mgl@1371: + pat = GEN_FCN (icode) (NULL_RTX); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return NULL_RTX; mgl@1371: + case AVR32_BUILTIN_XCHG: mgl@1371: + icode = CODE_FOR_sync_lock_test_and_setsi; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mode1 = insn_data[icode].operand[2].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) mgl@1371: + { mgl@1371: + op1 = copy_to_mode_reg (mode1, op1); mgl@1371: + } mgl@1371: + mgl@1371: + op0 = force_reg (GET_MODE (op0), op0); mgl@1371: + op0 = gen_rtx_MEM (GET_MODE (op0), op0); mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 1 to __builtin_xchg must be a pointer to an integer."); mgl@1371: + } mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + pat = GEN_FCN (icode) (target, op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: + case AVR32_BUILTIN_LDXI: mgl@1371: + icode = CODE_FOR_ldxi; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mode1 = insn_data[icode].operand[2].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + op0 = copy_to_mode_reg (mode0, op0); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) mgl@1371: + { mgl@1371: + op1 = copy_to_mode_reg (mode1, op1); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[3].predicate) (op2, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 3 to __builtin_ldxi must be a valid extract shift operand: (0|8|16|24)"); mgl@1371: + return gen_reg_rtx (mode0); mgl@1371: + } mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + pat = GEN_FCN (icode) (target, op0, op1, op2); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: + case AVR32_BUILTIN_BSWAP16: mgl@1371: + { mgl@1371: + icode = CODE_FOR_bswap_16; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg0_mode = TYPE_MODE (TREE_TYPE (arg0)); mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + if (arg0_mode != mode0) mgl@1371: + arg0 = build1 (NOP_EXPR, mgl@1371: + (*lang_hooks.types.type_for_mode) (mode0, 0), arg0); mgl@1371: + mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, HImode, 0); mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + if ( CONST_INT_P (op0) ) mgl@1371: + { mgl@1371: + HOST_WIDE_INT val = ( ((INTVAL (op0)&0x00ff) << 8) | mgl@1371: + ((INTVAL (op0)&0xff00) >> 8) ); mgl@1371: + /* Sign extend 16-bit value to host wide int */ mgl@1371: + val <<= (HOST_BITS_PER_WIDE_INT - 16); mgl@1371: + val >>= (HOST_BITS_PER_WIDE_INT - 16); mgl@1371: + op0 = GEN_INT(val); mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + emit_move_insn(target, op0); mgl@1371: + return target; mgl@1371: + } mgl@1371: + else mgl@1371: + op0 = copy_to_mode_reg (mode0, op0); mgl@1371: + } mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + { mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (target, op0); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + mgl@1371: + return target; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_BSWAP32: mgl@1371: + { mgl@1371: + icode = CODE_FOR_bswap_32; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + if ( CONST_INT_P (op0) ) mgl@1371: + { mgl@1371: + HOST_WIDE_INT val = ( ((INTVAL (op0)&0x000000ff) << 24) | mgl@1371: + ((INTVAL (op0)&0x0000ff00) << 8) | mgl@1371: + ((INTVAL (op0)&0x00ff0000) >> 8) | mgl@1371: + ((INTVAL (op0)&0xff000000) >> 24) ); mgl@1371: + /* Sign extend 32-bit value to host wide int */ mgl@1371: + val <<= (HOST_BITS_PER_WIDE_INT - 32); mgl@1371: + val >>= (HOST_BITS_PER_WIDE_INT - 32); mgl@1371: + op0 = GEN_INT(val); mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + emit_move_insn(target, op0); mgl@1371: + return target; mgl@1371: + } mgl@1371: + else mgl@1371: + op0 = copy_to_mode_reg (mode0, op0); mgl@1371: + } mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (target, op0); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + mgl@1371: + return target; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_MVCR_W: mgl@1371: + case AVR32_BUILTIN_MVCR_D: mgl@1371: + { mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + mgl@1371: + if (fcode == AVR32_BUILTIN_MVCR_W) mgl@1371: + icode = CODE_FOR_mvcrsi; mgl@1371: + else mgl@1371: + icode = CODE_FOR_mvcrdi; mgl@1371: + mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mgl@1371: + if (target == 0 mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 1 to __builtin_cop is not a valid coprocessor number."); mgl@1371: + error ("Number should be between 0 and 7."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op1, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 2 to __builtin_cop is not a valid coprocessor register number."); mgl@1371: + error ("Number should be between 0 and 15."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (target, op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + mgl@1371: + return target; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_MACSATHH_W: mgl@1371: + case AVR32_BUILTIN_MACWH_D: mgl@1371: + case AVR32_BUILTIN_MACHH_D: mgl@1371: + { mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); mgl@1371: + mgl@1371: + icode = ((fcode == AVR32_BUILTIN_MACSATHH_W) ? CODE_FOR_macsathh_w : mgl@1371: + (fcode == AVR32_BUILTIN_MACWH_D) ? CODE_FOR_macwh_d : mgl@1371: + CODE_FOR_machh_d); mgl@1371: + mgl@1371: + tmode = insn_data[icode].operand[0].mode; mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mode1 = insn_data[icode].operand[2].mode; mgl@1371: + mgl@1371: + mgl@1371: + if (!target mgl@1371: + || GET_MODE (target) != tmode mgl@1371: + || !(*insn_data[icode].operand[0].predicate) (target, tmode)) mgl@1371: + target = gen_reg_rtx (tmode); mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, tmode)) mgl@1371: + { mgl@1371: + /* If op0 is already a reg we must cast it to the correct mode. */ mgl@1371: + if (REG_P (op0)) mgl@1371: + op0 = convert_to_mode (tmode, op0, 1); mgl@1371: + else mgl@1371: + op0 = copy_to_mode_reg (tmode, op0); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, mode0)) mgl@1371: + { mgl@1371: + /* If op1 is already a reg we must cast it to the correct mode. */ mgl@1371: + if (REG_P (op1)) mgl@1371: + op1 = convert_to_mode (mode0, op1, 1); mgl@1371: + else mgl@1371: + op1 = copy_to_mode_reg (mode0, op1); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op2, mode1)) mgl@1371: + { mgl@1371: + /* If op1 is already a reg we must cast it to the correct mode. */ mgl@1371: + if (REG_P (op2)) mgl@1371: + op2 = convert_to_mode (mode1, op2, 1); mgl@1371: + else mgl@1371: + op2 = copy_to_mode_reg (mode1, op2); mgl@1371: + } mgl@1371: + mgl@1371: + emit_move_insn (target, op0); mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (target, op1, op2); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return target; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_MVRC_W: mgl@1371: + case AVR32_BUILTIN_MVRC_D: mgl@1371: + { mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); mgl@1371: + mgl@1371: + if (fcode == AVR32_BUILTIN_MVRC_W) mgl@1371: + icode = CODE_FOR_mvrcsi; mgl@1371: + else mgl@1371: + icode = CODE_FOR_mvrcdi; mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, SImode)) mgl@1371: + { mgl@1371: + error ("Parameter 1 is not a valid coprocessor number."); mgl@1371: + error ("Number should be between 0 and 7."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) mgl@1371: + { mgl@1371: + error ("Parameter 2 is not a valid coprocessor register number."); mgl@1371: + error ("Number should be between 0 and 15."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (GET_CODE (op2) == CONST_INT mgl@1371: + || GET_CODE (op2) == CONST mgl@1371: + || GET_CODE (op2) == SYMBOL_REF || GET_CODE (op2) == LABEL_REF) mgl@1371: + { mgl@1371: + op2 = force_const_mem (insn_data[icode].operand[2].mode, op2); mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op2, GET_MODE (op2))) mgl@1371: + op2 = copy_to_mode_reg (insn_data[icode].operand[2].mode, op2); mgl@1371: + mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (op0, op1, op2); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_COP: mgl@1371: + { mgl@1371: + rtx op3, op4; mgl@1371: + tree arg3, arg4; mgl@1371: + icode = CODE_FOR_cop; mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); mgl@1371: + arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); mgl@1371: + arg4 = mgl@1371: + TREE_VALUE (TREE_CHAIN mgl@1371: + (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))))); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); mgl@1371: + op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); mgl@1371: + op4 = expand_expr (arg4, NULL_RTX, VOIDmode, 0); mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[0].predicate) (op0, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 1 to __builtin_cop is not a valid coprocessor number."); mgl@1371: + error ("Number should be between 0 and 7."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op1, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 2 to __builtin_cop is not a valid coprocessor register number."); mgl@1371: + error ("Number should be between 0 and 15."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[2].predicate) (op2, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 3 to __builtin_cop is not a valid coprocessor register number."); mgl@1371: + error ("Number should be between 0 and 15."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[3].predicate) (op3, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 4 to __builtin_cop is not a valid coprocessor register number."); mgl@1371: + error ("Number should be between 0 and 15."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[4].predicate) (op4, SImode)) mgl@1371: + { mgl@1371: + error mgl@1371: + ("Parameter 5 to __builtin_cop is not a valid coprocessor operation."); mgl@1371: + error ("Number should be between 0 and 127."); mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + pat = GEN_FCN (icode) (op0, op1, op2, op3, op4); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + mgl@1371: + return target; mgl@1371: + } mgl@1371: + case AVR32_BUILTIN_MEMS: mgl@1371: + case AVR32_BUILTIN_MEMC: mgl@1371: + case AVR32_BUILTIN_MEMT: mgl@1371: + { mgl@1371: + if (!TARGET_RMW) mgl@1371: + error ("Trying to use __builtin_mem(s/c/t) when target does not support RMW insns."); mgl@1371: + mgl@1371: + switch (fcode) { mgl@1371: + case AVR32_BUILTIN_MEMS: mgl@1371: + icode = CODE_FOR_iorsi3; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_MEMC: mgl@1371: + icode = CODE_FOR_andsi3; mgl@1371: + break; mgl@1371: + case AVR32_BUILTIN_MEMT: mgl@1371: + icode = CODE_FOR_xorsi3; mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + arg0 = TREE_VALUE (arglist); mgl@1371: + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); mgl@1371: + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); mgl@1371: + if ( GET_CODE (op0) == SYMBOL_REF ) mgl@1371: + // This symbol must be RMW addressable mgl@1371: + SYMBOL_REF_FLAGS (op0) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT); mgl@1371: + op0 = gen_rtx_MEM(SImode, op0); mgl@1371: + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); mgl@1371: + mode0 = insn_data[icode].operand[1].mode; mgl@1371: + mgl@1371: + mgl@1371: + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) mgl@1371: + { mgl@1371: + error ("Parameter 1 to __builtin_mem(s/c/t) must be a Ks15<<2 address or a rmw addressable symbol."); mgl@1371: + } mgl@1371: + mgl@1371: + if ( !CONST_INT_P (op1) mgl@1371: + || INTVAL (op1) > 31 mgl@1371: + || INTVAL (op1) < 0 ) mgl@1371: + error ("Parameter 2 to __builtin_mem(s/c/t) must be a constant between 0 and 31."); mgl@1371: + mgl@1371: + if ( fcode == AVR32_BUILTIN_MEMC ) mgl@1371: + op1 = GEN_INT((~(1 << INTVAL(op1)))&0xffffffff); mgl@1371: + else mgl@1371: + op1 = GEN_INT((1 << INTVAL(op1))&0xffffffff); mgl@1371: + pat = GEN_FCN (icode) (op0, op0, op1); mgl@1371: + if (!pat) mgl@1371: + return 0; mgl@1371: + emit_insn (pat); mgl@1371: + return op0; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + mgl@1371: + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) mgl@1371: + if (d->code == fcode) mgl@1371: + return avr32_expand_binop_builtin (d->icode, arglist, target); mgl@1371: + mgl@1371: + mgl@1371: + /* @@@ Should really do something sensible here. */ mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Handle an "interrupt" or "isr" attribute; mgl@1371: + arguments as in struct attribute_spec.handler. */ mgl@1371: + mgl@1371: +static tree mgl@1371: +avr32_handle_isr_attribute (tree * node, tree name, tree args, mgl@1371: + int flags, bool * no_add_attrs) mgl@1371: +{ mgl@1371: + if (DECL_P (*node)) mgl@1371: + { mgl@1371: + if (TREE_CODE (*node) != FUNCTION_DECL) mgl@1371: + { mgl@1371: + warning (OPT_Wattributes,"`%s' attribute only applies to functions", mgl@1371: + IDENTIFIER_POINTER (name)); mgl@1371: + *no_add_attrs = true; mgl@1371: + } mgl@1371: + /* FIXME: the argument if any is checked for type attributes; should it mgl@1371: + be checked for decl ones? */ mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + if (TREE_CODE (*node) == FUNCTION_TYPE mgl@1371: + || TREE_CODE (*node) == METHOD_TYPE) mgl@1371: + { mgl@1371: + if (avr32_isr_value (args) == AVR32_FT_UNKNOWN) mgl@1371: + { mgl@1371: + warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name)); mgl@1371: + *no_add_attrs = true; mgl@1371: + } mgl@1371: + } mgl@1371: + else if (TREE_CODE (*node) == POINTER_TYPE mgl@1371: + && (TREE_CODE (TREE_TYPE (*node)) == FUNCTION_TYPE mgl@1371: + || TREE_CODE (TREE_TYPE (*node)) == METHOD_TYPE) mgl@1371: + && avr32_isr_value (args) != AVR32_FT_UNKNOWN) mgl@1371: + { mgl@1371: + *node = build_variant_type_copy (*node); mgl@1371: + TREE_TYPE (*node) = build_type_attribute_variant mgl@1371: + (TREE_TYPE (*node), mgl@1371: + tree_cons (name, args, TYPE_ATTRIBUTES (TREE_TYPE (*node)))); mgl@1371: + *no_add_attrs = true; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Possibly pass this attribute on from the type to a decl. */ mgl@1371: + if (flags & ((int) ATTR_FLAG_DECL_NEXT mgl@1371: + | (int) ATTR_FLAG_FUNCTION_NEXT mgl@1371: + | (int) ATTR_FLAG_ARRAY_NEXT)) mgl@1371: + { mgl@1371: + *no_add_attrs = true; mgl@1371: + return tree_cons (name, args, NULL_TREE); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + warning (OPT_Wattributes,"`%s' attribute ignored", IDENTIFIER_POINTER (name)); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + return NULL_TREE; mgl@1371: +} mgl@1371: + mgl@1371: +/* Handle an attribute requiring a FUNCTION_DECL; mgl@1371: + arguments as in struct attribute_spec.handler. */ mgl@1371: +static tree mgl@1371: +avr32_handle_fndecl_attribute (tree * node, tree name, mgl@1371: + tree args ATTRIBUTE_UNUSED, mgl@1371: + int flags ATTRIBUTE_UNUSED, mgl@1371: + bool * no_add_attrs) mgl@1371: +{ mgl@1371: + if (TREE_CODE (*node) != FUNCTION_DECL) mgl@1371: + { mgl@1371: + warning (OPT_Wattributes,"%qs attribute only applies to functions", mgl@1371: + IDENTIFIER_POINTER (name)); mgl@1371: + *no_add_attrs = true; mgl@1371: + } mgl@1371: + mgl@1371: + return NULL_TREE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Handle an acall attribute; mgl@1371: + arguments as in struct attribute_spec.handler. */ mgl@1371: + mgl@1371: +static tree mgl@1371: +avr32_handle_acall_attribute (tree * node, tree name, mgl@1371: + tree args ATTRIBUTE_UNUSED, mgl@1371: + int flags ATTRIBUTE_UNUSED, bool * no_add_attrs) mgl@1371: +{ mgl@1371: + if (TREE_CODE (*node) == FUNCTION_TYPE || TREE_CODE (*node) == METHOD_TYPE) mgl@1371: + { mgl@1371: + warning (OPT_Wattributes,"`%s' attribute not yet supported...", mgl@1371: + IDENTIFIER_POINTER (name)); mgl@1371: + *no_add_attrs = true; mgl@1371: + return NULL_TREE; mgl@1371: + } mgl@1371: + mgl@1371: + warning (OPT_Wattributes,"`%s' attribute only applies to functions", mgl@1371: + IDENTIFIER_POINTER (name)); mgl@1371: + *no_add_attrs = true; mgl@1371: + return NULL_TREE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Return 0 if the attributes for two types are incompatible, 1 if they mgl@1371: + are compatible, and 2 if they are nearly compatible (which causes a mgl@1371: + warning to be generated). */ mgl@1371: + mgl@1371: +static int mgl@1371: +avr32_comp_type_attributes (tree type1, tree type2) mgl@1371: +{ mgl@1371: + int acall1, acall2, isr1, isr2, naked1, naked2; mgl@1371: + mgl@1371: + /* Check for mismatch of non-default calling convention. */ mgl@1371: + if (TREE_CODE (type1) != FUNCTION_TYPE) mgl@1371: + return 1; mgl@1371: + mgl@1371: + /* Check for mismatched call attributes. */ mgl@1371: + acall1 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type1)) != NULL; mgl@1371: + acall2 = lookup_attribute ("acall", TYPE_ATTRIBUTES (type2)) != NULL; mgl@1371: + naked1 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type1)) != NULL; mgl@1371: + naked2 = lookup_attribute ("naked", TYPE_ATTRIBUTES (type2)) != NULL; mgl@1371: + isr1 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type1)) != NULL; mgl@1371: + if (!isr1) mgl@1371: + isr1 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type1)) != NULL; mgl@1371: + mgl@1371: + isr2 = lookup_attribute ("isr", TYPE_ATTRIBUTES (type2)) != NULL; mgl@1371: + if (!isr2) mgl@1371: + isr2 = lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type2)) != NULL; mgl@1371: + mgl@1371: + if ((acall1 && isr2) mgl@1371: + || (acall2 && isr1) || (naked1 && isr2) || (naked2 && isr1)) mgl@1371: + return 0; mgl@1371: + mgl@1371: + return 1; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Computes the type of the current function. */ mgl@1371: + mgl@1371: +static unsigned long mgl@1371: +avr32_compute_func_type (void) mgl@1371: +{ mgl@1371: + unsigned long type = AVR32_FT_UNKNOWN; mgl@1371: + tree a; mgl@1371: + tree attr; mgl@1371: + mgl@1371: + if (TREE_CODE (current_function_decl) != FUNCTION_DECL) mgl@1371: + abort (); mgl@1371: + mgl@1371: + /* Decide if the current function is volatile. Such functions never mgl@1371: + return, and many memory cycles can be saved by not storing register mgl@1371: + values that will never be needed again. This optimization was added to mgl@1371: + speed up context switching in a kernel application. */ mgl@1371: + if (optimize > 0 mgl@1371: + && TREE_NOTHROW (current_function_decl) mgl@1371: + && TREE_THIS_VOLATILE (current_function_decl)) mgl@1371: + type |= AVR32_FT_VOLATILE; mgl@1371: + mgl@1371: + if (cfun->static_chain_decl != NULL) mgl@1371: + type |= AVR32_FT_NESTED; mgl@1371: + mgl@1371: + attr = DECL_ATTRIBUTES (current_function_decl); mgl@1371: + mgl@1371: + a = lookup_attribute ("isr", attr); mgl@1371: + if (a == NULL_TREE) mgl@1371: + a = lookup_attribute ("interrupt", attr); mgl@1371: + mgl@1371: + if (a == NULL_TREE) mgl@1371: + type |= AVR32_FT_NORMAL; mgl@1371: + else mgl@1371: + type |= avr32_isr_value (TREE_VALUE (a)); mgl@1371: + mgl@1371: + mgl@1371: + a = lookup_attribute ("acall", attr); mgl@1371: + if (a != NULL_TREE) mgl@1371: + type |= AVR32_FT_ACALL; mgl@1371: + mgl@1371: + a = lookup_attribute ("naked", attr); mgl@1371: + if (a != NULL_TREE) mgl@1371: + type |= AVR32_FT_NAKED; mgl@1371: + mgl@1371: + return type; mgl@1371: +} mgl@1371: + mgl@1371: +/* Returns the type of the current function. */ mgl@1371: + mgl@1371: +static unsigned long mgl@1371: +avr32_current_func_type (void) mgl@1371: +{ mgl@1371: + if (AVR32_FUNC_TYPE (cfun->machine->func_type) == AVR32_FT_UNKNOWN) mgl@1371: + cfun->machine->func_type = avr32_compute_func_type (); mgl@1371: + mgl@1371: + return cfun->machine->func_type; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + This target hook should return true if we should not pass type solely mgl@1371: + in registers. The file expr.h defines a definition that is usually appropriate, mgl@1371: + refer to expr.h for additional documentation. mgl@1371: +*/ mgl@1371: +bool mgl@1371: +avr32_must_pass_in_stack (enum machine_mode mode ATTRIBUTE_UNUSED, tree type) mgl@1371: +{ mgl@1371: + if (type && AGGREGATE_TYPE_P (type) mgl@1371: + /* If the alignment is less than the size then pass in the struct on mgl@1371: + the stack. */ mgl@1371: + && ((unsigned int) TYPE_ALIGN_UNIT (type) < mgl@1371: + (unsigned int) int_size_in_bytes (type)) mgl@1371: + /* If we support unaligned word accesses then structs of size 4 and 8 mgl@1371: + can have any alignment and still be passed in registers. */ mgl@1371: + && !(TARGET_UNALIGNED_WORD mgl@1371: + && (int_size_in_bytes (type) == 4 mgl@1371: + || int_size_in_bytes (type) == 8)) mgl@1371: + /* Double word structs need only a word alignment. */ mgl@1371: + && !(int_size_in_bytes (type) == 8 && TYPE_ALIGN_UNIT (type) >= 4)) mgl@1371: + return true; mgl@1371: + mgl@1371: + if (type && AGGREGATE_TYPE_P (type) mgl@1371: + /* Structs of size 3,5,6,7 are always passed in registers. */ mgl@1371: + && (int_size_in_bytes (type) == 3 mgl@1371: + || int_size_in_bytes (type) == 5 mgl@1371: + || int_size_in_bytes (type) == 6 || int_size_in_bytes (type) == 7)) mgl@1371: + return true; mgl@1371: + mgl@1371: + mgl@1371: + return (type && TREE_ADDRESSABLE (type)); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +bool mgl@1371: +avr32_strict_argument_naming (CUMULATIVE_ARGS * ca ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + return true; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + This target hook should return true if an argument at the position indicated mgl@1371: + by cum should be passed by reference. This predicate is queried after target mgl@1371: + independent reasons for being passed by reference, such as TREE_ADDRESSABLE (type). mgl@1371: + mgl@1371: + If the hook returns true, a copy of that argument is made in memory and a mgl@1371: + pointer to the argument is passed instead of the argument itself. The pointer mgl@1371: + is passed in whatever way is appropriate for passing a pointer to that type. mgl@1371: +*/ mgl@1371: +bool mgl@1371: +avr32_pass_by_reference (CUMULATIVE_ARGS * cum ATTRIBUTE_UNUSED, mgl@1371: + enum machine_mode mode ATTRIBUTE_UNUSED, mgl@1371: + tree type, bool named ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + return (type && (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST)); mgl@1371: +} mgl@1371: + mgl@1371: +static int mgl@1371: +avr32_arg_partial_bytes (CUMULATIVE_ARGS * pcum ATTRIBUTE_UNUSED, mgl@1371: + enum machine_mode mode ATTRIBUTE_UNUSED, mgl@1371: + tree type ATTRIBUTE_UNUSED, mgl@1371: + bool named ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +struct gcc_target targetm = TARGET_INITIALIZER; mgl@1371: + mgl@1371: +/* mgl@1371: + Table used to convert from register number in the assembler instructions and mgl@1371: + the register numbers used in gcc. mgl@1371: +*/ mgl@1371: +const int avr32_function_arg_reglist[] = { mgl@1371: + INTERNAL_REGNUM (12), mgl@1371: + INTERNAL_REGNUM (11), mgl@1371: + INTERNAL_REGNUM (10), mgl@1371: + INTERNAL_REGNUM (9), mgl@1371: + INTERNAL_REGNUM (8) mgl@1371: +}; mgl@1371: + mgl@1371: +rtx avr32_compare_op0 = NULL_RTX; mgl@1371: +rtx avr32_compare_op1 = NULL_RTX; mgl@1371: +rtx avr32_compare_operator = NULL_RTX; mgl@1371: +rtx avr32_acc_cache = NULL_RTX; mgl@1371: + mgl@1371: +/* mgl@1371: + Returns nonzero if it is allowed to store a value of mode mode in hard mgl@1371: + register number regno. mgl@1371: +*/ mgl@1371: +int mgl@1371: +avr32_hard_regno_mode_ok (int regnr, enum machine_mode mode) mgl@1371: +{ mgl@1371: + /* We allow only float modes in the fp-registers */ mgl@1371: + if (regnr >= FIRST_FP_REGNUM mgl@1371: + && regnr <= LAST_FP_REGNUM && GET_MODE_CLASS (mode) != MODE_FLOAT) mgl@1371: + { mgl@1371: + return 0; mgl@1371: + } mgl@1371: + mgl@1371: + switch (mode) mgl@1371: + { mgl@1371: + case DImode: /* long long */ mgl@1371: + case DFmode: /* double */ mgl@1371: + case SCmode: /* __complex__ float */ mgl@1371: + case CSImode: /* __complex__ int */ mgl@1371: + if (regnr < 4) mgl@1371: + { /* long long int not supported in r12, sp, lr mgl@1371: + or pc. */ mgl@1371: + return 0; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + if (regnr % 2) /* long long int has to be refered in even mgl@1371: + registers. */ mgl@1371: + return 0; mgl@1371: + else mgl@1371: + return 1; mgl@1371: + } mgl@1371: + case CDImode: /* __complex__ long long */ mgl@1371: + case DCmode: /* __complex__ double */ mgl@1371: + case TImode: /* 16 bytes */ mgl@1371: + if (regnr < 7) mgl@1371: + return 0; mgl@1371: + else if (regnr % 2) mgl@1371: + return 0; mgl@1371: + else mgl@1371: + return 1; mgl@1371: + default: mgl@1371: + return 1; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +int mgl@1371: +avr32_rnd_operands (rtx add, rtx shift) mgl@1371: +{ mgl@1371: + if (GET_CODE (shift) == CONST_INT && mgl@1371: + GET_CODE (add) == CONST_INT && INTVAL (shift) > 0) mgl@1371: + { mgl@1371: + if ((1 << (INTVAL (shift) - 1)) == INTVAL (add)) mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +int mgl@1371: +avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, const char *str) mgl@1371: +{ mgl@1371: + switch (c) mgl@1371: + { mgl@1371: + case 'K': mgl@1371: + case 'I': mgl@1371: + { mgl@1371: + HOST_WIDE_INT min_value = 0, max_value = 0; mgl@1371: + char size_str[3]; mgl@1371: + int const_size; mgl@1371: + mgl@1371: + size_str[0] = str[2]; mgl@1371: + size_str[1] = str[3]; mgl@1371: + size_str[2] = '\0'; mgl@1371: + const_size = atoi (size_str); mgl@1371: + mgl@1371: + if (toupper (str[1]) == 'U') mgl@1371: + { mgl@1371: + min_value = 0; mgl@1371: + max_value = (1 << const_size) - 1; mgl@1371: + } mgl@1371: + else if (toupper (str[1]) == 'S') mgl@1371: + { mgl@1371: + min_value = -(1 << (const_size - 1)); mgl@1371: + max_value = (1 << (const_size - 1)) - 1; mgl@1371: + } mgl@1371: + mgl@1371: + if (c == 'I') mgl@1371: + { mgl@1371: + value = -value; mgl@1371: + } mgl@1371: + mgl@1371: + if (value >= min_value && value <= max_value) mgl@1371: + { mgl@1371: + return 1; mgl@1371: + } mgl@1371: + break; mgl@1371: + } mgl@1371: + case 'M': mgl@1371: + return avr32_mask_upper_bits_operand (GEN_INT (value), VOIDmode); mgl@1371: + case 'J': mgl@1371: + return avr32_hi16_immediate_operand (GEN_INT (value), VOIDmode); mgl@1371: + case 'O': mgl@1371: + return one_bit_set_operand (GEN_INT (value), VOIDmode); mgl@1371: + case 'N': mgl@1371: + return one_bit_cleared_operand (GEN_INT (value), VOIDmode); mgl@1371: + case 'L': mgl@1371: + /* The lower 16-bits are set. */ mgl@1371: + return ((value & 0xffff) == 0xffff) ; mgl@1371: + } mgl@1371: + mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/*Compute mask of which floating-point registers needs saving upon mgl@1371: + entry to this function*/ mgl@1371: +static unsigned long mgl@1371: +avr32_compute_save_fp_reg_mask (void) mgl@1371: +{ mgl@1371: + unsigned long func_type = avr32_current_func_type (); mgl@1371: + unsigned int save_reg_mask = 0; mgl@1371: + unsigned int reg; mgl@1371: + unsigned int max_reg = 7; mgl@1371: + int save_all_call_used_regs = FALSE; mgl@1371: + mgl@1371: + /* This only applies for hardware floating-point implementation. */ mgl@1371: + if (!TARGET_HARD_FLOAT) mgl@1371: + return 0; mgl@1371: + mgl@1371: + if (IS_INTERRUPT (func_type)) mgl@1371: + { mgl@1371: + mgl@1371: + /* Interrupt functions must not corrupt any registers, even call mgl@1371: + clobbered ones. If this is a leaf function we can just examine the mgl@1371: + registers used by the RTL, but otherwise we have to assume that mgl@1371: + whatever function is called might clobber anything, and so we have mgl@1371: + to save all the call-clobbered registers as well. */ mgl@1371: + max_reg = 13; mgl@1371: + save_all_call_used_regs = !current_function_is_leaf; mgl@1371: + } mgl@1371: + mgl@1371: + /* All used registers used must be saved */ mgl@1371: + for (reg = 0; reg <= max_reg; reg++) mgl@1371: + if (regs_ever_live[INTERNAL_FP_REGNUM (reg)] mgl@1371: + || (save_all_call_used_regs mgl@1371: + && call_used_regs[INTERNAL_FP_REGNUM (reg)])) mgl@1371: + save_reg_mask |= (1 << reg); mgl@1371: + mgl@1371: + return save_reg_mask; mgl@1371: +} mgl@1371: + mgl@1371: +/*Compute mask of registers which needs saving upon function entry */ mgl@1371: +static unsigned long mgl@1371: +avr32_compute_save_reg_mask (int push) mgl@1371: +{ mgl@1371: + unsigned long func_type; mgl@1371: + unsigned int save_reg_mask = 0; mgl@1371: + unsigned int reg; mgl@1371: + mgl@1371: + func_type = avr32_current_func_type (); mgl@1371: + mgl@1371: + if (IS_INTERRUPT (func_type)) mgl@1371: + { mgl@1371: + unsigned int max_reg = 12; mgl@1371: + mgl@1371: + mgl@1371: + /* Get the banking scheme for the interrupt */ mgl@1371: + switch (func_type) mgl@1371: + { mgl@1371: + case AVR32_FT_ISR_FULL: mgl@1371: + max_reg = 0; mgl@1371: + break; mgl@1371: + case AVR32_FT_ISR_HALF: mgl@1371: + max_reg = 7; mgl@1371: + break; mgl@1371: + case AVR32_FT_ISR_NONE: mgl@1371: + max_reg = 12; mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + /* Interrupt functions must not corrupt any registers, even call mgl@1371: + clobbered ones. If this is a leaf function we can just examine the mgl@1371: + registers used by the RTL, but otherwise we have to assume that mgl@1371: + whatever function is called might clobber anything, and so we have mgl@1371: + to save all the call-clobbered registers as well. */ mgl@1371: + mgl@1371: + /* Need not push the registers r8-r12 for AVR32A architectures, as this mgl@1371: + is automatially done in hardware. We also do not have any shadow mgl@1371: + registers. */ mgl@1371: + if (TARGET_UARCH_AVR32A) mgl@1371: + { mgl@1371: + max_reg = 7; mgl@1371: + func_type = AVR32_FT_ISR_NONE; mgl@1371: + } mgl@1371: + mgl@1371: + /* All registers which are used and is not shadowed must be saved */ mgl@1371: + for (reg = 0; reg <= max_reg; reg++) mgl@1371: + if (regs_ever_live[INTERNAL_REGNUM (reg)] mgl@1371: + || (!current_function_is_leaf mgl@1371: + && call_used_regs[INTERNAL_REGNUM (reg)])) mgl@1371: + save_reg_mask |= (1 << reg); mgl@1371: + mgl@1371: + /* Check LR */ mgl@1371: + if ((regs_ever_live[LR_REGNUM] mgl@1371: + || !current_function_is_leaf || frame_pointer_needed) mgl@1371: + /* Only non-shadowed register models */ mgl@1371: + && (func_type == AVR32_FT_ISR_NONE)) mgl@1371: + save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM)); mgl@1371: + mgl@1371: + /* Make sure that the GOT register is pushed. */ mgl@1371: + if (max_reg >= ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM) mgl@1371: + && current_function_uses_pic_offset_table) mgl@1371: + save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)); mgl@1371: + mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + int use_pushm = optimize_size; mgl@1371: + mgl@1371: + /* In the normal case we only need to save those registers which are mgl@1371: + call saved and which are used by this function. */ mgl@1371: + for (reg = 0; reg <= 7; reg++) mgl@1371: + if (regs_ever_live[INTERNAL_REGNUM (reg)] mgl@1371: + && !call_used_regs[INTERNAL_REGNUM (reg)]) mgl@1371: + save_reg_mask |= (1 << reg); mgl@1371: + mgl@1371: + /* Make sure that the GOT register is pushed. */ mgl@1371: + if (current_function_uses_pic_offset_table) mgl@1371: + save_reg_mask |= (1 << ASM_REGNUM (PIC_OFFSET_TABLE_REGNUM)); mgl@1371: + mgl@1371: + mgl@1371: + /* If we optimize for size and do not have anonymous arguments: use mgl@1371: + popm/pushm always */ mgl@1371: + if (use_pushm) mgl@1371: + { mgl@1371: + if ((save_reg_mask & (1 << 0)) mgl@1371: + || (save_reg_mask & (1 << 1)) mgl@1371: + || (save_reg_mask & (1 << 2)) || (save_reg_mask & (1 << 3))) mgl@1371: + save_reg_mask |= 0xf; mgl@1371: + mgl@1371: + if ((save_reg_mask & (1 << 4)) mgl@1371: + || (save_reg_mask & (1 << 5)) mgl@1371: + || (save_reg_mask & (1 << 6)) || (save_reg_mask & (1 << 7))) mgl@1371: + save_reg_mask |= 0xf0; mgl@1371: + mgl@1371: + if ((save_reg_mask & (1 << 8)) || (save_reg_mask & (1 << 9))) mgl@1371: + save_reg_mask |= 0x300; mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + /* Check LR */ mgl@1371: + if ((regs_ever_live[LR_REGNUM] mgl@1371: + || !current_function_is_leaf mgl@1371: + || (optimize_size mgl@1371: + && save_reg_mask mgl@1371: + && !current_function_calls_eh_return) || frame_pointer_needed)) mgl@1371: + { mgl@1371: + if (push mgl@1371: + /* Never pop LR into PC for functions which mgl@1371: + calls __builtin_eh_return, since we need to mgl@1371: + fix the SP after the restoring of the registers mgl@1371: + and before returning. */ mgl@1371: + || current_function_calls_eh_return) mgl@1371: + { mgl@1371: + /* Push/Pop LR */ mgl@1371: + save_reg_mask |= (1 << ASM_REGNUM (LR_REGNUM)); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Pop PC */ mgl@1371: + save_reg_mask |= (1 << ASM_REGNUM (PC_REGNUM)); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + /* Save registers so the exception handler can modify them. */ mgl@1371: + if (current_function_calls_eh_return) mgl@1371: + { mgl@1371: + unsigned int i; mgl@1371: + mgl@1371: + for (i = 0;; i++) mgl@1371: + { mgl@1371: + reg = EH_RETURN_DATA_REGNO (i); mgl@1371: + if (reg == INVALID_REGNUM) mgl@1371: + break; mgl@1371: + save_reg_mask |= 1 << ASM_REGNUM (reg); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + return save_reg_mask; mgl@1371: +} mgl@1371: + mgl@1371: +/*Compute total size in bytes of all saved registers */ mgl@1371: +static int mgl@1371: +avr32_get_reg_mask_size (int reg_mask) mgl@1371: +{ mgl@1371: + int reg, size; mgl@1371: + size = 0; mgl@1371: + mgl@1371: + for (reg = 0; reg <= 15; reg++) mgl@1371: + if (reg_mask & (1 << reg)) mgl@1371: + size += 4; mgl@1371: + mgl@1371: + return size; mgl@1371: +} mgl@1371: + mgl@1371: +/*Get a register from one of the registers which are saved onto the stack mgl@1371: + upon function entry */ mgl@1371: + mgl@1371: +static int mgl@1371: +avr32_get_saved_reg (int save_reg_mask) mgl@1371: +{ mgl@1371: + unsigned int reg; mgl@1371: + mgl@1371: + /* Find the first register which is saved in the saved_reg_mask */ mgl@1371: + for (reg = 0; reg <= 15; reg++) mgl@1371: + if (save_reg_mask & (1 << reg)) mgl@1371: + return reg; mgl@1371: + mgl@1371: + return -1; mgl@1371: +} mgl@1371: + mgl@1371: +/* Return 1 if it is possible to return using a single instruction. */ mgl@1371: +int mgl@1371: +avr32_use_return_insn (int iscond) mgl@1371: +{ mgl@1371: + unsigned int func_type = avr32_current_func_type (); mgl@1371: + unsigned long saved_int_regs; mgl@1371: + unsigned long saved_fp_regs; mgl@1371: + mgl@1371: + /* Never use a return instruction before reload has run. */ mgl@1371: + if (!reload_completed) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* Must adjust the stack for vararg functions. */ mgl@1371: + if (current_function_args_info.uses_anonymous_args) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* If there a stack adjstment. */ mgl@1371: + if (get_frame_size ()) mgl@1371: + return 0; mgl@1371: + mgl@1371: + saved_int_regs = avr32_compute_save_reg_mask (TRUE); mgl@1371: + saved_fp_regs = avr32_compute_save_fp_reg_mask (); mgl@1371: + mgl@1371: + /* Functions which have saved fp-regs on the stack can not be performed in mgl@1371: + one instruction */ mgl@1371: + if (saved_fp_regs) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* Conditional returns can not be performed in one instruction if we need mgl@1371: + to restore registers from the stack */ mgl@1371: + if (iscond && saved_int_regs) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* Conditional return can not be used for interrupt handlers. */ mgl@1371: + if (iscond && IS_INTERRUPT (func_type)) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* For interrupt handlers which needs to pop registers */ mgl@1371: + if (saved_int_regs && IS_INTERRUPT (func_type)) mgl@1371: + return 0; mgl@1371: + mgl@1371: + mgl@1371: + /* If there are saved registers but the LR isn't saved, then we need two mgl@1371: + instructions for the return. */ mgl@1371: + if (saved_int_regs && !(saved_int_regs & (1 << ASM_REGNUM (LR_REGNUM)))) mgl@1371: + return 0; mgl@1371: + mgl@1371: + mgl@1371: + return 1; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/*Generate some function prologue info in the assembly file*/ mgl@1371: + mgl@1371: +void mgl@1371: +avr32_target_asm_function_prologue (FILE * f, HOST_WIDE_INT frame_size) mgl@1371: +{ mgl@1371: + if (IS_NAKED (avr32_current_func_type ())) mgl@1371: + fprintf (f, mgl@1371: + "\t# Function is naked: Prologue and epilogue provided by programmer\n"); mgl@1371: + mgl@1371: + if (IS_INTERRUPT (avr32_current_func_type ())) mgl@1371: + { mgl@1371: + switch (avr32_current_func_type ()) mgl@1371: + { mgl@1371: + case AVR32_FT_ISR_FULL: mgl@1371: + fprintf (f, mgl@1371: + "\t# Interrupt Function: Fully shadowed register file\n"); mgl@1371: + break; mgl@1371: + case AVR32_FT_ISR_HALF: mgl@1371: + fprintf (f, mgl@1371: + "\t# Interrupt Function: Half shadowed register file\n"); mgl@1371: + break; mgl@1371: + default: mgl@1371: + case AVR32_FT_ISR_NONE: mgl@1371: + fprintf (f, "\t# Interrupt Function: No shadowed register file\n"); mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + fprintf (f, "\t# args = %i, frame = %li, pretend = %i\n", mgl@1371: + current_function_args_size, frame_size, mgl@1371: + current_function_pretend_args_size); mgl@1371: + mgl@1371: + fprintf (f, "\t# frame_needed = %i, leaf_function = %i\n", mgl@1371: + frame_pointer_needed, current_function_is_leaf); mgl@1371: + mgl@1371: + fprintf (f, "\t# uses_anonymous_args = %i\n", mgl@1371: + current_function_args_info.uses_anonymous_args); mgl@1371: + if (current_function_calls_eh_return) mgl@1371: + fprintf (f, "\t# Calls __builtin_eh_return.\n"); mgl@1371: + mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Generate and emit an insn that we will recognize as a pushm or stm. mgl@1371: + Unfortunately, since this insn does not reflect very well the actual mgl@1371: + semantics of the operation, we need to annotate the insn for the benefit mgl@1371: + of DWARF2 frame unwind information. */ mgl@1371: + mgl@1371: +int avr32_convert_to_reglist16 (int reglist8_vect); mgl@1371: + mgl@1371: +static rtx mgl@1371: +emit_multi_reg_push (int reglist, int usePUSHM) mgl@1371: +{ mgl@1371: + rtx insn; mgl@1371: + rtx dwarf; mgl@1371: + rtx tmp; mgl@1371: + rtx reg; mgl@1371: + int i; mgl@1371: + int nr_regs; mgl@1371: + int index = 0; mgl@1371: + mgl@1371: + if (usePUSHM) mgl@1371: + { mgl@1371: + insn = emit_insn (gen_pushm (gen_rtx_CONST_INT (SImode, reglist))); mgl@1371: + reglist = avr32_convert_to_reglist16 (reglist); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + insn = emit_insn (gen_stm (stack_pointer_rtx, mgl@1371: + gen_rtx_CONST_INT (SImode, reglist), mgl@1371: + gen_rtx_CONST_INT (SImode, 1))); mgl@1371: + } mgl@1371: + mgl@1371: + nr_regs = avr32_get_reg_mask_size (reglist) / 4; mgl@1371: + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1)); mgl@1371: + mgl@1371: + for (i = 15; i >= 0; i--) mgl@1371: + { mgl@1371: + if (reglist & (1 << i)) mgl@1371: + { mgl@1371: + reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (i)); mgl@1371: + tmp = gen_rtx_SET (VOIDmode, mgl@1371: + gen_rtx_MEM (SImode, mgl@1371: + plus_constant (stack_pointer_rtx, mgl@1371: + 4 * index)), reg); mgl@1371: + RTX_FRAME_RELATED_P (tmp) = 1; mgl@1371: + XVECEXP (dwarf, 0, 1 + index++) = tmp; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + tmp = gen_rtx_SET (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + gen_rtx_PLUS (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + GEN_INT (-4 * nr_regs))); mgl@1371: + RTX_FRAME_RELATED_P (tmp) = 1; mgl@1371: + XVECEXP (dwarf, 0, 0) = tmp; mgl@1371: + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, mgl@1371: + REG_NOTES (insn)); mgl@1371: + return insn; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +static rtx mgl@1371: +emit_multi_fp_reg_push (int reglist) mgl@1371: +{ mgl@1371: + rtx insn; mgl@1371: + rtx dwarf; mgl@1371: + rtx tmp; mgl@1371: + rtx reg; mgl@1371: + int i; mgl@1371: + int nr_regs; mgl@1371: + int index = 0; mgl@1371: + mgl@1371: + insn = emit_insn (gen_stm_fp (stack_pointer_rtx, mgl@1371: + gen_rtx_CONST_INT (SImode, reglist), mgl@1371: + gen_rtx_CONST_INT (SImode, 1))); mgl@1371: + mgl@1371: + nr_regs = avr32_get_reg_mask_size (reglist) / 4; mgl@1371: + dwarf = gen_rtx_SEQUENCE (VOIDmode, rtvec_alloc (nr_regs + 1)); mgl@1371: + mgl@1371: + for (i = 15; i >= 0; i--) mgl@1371: + { mgl@1371: + if (reglist & (1 << i)) mgl@1371: + { mgl@1371: + reg = gen_rtx_REG (SImode, INTERNAL_FP_REGNUM (i)); mgl@1371: + tmp = gen_rtx_SET (VOIDmode, mgl@1371: + gen_rtx_MEM (SImode, mgl@1371: + plus_constant (stack_pointer_rtx, mgl@1371: + 4 * index)), reg); mgl@1371: + RTX_FRAME_RELATED_P (tmp) = 1; mgl@1371: + XVECEXP (dwarf, 0, 1 + index++) = tmp; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + tmp = gen_rtx_SET (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + gen_rtx_PLUS (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + GEN_INT (-4 * nr_regs))); mgl@1371: + RTX_FRAME_RELATED_P (tmp) = 1; mgl@1371: + XVECEXP (dwarf, 0, 0) = tmp; mgl@1371: + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, mgl@1371: + REG_NOTES (insn)); mgl@1371: + return insn; mgl@1371: +} mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_gen_load_multiple (rtx * regs, int count, rtx from, mgl@1371: + int write_back, int in_struct_p, int scalar_p) mgl@1371: +{ mgl@1371: + mgl@1371: + rtx result; mgl@1371: + int i = 0, j; mgl@1371: + mgl@1371: + result = mgl@1371: + gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + (write_back ? 1 : 0))); mgl@1371: + mgl@1371: + if (write_back) mgl@1371: + { mgl@1371: + XVECEXP (result, 0, 0) mgl@1371: + = gen_rtx_SET (GET_MODE (from), from, mgl@1371: + plus_constant (from, count * 4)); mgl@1371: + i = 1; mgl@1371: + count++; mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + for (j = 0; i < count; i++, j++) mgl@1371: + { mgl@1371: + rtx unspec; mgl@1371: + rtx mem = gen_rtx_MEM (SImode, plus_constant (from, j * 4)); mgl@1371: + MEM_IN_STRUCT_P (mem) = in_struct_p; mgl@1371: + MEM_SCALAR_P (mem) = scalar_p; mgl@1371: + unspec = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, mem), UNSPEC_LDM); mgl@1371: + XVECEXP (result, 0, i) = gen_rtx_SET (VOIDmode, regs[j], unspec); mgl@1371: + } mgl@1371: + mgl@1371: + return result; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_gen_store_multiple (rtx * regs, int count, rtx to, mgl@1371: + int in_struct_p, int scalar_p) mgl@1371: +{ mgl@1371: + rtx result; mgl@1371: + int i = 0, j; mgl@1371: + mgl@1371: + result = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); mgl@1371: + mgl@1371: + for (j = 0; i < count; i++, j++) mgl@1371: + { mgl@1371: + rtx mem = gen_rtx_MEM (SImode, plus_constant (to, j * 4)); mgl@1371: + MEM_IN_STRUCT_P (mem) = in_struct_p; mgl@1371: + MEM_SCALAR_P (mem) = scalar_p; mgl@1371: + XVECEXP (result, 0, i) mgl@1371: + = gen_rtx_SET (VOIDmode, mem, mgl@1371: + gen_rtx_UNSPEC (VOIDmode, mgl@1371: + gen_rtvec (1, regs[j]), mgl@1371: + UNSPEC_STORE_MULTIPLE)); mgl@1371: + } mgl@1371: + mgl@1371: + return result; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Move a block of memory if it is word aligned or we support unaligned mgl@1371: + word memory accesses. The size must be maximum 64 bytes. */ mgl@1371: + mgl@1371: +int mgl@1371: +avr32_gen_movmemsi (rtx * operands) mgl@1371: +{ mgl@1371: + HOST_WIDE_INT bytes_to_go; mgl@1371: + rtx src, dst; mgl@1371: + rtx st_src, st_dst; mgl@1371: + int src_offset = 0, dst_offset = 0; mgl@1371: + int block_size; mgl@1371: + int dst_in_struct_p, src_in_struct_p; mgl@1371: + int dst_scalar_p, src_scalar_p; mgl@1371: + int unaligned; mgl@1371: + mgl@1371: + if (GET_CODE (operands[2]) != CONST_INT mgl@1371: + || GET_CODE (operands[3]) != CONST_INT mgl@1371: + || INTVAL (operands[2]) > 64 mgl@1371: + || ((INTVAL (operands[3]) & 3) && !TARGET_UNALIGNED_WORD)) mgl@1371: + return 0; mgl@1371: + mgl@1371: + unaligned = (INTVAL (operands[3]) & 3) != 0; mgl@1371: + mgl@1371: + block_size = 4; mgl@1371: + mgl@1371: + st_dst = XEXP (operands[0], 0); mgl@1371: + st_src = XEXP (operands[1], 0); mgl@1371: + mgl@1371: + dst_in_struct_p = MEM_IN_STRUCT_P (operands[0]); mgl@1371: + dst_scalar_p = MEM_SCALAR_P (operands[0]); mgl@1371: + src_in_struct_p = MEM_IN_STRUCT_P (operands[1]); mgl@1371: + src_scalar_p = MEM_SCALAR_P (operands[1]); mgl@1371: + mgl@1371: + dst = copy_to_mode_reg (SImode, st_dst); mgl@1371: + src = copy_to_mode_reg (SImode, st_src); mgl@1371: + mgl@1371: + bytes_to_go = INTVAL (operands[2]); mgl@1371: + mgl@1371: + while (bytes_to_go) mgl@1371: + { mgl@1371: + enum machine_mode move_mode; mgl@1371: + /* (Seems to be a problem with reloads for the movti pattern so this is mgl@1371: + disabled until that problem is resolved) mgl@1371: + UPDATE: Problem seems to be solved now.... */ mgl@1371: + if (bytes_to_go >= GET_MODE_SIZE (TImode) && !unaligned mgl@1371: + /* Do not emit ldm/stm for UC3 as ld.d/st.d is more optimal. */ mgl@1371: + && !TARGET_ARCH_UC) mgl@1371: + move_mode = TImode; mgl@1371: + else if ((bytes_to_go >= GET_MODE_SIZE (DImode)) && !unaligned) mgl@1371: + move_mode = DImode; mgl@1371: + else if (bytes_to_go >= GET_MODE_SIZE (SImode)) mgl@1371: + move_mode = SImode; mgl@1371: + else mgl@1371: + move_mode = QImode; mgl@1371: + mgl@1371: + { mgl@1371: + rtx src_mem; mgl@1371: + rtx dst_mem = gen_rtx_MEM (move_mode, mgl@1371: + gen_rtx_PLUS (SImode, dst, mgl@1371: + GEN_INT (dst_offset))); mgl@1371: + dst_offset += GET_MODE_SIZE (move_mode); mgl@1371: + if ( 0 /* This causes an error in GCC. Think there is mgl@1371: + something wrong in the gcse pass which causes REQ_EQUIV notes mgl@1371: + to be wrong so disabling it for now. */ mgl@1371: + && move_mode == TImode mgl@1371: + && INTVAL (operands[2]) > GET_MODE_SIZE (TImode) ) mgl@1371: + { mgl@1371: + src_mem = gen_rtx_MEM (move_mode, mgl@1371: + gen_rtx_POST_INC (SImode, src)); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + src_mem = gen_rtx_MEM (move_mode, mgl@1371: + gen_rtx_PLUS (SImode, src, mgl@1371: + GEN_INT (src_offset))); mgl@1371: + src_offset += GET_MODE_SIZE (move_mode); mgl@1371: + } mgl@1371: + mgl@1371: + bytes_to_go -= GET_MODE_SIZE (move_mode); mgl@1371: + mgl@1371: + MEM_IN_STRUCT_P (dst_mem) = dst_in_struct_p; mgl@1371: + MEM_SCALAR_P (dst_mem) = dst_scalar_p; mgl@1371: + mgl@1371: + MEM_IN_STRUCT_P (src_mem) = src_in_struct_p; mgl@1371: + MEM_SCALAR_P (src_mem) = src_scalar_p; mgl@1371: + emit_move_insn (dst_mem, src_mem); mgl@1371: + mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + return 1; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/*Expand the prologue instruction*/ mgl@1371: +void mgl@1371: +avr32_expand_prologue (void) mgl@1371: +{ mgl@1371: + rtx insn, dwarf; mgl@1371: + unsigned long saved_reg_mask, saved_fp_reg_mask; mgl@1371: + int reglist8 = 0; mgl@1371: + mgl@1371: + /* Naked functions does not have a prologue */ mgl@1371: + if (IS_NAKED (avr32_current_func_type ())) mgl@1371: + return; mgl@1371: + mgl@1371: + saved_reg_mask = avr32_compute_save_reg_mask (TRUE); mgl@1371: + mgl@1371: + if (saved_reg_mask) mgl@1371: + { mgl@1371: + /* Must push used registers */ mgl@1371: + mgl@1371: + /* Should we use POPM or LDM? */ mgl@1371: + int usePUSHM = TRUE; mgl@1371: + reglist8 = 0; mgl@1371: + if (((saved_reg_mask & (1 << 0)) || mgl@1371: + (saved_reg_mask & (1 << 1)) || mgl@1371: + (saved_reg_mask & (1 << 2)) || (saved_reg_mask & (1 << 3)))) mgl@1371: + { mgl@1371: + /* One of R0-R3 should at least be pushed */ mgl@1371: + if (((saved_reg_mask & (1 << 0)) && mgl@1371: + (saved_reg_mask & (1 << 1)) && mgl@1371: + (saved_reg_mask & (1 << 2)) && (saved_reg_mask & (1 << 3)))) mgl@1371: + { mgl@1371: + /* All should be pushed */ mgl@1371: + reglist8 |= 0x01; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + usePUSHM = FALSE; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (((saved_reg_mask & (1 << 4)) || mgl@1371: + (saved_reg_mask & (1 << 5)) || mgl@1371: + (saved_reg_mask & (1 << 6)) || (saved_reg_mask & (1 << 7)))) mgl@1371: + { mgl@1371: + /* One of R4-R7 should at least be pushed */ mgl@1371: + if (((saved_reg_mask & (1 << 4)) && mgl@1371: + (saved_reg_mask & (1 << 5)) && mgl@1371: + (saved_reg_mask & (1 << 6)) && (saved_reg_mask & (1 << 7)))) mgl@1371: + { mgl@1371: + if (usePUSHM) mgl@1371: + /* All should be pushed */ mgl@1371: + reglist8 |= 0x02; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + usePUSHM = FALSE; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (((saved_reg_mask & (1 << 8)) || (saved_reg_mask & (1 << 9)))) mgl@1371: + { mgl@1371: + /* One of R8-R9 should at least be pushed */ mgl@1371: + if (((saved_reg_mask & (1 << 8)) && (saved_reg_mask & (1 << 9)))) mgl@1371: + { mgl@1371: + if (usePUSHM) mgl@1371: + /* All should be pushed */ mgl@1371: + reglist8 |= 0x04; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + usePUSHM = FALSE; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << 10)) mgl@1371: + reglist8 |= 0x08; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << 11)) mgl@1371: + reglist8 |= 0x10; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << 12)) mgl@1371: + reglist8 |= 0x20; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << ASM_REGNUM (LR_REGNUM))) mgl@1371: + { mgl@1371: + /* Push LR */ mgl@1371: + reglist8 |= 0x40; mgl@1371: + } mgl@1371: + mgl@1371: + if (usePUSHM) mgl@1371: + { mgl@1371: + insn = emit_multi_reg_push (reglist8, TRUE); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + insn = emit_multi_reg_push (saved_reg_mask, FALSE); mgl@1371: + } mgl@1371: + RTX_FRAME_RELATED_P (insn) = 1; mgl@1371: + mgl@1371: + /* Prevent this instruction from being scheduled after any other mgl@1371: + instructions. */ mgl@1371: + emit_insn (gen_blockage ()); mgl@1371: + } mgl@1371: + mgl@1371: + saved_fp_reg_mask = avr32_compute_save_fp_reg_mask (); mgl@1371: + if (saved_fp_reg_mask) mgl@1371: + { mgl@1371: + insn = emit_multi_fp_reg_push (saved_fp_reg_mask); mgl@1371: + RTX_FRAME_RELATED_P (insn) = 1; mgl@1371: + mgl@1371: + /* Prevent this instruction from being scheduled after any other mgl@1371: + instructions. */ mgl@1371: + emit_insn (gen_blockage ()); mgl@1371: + } mgl@1371: + mgl@1371: + /* Set frame pointer */ mgl@1371: + if (frame_pointer_needed) mgl@1371: + { mgl@1371: + insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx); mgl@1371: + RTX_FRAME_RELATED_P (insn) = 1; mgl@1371: + } mgl@1371: + mgl@1371: + if (get_frame_size () > 0) mgl@1371: + { mgl@1371: + if (avr32_const_ok_for_constraint_p (get_frame_size (), 'K', "Ks21")) mgl@1371: + { mgl@1371: + insn = emit_insn (gen_rtx_SET (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + gen_rtx_PLUS (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + gen_rtx_CONST_INT mgl@1371: + (SImode, mgl@1371: + -get_frame_size mgl@1371: + ())))); mgl@1371: + RTX_FRAME_RELATED_P (insn) = 1; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Immediate is larger than k21 We must either check if we can use mgl@1371: + one of the pushed reegisters as temporary storage or we must mgl@1371: + make us a temp register by pushing a register to the stack. */ mgl@1371: + rtx temp_reg, const_pool_entry, insn; mgl@1371: + if (saved_reg_mask) mgl@1371: + { mgl@1371: + temp_reg = mgl@1371: + gen_rtx_REG (SImode, mgl@1371: + INTERNAL_REGNUM (avr32_get_saved_reg mgl@1371: + (saved_reg_mask))); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + temp_reg = gen_rtx_REG (SImode, INTERNAL_REGNUM (7)); mgl@1371: + emit_move_insn (gen_rtx_MEM mgl@1371: + (SImode, mgl@1371: + gen_rtx_PRE_DEC (SImode, stack_pointer_rtx)), mgl@1371: + temp_reg); mgl@1371: + } mgl@1371: + mgl@1371: + const_pool_entry = mgl@1371: + force_const_mem (SImode, mgl@1371: + gen_rtx_CONST_INT (SImode, get_frame_size ())); mgl@1371: + emit_move_insn (temp_reg, const_pool_entry); mgl@1371: + mgl@1371: + insn = emit_insn (gen_rtx_SET (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + gen_rtx_MINUS (SImode, mgl@1371: + stack_pointer_rtx, mgl@1371: + temp_reg))); mgl@1371: + mgl@1371: + dwarf = gen_rtx_SET (VOIDmode, stack_pointer_rtx, mgl@1371: + gen_rtx_PLUS (SImode, stack_pointer_rtx, mgl@1371: + GEN_INT (-get_frame_size ()))); mgl@1371: + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, mgl@1371: + dwarf, REG_NOTES (insn)); mgl@1371: + RTX_FRAME_RELATED_P (insn) = 1; mgl@1371: + mgl@1371: + if (!saved_reg_mask) mgl@1371: + { mgl@1371: + insn = mgl@1371: + emit_move_insn (temp_reg, mgl@1371: + gen_rtx_MEM (SImode, mgl@1371: + gen_rtx_POST_INC (SImode, mgl@1371: + gen_rtx_REG mgl@1371: + (SImode, mgl@1371: + 13)))); mgl@1371: + } mgl@1371: + mgl@1371: + /* Mark the temp register as dead */ mgl@1371: + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, temp_reg, mgl@1371: + REG_NOTES (insn)); mgl@1371: + mgl@1371: + mgl@1371: + } mgl@1371: + mgl@1371: + /* Prevent the the stack adjustment to be scheduled after any mgl@1371: + instructions using the frame pointer. */ mgl@1371: + emit_insn (gen_blockage ()); mgl@1371: + } mgl@1371: + mgl@1371: + /* Load GOT */ mgl@1371: + if (flag_pic) mgl@1371: + { mgl@1371: + avr32_load_pic_register (); mgl@1371: + mgl@1371: + /* gcc does not know that load or call instructions might use the pic mgl@1371: + register so it might schedule these instructions before the loading mgl@1371: + of the pic register. To avoid this emit a barrier for now. TODO! mgl@1371: + Find out a better way to let gcc know which instructions might use mgl@1371: + the pic register. */ mgl@1371: + emit_insn (gen_blockage ()); mgl@1371: + } mgl@1371: + return; mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_set_return_address (rtx source, rtx scratch) mgl@1371: +{ mgl@1371: + rtx addr; mgl@1371: + unsigned long saved_regs; mgl@1371: + mgl@1371: + saved_regs = avr32_compute_save_reg_mask (TRUE); mgl@1371: + mgl@1371: + if (!(saved_regs & (1 << ASM_REGNUM (LR_REGNUM)))) mgl@1371: + emit_move_insn (gen_rtx_REG (Pmode, LR_REGNUM), source); mgl@1371: + else mgl@1371: + { mgl@1371: + if (frame_pointer_needed) mgl@1371: + addr = gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM); mgl@1371: + else mgl@1371: + if (avr32_const_ok_for_constraint_p (get_frame_size (), 'K', "Ks16")) mgl@1371: + { mgl@1371: + addr = plus_constant (stack_pointer_rtx, get_frame_size ()); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + emit_insn (gen_movsi (scratch, GEN_INT (get_frame_size ()))); mgl@1371: + addr = scratch; mgl@1371: + } mgl@1371: + emit_move_insn (gen_rtx_MEM (Pmode, addr), source); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* Return the length of INSN. LENGTH is the initial length computed by mgl@1371: + attributes in the machine-description file. */ mgl@1371: + mgl@1371: +int mgl@1371: +avr32_adjust_insn_length (rtx insn ATTRIBUTE_UNUSED, mgl@1371: + int length ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + return length; mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_output_return_instruction (int single_ret_inst ATTRIBUTE_UNUSED, mgl@1371: + int iscond ATTRIBUTE_UNUSED, mgl@1371: + rtx cond ATTRIBUTE_UNUSED, rtx r12_imm) mgl@1371: +{ mgl@1371: + mgl@1371: + unsigned long saved_reg_mask, saved_fp_reg_mask; mgl@1371: + int insert_ret = TRUE; mgl@1371: + int reglist8 = 0; mgl@1371: + int stack_adjustment = get_frame_size (); mgl@1371: + unsigned int func_type = avr32_current_func_type (); mgl@1371: + FILE *f = asm_out_file; mgl@1371: + mgl@1371: + /* Naked functions does not have an epilogue */ mgl@1371: + if (IS_NAKED (func_type)) mgl@1371: + return; mgl@1371: + mgl@1371: + saved_fp_reg_mask = avr32_compute_save_fp_reg_mask (); mgl@1371: + mgl@1371: + saved_reg_mask = avr32_compute_save_reg_mask (FALSE); mgl@1371: + mgl@1371: + /* Reset frame pointer */ mgl@1371: + if (stack_adjustment > 0) mgl@1371: + { mgl@1371: + if (avr32_const_ok_for_constraint_p (stack_adjustment, 'I', "Is21")) mgl@1371: + { mgl@1371: + fprintf (f, "\tsub\tsp, %i # Reset Frame Pointer\n", mgl@1371: + -stack_adjustment); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* TODO! Is it safe to use r8 as scratch?? */ mgl@1371: + fprintf (f, "\tmov\tr8, lo(%i) # Reset Frame Pointer\n", mgl@1371: + -stack_adjustment); mgl@1371: + fprintf (f, "\torh\tr8, hi(%i) # Reset Frame Pointer\n", mgl@1371: + -stack_adjustment); mgl@1371: + fprintf (f, "\tadd\tsp, r8 # Reset Frame Pointer\n"); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (saved_fp_reg_mask) mgl@1371: + { mgl@1371: + char reglist[64]; /* 64 bytes should be enough... */ mgl@1371: + avr32_make_fp_reglist_w (saved_fp_reg_mask, (char *) reglist); mgl@1371: + fprintf (f, "\tldcm.w\tcp0, sp++, %s\n", reglist); mgl@1371: + if (saved_fp_reg_mask & ~0xff) mgl@1371: + { mgl@1371: + saved_fp_reg_mask &= ~0xff; mgl@1371: + avr32_make_fp_reglist_d (saved_fp_reg_mask, (char *) reglist); mgl@1371: + fprintf (f, "\tldcm.d\tcp0, sp++, %s\n", reglist); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (saved_reg_mask) mgl@1371: + { mgl@1371: + /* Must pop used registers */ mgl@1371: + mgl@1371: + /* Should we use POPM or LDM? */ mgl@1371: + int usePOPM = TRUE; mgl@1371: + if (((saved_reg_mask & (1 << 0)) || mgl@1371: + (saved_reg_mask & (1 << 1)) || mgl@1371: + (saved_reg_mask & (1 << 2)) || (saved_reg_mask & (1 << 3)))) mgl@1371: + { mgl@1371: + /* One of R0-R3 should at least be popped */ mgl@1371: + if (((saved_reg_mask & (1 << 0)) && mgl@1371: + (saved_reg_mask & (1 << 1)) && mgl@1371: + (saved_reg_mask & (1 << 2)) && (saved_reg_mask & (1 << 3)))) mgl@1371: + { mgl@1371: + /* All should be popped */ mgl@1371: + reglist8 |= 0x01; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + usePOPM = FALSE; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (((saved_reg_mask & (1 << 4)) || mgl@1371: + (saved_reg_mask & (1 << 5)) || mgl@1371: + (saved_reg_mask & (1 << 6)) || (saved_reg_mask & (1 << 7)))) mgl@1371: + { mgl@1371: + /* One of R0-R3 should at least be popped */ mgl@1371: + if (((saved_reg_mask & (1 << 4)) && mgl@1371: + (saved_reg_mask & (1 << 5)) && mgl@1371: + (saved_reg_mask & (1 << 6)) && (saved_reg_mask & (1 << 7)))) mgl@1371: + { mgl@1371: + if (usePOPM) mgl@1371: + /* All should be popped */ mgl@1371: + reglist8 |= 0x02; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + usePOPM = FALSE; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (((saved_reg_mask & (1 << 8)) || (saved_reg_mask & (1 << 9)))) mgl@1371: + { mgl@1371: + /* One of R8-R9 should at least be pushed */ mgl@1371: + if (((saved_reg_mask & (1 << 8)) && (saved_reg_mask & (1 << 9)))) mgl@1371: + { mgl@1371: + if (usePOPM) mgl@1371: + /* All should be pushed */ mgl@1371: + reglist8 |= 0x04; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + usePOPM = FALSE; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << 10)) mgl@1371: + reglist8 |= 0x08; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << 11)) mgl@1371: + reglist8 |= 0x10; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << 12)) mgl@1371: + reglist8 |= 0x20; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << ASM_REGNUM (LR_REGNUM))) mgl@1371: + /* Pop LR */ mgl@1371: + reglist8 |= 0x40; mgl@1371: + mgl@1371: + if (saved_reg_mask & (1 << ASM_REGNUM (PC_REGNUM))) mgl@1371: + /* Pop LR into PC. */ mgl@1371: + reglist8 |= 0x80; mgl@1371: + mgl@1371: + if (usePOPM) mgl@1371: + { mgl@1371: + char reglist[64]; /* 64 bytes should be enough... */ mgl@1371: + avr32_make_reglist8 (reglist8, (char *) reglist); mgl@1371: + mgl@1371: + if (reglist8 & 0x80) mgl@1371: + /* This instruction is also a return */ mgl@1371: + insert_ret = FALSE; mgl@1371: + mgl@1371: + if (r12_imm && !insert_ret) mgl@1371: + fprintf (f, "\tpopm\t%s, r12=%li\n", reglist, INTVAL (r12_imm)); mgl@1371: + else mgl@1371: + fprintf (f, "\tpopm\t%s\n", reglist); mgl@1371: + mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + char reglist[64]; /* 64 bytes should be enough... */ mgl@1371: + avr32_make_reglist16 (saved_reg_mask, (char *) reglist); mgl@1371: + if (saved_reg_mask & (1 << ASM_REGNUM (PC_REGNUM))) mgl@1371: + /* This instruction is also a return */ mgl@1371: + insert_ret = FALSE; mgl@1371: + mgl@1371: + if (r12_imm && !insert_ret) mgl@1371: + fprintf (f, "\tldm\tsp++, %s, r12=%li\n", reglist, mgl@1371: + INTVAL (r12_imm)); mgl@1371: + else mgl@1371: + fprintf (f, "\tldm\tsp++, %s\n", reglist); mgl@1371: + mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + mgl@1371: + /* Stack adjustment for exception handler. */ mgl@1371: + if (current_function_calls_eh_return) mgl@1371: + fprintf (f, "\tadd\tsp, r%d\n", ASM_REGNUM (EH_RETURN_STACKADJ_REGNO)); mgl@1371: + mgl@1371: + mgl@1371: + if (IS_INTERRUPT (func_type)) mgl@1371: + { mgl@1371: + fprintf (f, "\trete\n"); mgl@1371: + } mgl@1371: + else if (insert_ret) mgl@1371: + { mgl@1371: + if (r12_imm) mgl@1371: + fprintf (f, "\tretal\t%li\n", INTVAL (r12_imm)); mgl@1371: + else mgl@1371: + fprintf (f, "\tretal\tr12\n"); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* Function for converting a fp-register mask to a mgl@1371: + reglistCPD8 register list string. */ mgl@1371: +void mgl@1371: +avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string) mgl@1371: +{ mgl@1371: + int i; mgl@1371: + mgl@1371: + /* Make sure reglist_string is empty */ mgl@1371: + reglist_string[0] = '\0'; mgl@1371: + mgl@1371: + for (i = 0; i < NUM_FP_REGS; i += 2) mgl@1371: + { mgl@1371: + if (reglist_mask & (1 << i)) mgl@1371: + { mgl@1371: + strlen (reglist_string) ? mgl@1371: + sprintf (reglist_string, "%s, %s-%s", reglist_string, mgl@1371: + reg_names[INTERNAL_FP_REGNUM (i)], mgl@1371: + reg_names[INTERNAL_FP_REGNUM (i + 1)]) : mgl@1371: + sprintf (reglist_string, "%s-%s", mgl@1371: + reg_names[INTERNAL_FP_REGNUM (i)], mgl@1371: + reg_names[INTERNAL_FP_REGNUM (i + 1)]); mgl@1371: + } mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* Function for converting a fp-register mask to a mgl@1371: + reglistCP8 register list string. */ mgl@1371: +void mgl@1371: +avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string) mgl@1371: +{ mgl@1371: + int i; mgl@1371: + mgl@1371: + /* Make sure reglist_string is empty */ mgl@1371: + reglist_string[0] = '\0'; mgl@1371: + mgl@1371: + for (i = 0; i < NUM_FP_REGS; ++i) mgl@1371: + { mgl@1371: + if (reglist_mask & (1 << i)) mgl@1371: + { mgl@1371: + strlen (reglist_string) ? mgl@1371: + sprintf (reglist_string, "%s, %s", reglist_string, mgl@1371: + reg_names[INTERNAL_FP_REGNUM (i)]) : mgl@1371: + sprintf (reglist_string, "%s", reg_names[INTERNAL_FP_REGNUM (i)]); mgl@1371: + } mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_make_reglist16 (int reglist16_vect, char *reglist16_string) mgl@1371: +{ mgl@1371: + int i; mgl@1371: + mgl@1371: + /* Make sure reglist16_string is empty */ mgl@1371: + reglist16_string[0] = '\0'; mgl@1371: + mgl@1371: + for (i = 0; i < 16; ++i) mgl@1371: + { mgl@1371: + if (reglist16_vect & (1 << i)) mgl@1371: + { mgl@1371: + strlen (reglist16_string) ? mgl@1371: + sprintf (reglist16_string, "%s, %s", reglist16_string, mgl@1371: + reg_names[INTERNAL_REGNUM (i)]) : mgl@1371: + sprintf (reglist16_string, "%s", reg_names[INTERNAL_REGNUM (i)]); mgl@1371: + } mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_convert_to_reglist16 (int reglist8_vect) mgl@1371: +{ mgl@1371: + int reglist16_vect = 0; mgl@1371: + if (reglist8_vect & 0x1) mgl@1371: + reglist16_vect |= 0xF; mgl@1371: + if (reglist8_vect & 0x2) mgl@1371: + reglist16_vect |= 0xF0; mgl@1371: + if (reglist8_vect & 0x4) mgl@1371: + reglist16_vect |= 0x300; mgl@1371: + if (reglist8_vect & 0x8) mgl@1371: + reglist16_vect |= 0x400; mgl@1371: + if (reglist8_vect & 0x10) mgl@1371: + reglist16_vect |= 0x800; mgl@1371: + if (reglist8_vect & 0x20) mgl@1371: + reglist16_vect |= 0x1000; mgl@1371: + if (reglist8_vect & 0x40) mgl@1371: + reglist16_vect |= 0x4000; mgl@1371: + if (reglist8_vect & 0x80) mgl@1371: + reglist16_vect |= 0x8000; mgl@1371: + mgl@1371: + return reglist16_vect; mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_make_reglist8 (int reglist8_vect, char *reglist8_string) mgl@1371: +{ mgl@1371: + /* Make sure reglist8_string is empty */ mgl@1371: + reglist8_string[0] = '\0'; mgl@1371: + mgl@1371: + if (reglist8_vect & 0x1) mgl@1371: + sprintf (reglist8_string, "r0-r3"); mgl@1371: + if (reglist8_vect & 0x2) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r4-r7", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "r4-r7"); mgl@1371: + if (reglist8_vect & 0x4) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r8-r9", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "r8-r9"); mgl@1371: + if (reglist8_vect & 0x8) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r10", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "r10"); mgl@1371: + if (reglist8_vect & 0x10) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r11", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "r11"); mgl@1371: + if (reglist8_vect & 0x20) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, r12", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "r12"); mgl@1371: + if (reglist8_vect & 0x40) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, lr", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "lr"); mgl@1371: + if (reglist8_vect & 0x80) mgl@1371: + strlen (reglist8_string) ? sprintf (reglist8_string, "%s, pc", mgl@1371: + reglist8_string) : mgl@1371: + sprintf (reglist8_string, "pc"); mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_eh_return_data_regno (int n) mgl@1371: +{ mgl@1371: + if (n >= 0 && n <= 3) mgl@1371: + return 8 + n; mgl@1371: + else mgl@1371: + return INVALID_REGNUM; mgl@1371: +} mgl@1371: + mgl@1371: +/* Compute the distance from register FROM to register TO. mgl@1371: + These can be the arg pointer, the frame pointer or mgl@1371: + the stack pointer. mgl@1371: + Typical stack layout looks like this: mgl@1371: + mgl@1371: + old stack pointer -> | | mgl@1371: + ---- mgl@1371: + | | \ mgl@1371: + | | saved arguments for mgl@1371: + | | vararg functions mgl@1371: + arg_pointer -> | | / mgl@1371: + -- mgl@1371: + | | \ mgl@1371: + | | call saved mgl@1371: + | | registers mgl@1371: + | | / mgl@1371: + frame ptr -> -- mgl@1371: + | | \ mgl@1371: + | | local mgl@1371: + | | variables mgl@1371: + stack ptr --> | | / mgl@1371: + -- mgl@1371: + | | \ mgl@1371: + | | outgoing mgl@1371: + | | arguments mgl@1371: + | | / mgl@1371: + -- mgl@1371: + mgl@1371: + For a given funciton some or all of these stack compomnents mgl@1371: + may not be needed, giving rise to the possibility of mgl@1371: + eliminating some of the registers. mgl@1371: + mgl@1371: + The values returned by this function must reflect the behaviour mgl@1371: + of avr32_expand_prologue() and avr32_compute_save_reg_mask(). mgl@1371: + mgl@1371: + The sign of the number returned reflects the direction of stack mgl@1371: + growth, so the values are positive for all eliminations except mgl@1371: + from the soft frame pointer to the hard frame pointer. */ mgl@1371: + mgl@1371: + mgl@1371: +int mgl@1371: +avr32_initial_elimination_offset (int from, int to) mgl@1371: +{ mgl@1371: + int i; mgl@1371: + int call_saved_regs = 0; mgl@1371: + unsigned long saved_reg_mask, saved_fp_reg_mask; mgl@1371: + unsigned int local_vars = get_frame_size (); mgl@1371: + mgl@1371: + saved_reg_mask = avr32_compute_save_reg_mask (TRUE); mgl@1371: + saved_fp_reg_mask = avr32_compute_save_fp_reg_mask (); mgl@1371: + mgl@1371: + for (i = 0; i < 16; ++i) mgl@1371: + { mgl@1371: + if (saved_reg_mask & (1 << i)) mgl@1371: + call_saved_regs += 4; mgl@1371: + } mgl@1371: + mgl@1371: + for (i = 0; i < NUM_FP_REGS; ++i) mgl@1371: + { mgl@1371: + if (saved_fp_reg_mask & (1 << i)) mgl@1371: + call_saved_regs += 4; mgl@1371: + } mgl@1371: + mgl@1371: + switch (from) mgl@1371: + { mgl@1371: + case ARG_POINTER_REGNUM: mgl@1371: + switch (to) mgl@1371: + { mgl@1371: + case STACK_POINTER_REGNUM: mgl@1371: + return call_saved_regs + local_vars; mgl@1371: + case FRAME_POINTER_REGNUM: mgl@1371: + return call_saved_regs; mgl@1371: + default: mgl@1371: + abort (); mgl@1371: + } mgl@1371: + case FRAME_POINTER_REGNUM: mgl@1371: + switch (to) mgl@1371: + { mgl@1371: + case STACK_POINTER_REGNUM: mgl@1371: + return local_vars; mgl@1371: + default: mgl@1371: + abort (); mgl@1371: + } mgl@1371: + default: mgl@1371: + abort (); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Returns a rtx used when passing the next argument to a function. mgl@1371: + avr32_init_cumulative_args() and avr32_function_arg_advance() sets witch mgl@1371: + register to use. mgl@1371: +*/ mgl@1371: +rtx mgl@1371: +avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode, mgl@1371: + tree type, int named) mgl@1371: +{ mgl@1371: + int index = -1; mgl@1371: + mgl@1371: + HOST_WIDE_INT arg_size, arg_rsize; mgl@1371: + if (type) mgl@1371: + { mgl@1371: + arg_size = int_size_in_bytes (type); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + arg_size = GET_MODE_SIZE (mode); mgl@1371: + } mgl@1371: + arg_rsize = PUSH_ROUNDING (arg_size); mgl@1371: + mgl@1371: + /* mgl@1371: + The last time this macro is called, it is called with mode == VOIDmode, mgl@1371: + and its result is passed to the call or call_value pattern as operands 2 mgl@1371: + and 3 respectively. */ mgl@1371: + if (mode == VOIDmode) mgl@1371: + { mgl@1371: + return gen_rtx_CONST_INT (SImode, 22); /* ToDo: fixme. */ mgl@1371: + } mgl@1371: + mgl@1371: + if ((*targetm.calls.must_pass_in_stack) (mode, type) || !named) mgl@1371: + { mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + mgl@1371: + if (arg_rsize == 8) mgl@1371: + { mgl@1371: + /* use r11:r10 or r9:r8. */ mgl@1371: + if (!(GET_USED_INDEX (cum, 1) || GET_USED_INDEX (cum, 2))) mgl@1371: + index = 1; mgl@1371: + else if (!(GET_USED_INDEX (cum, 3) || GET_USED_INDEX (cum, 4))) mgl@1371: + index = 3; mgl@1371: + else mgl@1371: + index = -1; mgl@1371: + } mgl@1371: + else if (arg_rsize == 4) mgl@1371: + { /* Use first available register */ mgl@1371: + index = 0; mgl@1371: + while (index <= LAST_CUM_REG_INDEX && GET_USED_INDEX (cum, index)) mgl@1371: + index++; mgl@1371: + if (index > LAST_CUM_REG_INDEX) mgl@1371: + index = -1; mgl@1371: + } mgl@1371: + mgl@1371: + SET_REG_INDEX (cum, index); mgl@1371: + mgl@1371: + if (GET_REG_INDEX (cum) >= 0) mgl@1371: + return gen_rtx_REG (mode, mgl@1371: + avr32_function_arg_reglist[GET_REG_INDEX (cum)]); mgl@1371: + mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Set the register used for passing the first argument to a function. mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_init_cumulative_args (CUMULATIVE_ARGS * cum, mgl@1371: + tree fntype ATTRIBUTE_UNUSED, mgl@1371: + rtx libname ATTRIBUTE_UNUSED, mgl@1371: + tree fndecl ATTRIBUTE_UNUSED) mgl@1371: + { mgl@1371: + /* Set all registers as unused. */ mgl@1371: + SET_INDEXES_UNUSED (cum); mgl@1371: + mgl@1371: + /* Reset uses_anonymous_args */ mgl@1371: + cum->uses_anonymous_args = 0; mgl@1371: + mgl@1371: + /* Reset size of stack pushed arguments */ mgl@1371: + cum->stack_pushed_args_size = 0; mgl@1371: + } mgl@1371: + mgl@1371: +/* mgl@1371: + Set register used for passing the next argument to a function. Only the mgl@1371: + Scratch Registers are used. mgl@1371: + mgl@1371: + number name mgl@1371: + 15 r15 PC mgl@1371: + 14 r14 LR mgl@1371: + 13 r13 _SP_________ mgl@1371: + FIRST_CUM_REG 12 r12 _||_ mgl@1371: + 10 r11 || mgl@1371: + 11 r10 _||_ Scratch Registers mgl@1371: + 8 r9 || mgl@1371: + LAST_SCRATCH_REG 9 r8 _\/_________ mgl@1371: + 6 r7 /\ mgl@1371: + 7 r6 || mgl@1371: + 4 r5 || mgl@1371: + 5 r4 || mgl@1371: + 2 r3 || mgl@1371: + 3 r2 || mgl@1371: + 0 r1 || mgl@1371: + 1 r0 _||_________ mgl@1371: + mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_function_arg_advance (CUMULATIVE_ARGS * cum, enum machine_mode mode, mgl@1371: + tree type, int named ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + HOST_WIDE_INT arg_size, arg_rsize; mgl@1371: + mgl@1371: + if (type) mgl@1371: + { mgl@1371: + arg_size = int_size_in_bytes (type); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + arg_size = GET_MODE_SIZE (mode); mgl@1371: + } mgl@1371: + arg_rsize = PUSH_ROUNDING (arg_size); mgl@1371: + mgl@1371: + /* It the argument had to be passed in stack, no register is used. */ mgl@1371: + if ((*targetm.calls.must_pass_in_stack) (mode, type)) mgl@1371: + { mgl@1371: + cum->stack_pushed_args_size += PUSH_ROUNDING (int_size_in_bytes (type)); mgl@1371: + return; mgl@1371: + } mgl@1371: + mgl@1371: + /* Mark the used registers as "used". */ mgl@1371: + if (GET_REG_INDEX (cum) >= 0) mgl@1371: + { mgl@1371: + SET_USED_INDEX (cum, GET_REG_INDEX (cum)); mgl@1371: + if (arg_rsize == 8) mgl@1371: + { mgl@1371: + SET_USED_INDEX (cum, (GET_REG_INDEX (cum) + 1)); mgl@1371: + } mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Had to use stack */ mgl@1371: + cum->stack_pushed_args_size += arg_rsize; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Defines witch direction to go to find the next register to use if the mgl@1371: + argument is larger then one register or for arguments shorter than an mgl@1371: + int which is not promoted, such as the last part of structures with mgl@1371: + size not a multiple of 4. */ mgl@1371: +enum direction mgl@1371: +avr32_function_arg_padding (enum machine_mode mode ATTRIBUTE_UNUSED, mgl@1371: + tree type) mgl@1371: +{ mgl@1371: + /* Pad upward for all aggregates except byte and halfword sized aggregates mgl@1371: + which can be passed in registers. */ mgl@1371: + if (type mgl@1371: + && AGGREGATE_TYPE_P (type) mgl@1371: + && (int_size_in_bytes (type) != 1) mgl@1371: + && !((int_size_in_bytes (type) == 2) mgl@1371: + && TYPE_ALIGN_UNIT (type) >= 2) mgl@1371: + && (int_size_in_bytes (type) & 0x3)) mgl@1371: + { mgl@1371: + return upward; mgl@1371: + } mgl@1371: + mgl@1371: + return downward; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Return a rtx used for the return value from a function call. mgl@1371: +*/ mgl@1371: +rtx mgl@1371: +avr32_function_value (tree type, tree func, bool outgoing ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + if (avr32_return_in_memory (type, func)) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + if (int_size_in_bytes (type) <= 4) mgl@1371: + if (avr32_return_in_msb (type)) mgl@1371: + /* Aggregates of size less than a word which does align the data in the mgl@1371: + MSB must use SImode for r12. */ mgl@1371: + return gen_rtx_REG (SImode, RET_REGISTER); mgl@1371: + else mgl@1371: + return gen_rtx_REG (TYPE_MODE (type), RET_REGISTER); mgl@1371: + else if (int_size_in_bytes (type) <= 8) mgl@1371: + return gen_rtx_REG (TYPE_MODE (type), INTERNAL_REGNUM (11)); mgl@1371: + mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Return a rtx used for the return value from a library function call. mgl@1371: +*/ mgl@1371: +rtx mgl@1371: +avr32_libcall_value (enum machine_mode mode) mgl@1371: +{ mgl@1371: + mgl@1371: + if (GET_MODE_SIZE (mode) <= 4) mgl@1371: + return gen_rtx_REG (mode, RET_REGISTER); mgl@1371: + else if (GET_MODE_SIZE (mode) <= 8) mgl@1371: + return gen_rtx_REG (mode, INTERNAL_REGNUM (11)); mgl@1371: + else mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: +/* Return TRUE if X references a SYMBOL_REF. */ mgl@1371: +int mgl@1371: +symbol_mentioned_p (rtx x) mgl@1371: +{ mgl@1371: + const char *fmt; mgl@1371: + int i; mgl@1371: + mgl@1371: + if (GET_CODE (x) == SYMBOL_REF) mgl@1371: + return 1; mgl@1371: + mgl@1371: + fmt = GET_RTX_FORMAT (GET_CODE (x)); mgl@1371: + mgl@1371: + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) mgl@1371: + { mgl@1371: + if (fmt[i] == 'E') mgl@1371: + { mgl@1371: + int j; mgl@1371: + mgl@1371: + for (j = XVECLEN (x, i) - 1; j >= 0; j--) mgl@1371: + if (symbol_mentioned_p (XVECEXP (x, i, j))) mgl@1371: + return 1; mgl@1371: + } mgl@1371: + else if (fmt[i] == 'e' && symbol_mentioned_p (XEXP (x, i))) mgl@1371: + return 1; mgl@1371: + } mgl@1371: + mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: +/* Return TRUE if X references a LABEL_REF. */ mgl@1371: +int mgl@1371: +label_mentioned_p (rtx x) mgl@1371: +{ mgl@1371: + const char *fmt; mgl@1371: + int i; mgl@1371: + mgl@1371: + if (GET_CODE (x) == LABEL_REF) mgl@1371: + return 1; mgl@1371: + mgl@1371: + fmt = GET_RTX_FORMAT (GET_CODE (x)); mgl@1371: + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) mgl@1371: + { mgl@1371: + if (fmt[i] == 'E') mgl@1371: + { mgl@1371: + int j; mgl@1371: + mgl@1371: + for (j = XVECLEN (x, i) - 1; j >= 0; j--) mgl@1371: + if (label_mentioned_p (XVECEXP (x, i, j))) mgl@1371: + return 1; mgl@1371: + } mgl@1371: + else if (fmt[i] == 'e' && label_mentioned_p (XEXP (x, i))) mgl@1371: + return 1; mgl@1371: + } mgl@1371: + mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: +/* Return TRUE if X contains a MEM expression. */ mgl@1371: +int mgl@1371: +mem_mentioned_p (rtx x) mgl@1371: +{ mgl@1371: + const char *fmt; mgl@1371: + int i; mgl@1371: + mgl@1371: + if (MEM_P (x)) mgl@1371: + return 1; mgl@1371: + mgl@1371: + fmt = GET_RTX_FORMAT (GET_CODE (x)); mgl@1371: + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) mgl@1371: + { mgl@1371: + if (fmt[i] == 'E') mgl@1371: + { mgl@1371: + int j; mgl@1371: + mgl@1371: + for (j = XVECLEN (x, i) - 1; j >= 0; j--) mgl@1371: + if (mem_mentioned_p (XVECEXP (x, i, j))) mgl@1371: + return 1; mgl@1371: + } mgl@1371: + else if (fmt[i] == 'e' && mem_mentioned_p (XEXP (x, i))) mgl@1371: + return 1; mgl@1371: + } mgl@1371: + mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_legitimate_pic_operand_p (rtx x) mgl@1371: +{ mgl@1371: + mgl@1371: + /* We can't have const, this must be broken down to a symbol. */ mgl@1371: + if (GET_CODE (x) == CONST) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + /* Can't access symbols or labels via the constant pool either */ mgl@1371: + if ((GET_CODE (x) == SYMBOL_REF mgl@1371: + && CONSTANT_POOL_ADDRESS_P (x) mgl@1371: + && (symbol_mentioned_p (get_pool_constant (x)) mgl@1371: + || label_mentioned_p (get_pool_constant (x))))) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + return TRUE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +rtx mgl@1371: +legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED, mgl@1371: + rtx reg) mgl@1371: +{ mgl@1371: + mgl@1371: + if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) mgl@1371: + { mgl@1371: + int subregs = 0; mgl@1371: + mgl@1371: + if (reg == 0) mgl@1371: + { mgl@1371: + if (no_new_pseudos) mgl@1371: + abort (); mgl@1371: + else mgl@1371: + reg = gen_reg_rtx (Pmode); mgl@1371: + mgl@1371: + subregs = 1; mgl@1371: + } mgl@1371: + mgl@1371: + emit_move_insn (reg, orig); mgl@1371: + mgl@1371: + /* Only set current function as using pic offset table if flag_pic is mgl@1371: + set. This is because this function is also used if mgl@1371: + TARGET_HAS_ASM_ADDR_PSEUDOS is set. */ mgl@1371: + if (flag_pic) mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + mgl@1371: + /* Put a REG_EQUAL note on this insn, so that it can be optimized by mgl@1371: + loop. */ mgl@1371: + return reg; mgl@1371: + } mgl@1371: + else if (GET_CODE (orig) == CONST) mgl@1371: + { mgl@1371: + rtx base, offset; mgl@1371: + mgl@1371: + if (flag_pic mgl@1371: + && GET_CODE (XEXP (orig, 0)) == PLUS mgl@1371: + && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) mgl@1371: + return orig; mgl@1371: + mgl@1371: + if (reg == 0) mgl@1371: + { mgl@1371: + if (no_new_pseudos) mgl@1371: + abort (); mgl@1371: + else mgl@1371: + reg = gen_reg_rtx (Pmode); mgl@1371: + } mgl@1371: + mgl@1371: + if (GET_CODE (XEXP (orig, 0)) == PLUS) mgl@1371: + { mgl@1371: + base = mgl@1371: + legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); mgl@1371: + offset = mgl@1371: + legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, mgl@1371: + base == reg ? 0 : reg); mgl@1371: + } mgl@1371: + else mgl@1371: + abort (); mgl@1371: + mgl@1371: + if (GET_CODE (offset) == CONST_INT) mgl@1371: + { mgl@1371: + /* The base register doesn't really matter, we only want to test mgl@1371: + the index for the appropriate mode. */ mgl@1371: + if (!avr32_const_ok_for_constraint_p (INTVAL (offset), 'I', "Is21")) mgl@1371: + { mgl@1371: + if (!no_new_pseudos) mgl@1371: + offset = force_reg (Pmode, offset); mgl@1371: + else mgl@1371: + abort (); mgl@1371: + } mgl@1371: + mgl@1371: + if (GET_CODE (offset) == CONST_INT) mgl@1371: + return plus_constant (base, INTVAL (offset)); mgl@1371: + } mgl@1371: + mgl@1371: + return gen_rtx_PLUS (Pmode, base, offset); mgl@1371: + } mgl@1371: + mgl@1371: + return orig; mgl@1371: +} mgl@1371: + mgl@1371: +/* Generate code to load the PIC register. */ mgl@1371: +void mgl@1371: +avr32_load_pic_register (void) mgl@1371: +{ mgl@1371: + rtx l1, pic_tmp; mgl@1371: + rtx global_offset_table; mgl@1371: + mgl@1371: + if ((current_function_uses_pic_offset_table == 0) || TARGET_NO_INIT_GOT) mgl@1371: + return; mgl@1371: + mgl@1371: + if (!flag_pic) mgl@1371: + abort (); mgl@1371: + mgl@1371: + l1 = gen_label_rtx (); mgl@1371: + mgl@1371: + global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); mgl@1371: + pic_tmp = mgl@1371: + gen_rtx_CONST (Pmode, mgl@1371: + gen_rtx_MINUS (SImode, gen_rtx_LABEL_REF (Pmode, l1), mgl@1371: + global_offset_table)); mgl@1371: + emit_insn (gen_pic_load_addr mgl@1371: + (pic_offset_table_rtx, force_const_mem (SImode, pic_tmp))); mgl@1371: + emit_insn (gen_pic_compute_got_from_pc (pic_offset_table_rtx, l1)); mgl@1371: + mgl@1371: + /* Need to emit this whether or not we obey regdecls, since setjmp/longjmp mgl@1371: + can cause life info to screw up. */ mgl@1371: + emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx)); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* This hook should return true if values of type type are returned at the most mgl@1371: + significant end of a register (in other words, if they are padded at the mgl@1371: + least significant end). You can assume that type is returned in a register; mgl@1371: + the caller is required to check this. Note that the register provided by mgl@1371: + FUNCTION_VALUE must be able to hold the complete return value. For example, mgl@1371: + if a 1-, 2- or 3-byte structure is returned at the most significant end of a mgl@1371: + 4-byte register, FUNCTION_VALUE should provide an SImode rtx. */ mgl@1371: +bool mgl@1371: +avr32_return_in_msb (tree type ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + /* if ( AGGREGATE_TYPE_P (type) ) if ((int_size_in_bytes(type) == 1) || mgl@1371: + ((int_size_in_bytes(type) == 2) && TYPE_ALIGN_UNIT(type) >= 2)) return mgl@1371: + false; else return true; */ mgl@1371: + mgl@1371: + return false; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Returns one if a certain function value is going to be returned in memory mgl@1371: + and zero if it is going to be returned in a register. mgl@1371: + mgl@1371: + BLKmode and all other modes that is larger than 64 bits are returned in mgl@1371: + memory. mgl@1371: +*/ mgl@1371: +bool mgl@1371: +avr32_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + if (TYPE_MODE (type) == VOIDmode) mgl@1371: + return false; mgl@1371: + mgl@1371: + if (int_size_in_bytes (type) > (2 * UNITS_PER_WORD) mgl@1371: + || int_size_in_bytes (type) == -1) mgl@1371: + { mgl@1371: + return true; mgl@1371: + } mgl@1371: + mgl@1371: + /* If we have an aggregate then use the same mechanism as when checking if mgl@1371: + it should be passed on the stack. */ mgl@1371: + if (type mgl@1371: + && AGGREGATE_TYPE_P (type) mgl@1371: + && (*targetm.calls.must_pass_in_stack) (TYPE_MODE (type), type)) mgl@1371: + return true; mgl@1371: + mgl@1371: + return false; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Output the constant part of the trampoline. mgl@1371: + lddpc r0, pc[0x8:e] ; load static chain register mgl@1371: + lddpc pc, pc[0x8:e] ; jump to subrutine mgl@1371: + .long 0 ; Address to static chain, mgl@1371: + ; filled in by avr32_initialize_trampoline() mgl@1371: + .long 0 ; Address to subrutine, mgl@1371: + ; filled in by avr32_initialize_trampoline() mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_trampoline_template (FILE * file) mgl@1371: +{ mgl@1371: + fprintf (file, "\tlddpc r0, pc[8]\n"); mgl@1371: + fprintf (file, "\tlddpc pc, pc[8]\n"); mgl@1371: + /* make room for the address of the static chain. */ mgl@1371: + fprintf (file, "\t.long\t0\n"); mgl@1371: + /* make room for the address to the subrutine. */ mgl@1371: + fprintf (file, "\t.long\t0\n"); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Initialize the variable parts of a trampoline. mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_initialize_trampoline (rtx addr, rtx fnaddr, rtx static_chain) mgl@1371: +{ mgl@1371: + /* Store the address to the static chain. */ mgl@1371: + emit_move_insn (gen_rtx_MEM mgl@1371: + (SImode, plus_constant (addr, TRAMPOLINE_SIZE - 4)), mgl@1371: + static_chain); mgl@1371: + mgl@1371: + /* Store the address to the function. */ mgl@1371: + emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, TRAMPOLINE_SIZE)), mgl@1371: + fnaddr); mgl@1371: + mgl@1371: + emit_insn (gen_cache (gen_rtx_REG (SImode, 13), mgl@1371: + gen_rtx_CONST_INT (SImode, mgl@1371: + AVR32_CACHE_INVALIDATE_ICACHE))); mgl@1371: +} mgl@1371: + mgl@1371: +/* Return nonzero if X is valid as an addressing register. */ mgl@1371: +int mgl@1371: +avr32_address_register_rtx_p (rtx x, int strict_p) mgl@1371: +{ mgl@1371: + int regno; mgl@1371: + mgl@1371: + if (!register_operand(x, GET_MODE(x))) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* If strict we require the register to be a hard register. */ mgl@1371: + if (strict_p mgl@1371: + && !REG_P(x)) mgl@1371: + return 0; mgl@1371: + mgl@1371: + regno = REGNO (x); mgl@1371: + mgl@1371: + if (strict_p) mgl@1371: + return REGNO_OK_FOR_BASE_P (regno); mgl@1371: + mgl@1371: + return (regno <= LAST_REGNUM || regno >= FIRST_PSEUDO_REGISTER); mgl@1371: +} mgl@1371: + mgl@1371: +/* Return nonzero if INDEX is valid for an address index operand. */ mgl@1371: +int mgl@1371: +avr32_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) mgl@1371: +{ mgl@1371: + enum rtx_code code = GET_CODE (index); mgl@1371: + mgl@1371: + if (GET_MODE_SIZE (mode) > 8) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* Standard coprocessor addressing modes. */ mgl@1371: + if (code == CONST_INT) mgl@1371: + { mgl@1371: + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) mgl@1371: + /* Coprocessor mem insns has a smaller reach than ordinary mem insns */ mgl@1371: + return CONST_OK_FOR_CONSTRAINT_P (INTVAL (index), 'K', "Ku14"); mgl@1371: + else mgl@1371: + return CONST_OK_FOR_CONSTRAINT_P (INTVAL (index), 'K', "Ks16"); mgl@1371: + } mgl@1371: + mgl@1371: + if (avr32_address_register_rtx_p (index, strict_p)) mgl@1371: + return 1; mgl@1371: + mgl@1371: + if (code == MULT) mgl@1371: + { mgl@1371: + rtx xiop0 = XEXP (index, 0); mgl@1371: + rtx xiop1 = XEXP (index, 1); mgl@1371: + return ((avr32_address_register_rtx_p (xiop0, strict_p) mgl@1371: + && power_of_two_operand (xiop1, SImode) mgl@1371: + && (INTVAL (xiop1) <= 8)) mgl@1371: + || (avr32_address_register_rtx_p (xiop1, strict_p) mgl@1371: + && power_of_two_operand (xiop0, SImode) mgl@1371: + && (INTVAL (xiop0) <= 8))); mgl@1371: + } mgl@1371: + else if (code == ASHIFT) mgl@1371: + { mgl@1371: + rtx op = XEXP (index, 1); mgl@1371: + mgl@1371: + return (avr32_address_register_rtx_p (XEXP (index, 0), strict_p) mgl@1371: + && GET_CODE (op) == CONST_INT mgl@1371: + && INTVAL (op) > 0 && INTVAL (op) <= 3); mgl@1371: + } mgl@1371: + mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Used in the GO_IF_LEGITIMATE_ADDRESS macro. Returns a nonzero value if mgl@1371: + the RTX x is a legitimate memory address. mgl@1371: + mgl@1371: + Returns NO_REGS if the address is not legatime, GENERAL_REGS or ALL_REGS mgl@1371: + if it is. mgl@1371: +*/ mgl@1371: + mgl@1371: +/* Forward declaration*/ mgl@1371: +int is_minipool_label (rtx label); mgl@1371: + mgl@1371: +int mgl@1371: +avr32_legitimate_address (enum machine_mode mode, rtx x, int strict) mgl@1371: +{ mgl@1371: + mgl@1371: + switch (GET_CODE (x)) mgl@1371: + { mgl@1371: + case REG: mgl@1371: + return avr32_address_register_rtx_p (x, strict); mgl@1371: + case CONST_INT: mgl@1371: + return ((mode==SImode) mgl@1371: + && CONST_OK_FOR_CONSTRAINT_P(INTVAL(x), 'K', "Ks17")); mgl@1371: + case CONST: mgl@1371: + { mgl@1371: + rtx label = avr32_find_symbol (x); mgl@1371: + if (label mgl@1371: + && mgl@1371: + ((CONSTANT_POOL_ADDRESS_P (label) mgl@1371: + && !(flag_pic mgl@1371: + && (symbol_mentioned_p (get_pool_constant (label)) mgl@1371: + || label_mentioned_p (get_pool_constant (label))))) mgl@1371: + /* TODO! Can this ever happen??? */ mgl@1371: + || ((GET_CODE (label) == LABEL_REF) mgl@1371: + && GET_CODE (XEXP (label, 0)) == CODE_LABEL mgl@1371: + && is_minipool_label (XEXP (label, 0))) mgl@1371: + /*|| ((GET_CODE (label) == SYMBOL_REF) mgl@1371: + && mode == SImode mgl@1371: + && SYMBOL_REF_RMW_ADDR(label))*/)) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + } mgl@1371: + break; mgl@1371: + case LABEL_REF: mgl@1371: + if (GET_CODE (XEXP (x, 0)) == CODE_LABEL mgl@1371: + && is_minipool_label (XEXP (x, 0))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + break; mgl@1371: + case SYMBOL_REF: mgl@1371: + { mgl@1371: + if (CONSTANT_POOL_ADDRESS_P (x) mgl@1371: + && !(flag_pic mgl@1371: + && (symbol_mentioned_p (get_pool_constant (x)) mgl@1371: + || label_mentioned_p (get_pool_constant (x))))) mgl@1371: + return TRUE; mgl@1371: + else if (SYMBOL_REF_RCALL_FUNCTION_P (x) mgl@1371: + || (mode == SImode mgl@1371: + && SYMBOL_REF_RMW_ADDR (x))) mgl@1371: + return TRUE; mgl@1371: + break; mgl@1371: + } mgl@1371: + case PRE_DEC: /* (pre_dec (...)) */ mgl@1371: + case POST_INC: /* (post_inc (...)) */ mgl@1371: + return avr32_address_register_rtx_p (XEXP (x, 0), strict); mgl@1371: + case PLUS: /* (plus (...) (...)) */ mgl@1371: + { mgl@1371: + rtx xop0 = XEXP (x, 0); mgl@1371: + rtx xop1 = XEXP (x, 1); mgl@1371: + mgl@1371: + return ((avr32_address_register_rtx_p (xop0, strict) mgl@1371: + && avr32_legitimate_index_p (mode, xop1, strict)) mgl@1371: + || (avr32_address_register_rtx_p (xop1, strict) mgl@1371: + && avr32_legitimate_index_p (mode, xop0, strict))); mgl@1371: + } mgl@1371: + default: mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +int mgl@1371: +avr32_const_ok_for_move (HOST_WIDE_INT c) mgl@1371: +{ mgl@1371: + if ( TARGET_V2_INSNS ) mgl@1371: + return ( avr32_const_ok_for_constraint_p (c, 'K', "Ks21") mgl@1371: + /* movh instruction */ mgl@1371: + || avr32_hi16_immediate_operand (GEN_INT(c), VOIDmode) ); mgl@1371: + else mgl@1371: + return avr32_const_ok_for_constraint_p (c, 'K', "Ks21"); mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_const_double_immediate (rtx value) mgl@1371: +{ mgl@1371: + HOST_WIDE_INT hi, lo; mgl@1371: + mgl@1371: + if (GET_CODE (value) != CONST_DOUBLE) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + if (SCALAR_FLOAT_MODE_P (GET_MODE (value))) mgl@1371: + { mgl@1371: + HOST_WIDE_INT target_float[2]; mgl@1371: + hi = lo = 0; mgl@1371: + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (value), mgl@1371: + GET_MODE (value)); mgl@1371: + lo = target_float[0]; mgl@1371: + hi = target_float[1]; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + hi = CONST_DOUBLE_HIGH (value); mgl@1371: + lo = CONST_DOUBLE_LOW (value); mgl@1371: + } mgl@1371: + mgl@1371: + if (avr32_const_ok_for_constraint_p (lo, 'K', "Ks21") mgl@1371: + && (GET_MODE (value) == SFmode mgl@1371: + || avr32_const_ok_for_constraint_p (hi, 'K', "Ks21"))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +int mgl@1371: +avr32_legitimate_constant_p (rtx x) mgl@1371: +{ mgl@1371: + switch (GET_CODE (x)) mgl@1371: + { mgl@1371: + case CONST_INT: mgl@1371: + /* Check if we should put large immediate into constant pool mgl@1371: + or load them directly with mov/orh.*/ mgl@1371: + if (!avr32_imm_in_const_pool) mgl@1371: + return 1; mgl@1371: + mgl@1371: + return avr32_const_ok_for_move (INTVAL (x)); mgl@1371: + case CONST_DOUBLE: mgl@1371: + /* Check if we should put large immediate into constant pool mgl@1371: + or load them directly with mov/orh.*/ mgl@1371: + if (!avr32_imm_in_const_pool) mgl@1371: + return 1; mgl@1371: + mgl@1371: + if (GET_MODE (x) == SFmode mgl@1371: + || GET_MODE (x) == DFmode || GET_MODE (x) == DImode) mgl@1371: + return avr32_const_double_immediate (x); mgl@1371: + else mgl@1371: + return 0; mgl@1371: + case LABEL_REF: mgl@1371: + case SYMBOL_REF: mgl@1371: + return avr32_find_symbol (x) && (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS); mgl@1371: + case CONST: mgl@1371: + case HIGH: mgl@1371: + case CONST_VECTOR: mgl@1371: + return 0; mgl@1371: + default: mgl@1371: + printf ("%s():\n", __FUNCTION__); mgl@1371: + debug_rtx (x); mgl@1371: + return 1; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Strip any special encoding from labels */ mgl@1371: +const char * mgl@1371: +avr32_strip_name_encoding (const char *name) mgl@1371: +{ mgl@1371: + const char *stripped = name; mgl@1371: + mgl@1371: + while (1) mgl@1371: + { mgl@1371: + switch (stripped[0]) mgl@1371: + { mgl@1371: + case '#': mgl@1371: + stripped = strchr (name + 1, '#') + 1; mgl@1371: + break; mgl@1371: + case '*': mgl@1371: + stripped = &stripped[1]; mgl@1371: + break; mgl@1371: + default: mgl@1371: + return stripped; mgl@1371: + } mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* Do anything needed before RTL is emitted for each function. */ mgl@1371: +static struct machine_function * mgl@1371: +avr32_init_machine_status (void) mgl@1371: +{ mgl@1371: + struct machine_function *machine; mgl@1371: + machine = mgl@1371: + (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); mgl@1371: + mgl@1371: +#if AVR32_FT_UNKNOWN != 0 mgl@1371: + machine->func_type = AVR32_FT_UNKNOWN; mgl@1371: +#endif mgl@1371: + mgl@1371: + machine->minipool_label_head = 0; mgl@1371: + machine->minipool_label_tail = 0; mgl@1371: + machine->ifcvt_after_reload = 0; mgl@1371: + return machine; mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_init_expanders (void) mgl@1371: +{ mgl@1371: + /* Arrange to initialize and mark the machine per-function status. */ mgl@1371: + init_machine_status = avr32_init_machine_status; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Return an RTX indicating where the return address to the mgl@1371: + calling function can be found. */ mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + if (count != 0) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + return get_hard_reg_initial_val (Pmode, LR_REGNUM); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +void mgl@1371: +avr32_encode_section_info (tree decl, rtx rtl, int first) mgl@1371: +{ mgl@1371: + default_encode_section_info(decl, rtl, first); mgl@1371: + mgl@1371: + if ( TREE_CODE (decl) == VAR_DECL mgl@1371: + && (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF) mgl@1371: + && (lookup_attribute ("rmw_addressable", DECL_ATTRIBUTES (decl)) mgl@1371: + || TARGET_RMW_ADDRESSABLE_DATA) ){ mgl@1371: + if ( !TARGET_RMW || flag_pic ) mgl@1371: + return; mgl@1371: + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_asm_output_label (FILE * stream, const char *name) mgl@1371: +{ mgl@1371: + name = avr32_strip_name_encoding (name); mgl@1371: + mgl@1371: + /* Print the label. */ mgl@1371: + assemble_name (stream, name); mgl@1371: + fprintf (stream, ":\n"); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +void mgl@1371: +avr32_asm_weaken_label (FILE * stream, const char *name) mgl@1371: +{ mgl@1371: + fprintf (stream, "\t.weak "); mgl@1371: + assemble_name (stream, name); mgl@1371: + fprintf (stream, "\n"); mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Checks if a labelref is equal to a reserved word in the assembler. If it is, mgl@1371: + insert a '_' before the label name. mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_asm_output_labelref (FILE * stream, const char *name) mgl@1371: +{ mgl@1371: + int verbatim = FALSE; mgl@1371: + const char *stripped = name; mgl@1371: + int strip_finished = FALSE; mgl@1371: + mgl@1371: + while (!strip_finished) mgl@1371: + { mgl@1371: + switch (stripped[0]) mgl@1371: + { mgl@1371: + case '#': mgl@1371: + stripped = strchr (name + 1, '#') + 1; mgl@1371: + break; mgl@1371: + case '*': mgl@1371: + stripped = &stripped[1]; mgl@1371: + verbatim = TRUE; mgl@1371: + break; mgl@1371: + default: mgl@1371: + strip_finished = TRUE; mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (verbatim) mgl@1371: + fputs (stripped, stream); mgl@1371: + else mgl@1371: + asm_fprintf (stream, "%U%s", stripped); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Check if the comparison in compare_exp is redundant mgl@1371: + for the condition given in next_cond given that the mgl@1371: + needed flags are already set by an earlier instruction. mgl@1371: + Uses cc_prev_status to check this. mgl@1371: + mgl@1371: + Returns NULL_RTX if the compare is not redundant mgl@1371: + or the new condition to use in the conditional mgl@1371: + instruction if the compare is redundant. mgl@1371: +*/ mgl@1371: +static rtx mgl@1371: +is_compare_redundant (rtx compare_exp, rtx next_cond) mgl@1371: +{ mgl@1371: + int z_flag_valid = FALSE; mgl@1371: + int n_flag_valid = FALSE; mgl@1371: + rtx new_cond; mgl@1371: + mgl@1371: + if (GET_CODE (compare_exp) != COMPARE mgl@1371: + && GET_CODE (compare_exp) != AND) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + mgl@1371: + if (rtx_equal_p (cc_prev_status.mdep.value, compare_exp)) mgl@1371: + { mgl@1371: + /* cc0 already contains the correct comparison -> delete cmp insn */ mgl@1371: + return next_cond; mgl@1371: + } mgl@1371: + mgl@1371: + if (GET_MODE (compare_exp) != SImode) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + switch (cc_prev_status.mdep.flags) mgl@1371: + { mgl@1371: + case CC_SET_VNCZ: mgl@1371: + case CC_SET_NCZ: mgl@1371: + n_flag_valid = TRUE; mgl@1371: + case CC_SET_CZ: mgl@1371: + case CC_SET_Z: mgl@1371: + z_flag_valid = TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + if (cc_prev_status.mdep.value mgl@1371: + && GET_CODE (compare_exp) == COMPARE mgl@1371: + && REG_P (XEXP (compare_exp, 0)) mgl@1371: + && REGNO (XEXP (compare_exp, 0)) == REGNO (cc_prev_status.mdep.value) mgl@1371: + && GET_CODE (XEXP (compare_exp, 1)) == CONST_INT mgl@1371: + && next_cond != NULL_RTX) mgl@1371: + { mgl@1371: + if (INTVAL (XEXP (compare_exp, 1)) == 0 mgl@1371: + && z_flag_valid mgl@1371: + && (GET_CODE (next_cond) == EQ || GET_CODE (next_cond) == NE)) mgl@1371: + /* We can skip comparison Z flag is already reflecting ops[0] */ mgl@1371: + return next_cond; mgl@1371: + else if (n_flag_valid mgl@1371: + && ((INTVAL (XEXP (compare_exp, 1)) == 0 mgl@1371: + && (GET_CODE (next_cond) == GE mgl@1371: + || GET_CODE (next_cond) == LT)) mgl@1371: + || (INTVAL (XEXP (compare_exp, 1)) == -1 mgl@1371: + && (GET_CODE (next_cond) == GT mgl@1371: + || GET_CODE (next_cond) == LE)))) mgl@1371: + { mgl@1371: + /* We can skip comparison N flag is already reflecting ops[0], mgl@1371: + which means that we can use the mi/pl conditions to check if mgl@1371: + ops[0] is GE or LT 0. */ mgl@1371: + if ((GET_CODE (next_cond) == GE) || (GET_CODE (next_cond) == GT)) mgl@1371: + new_cond = mgl@1371: + gen_rtx_UNSPEC (GET_MODE (next_cond), gen_rtvec (2, cc0_rtx, const0_rtx), mgl@1371: + UNSPEC_COND_PL); mgl@1371: + else mgl@1371: + new_cond = mgl@1371: + gen_rtx_UNSPEC (GET_MODE (next_cond), gen_rtvec (2, cc0_rtx, const0_rtx), mgl@1371: + UNSPEC_COND_MI); mgl@1371: + return new_cond; mgl@1371: + } mgl@1371: + } mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: +/* Updates cc_status. */ mgl@1371: +void mgl@1371: +avr32_notice_update_cc (rtx exp, rtx insn) mgl@1371: +{ mgl@1371: + enum attr_cc attr_cc = get_attr_cc (insn); mgl@1371: + mgl@1371: + if ( attr_cc == CC_SET_Z_IF_NOT_V2 ) mgl@1371: + if (TARGET_V2_INSNS) mgl@1371: + attr_cc = CC_NONE; mgl@1371: + else mgl@1371: + attr_cc = CC_SET_Z; mgl@1371: + mgl@1371: + switch (attr_cc) mgl@1371: + { mgl@1371: + case CC_CALL_SET: mgl@1371: + CC_STATUS_INIT; mgl@1371: + FPCC_STATUS_INIT; mgl@1371: + /* Check if the function call returns a value in r12 */ mgl@1371: + if (REG_P (recog_data.operand[0]) mgl@1371: + && REGNO (recog_data.operand[0]) == RETVAL_REGNUM) mgl@1371: + { mgl@1371: + cc_status.flags = 0; mgl@1371: + cc_status.mdep.value = mgl@1371: + gen_rtx_COMPARE (SImode, recog_data.operand[0], const0_rtx); mgl@1371: + cc_status.mdep.flags = CC_SET_VNCZ; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + mgl@1371: + } mgl@1371: + break; mgl@1371: + case CC_COMPARE: mgl@1371: + { mgl@1371: + /* Check that compare will not be optimized away if so nothing should mgl@1371: + be done */ mgl@1371: + rtx compare_exp = SET_SRC (exp); mgl@1371: + /* Check if we have a tst expression. If so convert it to a mgl@1371: + compare with 0. */ mgl@1371: + if ( REG_P (SET_SRC (exp)) ) mgl@1371: + compare_exp = gen_rtx_COMPARE (GET_MODE (SET_SRC (exp)), mgl@1371: + SET_SRC (exp), mgl@1371: + const0_rtx); mgl@1371: + mgl@1371: + if (is_compare_redundant (compare_exp, get_next_insn_cond (insn)) == mgl@1371: + NULL_RTX) mgl@1371: + { mgl@1371: + mgl@1371: + /* Reset the nonstandard flag */ mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.flags = 0; mgl@1371: + cc_status.mdep.value = compare_exp; mgl@1371: + cc_status.mdep.flags = CC_SET_VNCZ; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + } mgl@1371: + } mgl@1371: + break; mgl@1371: + case CC_CMP_COND_INSN: mgl@1371: + { mgl@1371: + /* Conditional insn that emit the compare itself. */ mgl@1371: + rtx cmp; mgl@1371: + rtx cmp_op0, cmp_op1; mgl@1371: + rtx cond; mgl@1371: + rtx dest; mgl@1371: + rtx next_insn = next_nonnote_insn (insn); mgl@1371: + mgl@1371: + if ( GET_CODE (exp) == COND_EXEC ) mgl@1371: + { mgl@1371: + cmp_op0 = XEXP (COND_EXEC_TEST (exp), 0); mgl@1371: + cmp_op1 = XEXP (COND_EXEC_TEST (exp), 1); mgl@1371: + cond = COND_EXEC_TEST (exp); mgl@1371: + dest = SET_DEST (COND_EXEC_CODE (exp)); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* If then else conditional. compare operands are in operands mgl@1371: + 4 and 5. */ mgl@1371: + cmp_op0 = recog_data.operand[4]; mgl@1371: + cmp_op1 = recog_data.operand[5]; mgl@1371: + cond = recog_data.operand[1]; mgl@1371: + dest = SET_DEST (exp); mgl@1371: + } mgl@1371: + mgl@1371: + if ( GET_CODE (cmp_op0) == AND ) mgl@1371: + cmp = cmp_op0; mgl@1371: + else mgl@1371: + cmp = gen_rtx_COMPARE (GET_MODE (cmp_op0), mgl@1371: + cmp_op0, mgl@1371: + cmp_op1); mgl@1371: + mgl@1371: + /* Check if the conditional insns updates a register present mgl@1371: + in the comparison, if so then we must reset the cc_status. */ mgl@1371: + if (REG_P (dest) mgl@1371: + && (reg_mentioned_p (dest, cmp_op0) mgl@1371: + || reg_mentioned_p (dest, cmp_op1)) mgl@1371: + && GET_CODE (exp) != COND_EXEC ) mgl@1371: + { mgl@1371: + CC_STATUS_INIT; mgl@1371: + } mgl@1371: + else if (is_compare_redundant (cmp, cond) == NULL_RTX) mgl@1371: + { mgl@1371: + /* Reset the nonstandard flag */ mgl@1371: + CC_STATUS_INIT; mgl@1371: + if ( GET_CODE (cmp_op0) == AND ) mgl@1371: + { mgl@1371: + cc_status.flags = CC_INVERTED; mgl@1371: + cc_status.mdep.flags = CC_SET_Z; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + cc_status.flags = 0; mgl@1371: + cc_status.mdep.flags = CC_SET_VNCZ; mgl@1371: + } mgl@1371: + cc_status.mdep.value = cmp; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + /* Check if we have a COND_EXEC insn which updates one mgl@1371: + of the registers in the compare status. */ mgl@1371: + if (REG_P (dest) mgl@1371: + && (reg_mentioned_p (dest, cmp_op0) mgl@1371: + || reg_mentioned_p (dest, cmp_op1)) mgl@1371: + && GET_CODE (exp) == COND_EXEC ) mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 1; mgl@1371: + mgl@1371: + if ( cc_status.mdep.cond_exec_cmp_clobbered mgl@1371: + && GET_CODE (exp) == COND_EXEC mgl@1371: + && next_insn != NULL mgl@1371: + && INSN_P (next_insn) mgl@1371: + && !(GET_CODE (PATTERN (next_insn)) == COND_EXEC mgl@1371: + && rtx_equal_p (XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 0), cmp_op0) mgl@1371: + && rtx_equal_p (XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 1), cmp_op1) mgl@1371: + && (GET_CODE (COND_EXEC_TEST (PATTERN (next_insn))) == GET_CODE (cond) mgl@1371: + || GET_CODE (COND_EXEC_TEST (PATTERN (next_insn))) == reverse_condition (GET_CODE (cond)))) ) mgl@1371: + { mgl@1371: + /* We have a sequence of conditional insns where the compare status has been clobbered mgl@1371: + since the compare no longer reflects the content of the values to compare. */ mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 1; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + break; mgl@1371: + case CC_FPCOMPARE: mgl@1371: + /* Check that floating-point compare will not be optimized away if so mgl@1371: + nothing should be done */ mgl@1371: + if (!rtx_equal_p (cc_prev_status.mdep.fpvalue, SET_SRC (exp))) mgl@1371: + { mgl@1371: + /* cc0 already contains the correct comparison -> delete cmp insn */ mgl@1371: + /* Reset the nonstandard flag */ mgl@1371: + cc_status.mdep.fpvalue = SET_SRC (exp); mgl@1371: + cc_status.mdep.fpflags = CC_SET_CZ; mgl@1371: + } mgl@1371: + break; mgl@1371: + case CC_FROM_FPCC: mgl@1371: + /* Flags are updated with flags from Floating-point coprocessor, set mgl@1371: + CC_NOT_SIGNED flag since the flags are set so that unsigned mgl@1371: + condidion codes can be used directly. */ mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.flags = CC_NOT_SIGNED; mgl@1371: + cc_status.mdep.value = cc_status.mdep.fpvalue; mgl@1371: + cc_status.mdep.flags = cc_status.mdep.fpflags; mgl@1371: + break; mgl@1371: + case CC_BLD: mgl@1371: + /* Bit load is kind of like an inverted testsi, because the Z flag is mgl@1371: + inverted */ mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.flags = CC_INVERTED; mgl@1371: + cc_status.mdep.value = SET_SRC (exp); mgl@1371: + cc_status.mdep.flags = CC_SET_Z; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + break; mgl@1371: + case CC_NONE: mgl@1371: + /* Insn does not affect CC at all. Check if the instruction updates mgl@1371: + some of the register currently reflected in cc0 */ mgl@1371: + mgl@1371: + if ((GET_CODE (exp) == SET) mgl@1371: + && (cc_status.value1 || cc_status.value2 || cc_status.mdep.value) mgl@1371: + && (reg_mentioned_p (SET_DEST (exp), cc_status.value1) mgl@1371: + || reg_mentioned_p (SET_DEST (exp), cc_status.value2) mgl@1371: + || reg_mentioned_p (SET_DEST (exp), cc_status.mdep.value))) mgl@1371: + { mgl@1371: + CC_STATUS_INIT; mgl@1371: + } mgl@1371: + mgl@1371: + /* If this is a parallel we must step through each of the parallel mgl@1371: + expressions */ mgl@1371: + if (GET_CODE (exp) == PARALLEL) mgl@1371: + { mgl@1371: + int i; mgl@1371: + for (i = 0; i < XVECLEN (exp, 0); ++i) mgl@1371: + { mgl@1371: + rtx vec_exp = XVECEXP (exp, 0, i); mgl@1371: + if ((GET_CODE (vec_exp) == SET) mgl@1371: + && (cc_status.value1 || cc_status.value2 mgl@1371: + || cc_status.mdep.value) mgl@1371: + && (reg_mentioned_p (SET_DEST (vec_exp), cc_status.value1) mgl@1371: + || reg_mentioned_p (SET_DEST (vec_exp), mgl@1371: + cc_status.value2) mgl@1371: + || reg_mentioned_p (SET_DEST (vec_exp), mgl@1371: + cc_status.mdep.value))) mgl@1371: + { mgl@1371: + CC_STATUS_INIT; mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if we have memory opartions with post_inc or pre_dec on the mgl@1371: + register currently reflected in cc0 */ mgl@1371: + if (GET_CODE (exp) == SET mgl@1371: + && GET_CODE (SET_SRC (exp)) == MEM mgl@1371: + && (GET_CODE (XEXP (SET_SRC (exp), 0)) == POST_INC mgl@1371: + || GET_CODE (XEXP (SET_SRC (exp), 0)) == PRE_DEC) mgl@1371: + && mgl@1371: + (reg_mentioned_p mgl@1371: + (XEXP (XEXP (SET_SRC (exp), 0), 0), cc_status.value1) mgl@1371: + || reg_mentioned_p (XEXP (XEXP (SET_SRC (exp), 0), 0), mgl@1371: + cc_status.value2) mgl@1371: + || reg_mentioned_p (XEXP (XEXP (SET_SRC (exp), 0), 0), mgl@1371: + cc_status.mdep.value))) mgl@1371: + CC_STATUS_INIT; mgl@1371: + mgl@1371: + if (GET_CODE (exp) == SET mgl@1371: + && GET_CODE (SET_DEST (exp)) == MEM mgl@1371: + && (GET_CODE (XEXP (SET_DEST (exp), 0)) == POST_INC mgl@1371: + || GET_CODE (XEXP (SET_DEST (exp), 0)) == PRE_DEC) mgl@1371: + && mgl@1371: + (reg_mentioned_p mgl@1371: + (XEXP (XEXP (SET_DEST (exp), 0), 0), cc_status.value1) mgl@1371: + || reg_mentioned_p (XEXP (XEXP (SET_DEST (exp), 0), 0), mgl@1371: + cc_status.value2) mgl@1371: + || reg_mentioned_p (XEXP (XEXP (SET_DEST (exp), 0), 0), mgl@1371: + cc_status.mdep.value))) mgl@1371: + CC_STATUS_INIT; mgl@1371: + break; mgl@1371: + mgl@1371: + case CC_SET_VNCZ: mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.mdep.value = recog_data.operand[0]; mgl@1371: + cc_status.mdep.flags = CC_SET_VNCZ; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + break; mgl@1371: + mgl@1371: + case CC_SET_NCZ: mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.mdep.value = recog_data.operand[0]; mgl@1371: + cc_status.mdep.flags = CC_SET_NCZ; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + break; mgl@1371: + mgl@1371: + case CC_SET_CZ: mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.mdep.value = recog_data.operand[0]; mgl@1371: + cc_status.mdep.flags = CC_SET_CZ; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + break; mgl@1371: + mgl@1371: + case CC_SET_Z: mgl@1371: + CC_STATUS_INIT; mgl@1371: + cc_status.mdep.value = recog_data.operand[0]; mgl@1371: + cc_status.mdep.flags = CC_SET_Z; mgl@1371: + cc_status.mdep.cond_exec_cmp_clobbered = 0; mgl@1371: + break; mgl@1371: + mgl@1371: + case CC_CLOBBER: mgl@1371: + CC_STATUS_INIT; mgl@1371: + break; mgl@1371: + mgl@1371: + default: mgl@1371: + CC_STATUS_INIT; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Outputs to stdio stream stream the assembler syntax for an instruction mgl@1371: + operand x. x is an RTL expression. mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_print_operand (FILE * stream, rtx x, int code) mgl@1371: +{ mgl@1371: + int error = 0; mgl@1371: + mgl@1371: + if ( code == '?' ) mgl@1371: + { mgl@1371: + /* Predicable instruction, print condition code */ mgl@1371: + mgl@1371: + /* If the insn should not be conditional then do nothing. */ mgl@1371: + if ( current_insn_predicate == NULL_RTX ) mgl@1371: + return; mgl@1371: + mgl@1371: + /* Set x to the predicate to force printing mgl@1371: + the condition later on. */ mgl@1371: + x = current_insn_predicate; mgl@1371: + mgl@1371: + /* Reverse condition if useing bld insn. */ mgl@1371: + if ( GET_CODE (XEXP(current_insn_predicate,0)) == AND ) mgl@1371: + x = reversed_condition (current_insn_predicate); mgl@1371: + } mgl@1371: + else if ( code == '!' ) mgl@1371: + { mgl@1371: + /* Output compare for conditional insn if needed. */ mgl@1371: + rtx new_cond; mgl@1371: + gcc_assert ( current_insn_predicate != NULL_RTX ); mgl@1371: + new_cond = avr32_output_cmp(current_insn_predicate, mgl@1371: + GET_MODE(XEXP(current_insn_predicate,0)), mgl@1371: + XEXP(current_insn_predicate,0), mgl@1371: + XEXP(current_insn_predicate,1)); mgl@1371: + mgl@1371: + /* Check if the new condition is a special avr32 condition mgl@1371: + specified using UNSPECs. If so we must handle it differently. */ mgl@1371: + if ( GET_CODE (new_cond) == UNSPEC ) mgl@1371: + { mgl@1371: + current_insn_predicate = mgl@1371: + gen_rtx_UNSPEC (CCmode, mgl@1371: + gen_rtvec (2, mgl@1371: + XEXP(current_insn_predicate,0), mgl@1371: + XEXP(current_insn_predicate,1)), mgl@1371: + XINT (new_cond, 1)); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + PUT_CODE(current_insn_predicate, GET_CODE(new_cond)); mgl@1371: + } mgl@1371: + return; mgl@1371: + } mgl@1371: + mgl@1371: + switch (GET_CODE (x)) mgl@1371: + { mgl@1371: + case UNSPEC: mgl@1371: + switch (XINT (x, 1)) mgl@1371: + { mgl@1371: + case UNSPEC_COND_PL: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("mi", stream); mgl@1371: + else mgl@1371: + fputs ("pl", stream); mgl@1371: + break; mgl@1371: + case UNSPEC_COND_MI: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("pl", stream); mgl@1371: + else mgl@1371: + fputs ("mi", stream); mgl@1371: + break; mgl@1371: + default: mgl@1371: + error = 1; mgl@1371: + } mgl@1371: + break; mgl@1371: + case EQ: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("ne", stream); mgl@1371: + else mgl@1371: + fputs ("eq", stream); mgl@1371: + break; mgl@1371: + case NE: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("eq", stream); mgl@1371: + else mgl@1371: + fputs ("ne", stream); mgl@1371: + break; mgl@1371: + case GT: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("le", stream); mgl@1371: + else mgl@1371: + fputs ("gt", stream); mgl@1371: + break; mgl@1371: + case GTU: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("ls", stream); mgl@1371: + else mgl@1371: + fputs ("hi", stream); mgl@1371: + break; mgl@1371: + case LT: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("ge", stream); mgl@1371: + else mgl@1371: + fputs ("lt", stream); mgl@1371: + break; mgl@1371: + case LTU: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("hs", stream); mgl@1371: + else mgl@1371: + fputs ("lo", stream); mgl@1371: + break; mgl@1371: + case GE: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("lt", stream); mgl@1371: + else mgl@1371: + fputs ("ge", stream); mgl@1371: + break; mgl@1371: + case GEU: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("lo", stream); mgl@1371: + else mgl@1371: + fputs ("hs", stream); mgl@1371: + break; mgl@1371: + case LE: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("gt", stream); mgl@1371: + else mgl@1371: + fputs ("le", stream); mgl@1371: + break; mgl@1371: + case LEU: mgl@1371: + if (code == 'i') mgl@1371: + fputs ("hi", stream); mgl@1371: + else mgl@1371: + fputs ("ls", stream); mgl@1371: + break; mgl@1371: + case CONST_INT: mgl@1371: + { mgl@1371: + HOST_WIDE_INT value = INTVAL (x); mgl@1371: + mgl@1371: + switch (code) mgl@1371: + { mgl@1371: + case 'm': mgl@1371: + if ( HOST_BITS_PER_WIDE_INT > BITS_PER_WORD ) mgl@1371: + { mgl@1371: + /* A const_int can be used to represent DImode constants. */ mgl@1371: + value >>= BITS_PER_WORD; mgl@1371: + } mgl@1371: + /* We might get a const_int immediate for setting a DI register, mgl@1371: + we then must then return the correct sign extended DI. The most mgl@1371: + significant word is just a sign extension. */ mgl@1371: + else if (value < 0) mgl@1371: + value = -1; mgl@1371: + else mgl@1371: + value = 0; mgl@1371: + break; mgl@1371: + case 'i': mgl@1371: + value++; mgl@1371: + break; mgl@1371: + case 'p': mgl@1371: + { mgl@1371: + /* Set to bit position of first bit set in immediate */ mgl@1371: + int i, bitpos = 32; mgl@1371: + for (i = 0; i < 32; i++) mgl@1371: + if (value & (1 << i)) mgl@1371: + { mgl@1371: + bitpos = i; mgl@1371: + break; mgl@1371: + } mgl@1371: + value = bitpos; mgl@1371: + } mgl@1371: + break; mgl@1371: + case 'z': mgl@1371: + { mgl@1371: + /* Set to bit position of first bit cleared in immediate */ mgl@1371: + int i, bitpos = 32; mgl@1371: + for (i = 0; i < 32; i++) mgl@1371: + if (!(value & (1 << i))) mgl@1371: + { mgl@1371: + bitpos = i; mgl@1371: + break; mgl@1371: + } mgl@1371: + value = bitpos; mgl@1371: + } mgl@1371: + break; mgl@1371: + case 'r': mgl@1371: + { mgl@1371: + /* Reglist 8 */ mgl@1371: + char op[50]; mgl@1371: + op[0] = '\0'; mgl@1371: + mgl@1371: + if (value & 0x01) mgl@1371: + sprintf (op, "r0-r3"); mgl@1371: + if (value & 0x02) mgl@1371: + strlen (op) ? sprintf (op, "%s, r4-r7", op) : sprintf (op, mgl@1371: + "r4-r7"); mgl@1371: + if (value & 0x04) mgl@1371: + strlen (op) ? sprintf (op, "%s, r8-r9", op) : sprintf (op, mgl@1371: + "r8-r9"); mgl@1371: + if (value & 0x08) mgl@1371: + strlen (op) ? sprintf (op, "%s, r10", op) : sprintf (op, mgl@1371: + "r10"); mgl@1371: + if (value & 0x10) mgl@1371: + strlen (op) ? sprintf (op, "%s, r11", op) : sprintf (op, mgl@1371: + "r11"); mgl@1371: + if (value & 0x20) mgl@1371: + strlen (op) ? sprintf (op, "%s, r12", op) : sprintf (op, mgl@1371: + "r12"); mgl@1371: + if (value & 0x40) mgl@1371: + strlen (op) ? sprintf (op, "%s, lr", op) : sprintf (op, "lr"); mgl@1371: + if (value & 0x80) mgl@1371: + strlen (op) ? sprintf (op, "%s, pc", op) : sprintf (op, "pc"); mgl@1371: + mgl@1371: + fputs (op, stream); mgl@1371: + return; mgl@1371: + } mgl@1371: + case 's': mgl@1371: + { mgl@1371: + /* Reglist 16 */ mgl@1371: + char reglist16_string[100]; mgl@1371: + int i; mgl@1371: + reglist16_string[0] = '\0'; mgl@1371: + mgl@1371: + for (i = 0; i < 16; ++i) mgl@1371: + { mgl@1371: + if (value & (1 << i)) mgl@1371: + { mgl@1371: + strlen (reglist16_string) ? sprintf (reglist16_string, mgl@1371: + "%s, %s", mgl@1371: + reglist16_string, mgl@1371: + reg_names mgl@1371: + [INTERNAL_REGNUM mgl@1371: + (i)]) : mgl@1371: + sprintf (reglist16_string, "%s", mgl@1371: + reg_names[INTERNAL_REGNUM (i)]); mgl@1371: + } mgl@1371: + } mgl@1371: + fputs (reglist16_string, stream); mgl@1371: + return; mgl@1371: + } mgl@1371: + case 'C': mgl@1371: + { mgl@1371: + /* RegListCP8 */ mgl@1371: + char reglist_string[100]; mgl@1371: + avr32_make_fp_reglist_w (value, (char *) reglist_string); mgl@1371: + fputs (reglist_string, stream); mgl@1371: + return; mgl@1371: + } mgl@1371: + case 'D': mgl@1371: + { mgl@1371: + /* RegListCPD8 */ mgl@1371: + char reglist_string[100]; mgl@1371: + avr32_make_fp_reglist_d (value, (char *) reglist_string); mgl@1371: + fputs (reglist_string, stream); mgl@1371: + return; mgl@1371: + } mgl@1371: + case 'h': mgl@1371: + /* Print halfword part of word */ mgl@1371: + fputs (value ? "b" : "t", stream); mgl@1371: + return; mgl@1371: + } mgl@1371: + mgl@1371: + /* Print Value */ mgl@1371: + fprintf (stream, "%d", value); mgl@1371: + break; mgl@1371: + } mgl@1371: + case CONST_DOUBLE: mgl@1371: + { mgl@1371: + HOST_WIDE_INT hi, lo; mgl@1371: + if (SCALAR_FLOAT_MODE_P (GET_MODE (x))) mgl@1371: + { mgl@1371: + HOST_WIDE_INT target_float[2]; mgl@1371: + hi = lo = 0; mgl@1371: + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (x), mgl@1371: + GET_MODE (x)); mgl@1371: + /* For doubles the most significant part starts at index 0. */ mgl@1371: + if (GET_MODE_SIZE (GET_MODE (x)) > UNITS_PER_WORD) mgl@1371: + { mgl@1371: + hi = target_float[0]; mgl@1371: + lo = target_float[1]; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + lo = target_float[0]; mgl@1371: + } mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + hi = CONST_DOUBLE_HIGH (x); mgl@1371: + lo = CONST_DOUBLE_LOW (x); mgl@1371: + } mgl@1371: + mgl@1371: + if (code == 'm') mgl@1371: + fprintf (stream, "%ld", hi); mgl@1371: + else mgl@1371: + fprintf (stream, "%ld", lo); mgl@1371: + mgl@1371: + break; mgl@1371: + } mgl@1371: + case CONST: mgl@1371: + output_addr_const (stream, XEXP (XEXP (x, 0), 0)); mgl@1371: + fprintf (stream, "+%ld", INTVAL (XEXP (XEXP (x, 0), 1))); mgl@1371: + break; mgl@1371: + case REG: mgl@1371: + /* Swap register name if the register is DImode or DFmode. */ mgl@1371: + if (GET_MODE (x) == DImode || GET_MODE (x) == DFmode) mgl@1371: + { mgl@1371: + /* Double register must have an even numbered address */ mgl@1371: + gcc_assert (!(REGNO (x) % 2)); mgl@1371: + if (code == 'm') mgl@1371: + fputs (reg_names[true_regnum (x)], stream); mgl@1371: + else mgl@1371: + fputs (reg_names[true_regnum (x) + 1], stream); mgl@1371: + } mgl@1371: + else if (GET_MODE (x) == TImode) mgl@1371: + { mgl@1371: + switch (code) mgl@1371: + { mgl@1371: + case 'T': mgl@1371: + fputs (reg_names[true_regnum (x)], stream); mgl@1371: + break; mgl@1371: + case 'U': mgl@1371: + fputs (reg_names[true_regnum (x) + 1], stream); mgl@1371: + break; mgl@1371: + case 'L': mgl@1371: + fputs (reg_names[true_regnum (x) + 2], stream); mgl@1371: + break; mgl@1371: + case 'B': mgl@1371: + fputs (reg_names[true_regnum (x) + 3], stream); mgl@1371: + break; mgl@1371: + default: mgl@1371: + fprintf (stream, "%s, %s, %s, %s", mgl@1371: + reg_names[true_regnum (x) + 3], mgl@1371: + reg_names[true_regnum (x) + 2], mgl@1371: + reg_names[true_regnum (x) + 1], mgl@1371: + reg_names[true_regnum (x)]); mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + fputs (reg_names[true_regnum (x)], stream); mgl@1371: + } mgl@1371: + break; mgl@1371: + case CODE_LABEL: mgl@1371: + case LABEL_REF: mgl@1371: + case SYMBOL_REF: mgl@1371: + output_addr_const (stream, x); mgl@1371: + break; mgl@1371: + case MEM: mgl@1371: + switch (GET_CODE (XEXP (x, 0))) mgl@1371: + { mgl@1371: + case LABEL_REF: mgl@1371: + case SYMBOL_REF: mgl@1371: + output_addr_const (stream, XEXP (x, 0)); mgl@1371: + break; mgl@1371: + case MEM: mgl@1371: + switch (GET_CODE (XEXP (XEXP (x, 0), 0))) mgl@1371: + { mgl@1371: + case SYMBOL_REF: mgl@1371: + output_addr_const (stream, XEXP (XEXP (x, 0), 0)); mgl@1371: + break; mgl@1371: + default: mgl@1371: + error = 1; mgl@1371: + break; mgl@1371: + } mgl@1371: + break; mgl@1371: + case REG: mgl@1371: + avr32_print_operand (stream, XEXP (x, 0), 0); mgl@1371: + if (code != 'p') mgl@1371: + fputs ("[0]", stream); mgl@1371: + break; mgl@1371: + case PRE_DEC: mgl@1371: + fputs ("--", stream); mgl@1371: + avr32_print_operand (stream, XEXP (XEXP (x, 0), 0), 0); mgl@1371: + break; mgl@1371: + case POST_INC: mgl@1371: + avr32_print_operand (stream, XEXP (XEXP (x, 0), 0), 0); mgl@1371: + fputs ("++", stream); mgl@1371: + break; mgl@1371: + case PLUS: mgl@1371: + { mgl@1371: + rtx op0 = XEXP (XEXP (x, 0), 0); mgl@1371: + rtx op1 = XEXP (XEXP (x, 0), 1); mgl@1371: + rtx base = NULL_RTX, offset = NULL_RTX; mgl@1371: + mgl@1371: + if (avr32_address_register_rtx_p (op0, 1)) mgl@1371: + { mgl@1371: + base = op0; mgl@1371: + offset = op1; mgl@1371: + } mgl@1371: + else if (avr32_address_register_rtx_p (op1, 1)) mgl@1371: + { mgl@1371: + /* Operands are switched. */ mgl@1371: + base = op1; mgl@1371: + offset = op0; mgl@1371: + } mgl@1371: + mgl@1371: + gcc_assert (base && offset mgl@1371: + && avr32_address_register_rtx_p (base, 1) mgl@1371: + && avr32_legitimate_index_p (GET_MODE (x), offset, mgl@1371: + 1)); mgl@1371: + mgl@1371: + avr32_print_operand (stream, base, 0); mgl@1371: + fputs ("[", stream); mgl@1371: + avr32_print_operand (stream, offset, 0); mgl@1371: + fputs ("]", stream); mgl@1371: + break; mgl@1371: + } mgl@1371: + case CONST: mgl@1371: + output_addr_const (stream, XEXP (XEXP (XEXP (x, 0), 0), 0)); mgl@1371: + fprintf (stream, " + %ld", mgl@1371: + INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))); mgl@1371: + break; mgl@1371: + case CONST_INT: mgl@1371: + avr32_print_operand (stream, XEXP (x, 0), 0); mgl@1371: + break; mgl@1371: + default: mgl@1371: + error = 1; mgl@1371: + } mgl@1371: + break; mgl@1371: + case MULT: mgl@1371: + { mgl@1371: + int value = INTVAL (XEXP (x, 1)); mgl@1371: + mgl@1371: + /* Convert immediate in multiplication into a shift immediate */ mgl@1371: + switch (value) mgl@1371: + { mgl@1371: + case 2: mgl@1371: + value = 1; mgl@1371: + break; mgl@1371: + case 4: mgl@1371: + value = 2; mgl@1371: + break; mgl@1371: + case 8: mgl@1371: + value = 3; mgl@1371: + break; mgl@1371: + default: mgl@1371: + value = 0; mgl@1371: + } mgl@1371: + fprintf (stream, "%s << %i", reg_names[true_regnum (XEXP (x, 0))], mgl@1371: + value); mgl@1371: + break; mgl@1371: + } mgl@1371: + case ASHIFT: mgl@1371: + if (GET_CODE (XEXP (x, 1)) == CONST_INT) mgl@1371: + fprintf (stream, "%s << %i", reg_names[true_regnum (XEXP (x, 0))], mgl@1371: + (int) INTVAL (XEXP (x, 1))); mgl@1371: + else if (REG_P (XEXP (x, 1))) mgl@1371: + fprintf (stream, "%s << %s", reg_names[true_regnum (XEXP (x, 0))], mgl@1371: + reg_names[true_regnum (XEXP (x, 1))]); mgl@1371: + else mgl@1371: + { mgl@1371: + error = 1; mgl@1371: + } mgl@1371: + break; mgl@1371: + case LSHIFTRT: mgl@1371: + if (GET_CODE (XEXP (x, 1)) == CONST_INT) mgl@1371: + fprintf (stream, "%s >> %i", reg_names[true_regnum (XEXP (x, 0))], mgl@1371: + (int) INTVAL (XEXP (x, 1))); mgl@1371: + else if (REG_P (XEXP (x, 1))) mgl@1371: + fprintf (stream, "%s >> %s", reg_names[true_regnum (XEXP (x, 0))], mgl@1371: + reg_names[true_regnum (XEXP (x, 1))]); mgl@1371: + else mgl@1371: + { mgl@1371: + error = 1; mgl@1371: + } mgl@1371: + fprintf (stream, ">>"); mgl@1371: + break; mgl@1371: + case PARALLEL: mgl@1371: + { mgl@1371: + /* Load store multiple */ mgl@1371: + int i; mgl@1371: + int count = XVECLEN (x, 0); mgl@1371: + int reglist16 = 0; mgl@1371: + char reglist16_string[100]; mgl@1371: + mgl@1371: + for (i = 0; i < count; ++i) mgl@1371: + { mgl@1371: + rtx vec_elm = XVECEXP (x, 0, i); mgl@1371: + if (GET_MODE (vec_elm) != SET) mgl@1371: + { mgl@1371: + debug_rtx (vec_elm); mgl@1371: + internal_error ("Unknown element in parallel expression!"); mgl@1371: + } mgl@1371: + if (GET_MODE (XEXP (vec_elm, 0)) == REG) mgl@1371: + { mgl@1371: + /* Load multiple */ mgl@1371: + reglist16 |= 1 << ASM_REGNUM (REGNO (XEXP (vec_elm, 0))); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Store multiple */ mgl@1371: + reglist16 |= 1 << ASM_REGNUM (REGNO (XEXP (vec_elm, 1))); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + avr32_make_reglist16 (reglist16, reglist16_string); mgl@1371: + fputs (reglist16_string, stream); mgl@1371: + mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + case PLUS: mgl@1371: + { mgl@1371: + rtx op0 = XEXP (x, 0); mgl@1371: + rtx op1 = XEXP (x, 1); mgl@1371: + rtx base = NULL_RTX, offset = NULL_RTX; mgl@1371: + mgl@1371: + if (avr32_address_register_rtx_p (op0, 1)) mgl@1371: + { mgl@1371: + base = op0; mgl@1371: + offset = op1; mgl@1371: + } mgl@1371: + else if (avr32_address_register_rtx_p (op1, 1)) mgl@1371: + { mgl@1371: + /* Operands are switched. */ mgl@1371: + base = op1; mgl@1371: + offset = op0; mgl@1371: + } mgl@1371: + mgl@1371: + gcc_assert (base && offset mgl@1371: + && avr32_address_register_rtx_p (base, 1) mgl@1371: + && avr32_legitimate_index_p (GET_MODE (x), offset, 1)); mgl@1371: + mgl@1371: + avr32_print_operand (stream, base, 0); mgl@1371: + fputs ("[", stream); mgl@1371: + avr32_print_operand (stream, offset, 0); mgl@1371: + fputs ("]", stream); mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + default: mgl@1371: + error = 1; mgl@1371: + } mgl@1371: + mgl@1371: + if (error) mgl@1371: + { mgl@1371: + debug_rtx (x); mgl@1371: + internal_error ("Illegal expression for avr32_print_operand"); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_get_note_reg_equiv (rtx insn) mgl@1371: +{ mgl@1371: + rtx note; mgl@1371: + mgl@1371: + note = find_reg_note (insn, REG_EQUIV, NULL_RTX); mgl@1371: + mgl@1371: + if (note != NULL_RTX) mgl@1371: + return XEXP (note, 0); mgl@1371: + else mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Outputs to stdio stream stream the assembler syntax for an instruction mgl@1371: + operand that is a memory reference whose address is x. x is an RTL mgl@1371: + expression. mgl@1371: + mgl@1371: + ToDo: fixme. mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_print_operand_address (FILE * stream, rtx x) mgl@1371: +{ mgl@1371: + fprintf (stream, "(%d) /* address */", REGNO (x)); mgl@1371: +} mgl@1371: + mgl@1371: +/* Return true if _GLOBAL_OFFSET_TABLE_ symbol is mentioned. */ mgl@1371: +bool mgl@1371: +avr32_got_mentioned_p (rtx addr) mgl@1371: +{ mgl@1371: + if (GET_CODE (addr) == MEM) mgl@1371: + addr = XEXP (addr, 0); mgl@1371: + while (GET_CODE (addr) == CONST) mgl@1371: + addr = XEXP (addr, 0); mgl@1371: + if (GET_CODE (addr) == SYMBOL_REF) mgl@1371: + { mgl@1371: + return streq (XSTR (addr, 0), "_GLOBAL_OFFSET_TABLE_"); mgl@1371: + } mgl@1371: + if (GET_CODE (addr) == PLUS || GET_CODE (addr) == MINUS) mgl@1371: + { mgl@1371: + bool l1, l2; mgl@1371: + mgl@1371: + l1 = avr32_got_mentioned_p (XEXP (addr, 0)); mgl@1371: + l2 = avr32_got_mentioned_p (XEXP (addr, 1)); mgl@1371: + return l1 || l2; mgl@1371: + } mgl@1371: + return false; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Find the symbol in an address expression. */ mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_find_symbol (rtx addr) mgl@1371: +{ mgl@1371: + if (GET_CODE (addr) == MEM) mgl@1371: + addr = XEXP (addr, 0); mgl@1371: + mgl@1371: + while (GET_CODE (addr) == CONST) mgl@1371: + addr = XEXP (addr, 0); mgl@1371: + mgl@1371: + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) mgl@1371: + return addr; mgl@1371: + if (GET_CODE (addr) == PLUS) mgl@1371: + { mgl@1371: + rtx l1, l2; mgl@1371: + mgl@1371: + l1 = avr32_find_symbol (XEXP (addr, 0)); mgl@1371: + l2 = avr32_find_symbol (XEXP (addr, 1)); mgl@1371: + if (l1 != NULL_RTX && l2 == NULL_RTX) mgl@1371: + return l1; mgl@1371: + else if (l1 == NULL_RTX && l2 != NULL_RTX) mgl@1371: + return l2; mgl@1371: + } mgl@1371: + mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Routines for manipulation of the constant pool. */ mgl@1371: + mgl@1371: +/* AVR32 instructions cannot load a large constant directly into a mgl@1371: + register; they have to come from a pc relative load. The constant mgl@1371: + must therefore be placed in the addressable range of the pc mgl@1371: + relative load. Depending on the precise pc relative load mgl@1371: + instruction the range is somewhere between 256 bytes and 4k. This mgl@1371: + means that we often have to dump a constant inside a function, and mgl@1371: + generate code to branch around it. mgl@1371: + mgl@1371: + It is important to minimize this, since the branches will slow mgl@1371: + things down and make the code larger. mgl@1371: + mgl@1371: + Normally we can hide the table after an existing unconditional mgl@1371: + branch so that there is no interruption of the flow, but in the mgl@1371: + worst case the code looks like this: mgl@1371: + mgl@1371: + lddpc rn, L1 mgl@1371: + ... mgl@1371: + rjmp L2 mgl@1371: + align mgl@1371: + L1: .long value mgl@1371: + L2: mgl@1371: + ... mgl@1371: + mgl@1371: + lddpc rn, L3 mgl@1371: + ... mgl@1371: + rjmp L4 mgl@1371: + align mgl@1371: + L3: .long value mgl@1371: + L4: mgl@1371: + ... mgl@1371: + mgl@1371: + We fix this by performing a scan after scheduling, which notices mgl@1371: + which instructions need to have their operands fetched from the mgl@1371: + constant table and builds the table. mgl@1371: + mgl@1371: + The algorithm starts by building a table of all the constants that mgl@1371: + need fixing up and all the natural barriers in the function (places mgl@1371: + where a constant table can be dropped without breaking the flow). mgl@1371: + For each fixup we note how far the pc-relative replacement will be mgl@1371: + able to reach and the offset of the instruction into the function. mgl@1371: + mgl@1371: + Having built the table we then group the fixes together to form mgl@1371: + tables that are as large as possible (subject to addressing mgl@1371: + constraints) and emit each table of constants after the last mgl@1371: + barrier that is within range of all the instructions in the group. mgl@1371: + If a group does not contain a barrier, then we forcibly create one mgl@1371: + by inserting a jump instruction into the flow. Once the table has mgl@1371: + been inserted, the insns are then modified to reference the mgl@1371: + relevant entry in the pool. mgl@1371: + mgl@1371: + Possible enhancements to the algorithm (not implemented) are: mgl@1371: + mgl@1371: + 1) For some processors and object formats, there may be benefit in mgl@1371: + aligning the pools to the start of cache lines; this alignment mgl@1371: + would need to be taken into account when calculating addressability mgl@1371: + of a pool. */ mgl@1371: + mgl@1371: +/* These typedefs are located at the start of this file, so that mgl@1371: + they can be used in the prototypes there. This comment is to mgl@1371: + remind readers of that fact so that the following structures mgl@1371: + can be understood more easily. mgl@1371: + mgl@1371: + typedef struct minipool_node Mnode; mgl@1371: + typedef struct minipool_fixup Mfix; */ mgl@1371: + mgl@1371: +struct minipool_node mgl@1371: +{ mgl@1371: + /* Doubly linked chain of entries. */ mgl@1371: + Mnode *next; mgl@1371: + Mnode *prev; mgl@1371: + /* The maximum offset into the code that this entry can be placed. While mgl@1371: + pushing fixes for forward references, all entries are sorted in order of mgl@1371: + increasing max_address. */ mgl@1371: + HOST_WIDE_INT max_address; mgl@1371: + /* Similarly for an entry inserted for a backwards ref. */ mgl@1371: + HOST_WIDE_INT min_address; mgl@1371: + /* The number of fixes referencing this entry. This can become zero if we mgl@1371: + "unpush" an entry. In this case we ignore the entry when we come to mgl@1371: + emit the code. */ mgl@1371: + int refcount; mgl@1371: + /* The offset from the start of the minipool. */ mgl@1371: + HOST_WIDE_INT offset; mgl@1371: + /* The value in table. */ mgl@1371: + rtx value; mgl@1371: + /* The mode of value. */ mgl@1371: + enum machine_mode mode; mgl@1371: + /* The size of the value. */ mgl@1371: + int fix_size; mgl@1371: +}; mgl@1371: + mgl@1371: +struct minipool_fixup mgl@1371: +{ mgl@1371: + Mfix *next; mgl@1371: + rtx insn; mgl@1371: + HOST_WIDE_INT address; mgl@1371: + rtx *loc; mgl@1371: + enum machine_mode mode; mgl@1371: + int fix_size; mgl@1371: + rtx value; mgl@1371: + Mnode *minipool; mgl@1371: + HOST_WIDE_INT forwards; mgl@1371: + HOST_WIDE_INT backwards; mgl@1371: +}; mgl@1371: + mgl@1371: + mgl@1371: +/* Fixes less than a word need padding out to a word boundary. */ mgl@1371: +#define MINIPOOL_FIX_SIZE(mode, value) \ mgl@1371: + (IS_FORCE_MINIPOOL(value) ? 0 : \ mgl@1371: + (GET_MODE_SIZE ((mode)) >= 4 ? GET_MODE_SIZE ((mode)) : 4)) mgl@1371: + mgl@1371: +#define IS_FORCE_MINIPOOL(x) \ mgl@1371: + (GET_CODE(x) == UNSPEC && \ mgl@1371: + XINT(x, 1) == UNSPEC_FORCE_MINIPOOL) mgl@1371: + mgl@1371: +static Mnode *minipool_vector_head; mgl@1371: +static Mnode *minipool_vector_tail; mgl@1371: + mgl@1371: +/* The linked list of all minipool fixes required for this function. */ mgl@1371: +Mfix *minipool_fix_head; mgl@1371: +Mfix *minipool_fix_tail; mgl@1371: +/* The fix entry for the current minipool, once it has been placed. */ mgl@1371: +Mfix *minipool_barrier; mgl@1371: + mgl@1371: +/* Determines if INSN is the start of a jump table. Returns the end mgl@1371: + of the TABLE or NULL_RTX. */ mgl@1371: +static rtx mgl@1371: +is_jump_table (rtx insn) mgl@1371: +{ mgl@1371: + rtx table; mgl@1371: + mgl@1371: + if (GET_CODE (insn) == JUMP_INSN mgl@1371: + && JUMP_LABEL (insn) != NULL mgl@1371: + && ((table = next_real_insn (JUMP_LABEL (insn))) mgl@1371: + == next_real_insn (insn)) mgl@1371: + && table != NULL mgl@1371: + && GET_CODE (table) == JUMP_INSN mgl@1371: + && (GET_CODE (PATTERN (table)) == ADDR_VEC mgl@1371: + || GET_CODE (PATTERN (table)) == ADDR_DIFF_VEC)) mgl@1371: + return table; mgl@1371: + mgl@1371: + return NULL_RTX; mgl@1371: +} mgl@1371: + mgl@1371: +static HOST_WIDE_INT mgl@1371: +get_jump_table_size (rtx insn) mgl@1371: +{ mgl@1371: + /* ADDR_VECs only take room if read-only data does into the text section. */ mgl@1371: + if (JUMP_TABLES_IN_TEXT_SECTION mgl@1371: +#if !defined(READONLY_DATA_SECTION_ASM_OP) mgl@1371: + || 1 mgl@1371: +#endif mgl@1371: + ) mgl@1371: + { mgl@1371: + rtx body = PATTERN (insn); mgl@1371: + int elt = GET_CODE (body) == ADDR_DIFF_VEC ? 1 : 0; mgl@1371: + mgl@1371: + return GET_MODE_SIZE (GET_MODE (body)) * XVECLEN (body, elt); mgl@1371: + } mgl@1371: + mgl@1371: + return 0; mgl@1371: +} mgl@1371: + mgl@1371: +/* Move a minipool fix MP from its current location to before MAX_MP. mgl@1371: + If MAX_MP is NULL, then MP doesn't need moving, but the addressing mgl@1371: + constraints may need updating. */ mgl@1371: +static Mnode * mgl@1371: +move_minipool_fix_forward_ref (Mnode * mp, Mnode * max_mp, mgl@1371: + HOST_WIDE_INT max_address) mgl@1371: +{ mgl@1371: + /* This should never be true and the code below assumes these are mgl@1371: + different. */ mgl@1371: + if (mp == max_mp) mgl@1371: + abort (); mgl@1371: + mgl@1371: + if (max_mp == NULL) mgl@1371: + { mgl@1371: + if (max_address < mp->max_address) mgl@1371: + mp->max_address = max_address; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + if (max_address > max_mp->max_address - mp->fix_size) mgl@1371: + mp->max_address = max_mp->max_address - mp->fix_size; mgl@1371: + else mgl@1371: + mp->max_address = max_address; mgl@1371: + mgl@1371: + /* Unlink MP from its current position. Since max_mp is non-null, mgl@1371: + mp->prev must be non-null. */ mgl@1371: + mp->prev->next = mp->next; mgl@1371: + if (mp->next != NULL) mgl@1371: + mp->next->prev = mp->prev; mgl@1371: + else mgl@1371: + minipool_vector_tail = mp->prev; mgl@1371: + mgl@1371: + /* Re-insert it before MAX_MP. */ mgl@1371: + mp->next = max_mp; mgl@1371: + mp->prev = max_mp->prev; mgl@1371: + max_mp->prev = mp; mgl@1371: + mgl@1371: + if (mp->prev != NULL) mgl@1371: + mp->prev->next = mp; mgl@1371: + else mgl@1371: + minipool_vector_head = mp; mgl@1371: + } mgl@1371: + mgl@1371: + /* Save the new entry. */ mgl@1371: + max_mp = mp; mgl@1371: + mgl@1371: + /* Scan over the preceding entries and adjust their addresses as required. mgl@1371: + */ mgl@1371: + while (mp->prev != NULL mgl@1371: + && mp->prev->max_address > mp->max_address - mp->prev->fix_size) mgl@1371: + { mgl@1371: + mp->prev->max_address = mp->max_address - mp->prev->fix_size; mgl@1371: + mp = mp->prev; mgl@1371: + } mgl@1371: + mgl@1371: + return max_mp; mgl@1371: +} mgl@1371: + mgl@1371: +/* Add a constant to the minipool for a forward reference. Returns the mgl@1371: + node added or NULL if the constant will not fit in this pool. */ mgl@1371: +static Mnode * mgl@1371: +add_minipool_forward_ref (Mfix * fix) mgl@1371: +{ mgl@1371: + /* If set, max_mp is the first pool_entry that has a lower constraint than mgl@1371: + the one we are trying to add. */ mgl@1371: + Mnode *max_mp = NULL; mgl@1371: + HOST_WIDE_INT max_address = fix->address + fix->forwards; mgl@1371: + Mnode *mp; mgl@1371: + mgl@1371: + /* If this fix's address is greater than the address of the first entry, mgl@1371: + then we can't put the fix in this pool. We subtract the size of the mgl@1371: + current fix to ensure that if the table is fully packed we still have mgl@1371: + enough room to insert this value by suffling the other fixes forwards. */ mgl@1371: + if (minipool_vector_head && mgl@1371: + fix->address >= minipool_vector_head->max_address - fix->fix_size) mgl@1371: + return NULL; mgl@1371: + mgl@1371: + /* Scan the pool to see if a constant with the same value has already been mgl@1371: + added. While we are doing this, also note the location where we must mgl@1371: + insert the constant if it doesn't already exist. */ mgl@1371: + for (mp = minipool_vector_head; mp != NULL; mp = mp->next) mgl@1371: + { mgl@1371: + if (GET_CODE (fix->value) == GET_CODE (mp->value) mgl@1371: + && fix->mode == mp->mode mgl@1371: + && (GET_CODE (fix->value) != CODE_LABEL mgl@1371: + || (CODE_LABEL_NUMBER (fix->value) mgl@1371: + == CODE_LABEL_NUMBER (mp->value))) mgl@1371: + && rtx_equal_p (fix->value, mp->value)) mgl@1371: + { mgl@1371: + /* More than one fix references this entry. */ mgl@1371: + mp->refcount++; mgl@1371: + return move_minipool_fix_forward_ref (mp, max_mp, max_address); mgl@1371: + } mgl@1371: + mgl@1371: + /* Note the insertion point if necessary. */ mgl@1371: + if (max_mp == NULL && mp->max_address > max_address) mgl@1371: + max_mp = mp; mgl@1371: + mgl@1371: + } mgl@1371: + mgl@1371: + /* The value is not currently in the minipool, so we need to create a new mgl@1371: + entry for it. If MAX_MP is NULL, the entry will be put on the end of mgl@1371: + the list since the placement is less constrained than any existing mgl@1371: + entry. Otherwise, we insert the new fix before MAX_MP and, if mgl@1371: + necessary, adjust the constraints on the other entries. */ mgl@1371: + mp = xmalloc (sizeof (*mp)); mgl@1371: + mp->fix_size = fix->fix_size; mgl@1371: + mp->mode = fix->mode; mgl@1371: + mp->value = fix->value; mgl@1371: + mp->refcount = 1; mgl@1371: + /* Not yet required for a backwards ref. */ mgl@1371: + mp->min_address = -65536; mgl@1371: + mgl@1371: + if (max_mp == NULL) mgl@1371: + { mgl@1371: + mp->max_address = max_address; mgl@1371: + mp->next = NULL; mgl@1371: + mp->prev = minipool_vector_tail; mgl@1371: + mgl@1371: + if (mp->prev == NULL) mgl@1371: + { mgl@1371: + minipool_vector_head = mp; mgl@1371: + minipool_vector_label = gen_label_rtx (); mgl@1371: + } mgl@1371: + else mgl@1371: + mp->prev->next = mp; mgl@1371: + mgl@1371: + minipool_vector_tail = mp; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + if (max_address > max_mp->max_address - mp->fix_size) mgl@1371: + mp->max_address = max_mp->max_address - mp->fix_size; mgl@1371: + else mgl@1371: + mp->max_address = max_address; mgl@1371: + mgl@1371: + mp->next = max_mp; mgl@1371: + mp->prev = max_mp->prev; mgl@1371: + max_mp->prev = mp; mgl@1371: + if (mp->prev != NULL) mgl@1371: + mp->prev->next = mp; mgl@1371: + else mgl@1371: + minipool_vector_head = mp; mgl@1371: + } mgl@1371: + mgl@1371: + /* Save the new entry. */ mgl@1371: + max_mp = mp; mgl@1371: + mgl@1371: + /* Scan over the preceding entries and adjust their addresses as required. mgl@1371: + */ mgl@1371: + while (mp->prev != NULL mgl@1371: + && mp->prev->max_address > mp->max_address - mp->prev->fix_size) mgl@1371: + { mgl@1371: + mp->prev->max_address = mp->max_address - mp->prev->fix_size; mgl@1371: + mp = mp->prev; mgl@1371: + } mgl@1371: + mgl@1371: + return max_mp; mgl@1371: +} mgl@1371: + mgl@1371: +static Mnode * mgl@1371: +move_minipool_fix_backward_ref (Mnode * mp, Mnode * min_mp, mgl@1371: + HOST_WIDE_INT min_address) mgl@1371: +{ mgl@1371: + HOST_WIDE_INT offset; mgl@1371: + mgl@1371: + /* This should never be true, and the code below assumes these are mgl@1371: + different. */ mgl@1371: + if (mp == min_mp) mgl@1371: + abort (); mgl@1371: + mgl@1371: + if (min_mp == NULL) mgl@1371: + { mgl@1371: + if (min_address > mp->min_address) mgl@1371: + mp->min_address = min_address; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* We will adjust this below if it is too loose. */ mgl@1371: + mp->min_address = min_address; mgl@1371: + mgl@1371: + /* Unlink MP from its current position. Since min_mp is non-null, mgl@1371: + mp->next must be non-null. */ mgl@1371: + mp->next->prev = mp->prev; mgl@1371: + if (mp->prev != NULL) mgl@1371: + mp->prev->next = mp->next; mgl@1371: + else mgl@1371: + minipool_vector_head = mp->next; mgl@1371: + mgl@1371: + /* Reinsert it after MIN_MP. */ mgl@1371: + mp->prev = min_mp; mgl@1371: + mp->next = min_mp->next; mgl@1371: + min_mp->next = mp; mgl@1371: + if (mp->next != NULL) mgl@1371: + mp->next->prev = mp; mgl@1371: + else mgl@1371: + minipool_vector_tail = mp; mgl@1371: + } mgl@1371: + mgl@1371: + min_mp = mp; mgl@1371: + mgl@1371: + offset = 0; mgl@1371: + for (mp = minipool_vector_head; mp != NULL; mp = mp->next) mgl@1371: + { mgl@1371: + mp->offset = offset; mgl@1371: + if (mp->refcount > 0) mgl@1371: + offset += mp->fix_size; mgl@1371: + mgl@1371: + if (mp->next && mp->next->min_address < mp->min_address + mp->fix_size) mgl@1371: + mp->next->min_address = mp->min_address + mp->fix_size; mgl@1371: + } mgl@1371: + mgl@1371: + return min_mp; mgl@1371: +} mgl@1371: + mgl@1371: +/* Add a constant to the minipool for a backward reference. Returns the mgl@1371: + node added or NULL if the constant will not fit in this pool. mgl@1371: + mgl@1371: + Note that the code for insertion for a backwards reference can be mgl@1371: + somewhat confusing because the calculated offsets for each fix do mgl@1371: + not take into account the size of the pool (which is still under mgl@1371: + construction. */ mgl@1371: +static Mnode * mgl@1371: +add_minipool_backward_ref (Mfix * fix) mgl@1371: +{ mgl@1371: + /* If set, min_mp is the last pool_entry that has a lower constraint than mgl@1371: + the one we are trying to add. */ mgl@1371: + Mnode *min_mp = NULL; mgl@1371: + /* This can be negative, since it is only a constraint. */ mgl@1371: + HOST_WIDE_INT min_address = fix->address - fix->backwards; mgl@1371: + Mnode *mp; mgl@1371: + mgl@1371: + /* If we can't reach the current pool from this insn, or if we can't insert mgl@1371: + this entry at the end of the pool without pushing other fixes out of mgl@1371: + range, then we don't try. This ensures that we can't fail later on. */ mgl@1371: + if (min_address >= minipool_barrier->address mgl@1371: + || (minipool_vector_tail->min_address + fix->fix_size mgl@1371: + >= minipool_barrier->address)) mgl@1371: + return NULL; mgl@1371: + mgl@1371: + /* Scan the pool to see if a constant with the same value has already been mgl@1371: + added. While we are doing this, also note the location where we must mgl@1371: + insert the constant if it doesn't already exist. */ mgl@1371: + for (mp = minipool_vector_tail; mp != NULL; mp = mp->prev) mgl@1371: + { mgl@1371: + if (GET_CODE (fix->value) == GET_CODE (mp->value) mgl@1371: + && fix->mode == mp->mode mgl@1371: + && (GET_CODE (fix->value) != CODE_LABEL mgl@1371: + || (CODE_LABEL_NUMBER (fix->value) mgl@1371: + == CODE_LABEL_NUMBER (mp->value))) mgl@1371: + && rtx_equal_p (fix->value, mp->value) mgl@1371: + /* Check that there is enough slack to move this entry to the end mgl@1371: + of the table (this is conservative). */ mgl@1371: + && (mp->max_address mgl@1371: + > (minipool_barrier->address mgl@1371: + + minipool_vector_tail->offset mgl@1371: + + minipool_vector_tail->fix_size))) mgl@1371: + { mgl@1371: + mp->refcount++; mgl@1371: + return move_minipool_fix_backward_ref (mp, min_mp, min_address); mgl@1371: + } mgl@1371: + mgl@1371: + if (min_mp != NULL) mgl@1371: + mp->min_address += fix->fix_size; mgl@1371: + else mgl@1371: + { mgl@1371: + /* Note the insertion point if necessary. */ mgl@1371: + if (mp->min_address < min_address) mgl@1371: + { mgl@1371: + min_mp = mp; mgl@1371: + } mgl@1371: + else if (mp->max_address mgl@1371: + < minipool_barrier->address + mp->offset + fix->fix_size) mgl@1371: + { mgl@1371: + /* Inserting before this entry would push the fix beyond its mgl@1371: + maximum address (which can happen if we have re-located a mgl@1371: + forwards fix); force the new fix to come after it. */ mgl@1371: + min_mp = mp; mgl@1371: + min_address = mp->min_address + fix->fix_size; mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + /* We need to create a new entry. */ mgl@1371: + mp = xmalloc (sizeof (*mp)); mgl@1371: + mp->fix_size = fix->fix_size; mgl@1371: + mp->mode = fix->mode; mgl@1371: + mp->value = fix->value; mgl@1371: + mp->refcount = 1; mgl@1371: + mp->max_address = minipool_barrier->address + 65536; mgl@1371: + mgl@1371: + mp->min_address = min_address; mgl@1371: + mgl@1371: + if (min_mp == NULL) mgl@1371: + { mgl@1371: + mp->prev = NULL; mgl@1371: + mp->next = minipool_vector_head; mgl@1371: + mgl@1371: + if (mp->next == NULL) mgl@1371: + { mgl@1371: + minipool_vector_tail = mp; mgl@1371: + minipool_vector_label = gen_label_rtx (); mgl@1371: + } mgl@1371: + else mgl@1371: + mp->next->prev = mp; mgl@1371: + mgl@1371: + minipool_vector_head = mp; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + mp->next = min_mp->next; mgl@1371: + mp->prev = min_mp; mgl@1371: + min_mp->next = mp; mgl@1371: + mgl@1371: + if (mp->next != NULL) mgl@1371: + mp->next->prev = mp; mgl@1371: + else mgl@1371: + minipool_vector_tail = mp; mgl@1371: + } mgl@1371: + mgl@1371: + /* Save the new entry. */ mgl@1371: + min_mp = mp; mgl@1371: + mgl@1371: + if (mp->prev) mgl@1371: + mp = mp->prev; mgl@1371: + else mgl@1371: + mp->offset = 0; mgl@1371: + mgl@1371: + /* Scan over the following entries and adjust their offsets. */ mgl@1371: + while (mp->next != NULL) mgl@1371: + { mgl@1371: + if (mp->next->min_address < mp->min_address + mp->fix_size) mgl@1371: + mp->next->min_address = mp->min_address + mp->fix_size; mgl@1371: + mgl@1371: + if (mp->refcount) mgl@1371: + mp->next->offset = mp->offset + mp->fix_size; mgl@1371: + else mgl@1371: + mp->next->offset = mp->offset; mgl@1371: + mgl@1371: + mp = mp->next; mgl@1371: + } mgl@1371: + mgl@1371: + return min_mp; mgl@1371: +} mgl@1371: + mgl@1371: +static void mgl@1371: +assign_minipool_offsets (Mfix * barrier) mgl@1371: +{ mgl@1371: + HOST_WIDE_INT offset = 0; mgl@1371: + Mnode *mp; mgl@1371: + mgl@1371: + minipool_barrier = barrier; mgl@1371: + mgl@1371: + for (mp = minipool_vector_head; mp != NULL; mp = mp->next) mgl@1371: + { mgl@1371: + mp->offset = offset; mgl@1371: + mgl@1371: + if (mp->refcount > 0) mgl@1371: + offset += mp->fix_size; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* Print a symbolic form of X to the debug file, F. */ mgl@1371: +static void mgl@1371: +avr32_print_value (FILE * f, rtx x) mgl@1371: +{ mgl@1371: + switch (GET_CODE (x)) mgl@1371: + { mgl@1371: + case CONST_INT: mgl@1371: + fprintf (f, "0x%x", (int) INTVAL (x)); mgl@1371: + return; mgl@1371: + mgl@1371: + case CONST_DOUBLE: mgl@1371: + fprintf (f, "<0x%lx,0x%lx>", (long) XWINT (x, 2), (long) XWINT (x, 3)); mgl@1371: + return; mgl@1371: + mgl@1371: + case CONST_VECTOR: mgl@1371: + { mgl@1371: + int i; mgl@1371: + mgl@1371: + fprintf (f, "<"); mgl@1371: + for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) mgl@1371: + { mgl@1371: + fprintf (f, "0x%x", (int) INTVAL (CONST_VECTOR_ELT (x, i))); mgl@1371: + if (i < (CONST_VECTOR_NUNITS (x) - 1)) mgl@1371: + fputc (',', f); mgl@1371: + } mgl@1371: + fprintf (f, ">"); mgl@1371: + } mgl@1371: + return; mgl@1371: + mgl@1371: + case CONST_STRING: mgl@1371: + fprintf (f, "\"%s\"", XSTR (x, 0)); mgl@1371: + return; mgl@1371: + mgl@1371: + case SYMBOL_REF: mgl@1371: + fprintf (f, "`%s'", XSTR (x, 0)); mgl@1371: + return; mgl@1371: + mgl@1371: + case LABEL_REF: mgl@1371: + fprintf (f, "L%d", INSN_UID (XEXP (x, 0))); mgl@1371: + return; mgl@1371: + mgl@1371: + case CONST: mgl@1371: + avr32_print_value (f, XEXP (x, 0)); mgl@1371: + return; mgl@1371: + mgl@1371: + case PLUS: mgl@1371: + avr32_print_value (f, XEXP (x, 0)); mgl@1371: + fprintf (f, "+"); mgl@1371: + avr32_print_value (f, XEXP (x, 1)); mgl@1371: + return; mgl@1371: + mgl@1371: + case PC: mgl@1371: + fprintf (f, "pc"); mgl@1371: + return; mgl@1371: + mgl@1371: + default: mgl@1371: + fprintf (f, "????"); mgl@1371: + return; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +is_minipool_label (rtx label) mgl@1371: +{ mgl@1371: + minipool_labels *cur_mp_label = cfun->machine->minipool_label_head; mgl@1371: + mgl@1371: + if (GET_CODE (label) != CODE_LABEL) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + while (cur_mp_label) mgl@1371: + { mgl@1371: + if (CODE_LABEL_NUMBER (label) mgl@1371: + == CODE_LABEL_NUMBER (cur_mp_label->label)) mgl@1371: + return TRUE; mgl@1371: + cur_mp_label = cur_mp_label->next; mgl@1371: + } mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: +static void mgl@1371: +new_minipool_label (rtx label) mgl@1371: +{ mgl@1371: + if (!cfun->machine->minipool_label_head) mgl@1371: + { mgl@1371: + cfun->machine->minipool_label_head = mgl@1371: + ggc_alloc (sizeof (minipool_labels)); mgl@1371: + cfun->machine->minipool_label_tail = cfun->machine->minipool_label_head; mgl@1371: + cfun->machine->minipool_label_head->label = label; mgl@1371: + cfun->machine->minipool_label_head->next = 0; mgl@1371: + cfun->machine->minipool_label_head->prev = 0; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + cfun->machine->minipool_label_tail->next = mgl@1371: + ggc_alloc (sizeof (minipool_labels)); mgl@1371: + cfun->machine->minipool_label_tail->next->label = label; mgl@1371: + cfun->machine->minipool_label_tail->next->next = 0; mgl@1371: + cfun->machine->minipool_label_tail->next->prev = mgl@1371: + cfun->machine->minipool_label_tail; mgl@1371: + cfun->machine->minipool_label_tail = mgl@1371: + cfun->machine->minipool_label_tail->next; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* Output the literal table */ mgl@1371: +static void mgl@1371: +dump_minipool (rtx scan) mgl@1371: +{ mgl@1371: + Mnode *mp; mgl@1371: + Mnode *nmp; mgl@1371: + mgl@1371: + if (dump_file) mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", mgl@1371: + INSN_UID (scan), (unsigned long) minipool_barrier->address, 4); mgl@1371: + mgl@1371: + scan = emit_insn_after (gen_consttable_start (), scan); mgl@1371: + scan = emit_insn_after (gen_align_4 (), scan); mgl@1371: + scan = emit_label_after (minipool_vector_label, scan); mgl@1371: + new_minipool_label (minipool_vector_label); mgl@1371: + mgl@1371: + for (mp = minipool_vector_head; mp != NULL; mp = nmp) mgl@1371: + { mgl@1371: + if (mp->refcount > 0) mgl@1371: + { mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Offset %u, min %ld, max %ld ", mgl@1371: + (unsigned) mp->offset, (unsigned long) mp->min_address, mgl@1371: + (unsigned long) mp->max_address); mgl@1371: + avr32_print_value (dump_file, mp->value); mgl@1371: + fputc ('\n', dump_file); mgl@1371: + } mgl@1371: + mgl@1371: + switch (mp->fix_size) mgl@1371: + { mgl@1371: +#ifdef HAVE_consttable_4 mgl@1371: + case 4: mgl@1371: + scan = emit_insn_after (gen_consttable_4 (mp->value), scan); mgl@1371: + break; mgl@1371: + mgl@1371: +#endif mgl@1371: +#ifdef HAVE_consttable_8 mgl@1371: + case 8: mgl@1371: + scan = emit_insn_after (gen_consttable_8 (mp->value), scan); mgl@1371: + break; mgl@1371: + mgl@1371: +#endif mgl@1371: +#ifdef HAVE_consttable_16 mgl@1371: + case 16: mgl@1371: + scan = emit_insn_after (gen_consttable_16 (mp->value), scan); mgl@1371: + break; mgl@1371: + mgl@1371: +#endif mgl@1371: + case 0: mgl@1371: + /* This can happen for force-minipool entries which just are mgl@1371: + there to force the minipool to be generate. */ mgl@1371: + break; mgl@1371: + default: mgl@1371: + abort (); mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + nmp = mp->next; mgl@1371: + free (mp); mgl@1371: + } mgl@1371: + mgl@1371: + minipool_vector_head = minipool_vector_tail = NULL; mgl@1371: + scan = emit_insn_after (gen_consttable_end (), scan); mgl@1371: + scan = emit_barrier_after (scan); mgl@1371: +} mgl@1371: + mgl@1371: +/* Return the cost of forcibly inserting a barrier after INSN. */ mgl@1371: +static int mgl@1371: +avr32_barrier_cost (rtx insn) mgl@1371: +{ mgl@1371: + /* Basing the location of the pool on the loop depth is preferable, but at mgl@1371: + the moment, the basic block information seems to be corrupt by this mgl@1371: + stage of the compilation. */ mgl@1371: + int base_cost = 50; mgl@1371: + rtx next = next_nonnote_insn (insn); mgl@1371: + mgl@1371: + if (next != NULL && GET_CODE (next) == CODE_LABEL) mgl@1371: + base_cost -= 20; mgl@1371: + mgl@1371: + switch (GET_CODE (insn)) mgl@1371: + { mgl@1371: + case CODE_LABEL: mgl@1371: + /* It will always be better to place the table before the label, rather mgl@1371: + than after it. */ mgl@1371: + return 50; mgl@1371: + mgl@1371: + case INSN: mgl@1371: + case CALL_INSN: mgl@1371: + return base_cost; mgl@1371: + mgl@1371: + case JUMP_INSN: mgl@1371: + return base_cost - 10; mgl@1371: + mgl@1371: + default: mgl@1371: + return base_cost + 10; mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* Find the best place in the insn stream in the range mgl@1371: + (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. mgl@1371: + Create the barrier by inserting a jump and add a new fix entry for mgl@1371: + it. */ mgl@1371: +static Mfix * mgl@1371: +create_fix_barrier (Mfix * fix, HOST_WIDE_INT max_address) mgl@1371: +{ mgl@1371: + HOST_WIDE_INT count = 0; mgl@1371: + rtx barrier; mgl@1371: + rtx from = fix->insn; mgl@1371: + rtx selected = from; mgl@1371: + int selected_cost; mgl@1371: + HOST_WIDE_INT selected_address; mgl@1371: + Mfix *new_fix; mgl@1371: + HOST_WIDE_INT max_count = max_address - fix->address; mgl@1371: + rtx label = gen_label_rtx (); mgl@1371: + mgl@1371: + selected_cost = avr32_barrier_cost (from); mgl@1371: + selected_address = fix->address; mgl@1371: + mgl@1371: + while (from && count < max_count) mgl@1371: + { mgl@1371: + rtx tmp; mgl@1371: + int new_cost; mgl@1371: + mgl@1371: + /* This code shouldn't have been called if there was a natural barrier mgl@1371: + within range. */ mgl@1371: + if (GET_CODE (from) == BARRIER) mgl@1371: + abort (); mgl@1371: + mgl@1371: + /* Count the length of this insn. */ mgl@1371: + count += get_attr_length (from); mgl@1371: + mgl@1371: + /* If there is a jump table, add its length. */ mgl@1371: + tmp = is_jump_table (from); mgl@1371: + if (tmp != NULL) mgl@1371: + { mgl@1371: + count += get_jump_table_size (tmp); mgl@1371: + mgl@1371: + /* Jump tables aren't in a basic block, so base the cost on the mgl@1371: + dispatch insn. If we select this location, we will still put mgl@1371: + the pool after the table. */ mgl@1371: + new_cost = avr32_barrier_cost (from); mgl@1371: + mgl@1371: + if (count < max_count && new_cost <= selected_cost) mgl@1371: + { mgl@1371: + selected = tmp; mgl@1371: + selected_cost = new_cost; mgl@1371: + selected_address = fix->address + count; mgl@1371: + } mgl@1371: + mgl@1371: + /* Continue after the dispatch table. */ mgl@1371: + from = NEXT_INSN (tmp); mgl@1371: + continue; mgl@1371: + } mgl@1371: + mgl@1371: + new_cost = avr32_barrier_cost (from); mgl@1371: + mgl@1371: + if (count < max_count && new_cost <= selected_cost) mgl@1371: + { mgl@1371: + selected = from; mgl@1371: + selected_cost = new_cost; mgl@1371: + selected_address = fix->address + count; mgl@1371: + } mgl@1371: + mgl@1371: + from = NEXT_INSN (from); mgl@1371: + } mgl@1371: + mgl@1371: + /* Create a new JUMP_INSN that branches around a barrier. */ mgl@1371: + from = emit_jump_insn_after (gen_jump (label), selected); mgl@1371: + JUMP_LABEL (from) = label; mgl@1371: + barrier = emit_barrier_after (from); mgl@1371: + emit_label_after (label, barrier); mgl@1371: + mgl@1371: + /* Create a minipool barrier entry for the new barrier. */ mgl@1371: + new_fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*new_fix)); mgl@1371: + new_fix->insn = barrier; mgl@1371: + new_fix->address = selected_address; mgl@1371: + new_fix->next = fix->next; mgl@1371: + fix->next = new_fix; mgl@1371: + mgl@1371: + return new_fix; mgl@1371: +} mgl@1371: + mgl@1371: +/* Record that there is a natural barrier in the insn stream at mgl@1371: + ADDRESS. */ mgl@1371: +static void mgl@1371: +push_minipool_barrier (rtx insn, HOST_WIDE_INT address) mgl@1371: +{ mgl@1371: + Mfix *fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*fix)); mgl@1371: + mgl@1371: + fix->insn = insn; mgl@1371: + fix->address = address; mgl@1371: + mgl@1371: + fix->next = NULL; mgl@1371: + if (minipool_fix_head != NULL) mgl@1371: + minipool_fix_tail->next = fix; mgl@1371: + else mgl@1371: + minipool_fix_head = fix; mgl@1371: + mgl@1371: + minipool_fix_tail = fix; mgl@1371: +} mgl@1371: + mgl@1371: +/* Record INSN, which will need fixing up to load a value from the mgl@1371: + minipool. ADDRESS is the offset of the insn since the start of the mgl@1371: + function; LOC is a pointer to the part of the insn which requires mgl@1371: + fixing; VALUE is the constant that must be loaded, which is of type mgl@1371: + MODE. */ mgl@1371: +static void mgl@1371: +push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx * loc, mgl@1371: + enum machine_mode mode, rtx value) mgl@1371: +{ mgl@1371: + Mfix *fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (*fix)); mgl@1371: + rtx body = PATTERN (insn); mgl@1371: + mgl@1371: + fix->insn = insn; mgl@1371: + fix->address = address; mgl@1371: + fix->loc = loc; mgl@1371: + fix->mode = mode; mgl@1371: + fix->fix_size = MINIPOOL_FIX_SIZE (mode, value); mgl@1371: + fix->value = value; mgl@1371: + mgl@1371: + if (GET_CODE (body) == PARALLEL) mgl@1371: + { mgl@1371: + /* Mcall : Ks16 << 2 */ mgl@1371: + fix->forwards = ((1 << 15) - 1) << 2; mgl@1371: + fix->backwards = (1 << 15) << 2; mgl@1371: + } mgl@1371: + else if (GET_CODE (body) == SET mgl@1371: + && GET_MODE_SIZE (GET_MODE (SET_DEST (body))) == 4) mgl@1371: + { mgl@1371: + /* Word Load */ mgl@1371: + if (TARGET_HARD_FLOAT mgl@1371: + && GET_MODE_CLASS (GET_MODE (SET_DEST (body))) == MODE_FLOAT) mgl@1371: + { mgl@1371: + /* Ldc0.w : Ku12 << 2 */ mgl@1371: + fix->forwards = ((1 << 12) - 1) << 2; mgl@1371: + fix->backwards = 0; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + if (optimize_size) mgl@1371: + { mgl@1371: + /* Lddpc : Ku7 << 2 */ mgl@1371: + fix->forwards = ((1 << 7) - 1) << 2; mgl@1371: + fix->backwards = 0; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Ld.w : Ks16 */ mgl@1371: + fix->forwards = ((1 << 15) - 4); mgl@1371: + fix->backwards = (1 << 15); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + else if (GET_CODE (body) == SET mgl@1371: + && GET_MODE_SIZE (GET_MODE (SET_DEST (body))) == 8) mgl@1371: + { mgl@1371: + /* Double word load */ mgl@1371: + if (TARGET_HARD_FLOAT mgl@1371: + && GET_MODE_CLASS (GET_MODE (SET_DEST (body))) == MODE_FLOAT) mgl@1371: + { mgl@1371: + /* Ldc0.d : Ku12 << 2 */ mgl@1371: + fix->forwards = ((1 << 12) - 1) << 2; mgl@1371: + fix->backwards = 0; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Ld.d : Ks16 */ mgl@1371: + fix->forwards = ((1 << 15) - 4); mgl@1371: + fix->backwards = (1 << 15); mgl@1371: + } mgl@1371: + } mgl@1371: + else if (GET_CODE (body) == UNSPEC_VOLATILE mgl@1371: + && XINT (body, 1) == VUNSPEC_MVRC) mgl@1371: + { mgl@1371: + /* Coprocessor load */ mgl@1371: + /* Ldc : Ku8 << 2 */ mgl@1371: + fix->forwards = ((1 << 8) - 1) << 2; mgl@1371: + fix->backwards = 0; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Assume worst case which is lddpc insn. */ mgl@1371: + fix->forwards = ((1 << 7) - 1) << 2; mgl@1371: + fix->backwards = 0; mgl@1371: + } mgl@1371: + mgl@1371: + fix->minipool = NULL; mgl@1371: + mgl@1371: + /* If an insn doesn't have a range defined for it, then it isn't expecting mgl@1371: + to be reworked by this code. Better to abort now than to generate duff mgl@1371: + assembly code. */ mgl@1371: + if (fix->forwards == 0 && fix->backwards == 0) mgl@1371: + abort (); mgl@1371: + mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; %smode fixup for i%d; addr %lu, range (%ld,%ld): ", mgl@1371: + GET_MODE_NAME (mode), mgl@1371: + INSN_UID (insn), (unsigned long) address, mgl@1371: + -1 * (long) fix->backwards, (long) fix->forwards); mgl@1371: + avr32_print_value (dump_file, fix->value); mgl@1371: + fprintf (dump_file, "\n"); mgl@1371: + } mgl@1371: + mgl@1371: + /* Add it to the chain of fixes. */ mgl@1371: + fix->next = NULL; mgl@1371: + mgl@1371: + if (minipool_fix_head != NULL) mgl@1371: + minipool_fix_tail->next = fix; mgl@1371: + else mgl@1371: + minipool_fix_head = fix; mgl@1371: + mgl@1371: + minipool_fix_tail = fix; mgl@1371: +} mgl@1371: + mgl@1371: +/* Scan INSN and note any of its operands that need fixing. mgl@1371: + If DO_PUSHES is false we do not actually push any of the fixups mgl@1371: + needed. The function returns TRUE is any fixups were needed/pushed. mgl@1371: + This is used by avr32_memory_load_p() which needs to know about loads mgl@1371: + of constants that will be converted into minipool loads. */ mgl@1371: +static bool mgl@1371: +note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) mgl@1371: +{ mgl@1371: + bool result = false; mgl@1371: + int opno; mgl@1371: + mgl@1371: + extract_insn (insn); mgl@1371: + mgl@1371: + if (!constrain_operands (1)) mgl@1371: + fatal_insn_not_found (insn); mgl@1371: + mgl@1371: + if (recog_data.n_alternatives == 0) mgl@1371: + return false; mgl@1371: + mgl@1371: + /* Fill in recog_op_alt with information about the constraints of this mgl@1371: + insn. */ mgl@1371: + preprocess_constraints (); mgl@1371: + mgl@1371: + for (opno = 0; opno < recog_data.n_operands; opno++) mgl@1371: + { mgl@1371: + rtx op; mgl@1371: + mgl@1371: + /* Things we need to fix can only occur in inputs. */ mgl@1371: + if (recog_data.operand_type[opno] != OP_IN) mgl@1371: + continue; mgl@1371: + mgl@1371: + op = recog_data.operand[opno]; mgl@1371: + mgl@1371: + if (avr32_const_pool_ref_operand (op, GET_MODE (op))) mgl@1371: + { mgl@1371: + if (do_pushes) mgl@1371: + { mgl@1371: + rtx cop = avoid_constant_pool_reference (op); mgl@1371: + mgl@1371: + /* Casting the address of something to a mode narrower than a mgl@1371: + word can cause avoid_constant_pool_reference() to return the mgl@1371: + pool reference itself. That's no good to us here. Lets mgl@1371: + just hope that we can use the constant pool value directly. mgl@1371: + */ mgl@1371: + if (op == cop) mgl@1371: + cop = get_pool_constant (XEXP (op, 0)); mgl@1371: + mgl@1371: + push_minipool_fix (insn, address, mgl@1371: + recog_data.operand_loc[opno], mgl@1371: + recog_data.operand_mode[opno], cop); mgl@1371: + } mgl@1371: + mgl@1371: + result = true; mgl@1371: + } mgl@1371: + else if (TARGET_HAS_ASM_ADDR_PSEUDOS mgl@1371: + && avr32_address_operand (op, GET_MODE (op))) mgl@1371: + { mgl@1371: + /* Handle pseudo instructions using a direct address. These pseudo mgl@1371: + instructions might need entries in the constant pool and we must mgl@1371: + therefor create a constant pool for them, in case the mgl@1371: + assembler/linker needs to insert entries. */ mgl@1371: + if (do_pushes) mgl@1371: + { mgl@1371: + /* Push a dummy constant pool entry so that the .cpool mgl@1371: + directive should be inserted on the appropriate place in the mgl@1371: + code even if there are no real constant pool entries. This mgl@1371: + is used by the assembler and linker to know where to put mgl@1371: + generated constant pool entries. */ mgl@1371: + push_minipool_fix (insn, address, mgl@1371: + recog_data.operand_loc[opno], mgl@1371: + recog_data.operand_mode[opno], mgl@1371: + gen_rtx_UNSPEC (VOIDmode, mgl@1371: + gen_rtvec (1, const0_rtx), mgl@1371: + UNSPEC_FORCE_MINIPOOL)); mgl@1371: + result = true; mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + return result; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +static int mgl@1371: +avr32_insn_is_cast (rtx insn) mgl@1371: +{ mgl@1371: + mgl@1371: + if (NONJUMP_INSN_P (insn) mgl@1371: + && GET_CODE (PATTERN (insn)) == SET mgl@1371: + && (GET_CODE (SET_SRC (PATTERN (insn))) == ZERO_EXTEND mgl@1371: + || GET_CODE (SET_SRC (PATTERN (insn))) == SIGN_EXTEND) mgl@1371: + && REG_P (XEXP (SET_SRC (PATTERN (insn)), 0)) mgl@1371: + && REG_P (SET_DEST (PATTERN (insn)))) mgl@1371: + return true; mgl@1371: + return false; mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: + Replace all occurances of reg FROM with reg TO in X */ mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_replace_reg (rtx x, rtx from, rtx to) mgl@1371: +{ mgl@1371: + int i, j; mgl@1371: + const char *fmt; mgl@1371: + mgl@1371: + gcc_assert ( REG_P (from) && REG_P (to) ); mgl@1371: + mgl@1371: + /* Allow this function to make replacements in EXPR_LISTs. */ mgl@1371: + if (x == 0) mgl@1371: + return 0; mgl@1371: + mgl@1371: + if (rtx_equal_p (x, from)) mgl@1371: + return to; mgl@1371: + mgl@1371: + if (GET_CODE (x) == SUBREG) mgl@1371: + { mgl@1371: + rtx new = avr32_replace_reg (SUBREG_REG (x), from, to); mgl@1371: + mgl@1371: + if (GET_CODE (new) == CONST_INT) mgl@1371: + { mgl@1371: + x = simplify_subreg (GET_MODE (x), new, mgl@1371: + GET_MODE (SUBREG_REG (x)), mgl@1371: + SUBREG_BYTE (x)); mgl@1371: + gcc_assert (x); mgl@1371: + } mgl@1371: + else mgl@1371: + SUBREG_REG (x) = new; mgl@1371: + mgl@1371: + return x; mgl@1371: + } mgl@1371: + else if (GET_CODE (x) == ZERO_EXTEND) mgl@1371: + { mgl@1371: + rtx new = avr32_replace_reg (XEXP (x, 0), from, to); mgl@1371: + mgl@1371: + if (GET_CODE (new) == CONST_INT) mgl@1371: + { mgl@1371: + x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), mgl@1371: + new, GET_MODE (XEXP (x, 0))); mgl@1371: + gcc_assert (x); mgl@1371: + } mgl@1371: + else mgl@1371: + XEXP (x, 0) = new; mgl@1371: + mgl@1371: + return x; mgl@1371: + } mgl@1371: + mgl@1371: + fmt = GET_RTX_FORMAT (GET_CODE (x)); mgl@1371: + for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) mgl@1371: + { mgl@1371: + if (fmt[i] == 'e') mgl@1371: + XEXP (x, i) = avr32_replace_reg (XEXP (x, i), from, to); mgl@1371: + else if (fmt[i] == 'E') mgl@1371: + for (j = XVECLEN (x, i) - 1; j >= 0; j--) mgl@1371: + XVECEXP (x, i, j) = avr32_replace_reg (XVECEXP (x, i, j), from, to); mgl@1371: + } mgl@1371: + mgl@1371: + return x; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* FIXME: The level of nesting in this function is way too deep. It needs to be mgl@1371: + torn apart. */ mgl@1371: +static void mgl@1371: +avr32_reorg_optimization (void) mgl@1371: +{ mgl@1371: + rtx first = get_first_nonnote_insn (); mgl@1371: + rtx insn; mgl@1371: + mgl@1371: + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0))) mgl@1371: + { mgl@1371: + mgl@1371: + /* Scan through all insns looking for cast operations. */ mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, ";; Deleting redundant cast operations:\n"); mgl@1371: + } mgl@1371: + for (insn = first; insn; insn = NEXT_INSN (insn)) mgl@1371: + { mgl@1371: + rtx reg, src_reg, scan; mgl@1371: + enum machine_mode mode; mgl@1371: + int unused_cast; mgl@1371: + rtx label_ref; mgl@1371: + mgl@1371: + if (avr32_insn_is_cast (insn) mgl@1371: + && (GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == QImode mgl@1371: + || GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == HImode)) mgl@1371: + { mgl@1371: + mode = GET_MODE (XEXP (SET_SRC (PATTERN (insn)), 0)); mgl@1371: + reg = SET_DEST (PATTERN (insn)); mgl@1371: + src_reg = XEXP (SET_SRC (PATTERN (insn)), 0); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + continue; mgl@1371: + } mgl@1371: + mgl@1371: + unused_cast = false; mgl@1371: + label_ref = NULL_RTX; mgl@1371: + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan)) mgl@1371: + { mgl@1371: + /* Check if we have reached the destination of a simple mgl@1371: + conditional jump which we have already scanned past. If so, mgl@1371: + we can safely continue scanning. */ mgl@1371: + if (LABEL_P (scan) && label_ref != NULL_RTX) mgl@1371: + { mgl@1371: + if (CODE_LABEL_NUMBER (scan) == mgl@1371: + CODE_LABEL_NUMBER (XEXP (label_ref, 0))) mgl@1371: + label_ref = NULL_RTX; mgl@1371: + else mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + if (!INSN_P (scan)) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* For conditional jumps we can manage to keep on scanning if mgl@1371: + we meet the destination label later on before any new jump mgl@1371: + insns occure. */ mgl@1371: + if (GET_CODE (scan) == JUMP_INSN) mgl@1371: + { mgl@1371: + if (any_condjump_p (scan) && label_ref == NULL_RTX) mgl@1371: + label_ref = condjump_label (scan); mgl@1371: + else mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if we have a call and the register is used as an argument. */ mgl@1371: + if (CALL_P (scan) mgl@1371: + && find_reg_fusage (scan, USE, reg) ) mgl@1371: + break; mgl@1371: + mgl@1371: + if (!reg_mentioned_p (reg, PATTERN (scan))) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* Check if casted register is used in this insn */ mgl@1371: + if ((regno_use_in (REGNO (reg), PATTERN (scan)) != NULL_RTX) mgl@1371: + && (GET_MODE (regno_use_in (REGNO (reg), PATTERN (scan))) == mgl@1371: + GET_MODE (reg))) mgl@1371: + { mgl@1371: + /* If not used in the source to the set or in a memory mgl@1371: + expression in the destiantion then the register is used mgl@1371: + as a destination and is really dead. */ mgl@1371: + if (single_set (scan) mgl@1371: + && GET_CODE (PATTERN (scan)) == SET mgl@1371: + && REG_P (SET_DEST (PATTERN (scan))) mgl@1371: + && !regno_use_in (REGNO (reg), SET_SRC (PATTERN (scan))) mgl@1371: + && label_ref == NULL_RTX) mgl@1371: + { mgl@1371: + unused_cast = true; mgl@1371: + } mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if register is dead or set in this insn */ mgl@1371: + if (dead_or_set_p (scan, reg)) mgl@1371: + { mgl@1371: + unused_cast = true; mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if we have unresolved conditional jumps */ mgl@1371: + if (label_ref != NULL_RTX) mgl@1371: + continue; mgl@1371: + mgl@1371: + if (unused_cast) mgl@1371: + { mgl@1371: + if (REGNO (reg) == REGNO (XEXP (SET_SRC (PATTERN (insn)), 0))) mgl@1371: + { mgl@1371: + /* One operand cast, safe to delete */ mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; INSN %i removed, casted register %i value not used.\n", mgl@1371: + INSN_UID (insn), REGNO (reg)); mgl@1371: + } mgl@1371: + SET_INSN_DELETED (insn); mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (insn) = -1; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Two operand cast, which really could be substituted with mgl@1371: + a move, if the source register is dead after the cast mgl@1371: + insn and then the insn which sets the source register mgl@1371: + could instead directly set the destination register for mgl@1371: + the cast. As long as there are no insns in between which mgl@1371: + uses the register. */ mgl@1371: + rtx link = NULL_RTX; mgl@1371: + rtx set; mgl@1371: + rtx src_reg = XEXP (SET_SRC (PATTERN (insn)), 0); mgl@1371: + unused_cast = false; mgl@1371: + mgl@1371: + if (!find_reg_note (insn, REG_DEAD, src_reg)) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* Search for the insn which sets the source register */ mgl@1371: + for (link = LOG_LINKS (insn); link; link = XEXP (link, 1)) mgl@1371: + { mgl@1371: + if (REG_NOTE_KIND (link) != 0) mgl@1371: + continue; mgl@1371: + set = single_set (XEXP (link, 0)); mgl@1371: + if (set && rtx_equal_p (src_reg, SET_DEST (set))) mgl@1371: + { mgl@1371: + link = XEXP (link, 0); mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + /* Found no link or link is a call insn where we can not mgl@1371: + change the destination register */ mgl@1371: + if (link == NULL_RTX || CALL_P (link)) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* Scan through all insn between link and insn */ mgl@1371: + for (scan = NEXT_INSN (link); scan; scan = NEXT_INSN (scan)) mgl@1371: + { mgl@1371: + /* Don't try to trace forward past a CODE_LABEL if we mgl@1371: + haven't seen INSN yet. Ordinarily, we will only mgl@1371: + find the setting insn in LOG_LINKS if it is in the mgl@1371: + same basic block. However, cross-jumping can insert mgl@1371: + code labels in between the load and the call, and mgl@1371: + can result in situations where a single call insn mgl@1371: + may have two targets depending on where we came mgl@1371: + from. */ mgl@1371: + mgl@1371: + if (GET_CODE (scan) == CODE_LABEL) mgl@1371: + break; mgl@1371: + mgl@1371: + if (!INSN_P (scan)) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* Don't try to trace forward past a JUMP. To optimize mgl@1371: + safely, we would have to check that all the mgl@1371: + instructions at the jump destination did not use REG. mgl@1371: + */ mgl@1371: + mgl@1371: + if (GET_CODE (scan) == JUMP_INSN) mgl@1371: + { mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + if (!reg_mentioned_p (src_reg, PATTERN (scan))) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* We have reached the cast insn */ mgl@1371: + if (scan == insn) mgl@1371: + { mgl@1371: + /* We can remove cast and replace the destination mgl@1371: + register of the link insn with the destination mgl@1371: + of the cast */ mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; INSN %i removed, casted value unused. " mgl@1371: + "Destination of removed cast operation: register %i, folded into INSN %i.\n", mgl@1371: + INSN_UID (insn), REGNO (reg), mgl@1371: + INSN_UID (link)); mgl@1371: + } mgl@1371: + /* Update link insn */ mgl@1371: + SET_DEST (PATTERN (link)) = mgl@1371: + gen_rtx_REG (mode, REGNO (reg)); mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (link) = -1; mgl@1371: + mgl@1371: + /* Delete insn */ mgl@1371: + SET_INSN_DELETED (insn); mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (insn) = -1; mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0))) mgl@1371: + { mgl@1371: + mgl@1371: + /* Scan through all insns looking for shifted add operations */ mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Deleting redundant shifted add operations:\n"); mgl@1371: + } mgl@1371: + for (insn = first; insn; insn = NEXT_INSN (insn)) mgl@1371: + { mgl@1371: + rtx reg, mem_expr, scan, op0, op1; mgl@1371: + int add_only_used_as_pointer; mgl@1371: + mgl@1371: + if (INSN_P (insn) mgl@1371: + && GET_CODE (PATTERN (insn)) == SET mgl@1371: + && GET_CODE (SET_SRC (PATTERN (insn))) == PLUS mgl@1371: + && (GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == MULT mgl@1371: + || GET_CODE (XEXP (SET_SRC (PATTERN (insn)), 0)) == ASHIFT) mgl@1371: + && GET_CODE (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 1)) == mgl@1371: + CONST_INT && REG_P (SET_DEST (PATTERN (insn))) mgl@1371: + && REG_P (XEXP (SET_SRC (PATTERN (insn)), 1)) mgl@1371: + && REG_P (XEXP (XEXP (SET_SRC (PATTERN (insn)), 0), 0))) mgl@1371: + { mgl@1371: + reg = SET_DEST (PATTERN (insn)); mgl@1371: + mem_expr = SET_SRC (PATTERN (insn)); mgl@1371: + op0 = XEXP (XEXP (mem_expr, 0), 0); mgl@1371: + op1 = XEXP (mem_expr, 1); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + continue; mgl@1371: + } mgl@1371: + mgl@1371: + /* Scan forward the check if the result of the shifted add mgl@1371: + operation is only used as an address in memory operations and mgl@1371: + that the operands to the shifted add are not clobbered. */ mgl@1371: + add_only_used_as_pointer = false; mgl@1371: + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan)) mgl@1371: + { mgl@1371: + if (!INSN_P (scan)) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* Don't try to trace forward past a JUMP or CALL. To optimize mgl@1371: + safely, we would have to check that all the instructions at mgl@1371: + the jump destination did not use REG. */ mgl@1371: + mgl@1371: + if (GET_CODE (scan) == JUMP_INSN) mgl@1371: + { mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + /* If used in a call insn then we cannot optimize it away */ mgl@1371: + if (CALL_P (scan) && find_regno_fusage (scan, USE, REGNO (reg))) mgl@1371: + break; mgl@1371: + mgl@1371: + /* If any of the operands of the shifted add are clobbered we mgl@1371: + cannot optimize the shifted adda away */ mgl@1371: + if ((reg_set_p (op0, scan) && (REGNO (op0) != REGNO (reg))) mgl@1371: + || (reg_set_p (op1, scan) && (REGNO (op1) != REGNO (reg)))) mgl@1371: + break; mgl@1371: + mgl@1371: + if (!reg_mentioned_p (reg, PATTERN (scan))) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* If used any other place than as a pointer or as the mgl@1371: + destination register we failed */ mgl@1371: + if (!(single_set (scan) mgl@1371: + && GET_CODE (PATTERN (scan)) == SET mgl@1371: + && ((MEM_P (SET_DEST (PATTERN (scan))) mgl@1371: + && REG_P (XEXP (SET_DEST (PATTERN (scan)), 0)) mgl@1371: + && REGNO (XEXP (SET_DEST (PATTERN (scan)), 0)) == REGNO (reg)) mgl@1371: + || (MEM_P (SET_SRC (PATTERN (scan))) mgl@1371: + && REG_P (XEXP (SET_SRC (PATTERN (scan)), 0)) mgl@1371: + && REGNO (XEXP mgl@1371: + (SET_SRC (PATTERN (scan)), 0)) == REGNO (reg)))) mgl@1371: + && !(GET_CODE (PATTERN (scan)) == SET mgl@1371: + && REG_P (SET_DEST (PATTERN (scan))) mgl@1371: + && !regno_use_in (REGNO (reg), mgl@1371: + SET_SRC (PATTERN (scan))))) mgl@1371: + break; mgl@1371: + mgl@1371: + /* We cannot replace the pointer in TImode insns mgl@1371: + as these has a differene addressing mode than the other mgl@1371: + memory insns. */ mgl@1371: + if ( GET_MODE (SET_DEST (PATTERN (scan))) == TImode ) mgl@1371: + break; mgl@1371: + mgl@1371: + /* Check if register is dead or set in this insn */ mgl@1371: + if (dead_or_set_p (scan, reg)) mgl@1371: + { mgl@1371: + add_only_used_as_pointer = true; mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + if (add_only_used_as_pointer) mgl@1371: + { mgl@1371: + /* Lets delete the add insn and replace all memory references mgl@1371: + which uses the pointer with the full expression. */ mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Deleting INSN %i since address expression can be folded into all " mgl@1371: + "memory references using this expression\n", mgl@1371: + INSN_UID (insn)); mgl@1371: + } mgl@1371: + SET_INSN_DELETED (insn); mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (insn) = -1; mgl@1371: + mgl@1371: + for (scan = NEXT_INSN (insn); scan; scan = NEXT_INSN (scan)) mgl@1371: + { mgl@1371: + if (!INSN_P (scan)) mgl@1371: + continue; mgl@1371: + mgl@1371: + if (!reg_mentioned_p (reg, PATTERN (scan))) mgl@1371: + continue; mgl@1371: + mgl@1371: + /* If used any other place than as a pointer or as the mgl@1371: + destination register we failed */ mgl@1371: + if ((single_set (scan) mgl@1371: + && GET_CODE (PATTERN (scan)) == SET mgl@1371: + && ((MEM_P (SET_DEST (PATTERN (scan))) mgl@1371: + && REG_P (XEXP (SET_DEST (PATTERN (scan)), 0)) mgl@1371: + && REGNO (XEXP (SET_DEST (PATTERN (scan)), 0)) == mgl@1371: + REGNO (reg)) || (MEM_P (SET_SRC (PATTERN (scan))) mgl@1371: + && mgl@1371: + REG_P (XEXP mgl@1371: + (SET_SRC (PATTERN (scan)), mgl@1371: + 0)) mgl@1371: + && mgl@1371: + REGNO (XEXP mgl@1371: + (SET_SRC (PATTERN (scan)), mgl@1371: + 0)) == REGNO (reg))))) mgl@1371: + { mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Register %i replaced by indexed address in INSN %i\n", mgl@1371: + REGNO (reg), INSN_UID (scan)); mgl@1371: + } mgl@1371: + if (MEM_P (SET_DEST (PATTERN (scan)))) mgl@1371: + XEXP (SET_DEST (PATTERN (scan)), 0) = mem_expr; mgl@1371: + else mgl@1371: + XEXP (SET_SRC (PATTERN (scan)), 0) = mem_expr; mgl@1371: + } mgl@1371: + mgl@1371: + /* Check if register is dead or set in this insn */ mgl@1371: + if (dead_or_set_p (scan, reg)) mgl@1371: + { mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + if (TARGET_MD_REORG_OPTIMIZATION && (optimize_size || (optimize > 0))) mgl@1371: + { mgl@1371: + mgl@1371: + /* Scan through all insns looking for conditional register to mgl@1371: + register move operations */ mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Folding redundant conditional move operations:\n"); mgl@1371: + } mgl@1371: + for (insn = first; insn; insn = next_nonnote_insn (insn)) mgl@1371: + { mgl@1371: + rtx src_reg, dst_reg, scan, test; mgl@1371: + mgl@1371: + if (INSN_P (insn) mgl@1371: + && GET_CODE (PATTERN (insn)) == COND_EXEC mgl@1371: + && GET_CODE (COND_EXEC_CODE (PATTERN (insn))) == SET mgl@1371: + && REG_P (SET_SRC (COND_EXEC_CODE (PATTERN (insn)))) mgl@1371: + && REG_P (SET_DEST (COND_EXEC_CODE (PATTERN (insn)))) mgl@1371: + && find_reg_note (insn, REG_DEAD, SET_SRC (COND_EXEC_CODE (PATTERN (insn))))) mgl@1371: + { mgl@1371: + src_reg = SET_SRC (COND_EXEC_CODE (PATTERN (insn))); mgl@1371: + dst_reg = SET_DEST (COND_EXEC_CODE (PATTERN (insn))); mgl@1371: + test = COND_EXEC_TEST (PATTERN (insn)); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + continue; mgl@1371: + } mgl@1371: + mgl@1371: + /* Scan backward through the rest of insns in this if-then or if-else mgl@1371: + block and check if we can fold the move into another of the conditional mgl@1371: + insns in the same block. */ mgl@1371: + scan = prev_nonnote_insn (insn); mgl@1371: + while (INSN_P (scan) mgl@1371: + && GET_CODE (PATTERN (scan)) == COND_EXEC mgl@1371: + && rtx_equal_p (COND_EXEC_TEST (PATTERN (scan)), test)) mgl@1371: + { mgl@1371: + rtx pattern = COND_EXEC_CODE (PATTERN (scan)); mgl@1371: + if ( GET_CODE (pattern) == PARALLEL ) mgl@1371: + pattern = XVECEXP (pattern, 0, 0); mgl@1371: + mgl@1371: + if ( reg_set_p (src_reg, pattern) ) mgl@1371: + { mgl@1371: + /* Fold in the destination register for the cond. move mgl@1371: + into this insn. */ mgl@1371: + SET_DEST (pattern) = dst_reg; mgl@1371: + if (dump_file) mgl@1371: + { mgl@1371: + fprintf (dump_file, mgl@1371: + ";; Deleting INSN %i since this operation can be folded into INSN %i\n", mgl@1371: + INSN_UID (insn), INSN_UID (scan)); mgl@1371: + } mgl@1371: + mgl@1371: + /* Scan and check if any of the insns in between uses the src_reg. We mgl@1371: + must then replace it with the dst_reg. */ mgl@1371: + while ( (scan = next_nonnote_insn (scan)) != insn ){ mgl@1371: + avr32_replace_reg (scan, src_reg, dst_reg); mgl@1371: + } mgl@1371: + /* Delete the insn. */ mgl@1371: + SET_INSN_DELETED (insn); mgl@1371: + mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (insn) = -1; mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + /* If the destination register is used but not set in this insn mgl@1371: + we cannot fold. */ mgl@1371: + if ( reg_mentioned_p (dst_reg, pattern) ) mgl@1371: + break; mgl@1371: + mgl@1371: + scan = prev_nonnote_insn (scan); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: +} mgl@1371: + mgl@1371: +/* Exported to toplev.c. mgl@1371: + mgl@1371: + Do a final pass over the function, just before delayed branch mgl@1371: + scheduling. */ mgl@1371: + mgl@1371: +static void mgl@1371: +avr32_reorg (void) mgl@1371: +{ mgl@1371: + rtx insn; mgl@1371: + HOST_WIDE_INT address = 0; mgl@1371: + Mfix *fix; mgl@1371: + mgl@1371: + minipool_fix_head = minipool_fix_tail = NULL; mgl@1371: + mgl@1371: + /* The first insn must always be a note, or the code below won't scan it mgl@1371: + properly. */ mgl@1371: + insn = get_insns (); mgl@1371: + if (GET_CODE (insn) != NOTE) mgl@1371: + abort (); mgl@1371: + mgl@1371: + /* Scan all the insns and record the operands that will need fixing. */ mgl@1371: + for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) mgl@1371: + { mgl@1371: + if (GET_CODE (insn) == BARRIER) mgl@1371: + push_minipool_barrier (insn, address); mgl@1371: + else if (INSN_P (insn)) mgl@1371: + { mgl@1371: + rtx table; mgl@1371: + mgl@1371: + note_invalid_constants (insn, address, true); mgl@1371: + address += get_attr_length (insn); mgl@1371: + mgl@1371: + /* If the insn is a vector jump, add the size of the table and skip mgl@1371: + the table. */ mgl@1371: + if ((table = is_jump_table (insn)) != NULL) mgl@1371: + { mgl@1371: + address += get_jump_table_size (table); mgl@1371: + insn = table; mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + fix = minipool_fix_head; mgl@1371: + mgl@1371: + /* Now scan the fixups and perform the required changes. */ mgl@1371: + while (fix) mgl@1371: + { mgl@1371: + Mfix *ftmp; mgl@1371: + Mfix *fdel; mgl@1371: + Mfix *last_added_fix; mgl@1371: + Mfix *last_barrier = NULL; mgl@1371: + Mfix *this_fix; mgl@1371: + mgl@1371: + /* Skip any further barriers before the next fix. */ mgl@1371: + while (fix && GET_CODE (fix->insn) == BARRIER) mgl@1371: + fix = fix->next; mgl@1371: + mgl@1371: + /* No more fixes. */ mgl@1371: + if (fix == NULL) mgl@1371: + break; mgl@1371: + mgl@1371: + last_added_fix = NULL; mgl@1371: + mgl@1371: + for (ftmp = fix; ftmp; ftmp = ftmp->next) mgl@1371: + { mgl@1371: + if (GET_CODE (ftmp->insn) == BARRIER) mgl@1371: + { mgl@1371: + if (ftmp->address >= minipool_vector_head->max_address) mgl@1371: + break; mgl@1371: + mgl@1371: + last_barrier = ftmp; mgl@1371: + } mgl@1371: + else if ((ftmp->minipool = add_minipool_forward_ref (ftmp)) == NULL) mgl@1371: + break; mgl@1371: + mgl@1371: + last_added_fix = ftmp; /* Keep track of the last fix added. mgl@1371: + */ mgl@1371: + } mgl@1371: + mgl@1371: + /* If we found a barrier, drop back to that; any fixes that we could mgl@1371: + have reached but come after the barrier will now go in the next mgl@1371: + mini-pool. */ mgl@1371: + if (last_barrier != NULL) mgl@1371: + { mgl@1371: + /* Reduce the refcount for those fixes that won't go into this pool mgl@1371: + after all. */ mgl@1371: + for (fdel = last_barrier->next; mgl@1371: + fdel && fdel != ftmp; fdel = fdel->next) mgl@1371: + { mgl@1371: + fdel->minipool->refcount--; mgl@1371: + fdel->minipool = NULL; mgl@1371: + } mgl@1371: + mgl@1371: + ftmp = last_barrier; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* ftmp is first fix that we can't fit into this pool and there no mgl@1371: + natural barriers that we could use. Insert a new barrier in the mgl@1371: + code somewhere between the previous fix and this one, and mgl@1371: + arrange to jump around it. */ mgl@1371: + HOST_WIDE_INT max_address; mgl@1371: + mgl@1371: + /* The last item on the list of fixes must be a barrier, so we can mgl@1371: + never run off the end of the list of fixes without last_barrier mgl@1371: + being set. */ mgl@1371: + if (ftmp == NULL) mgl@1371: + abort (); mgl@1371: + mgl@1371: + max_address = minipool_vector_head->max_address; mgl@1371: + /* Check that there isn't another fix that is in range that we mgl@1371: + couldn't fit into this pool because the pool was already too mgl@1371: + large: we need to put the pool before such an instruction. */ mgl@1371: + if (ftmp->address < max_address) mgl@1371: + max_address = ftmp->address; mgl@1371: + mgl@1371: + last_barrier = create_fix_barrier (last_added_fix, max_address); mgl@1371: + } mgl@1371: + mgl@1371: + assign_minipool_offsets (last_barrier); mgl@1371: + mgl@1371: + while (ftmp) mgl@1371: + { mgl@1371: + if (GET_CODE (ftmp->insn) != BARRIER mgl@1371: + && ((ftmp->minipool = add_minipool_backward_ref (ftmp)) mgl@1371: + == NULL)) mgl@1371: + break; mgl@1371: + mgl@1371: + ftmp = ftmp->next; mgl@1371: + } mgl@1371: + mgl@1371: + /* Scan over the fixes we have identified for this pool, fixing them up mgl@1371: + and adding the constants to the pool itself. */ mgl@1371: + for (this_fix = fix; this_fix && ftmp != this_fix; mgl@1371: + this_fix = this_fix->next) mgl@1371: + if (GET_CODE (this_fix->insn) != BARRIER mgl@1371: + /* Do nothing for entries present just to force the insertion of mgl@1371: + a minipool. */ mgl@1371: + && !IS_FORCE_MINIPOOL (this_fix->value)) mgl@1371: + { mgl@1371: + rtx addr = plus_constant (gen_rtx_LABEL_REF (VOIDmode, mgl@1371: + minipool_vector_label), mgl@1371: + this_fix->minipool->offset); mgl@1371: + *this_fix->loc = gen_rtx_MEM (this_fix->mode, addr); mgl@1371: + } mgl@1371: + mgl@1371: + dump_minipool (last_barrier->insn); mgl@1371: + fix = ftmp; mgl@1371: + } mgl@1371: + mgl@1371: + /* Free the minipool memory. */ mgl@1371: + obstack_free (&minipool_obstack, minipool_startobj); mgl@1371: + mgl@1371: + avr32_reorg_optimization (); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Hook for doing some final scanning of instructions. Does nothing yet...*/ mgl@1371: +void mgl@1371: +avr32_final_prescan_insn (rtx insn ATTRIBUTE_UNUSED, mgl@1371: + rtx * opvec ATTRIBUTE_UNUSED, mgl@1371: + int noperands ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + return; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Function for changing the condition on the next instruction, mgl@1371: + should be used when emmiting compare instructions and mgl@1371: + the condition of the next instruction needs to change. mgl@1371: +*/ mgl@1371: +int mgl@1371: +set_next_insn_cond (rtx cur_insn, rtx new_cond) mgl@1371: +{ mgl@1371: + rtx next_insn = next_nonnote_insn (cur_insn); mgl@1371: + if ((next_insn != NULL_RTX) mgl@1371: + && (INSN_P (next_insn))) mgl@1371: + { mgl@1371: + if ((GET_CODE (PATTERN (next_insn)) == SET) mgl@1371: + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE)) mgl@1371: + { mgl@1371: + /* Branch instructions */ mgl@1371: + XEXP (SET_SRC (PATTERN (next_insn)), 0) = new_cond; mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (next_insn) = -1; mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + else if ((GET_CODE (PATTERN (next_insn)) == SET) mgl@1371: + && avr32_comparison_operator (SET_SRC (PATTERN (next_insn)), mgl@1371: + GET_MODE (SET_SRC (PATTERN (next_insn))))) mgl@1371: + { mgl@1371: + /* scc with no compare */ mgl@1371: + SET_SRC (PATTERN (next_insn)) = new_cond; mgl@1371: + /* Force the instruction to be recognized again */ mgl@1371: + INSN_CODE (next_insn) = -1; mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + else if (GET_CODE (PATTERN (next_insn)) == COND_EXEC) mgl@1371: + { mgl@1371: + if ( GET_CODE (new_cond) == UNSPEC ) mgl@1371: + { mgl@1371: + COND_EXEC_TEST (PATTERN (next_insn)) = mgl@1371: + gen_rtx_UNSPEC (CCmode, mgl@1371: + gen_rtvec (2, mgl@1371: + XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 0), mgl@1371: + XEXP (COND_EXEC_TEST (PATTERN (next_insn)), 1)), mgl@1371: + XINT (new_cond, 1)); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + PUT_CODE(COND_EXEC_TEST (PATTERN (next_insn)), GET_CODE(new_cond)); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: +/* Function for obtaining the condition for the next instruction mgl@1371: + after cur_insn. mgl@1371: +*/ mgl@1371: +rtx mgl@1371: +get_next_insn_cond (rtx cur_insn) mgl@1371: +{ mgl@1371: + rtx next_insn = next_nonnote_insn (cur_insn); mgl@1371: + rtx cond = NULL_RTX; mgl@1371: + if (next_insn != NULL_RTX mgl@1371: + && INSN_P (next_insn)) mgl@1371: + { mgl@1371: + if ((GET_CODE (PATTERN (next_insn)) == SET) mgl@1371: + && (GET_CODE (SET_SRC (PATTERN (next_insn))) == IF_THEN_ELSE)) mgl@1371: + { mgl@1371: + /* Branch and cond if then else instructions */ mgl@1371: + cond = XEXP (SET_SRC (PATTERN (next_insn)), 0); mgl@1371: + } mgl@1371: + else if ((GET_CODE (PATTERN (next_insn)) == SET) mgl@1371: + && avr32_comparison_operator (SET_SRC (PATTERN (next_insn)), mgl@1371: + GET_MODE (SET_SRC (PATTERN (next_insn))))) mgl@1371: + { mgl@1371: + /* scc with no compare */ mgl@1371: + cond = SET_SRC (PATTERN (next_insn)); mgl@1371: + } mgl@1371: + else if (GET_CODE (PATTERN (next_insn)) == COND_EXEC) mgl@1371: + { mgl@1371: + cond = COND_EXEC_TEST (PATTERN (next_insn)); mgl@1371: + } mgl@1371: + } mgl@1371: + return cond; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_output_cmp (rtx cond, enum machine_mode mode, rtx op0, rtx op1) mgl@1371: +{ mgl@1371: + mgl@1371: + rtx new_cond = NULL_RTX; mgl@1371: + rtx ops[2]; mgl@1371: + rtx compare_pattern; mgl@1371: + ops[0] = op0; mgl@1371: + ops[1] = op1; mgl@1371: + mgl@1371: + if ( GET_CODE (op0) == AND ) mgl@1371: + compare_pattern = op0; mgl@1371: + else mgl@1371: + compare_pattern = gen_rtx_COMPARE (mode, op0, op1); mgl@1371: + mgl@1371: + new_cond = is_compare_redundant (compare_pattern, cond); mgl@1371: + mgl@1371: + if (new_cond != NULL_RTX) mgl@1371: + return new_cond; mgl@1371: + mgl@1371: + /* Check if we are inserting a bit-load instead of a compare. */ mgl@1371: + if ( GET_CODE (op0) == AND ) mgl@1371: + { mgl@1371: + ops[0] = XEXP (op0, 0); mgl@1371: + ops[1] = XEXP (op0, 1); mgl@1371: + output_asm_insn ("bld\t%0, %p1", ops); mgl@1371: + return cond; mgl@1371: + } mgl@1371: + mgl@1371: + /* Insert compare */ mgl@1371: + switch (mode) mgl@1371: + { mgl@1371: + case QImode: mgl@1371: + output_asm_insn ("cp.b\t%0, %1", ops); mgl@1371: + break; mgl@1371: + case HImode: mgl@1371: + output_asm_insn ("cp.h\t%0, %1", ops); mgl@1371: + break; mgl@1371: + case SImode: mgl@1371: + output_asm_insn ("cp.w\t%0, %1", ops); mgl@1371: + break; mgl@1371: + case DImode: mgl@1371: + if (GET_CODE (op1) != REG) mgl@1371: + output_asm_insn ("cp.w\t%0, %1\ncpc\t%m0", ops); mgl@1371: + else mgl@1371: + output_asm_insn ("cp.w\t%0, %1\ncpc\t%m0, %m1", ops); mgl@1371: + break; mgl@1371: + default: mgl@1371: + internal_error ("Unknown comparison mode"); mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + return cond; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_load_multiple_operation (rtx op, mgl@1371: + enum machine_mode mode ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + int count = XVECLEN (op, 0); mgl@1371: + unsigned int dest_regno; mgl@1371: + rtx src_addr; mgl@1371: + rtx elt; mgl@1371: + int i = 1, base = 0; mgl@1371: + mgl@1371: + if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* Check to see if this might be a write-back. */ mgl@1371: + if (GET_CODE (SET_SRC (elt = XVECEXP (op, 0, 0))) == PLUS) mgl@1371: + { mgl@1371: + i++; mgl@1371: + base = 1; mgl@1371: + mgl@1371: + /* Now check it more carefully. */ mgl@1371: + if (GET_CODE (SET_DEST (elt)) != REG mgl@1371: + || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG mgl@1371: + || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT mgl@1371: + || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) mgl@1371: + return 0; mgl@1371: + } mgl@1371: + mgl@1371: + /* Perform a quick check so we don't blow up below. */ mgl@1371: + if (count <= 1 mgl@1371: + || GET_CODE (XVECEXP (op, 0, i - 1)) != SET mgl@1371: + || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != REG mgl@1371: + || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != UNSPEC) mgl@1371: + return 0; mgl@1371: + mgl@1371: + dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, i - 1))); mgl@1371: + src_addr = XEXP (SET_SRC (XVECEXP (op, 0, i - 1)), 0); mgl@1371: + mgl@1371: + for (; i < count; i++) mgl@1371: + { mgl@1371: + elt = XVECEXP (op, 0, i); mgl@1371: + mgl@1371: + if (GET_CODE (elt) != SET mgl@1371: + || GET_CODE (SET_DEST (elt)) != REG mgl@1371: + || GET_MODE (SET_DEST (elt)) != SImode mgl@1371: + || GET_CODE (SET_SRC (elt)) != UNSPEC) mgl@1371: + return 0; mgl@1371: + } mgl@1371: + mgl@1371: + return 1; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_store_multiple_operation (rtx op, mgl@1371: + enum machine_mode mode ATTRIBUTE_UNUSED) mgl@1371: +{ mgl@1371: + int count = XVECLEN (op, 0); mgl@1371: + int src_regno; mgl@1371: + rtx dest_addr; mgl@1371: + rtx elt; mgl@1371: + int i = 1; mgl@1371: + mgl@1371: + if (count <= 1 || GET_CODE (XVECEXP (op, 0, 0)) != SET) mgl@1371: + return 0; mgl@1371: + mgl@1371: + /* Perform a quick check so we don't blow up below. */ mgl@1371: + if (count <= i mgl@1371: + || GET_CODE (XVECEXP (op, 0, i - 1)) != SET mgl@1371: + || GET_CODE (SET_DEST (XVECEXP (op, 0, i - 1))) != MEM mgl@1371: + || GET_CODE (SET_SRC (XVECEXP (op, 0, i - 1))) != UNSPEC) mgl@1371: + return 0; mgl@1371: + mgl@1371: + src_regno = REGNO (SET_SRC (XVECEXP (op, 0, i - 1))); mgl@1371: + dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, i - 1)), 0); mgl@1371: + mgl@1371: + for (; i < count; i++) mgl@1371: + { mgl@1371: + elt = XVECEXP (op, 0, i); mgl@1371: + mgl@1371: + if (GET_CODE (elt) != SET mgl@1371: + || GET_CODE (SET_DEST (elt)) != MEM mgl@1371: + || GET_MODE (SET_DEST (elt)) != SImode mgl@1371: + || GET_CODE (SET_SRC (elt)) != UNSPEC) mgl@1371: + return 0; mgl@1371: + } mgl@1371: + mgl@1371: + return 1; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_valid_macmac_bypass (rtx insn_out, rtx insn_in) mgl@1371: +{ mgl@1371: + /* Check if they use the same accumulator */ mgl@1371: + if (rtx_equal_p mgl@1371: + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in)))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_valid_mulmac_bypass (rtx insn_out, rtx insn_in) mgl@1371: +{ mgl@1371: + /* mgl@1371: + Check if the mul instruction produces the accumulator for the mac mgl@1371: + instruction. */ mgl@1371: + if (rtx_equal_p mgl@1371: + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in)))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_store_bypass (rtx insn_out, rtx insn_in) mgl@1371: +{ mgl@1371: + /* Only valid bypass if the output result is used as an src in the store mgl@1371: + instruction, NOT if used as a pointer or base. */ mgl@1371: + if (rtx_equal_p mgl@1371: + (SET_DEST (PATTERN (insn_out)), SET_SRC (PATTERN (insn_in)))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_mul_waw_bypass (rtx insn_out, rtx insn_in) mgl@1371: +{ mgl@1371: + /* Check if the register holding the result from the mul instruction is mgl@1371: + used as a result register in the input instruction. */ mgl@1371: + if (rtx_equal_p mgl@1371: + (SET_DEST (PATTERN (insn_out)), SET_DEST (PATTERN (insn_in)))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: +int mgl@1371: +avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in) mgl@1371: +{ mgl@1371: + /* Check if the first loaded word in insn_out is used in insn_in. */ mgl@1371: + rtx dst_reg; mgl@1371: + rtx second_loaded_reg; mgl@1371: + mgl@1371: + /* If this is a double alu operation then the bypass is not valid */ mgl@1371: + if ((get_attr_type (insn_in) == TYPE_ALU mgl@1371: + || get_attr_type (insn_in) == TYPE_ALU2) mgl@1371: + && (GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (insn_out)))) > 4)) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + /* Get the destination register in the load */ mgl@1371: + if (!REG_P (SET_DEST (PATTERN (insn_out)))) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + dst_reg = SET_DEST (PATTERN (insn_out)); mgl@1371: + second_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 1); mgl@1371: + mgl@1371: + if (!reg_mentioned_p (second_loaded_reg, PATTERN (insn_in))) mgl@1371: + return TRUE; mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +int mgl@1371: +avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in) mgl@1371: +{ mgl@1371: + /* mgl@1371: + Check if the two first loaded word in insn_out are used in insn_in. */ mgl@1371: + rtx dst_reg; mgl@1371: + rtx third_loaded_reg, fourth_loaded_reg; mgl@1371: + mgl@1371: + /* Get the destination register in the load */ mgl@1371: + if (!REG_P (SET_DEST (PATTERN (insn_out)))) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + dst_reg = SET_DEST (PATTERN (insn_out)); mgl@1371: + third_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 2); mgl@1371: + fourth_loaded_reg = gen_rtx_REG (SImode, REGNO (dst_reg) + 3); mgl@1371: + mgl@1371: + if (!reg_mentioned_p (third_loaded_reg, PATTERN (insn_in)) mgl@1371: + && !reg_mentioned_p (fourth_loaded_reg, PATTERN (insn_in))) mgl@1371: + { mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + mgl@1371: + return FALSE; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_ifcvt_modify_test (ce_if_block_t *ce_info, mgl@1371: + rtx test ){ mgl@1371: + rtx branch_insn; mgl@1371: + rtx cmp_test; mgl@1371: + rtx compare_op0; mgl@1371: + rtx compare_op1; mgl@1371: + mgl@1371: + mgl@1371: + if ( !ce_info mgl@1371: + || test == NULL_RTX mgl@1371: + || !reg_mentioned_p (cc0_rtx, test)) mgl@1371: + return test; mgl@1371: + mgl@1371: + branch_insn = BB_END (ce_info->test_bb); mgl@1371: + cmp_test = PATTERN(prev_nonnote_insn (branch_insn)); mgl@1371: + mgl@1371: + if (GET_CODE(cmp_test) != SET mgl@1371: + || !CC0_P(XEXP(cmp_test, 0)) ) mgl@1371: + return cmp_test; mgl@1371: + mgl@1371: + if ( GET_CODE(SET_SRC(cmp_test)) == COMPARE ){ mgl@1371: + compare_op0 = XEXP(SET_SRC(cmp_test), 0); mgl@1371: + compare_op1 = XEXP(SET_SRC(cmp_test), 1); mgl@1371: + } else { mgl@1371: + compare_op0 = SET_SRC(cmp_test); mgl@1371: + compare_op1 = const0_rtx; mgl@1371: + } mgl@1371: + mgl@1371: + return gen_rtx_fmt_ee (GET_CODE(test), GET_MODE (compare_op0), mgl@1371: + compare_op0, compare_op1); mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +rtx mgl@1371: +avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, mgl@1371: + rtx pattern, mgl@1371: + rtx insn, mgl@1371: + int *num_true_changes){ mgl@1371: + rtx test = COND_EXEC_TEST(pattern); mgl@1371: + rtx op = COND_EXEC_CODE(pattern); mgl@1371: + rtx cmp_insn; mgl@1371: + rtx cond_exec_insn; mgl@1371: + int inputs_set_outside_ifblock = 1; mgl@1371: + basic_block current_bb = BLOCK_FOR_INSN (insn); mgl@1371: + rtx bb_insn ; mgl@1371: + enum machine_mode mode = GET_MODE (XEXP (op, 0)); mgl@1371: + mgl@1371: + if (CC0_P(XEXP(test, 0))) mgl@1371: + test = avr32_ifcvt_modify_test (ce_info, mgl@1371: + test ); mgl@1371: + mgl@1371: + pattern = gen_rtx_COND_EXEC (VOIDmode, test, op); mgl@1371: + mgl@1371: + if ( !reload_completed ) mgl@1371: + { mgl@1371: + rtx start; mgl@1371: + int num_insns; mgl@1371: + int max_insns = MAX_CONDITIONAL_EXECUTE; mgl@1371: + mgl@1371: + if ( !ce_info ) mgl@1371: + return op; mgl@1371: + mgl@1371: + /* Check if the insn is not suitable for conditional mgl@1371: + execution. */ mgl@1371: + start_sequence (); mgl@1371: + cond_exec_insn = emit_insn (pattern); mgl@1371: + if ( recog_memoized (cond_exec_insn) < 0 mgl@1371: + && !no_new_pseudos ) mgl@1371: + { mgl@1371: + /* Insn is not suitable for conditional execution, try mgl@1371: + to fix it up by using an extra scratch register or mgl@1371: + by pulling the operation outside the if-then-else mgl@1371: + and then emiting a conditional move inside the if-then-else. */ mgl@1371: + end_sequence (); mgl@1371: + if ( GET_CODE (op) != SET mgl@1371: + || !REG_P (SET_DEST (op)) mgl@1371: + || GET_CODE (SET_SRC (op)) == IF_THEN_ELSE mgl@1371: + || GET_MODE_SIZE (mode) > UNITS_PER_WORD ) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + /* Check if any of the input operands to the insn is set inside the mgl@1371: + current block. */ mgl@1371: + if ( current_bb->index == ce_info->then_bb->index ) mgl@1371: + start = PREV_INSN (BB_HEAD (ce_info->then_bb)); mgl@1371: + else mgl@1371: + start = PREV_INSN (BB_HEAD (ce_info->else_bb)); mgl@1371: + mgl@1371: + mgl@1371: + for ( bb_insn = next_nonnote_insn (start); bb_insn != insn; bb_insn = next_nonnote_insn (bb_insn) ) mgl@1371: + { mgl@1371: + rtx set = single_set (bb_insn); mgl@1371: + mgl@1371: + if ( set && reg_mentioned_p (SET_DEST (set), SET_SRC (op))) mgl@1371: + { mgl@1371: + inputs_set_outside_ifblock = 0; mgl@1371: + break; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + cmp_insn = prev_nonnote_insn (BB_END (ce_info->test_bb)); mgl@1371: + mgl@1371: + mgl@1371: + /* Check if we can insert more insns. */ mgl@1371: + num_insns = ( ce_info->num_then_insns + mgl@1371: + ce_info->num_else_insns + mgl@1371: + ce_info->num_cond_clobber_insns + mgl@1371: + ce_info->num_extra_move_insns ); mgl@1371: + mgl@1371: + if ( ce_info->num_else_insns != 0 ) mgl@1371: + max_insns *=2; mgl@1371: + mgl@1371: + if ( num_insns >= max_insns ) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + /* Check if we have an instruction which might be converted to mgl@1371: + conditional form if we give it a scratch register to clobber. */ mgl@1371: + { mgl@1371: + rtx clobber_insn; mgl@1371: + rtx scratch_reg = gen_reg_rtx (mode); mgl@1371: + rtx new_pattern = copy_rtx (pattern); mgl@1371: + rtx set_src = SET_SRC (COND_EXEC_CODE (new_pattern)); mgl@1371: + mgl@1371: + rtx clobber = gen_rtx_CLOBBER (mode, scratch_reg); mgl@1371: + rtx vec[2] = { COND_EXEC_CODE (new_pattern), clobber }; mgl@1371: + COND_EXEC_CODE (new_pattern) = gen_rtx_PARALLEL (mode, gen_rtvec_v (2, vec)); mgl@1371: + mgl@1371: + start_sequence (); mgl@1371: + clobber_insn = emit_insn (new_pattern); mgl@1371: + mgl@1371: + if ( recog_memoized (clobber_insn) >= 0 mgl@1371: + && ( ( GET_RTX_LENGTH (GET_CODE (set_src)) == 2 mgl@1371: + && CONST_INT_P (XEXP (set_src, 1)) mgl@1371: + && avr32_const_ok_for_constraint_p (INTVAL (XEXP (set_src, 1)), 'K', "Ks08") ) mgl@1371: + || !ce_info->else_bb mgl@1371: + || current_bb->index == ce_info->else_bb->index )) mgl@1371: + { mgl@1371: + end_sequence (); mgl@1371: + /* Force the insn to be recognized again. */ mgl@1371: + INSN_CODE (insn) = -1; mgl@1371: + mgl@1371: + /* If this is the first change in this IF-block then mgl@1371: + signal that we have made a change. */ mgl@1371: + if ( ce_info->num_cond_clobber_insns == 0 mgl@1371: + && ce_info->num_extra_move_insns == 0 ) mgl@1371: + *num_true_changes += 1; mgl@1371: + mgl@1371: + ce_info->num_cond_clobber_insns++; mgl@1371: + mgl@1371: + if (dump_file) mgl@1371: + fprintf (dump_file, mgl@1371: + "\nReplacing INSN %d with an insn using a scratch register for later ifcvt passes...\n", mgl@1371: + INSN_UID (insn)); mgl@1371: + mgl@1371: + return COND_EXEC_CODE (new_pattern); mgl@1371: + } mgl@1371: + end_sequence (); mgl@1371: + } mgl@1371: + mgl@1371: + if ( inputs_set_outside_ifblock ) mgl@1371: + { mgl@1371: + /* Check if the insn before the cmp is an and which used mgl@1371: + together with the cmp can be optimized into a bld. If mgl@1371: + so then we should try to put the insn before the and mgl@1371: + so that we can catch the bld peephole. */ mgl@1371: + rtx set; mgl@1371: + rtx insn_before_cmp_insn = prev_nonnote_insn (cmp_insn); mgl@1371: + if (insn_before_cmp_insn mgl@1371: + && (set = single_set (insn_before_cmp_insn)) mgl@1371: + && GET_CODE (SET_SRC (set)) == AND mgl@1371: + && one_bit_set_operand (XEXP (SET_SRC (set), 1), SImode) mgl@1371: + /* Also make sure that the insn does not set any mgl@1371: + of the input operands to the insn we are pulling out. */ mgl@1371: + && !reg_mentioned_p (SET_DEST (set), SET_SRC (op)) ) mgl@1371: + cmp_insn = prev_nonnote_insn (cmp_insn); mgl@1371: + mgl@1371: + /* We can try to put the operation outside the if-then-else mgl@1371: + blocks and insert a move. */ mgl@1371: + if ( !insn_invalid_p (insn) mgl@1371: + /* Do not allow conditional insns to be moved outside the mgl@1371: + if-then-else. */ mgl@1371: + && !reg_mentioned_p (cc0_rtx, insn) mgl@1371: + /* We cannot move memory loads outside of the if-then-else mgl@1371: + since the memory access should not be perfomed if the mgl@1371: + condition is not met. */ mgl@1371: + && !mem_mentioned_p (SET_SRC (op)) ) mgl@1371: + { mgl@1371: + rtx scratch_reg = gen_reg_rtx (mode); mgl@1371: + rtx op_pattern = copy_rtx (op); mgl@1371: + rtx new_insn, seq; mgl@1371: + rtx link, prev_link; mgl@1371: + op = copy_rtx (op); mgl@1371: + /* Emit the operation to a temp reg before the compare, mgl@1371: + and emit a move inside the if-then-else, hoping that the mgl@1371: + whole if-then-else can be converted to conditional mgl@1371: + execution. */ mgl@1371: + SET_DEST (op_pattern) = scratch_reg; mgl@1371: + start_sequence (); mgl@1371: + new_insn = emit_insn (op_pattern); mgl@1371: + seq = get_insns(); mgl@1371: + end_sequence (); mgl@1371: + mgl@1371: + /* Check again that the insn is valid. For some insns the insn might mgl@1371: + become invalid if the destination register is changed. Ie. for mulacc mgl@1371: + operations. */ mgl@1371: + if ( insn_invalid_p (new_insn) ) mgl@1371: + return NULL_RTX; mgl@1371: + mgl@1371: + emit_insn_before_setloc (seq, cmp_insn, INSN_LOCATOR (insn)); mgl@1371: + mgl@1371: + if (dump_file) mgl@1371: + fprintf (dump_file, mgl@1371: + "\nMoving INSN %d out of IF-block by adding INSN %d...\n", mgl@1371: + INSN_UID (insn), INSN_UID (new_insn)); mgl@1371: + mgl@1371: + ce_info->extra_move_insns[ce_info->num_extra_move_insns] = insn; mgl@1371: + ce_info->moved_insns[ce_info->num_extra_move_insns] = new_insn; mgl@1371: + XEXP (op, 1) = scratch_reg; mgl@1371: + /* Force the insn to be recognized again. */ mgl@1371: + INSN_CODE (insn) = -1; mgl@1371: + mgl@1371: + /* Move REG_DEAD notes to the moved insn. */ mgl@1371: + prev_link = NULL_RTX; mgl@1371: + for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) mgl@1371: + { mgl@1371: + if (REG_NOTE_KIND (link) == REG_DEAD) mgl@1371: + { mgl@1371: + /* Add the REG_DEAD note to the new insn. */ mgl@1371: + rtx dead_reg = XEXP (link, 0); mgl@1371: + REG_NOTES (new_insn) = gen_rtx_EXPR_LIST (REG_DEAD, dead_reg, REG_NOTES (new_insn)); mgl@1371: + /* Remove the REG_DEAD note from the insn we convert to a move. */ mgl@1371: + if ( prev_link ) mgl@1371: + XEXP (prev_link, 1) = XEXP (link, 1); mgl@1371: + else mgl@1371: + REG_NOTES (insn) = XEXP (link, 1); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + prev_link = link; mgl@1371: + } mgl@1371: + } mgl@1371: + /* Add a REG_DEAD note to signal that the scratch register is dead. */ mgl@1371: + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_DEAD, scratch_reg, REG_NOTES (insn)); mgl@1371: + mgl@1371: + /* If this is the first change in this IF-block then mgl@1371: + signal that we have made a change. */ mgl@1371: + if ( ce_info->num_cond_clobber_insns == 0 mgl@1371: + && ce_info->num_extra_move_insns == 0 ) mgl@1371: + *num_true_changes += 1; mgl@1371: + mgl@1371: + ce_info->num_extra_move_insns++; mgl@1371: + return op; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + /* We failed to fixup the insns, so this if-then-else can not be made mgl@1371: + conditional. Just return NULL_RTX so that the if-then-else conversion mgl@1371: + for this if-then-else will be cancelled. */ mgl@1371: + return NULL_RTX; mgl@1371: + } mgl@1371: + end_sequence (); mgl@1371: + return op; mgl@1371: + } mgl@1371: + mgl@1371: + /* Signal that we have started if conversion after reload, which means mgl@1371: + that it should be safe to split all the predicable clobber insns which mgl@1371: + did not become cond_exec back into a simpler form if possible. */ mgl@1371: + cfun->machine->ifcvt_after_reload = 1; mgl@1371: + mgl@1371: + return pattern; mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +void mgl@1371: +avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, mgl@1371: + int *num_true_changes) mgl@1371: +{ mgl@1371: + int n; mgl@1371: + mgl@1371: + if ( ce_info->num_extra_move_insns > 0 mgl@1371: + && ce_info->num_cond_clobber_insns == 0) mgl@1371: + /* Signal that we did not do any changes after all. */ mgl@1371: + *num_true_changes -= 1; mgl@1371: + mgl@1371: + /* Remove any inserted move insns. */ mgl@1371: + for ( n = 0; n < ce_info->num_extra_move_insns; n++ ) mgl@1371: + { mgl@1371: + rtx link, prev_link; mgl@1371: + mgl@1371: + /* Remove REG_DEAD note since we are not needing the scratch register anyway. */ mgl@1371: + prev_link = NULL_RTX; mgl@1371: + for (link = REG_NOTES (ce_info->extra_move_insns[n]); link; link = XEXP (link, 1)) mgl@1371: + { mgl@1371: + if (REG_NOTE_KIND (link) == REG_DEAD) mgl@1371: + { mgl@1371: + if ( prev_link ) mgl@1371: + XEXP (prev_link, 1) = XEXP (link, 1); mgl@1371: + else mgl@1371: + REG_NOTES (ce_info->extra_move_insns[n]) = XEXP (link, 1); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + prev_link = link; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + /* Revert all reg_notes for the moved insn. */ mgl@1371: + for (link = REG_NOTES (ce_info->moved_insns[n]); link; link = XEXP (link, 1)) mgl@1371: + { mgl@1371: + REG_NOTES (ce_info->extra_move_insns[n]) = gen_rtx_EXPR_LIST (REG_NOTE_KIND (link), mgl@1371: + XEXP (link, 0), mgl@1371: + REG_NOTES (ce_info->extra_move_insns[n])); mgl@1371: + } mgl@1371: + mgl@1371: + /* Remove the moved insn. */ mgl@1371: + remove_insn ( ce_info->moved_insns[n] ); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +/* Function returning TRUE if INSN with OPERANDS is a splittable mgl@1371: + conditional immediate clobber insn. We assume that the insn is mgl@1371: + already a conditional immediate clobber insns and do not check mgl@1371: + for that. */ mgl@1371: +int mgl@1371: +avr32_cond_imm_clobber_splittable (rtx insn, mgl@1371: + rtx operands[]) mgl@1371: +{ mgl@1371: + if ( (REGNO (operands[0]) != REGNO (operands[1])) mgl@1371: + && (logical_binary_operator (SET_SRC (XVECEXP (PATTERN (insn),0,0)), VOIDmode) mgl@1371: + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == PLUS mgl@1371: + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'I', "Is16")) mgl@1371: + || (GET_CODE (SET_SRC (XVECEXP (PATTERN (insn),0,0))) == MINUS mgl@1371: + && !avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks16"))) ) mgl@1371: + return FALSE; mgl@1371: + mgl@1371: + return TRUE; mgl@1371: +} mgl@1371: + mgl@1371: +/* Function for getting an integer value from a const_int or const_double mgl@1371: + expression regardless of the HOST_WIDE_INT size. Each target cpu word mgl@1371: + will be put into the val array where the LSW will be stored at the lowest mgl@1371: + address and so forth. Assumes that const_expr is either a const_int or mgl@1371: + const_double. Only valid for modes which have sizes that are a multiple mgl@1371: + of the word size. mgl@1371: +*/ mgl@1371: +void mgl@1371: +avr32_get_intval (enum machine_mode mode, mgl@1371: + rtx const_expr, mgl@1371: + HOST_WIDE_INT *val) mgl@1371: +{ mgl@1371: + int words_in_mode = GET_MODE_SIZE (mode)/UNITS_PER_WORD; mgl@1371: + const int words_in_const_int = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; mgl@1371: + mgl@1371: + if ( GET_CODE(const_expr) == CONST_DOUBLE ){ mgl@1371: + HOST_WIDE_INT hi = CONST_DOUBLE_HIGH(const_expr); mgl@1371: + HOST_WIDE_INT lo = CONST_DOUBLE_LOW(const_expr); mgl@1371: + /* Evaluate hi and lo values of const_double. */ mgl@1371: + avr32_get_intval (mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0), mgl@1371: + GEN_INT (lo), mgl@1371: + &val[0]); mgl@1371: + avr32_get_intval (mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0), mgl@1371: + GEN_INT (hi), mgl@1371: + &val[words_in_const_int]); mgl@1371: + } else if ( GET_CODE(const_expr) == CONST_INT ){ mgl@1371: + HOST_WIDE_INT value = INTVAL(const_expr); mgl@1371: + int word; mgl@1371: + for ( word = 0; (word < words_in_mode) && (word < words_in_const_int); word++ ){ mgl@1371: + /* Shift word up to the MSW and shift down again to extract the mgl@1371: + word and sign-extend. */ mgl@1371: + int lshift = (words_in_const_int - word - 1) * BITS_PER_WORD; mgl@1371: + int rshift = (words_in_const_int-1) * BITS_PER_WORD; mgl@1371: + val[word] = (value << lshift) >> rshift; mgl@1371: + } mgl@1371: + mgl@1371: + for ( ; word < words_in_mode; word++ ){ mgl@1371: + /* Just put the sign bits in the remaining words. */ mgl@1371: + val[word] = value < 0 ? -1 : 0; mgl@1371: + } mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +void mgl@1371: +avr32_split_const_expr (enum machine_mode mode, mgl@1371: + enum machine_mode new_mode, mgl@1371: + rtx expr, mgl@1371: + rtx *split_expr) mgl@1371: +{ mgl@1371: + int i, word; mgl@1371: + int words_in_intval = GET_MODE_SIZE (mode)/UNITS_PER_WORD; mgl@1371: + int words_in_split_values = GET_MODE_SIZE (new_mode)/UNITS_PER_WORD; mgl@1371: + const int words_in_const_int = HOST_BITS_PER_WIDE_INT / BITS_PER_WORD; mgl@1371: + HOST_WIDE_INT *val = alloca (words_in_intval * UNITS_PER_WORD); mgl@1371: + mgl@1371: + avr32_get_intval (mode, expr, val); mgl@1371: + mgl@1371: + for ( i=0; i < (words_in_intval/words_in_split_values); i++ ) mgl@1371: + { mgl@1371: + HOST_WIDE_INT value_lo = 0, value_hi = 0; mgl@1371: + for ( word = 0; word < words_in_split_values; word++ ) mgl@1371: + { mgl@1371: + if ( word >= words_in_const_int ) mgl@1371: + value_hi |= ((val[i * words_in_split_values + word] & mgl@1371: + (((HOST_WIDE_INT)1 << BITS_PER_WORD)-1)) mgl@1371: + << (BITS_PER_WORD * (word - words_in_const_int))); mgl@1371: + else mgl@1371: + value_lo |= ((val[i * words_in_split_values + word] & mgl@1371: + (((HOST_WIDE_INT)1 << BITS_PER_WORD)-1)) mgl@1371: + << (BITS_PER_WORD * word)); mgl@1371: + } mgl@1371: + split_expr[i] = immed_double_const(value_lo, value_hi, new_mode); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* Set up library functions to comply to AVR32 ABI */ mgl@1371: + mgl@1371: +static void mgl@1371: +avr32_init_libfuncs (void) mgl@1371: +{ mgl@1371: + /* Convert gcc run-time function names to AVR32 ABI names */ mgl@1371: + mgl@1371: + /* Double-precision floating-point arithmetic. */ mgl@1371: + set_optab_libfunc (neg_optab, DFmode, NULL); mgl@1371: + mgl@1371: + /* Double-precision comparisons. */ mgl@1371: + set_optab_libfunc (eq_optab, DFmode, "__avr32_f64_cmp_eq"); mgl@1371: + set_optab_libfunc (ne_optab, DFmode, NULL); mgl@1371: + set_optab_libfunc (lt_optab, DFmode, "__avr32_f64_cmp_lt"); mgl@1371: + set_optab_libfunc (le_optab, DFmode, NULL); mgl@1371: + set_optab_libfunc (ge_optab, DFmode, "__avr32_f64_cmp_ge"); mgl@1371: + set_optab_libfunc (gt_optab, DFmode, NULL); mgl@1371: + mgl@1371: + /* Single-precision floating-point arithmetic. */ mgl@1371: + set_optab_libfunc (smul_optab, SFmode, "__avr32_f32_mul"); mgl@1371: + set_optab_libfunc (neg_optab, SFmode, NULL); mgl@1371: + mgl@1371: + /* Single-precision comparisons. */ mgl@1371: + set_optab_libfunc (eq_optab, SFmode, "__avr32_f32_cmp_eq"); mgl@1371: + set_optab_libfunc (ne_optab, SFmode, NULL); mgl@1371: + set_optab_libfunc (lt_optab, SFmode, "__avr32_f32_cmp_lt"); mgl@1371: + set_optab_libfunc (le_optab, SFmode, NULL); mgl@1371: + set_optab_libfunc (ge_optab, SFmode, "__avr32_f32_cmp_ge"); mgl@1371: + set_optab_libfunc (gt_optab, SFmode, NULL); mgl@1371: + mgl@1371: + /* Floating-point to integer conversions. */ mgl@1371: + set_conv_libfunc (sfix_optab, SImode, DFmode, "__avr32_f64_to_s32"); mgl@1371: + set_conv_libfunc (ufix_optab, SImode, DFmode, "__avr32_f64_to_u32"); mgl@1371: + set_conv_libfunc (sfix_optab, DImode, DFmode, "__avr32_f64_to_s64"); mgl@1371: + set_conv_libfunc (ufix_optab, DImode, DFmode, "__avr32_f64_to_u64"); mgl@1371: + set_conv_libfunc (sfix_optab, SImode, SFmode, "__avr32_f32_to_s32"); mgl@1371: + set_conv_libfunc (ufix_optab, SImode, SFmode, "__avr32_f32_to_u32"); mgl@1371: + set_conv_libfunc (sfix_optab, DImode, SFmode, "__avr32_f32_to_s64"); mgl@1371: + set_conv_libfunc (ufix_optab, DImode, SFmode, "__avr32_f32_to_u64"); mgl@1371: + mgl@1371: + /* Conversions between floating types. */ mgl@1371: + set_conv_libfunc (trunc_optab, SFmode, DFmode, "__avr32_f64_to_f32"); mgl@1371: + set_conv_libfunc (sext_optab, DFmode, SFmode, "__avr32_f32_to_f64"); mgl@1371: + mgl@1371: + /* Integer to floating-point conversions. Table 8. */ mgl@1371: + set_conv_libfunc (sfloat_optab, DFmode, SImode, "__avr32_s32_to_f64"); mgl@1371: + set_conv_libfunc (sfloat_optab, DFmode, DImode, "__avr32_s64_to_f64"); mgl@1371: + set_conv_libfunc (sfloat_optab, SFmode, SImode, "__avr32_s32_to_f32"); mgl@1371: + set_conv_libfunc (sfloat_optab, SFmode, DImode, "__avr32_s64_to_f32"); mgl@1371: + set_conv_libfunc (ufloat_optab, DFmode, SImode, "__avr32_u32_to_f64"); mgl@1371: + set_conv_libfunc (ufloat_optab, SFmode, SImode, "__avr32_u32_to_f32"); mgl@1371: + /* TODO: Add these to gcc library functions */ mgl@1371: + //set_conv_libfunc (ufloat_optab, DFmode, DImode, NULL); mgl@1371: + //set_conv_libfunc (ufloat_optab, SFmode, DImode, NULL); mgl@1371: + mgl@1371: + /* Long long. Table 9. */ mgl@1371: + set_optab_libfunc (smul_optab, DImode, "__avr32_mul64"); mgl@1371: + set_optab_libfunc (sdiv_optab, DImode, "__avr32_sdiv64"); mgl@1371: + set_optab_libfunc (udiv_optab, DImode, "__avr32_udiv64"); mgl@1371: + set_optab_libfunc (smod_optab, DImode, "__avr32_smod64"); mgl@1371: + set_optab_libfunc (umod_optab, DImode, "__avr32_umod64"); mgl@1371: + set_optab_libfunc (ashl_optab, DImode, "__avr32_lsl64"); mgl@1371: + set_optab_libfunc (lshr_optab, DImode, "__avr32_lsr64"); mgl@1371: + set_optab_libfunc (ashr_optab, DImode, "__avr32_asr64"); mgl@1371: + mgl@1371: + /* Floating point library functions which have fast versions. */ mgl@1371: + if ( TARGET_FAST_FLOAT ) mgl@1371: + { mgl@1371: + set_optab_libfunc (sdiv_optab, DFmode, "__avr32_f64_div_fast"); mgl@1371: + set_optab_libfunc (smul_optab, DFmode, "__avr32_f64_mul_fast"); mgl@1371: + set_optab_libfunc (add_optab, DFmode, "__avr32_f64_add_fast"); mgl@1371: + set_optab_libfunc (sub_optab, DFmode, "__avr32_f64_sub_fast"); mgl@1371: + set_optab_libfunc (add_optab, SFmode, "__avr32_f32_add_fast"); mgl@1371: + set_optab_libfunc (sub_optab, SFmode, "__avr32_f32_sub_fast"); mgl@1371: + set_optab_libfunc (sdiv_optab, SFmode, "__avr32_f32_div_fast"); mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + set_optab_libfunc (sdiv_optab, DFmode, "__avr32_f64_div"); mgl@1371: + set_optab_libfunc (smul_optab, DFmode, "__avr32_f64_mul"); mgl@1371: + set_optab_libfunc (add_optab, DFmode, "__avr32_f64_add"); mgl@1371: + set_optab_libfunc (sub_optab, DFmode, "__avr32_f64_sub"); mgl@1371: + set_optab_libfunc (add_optab, SFmode, "__avr32_f32_add"); mgl@1371: + set_optab_libfunc (sub_optab, SFmode, "__avr32_f32_sub"); mgl@1371: + set_optab_libfunc (sdiv_optab, SFmode, "__avr32_f32_div"); mgl@1371: + } mgl@1371: +} mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32-elf.h mgl@1371: @@ -0,0 +1,84 @@ mgl@1371: +/* mgl@1371: + Elf specific definitions. mgl@1371: + Copyright 2003-2006 Atmel Corporation. mgl@1371: + mgl@1371: + Written by Ronny Pedersen, Atmel Norway, mgl@1371: + mgl@1371: + This file is part of GCC. mgl@1371: + mgl@1371: + This program is free software; you can redistribute it and/or modify mgl@1371: + it under the terms of the GNU General Public License as published by mgl@1371: + the Free Software Foundation; either version 2 of the License, or mgl@1371: + (at your option) any later version. mgl@1371: + mgl@1371: + This program is distributed in the hope that it will be useful, mgl@1371: + but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: + GNU General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; if not, write to the Free Software mgl@1371: + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ mgl@1371: + mgl@1371: + mgl@1371: +/***************************************************************************** mgl@1371: + * Controlling the Compilator Driver, 'gcc' mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* Run-time Target Specification. */ mgl@1371: +#undef TARGET_VERSION mgl@1371: +#define TARGET_VERSION fputs (" (AVR32 GNU with ELF)", stderr); mgl@1371: + mgl@1371: +/* mgl@1371: +Another C string constant used much like LINK_SPEC. The mgl@1371: +difference between the two is that STARTFILE_SPEC is used at mgl@1371: +the very beginning of the command given to the linker. mgl@1371: + mgl@1371: +If this macro is not defined, a default is provided that loads the mgl@1371: +standard C startup file from the usual place. See gcc.c. mgl@1371: +*/ mgl@1371: +#undef STARTFILE_SPEC mgl@1371: +#define STARTFILE_SPEC "crt0%O%s crti%O%s crtbegin%O%s" mgl@1371: + mgl@1371: +#undef LINK_SPEC mgl@1371: +#define LINK_SPEC "%{muse-oscall:--defsym __do_not_use_oscall_coproc__=0} %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}} %{mpart=uc3a3revd:-mavr32elf_uc3a3256s;:%{mpart=*:-mavr32elf_%*}} %{mcpu=*:-mavr32elf_%*}" mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Another C string constant used much like LINK_SPEC. The mgl@1371: +difference between the two is that ENDFILE_SPEC is used at mgl@1371: +the very end of the command given to the linker. mgl@1371: + mgl@1371: +Do not define this macro if it does not need to do anything. mgl@1371: +*/ mgl@1371: +#undef ENDFILE_SPEC mgl@1371: +#define ENDFILE_SPEC "crtend%O%s crtn%O%s" mgl@1371: + mgl@1371: + mgl@1371: +/* Target CPU builtins. */ mgl@1371: +#define TARGET_CPU_CPP_BUILTINS() \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + builtin_define ("__avr32__"); \ mgl@1371: + builtin_define ("__AVR32__"); \ mgl@1371: + builtin_define ("__AVR32_ELF__"); \ mgl@1371: + builtin_define (avr32_part->macro); \ mgl@1371: + builtin_define (avr32_arch->macro); \ mgl@1371: + if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \ mgl@1371: + builtin_define ("__AVR32_AVR32A__"); \ mgl@1371: + else \ mgl@1371: + builtin_define ("__AVR32_AVR32B__"); \ mgl@1371: + if (TARGET_UNALIGNED_WORD) \ mgl@1371: + builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \ mgl@1371: + if (TARGET_SIMD) \ mgl@1371: + builtin_define ("__AVR32_HAS_SIMD__"); \ mgl@1371: + if (TARGET_DSP) \ mgl@1371: + builtin_define ("__AVR32_HAS_DSP__"); \ mgl@1371: + if (TARGET_RMW) \ mgl@1371: + builtin_define ("__AVR32_HAS_RMW__"); \ mgl@1371: + if (TARGET_BRANCH_PRED) \ mgl@1371: + builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \ mgl@1371: + if (TARGET_FAST_FLOAT) \ mgl@1371: + builtin_define ("__AVR32_FAST_FLOAT__"); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32.h mgl@1371: @@ -0,0 +1,3347 @@ mgl@1371: +/* mgl@1371: + Definitions of target machine for AVR32. mgl@1371: + Copyright 2003-2006 Atmel Corporation. mgl@1371: + mgl@1371: + Written by Ronny Pedersen, Atmel Norway, mgl@1371: + Initial porting by Anders �dland. mgl@1371: + mgl@1371: + This file is part of GCC. mgl@1371: + mgl@1371: + This program is free software; you can redistribute it and/or modify mgl@1371: + it under the terms of the GNU General Public License as published by mgl@1371: + the Free Software Foundation; either version 2 of the License, or mgl@1371: + (at your option) any later version. mgl@1371: + mgl@1371: + This program is distributed in the hope that it will be useful, mgl@1371: + but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: + GNU General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; if not, write to the Free Software mgl@1371: + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ mgl@1371: + mgl@1371: +#ifndef GCC_AVR32_H mgl@1371: +#define GCC_AVR32_H mgl@1371: + mgl@1371: + mgl@1371: +#ifndef OBJECT_FORMAT_ELF mgl@1371: +#error avr32.h included before elfos.h mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifndef LOCAL_LABEL_PREFIX mgl@1371: +#define LOCAL_LABEL_PREFIX "." mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifndef SUBTARGET_CPP_SPEC mgl@1371: +#define SUBTARGET_CPP_SPEC "-D__ELF__" mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +extern struct rtx_def *avr32_compare_op0; mgl@1371: +extern struct rtx_def *avr32_compare_op1; mgl@1371: + mgl@1371: + mgl@1371: +extern struct rtx_def *avr32_acc_cache; mgl@1371: + mgl@1371: +/* cache instruction op5 codes */ mgl@1371: +#define AVR32_CACHE_INVALIDATE_ICACHE 1 mgl@1371: + mgl@1371: +/* These bits describe the different types of function supported mgl@1371: + by the AVR32 backend. They are exclusive. ie a function cannot be both a mgl@1371: + normal function and an interworked function, for example. Knowing the mgl@1371: + type of a function is important for determining its prologue and mgl@1371: + epilogue sequences. mgl@1371: + Note value 7 is currently unassigned. Also note that the interrupt mgl@1371: + function types all have bit 2 set, so that they can be tested for easily. mgl@1371: + Note that 0 is deliberately chosen for AVR32_FT_UNKNOWN so that when the mgl@1371: + machine_function structure is initialized (to zero) func_type will mgl@1371: + default to unknown. This will force the first use of avr32_current_func_type mgl@1371: + to call avr32_compute_func_type. */ mgl@1371: +#define AVR32_FT_UNKNOWN 0 /* Type has not yet been determined. mgl@1371: + */ mgl@1371: +#define AVR32_FT_NORMAL 1 /* Your normal, straightforward mgl@1371: + function. */ mgl@1371: +#define AVR32_FT_ACALL 2 /* An acall function. */ mgl@1371: +#define AVR32_FT_EXCEPTION_HANDLER 3 /* A C++ exception handler. */ mgl@1371: +#define AVR32_FT_ISR_FULL 4 /* A fully shadowed interrupt mode. */ mgl@1371: +#define AVR32_FT_ISR_HALF 5 /* A half shadowed interrupt mode. */ mgl@1371: +#define AVR32_FT_ISR_NONE 6 /* No shadow registers. */ mgl@1371: + mgl@1371: +#define AVR32_FT_TYPE_MASK ((1 << 3) - 1) mgl@1371: + mgl@1371: +/* In addition functions can have several type modifiers, mgl@1371: + outlined by these bit masks: */ mgl@1371: +#define AVR32_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR mgl@1371: + and above. */ mgl@1371: +#define AVR32_FT_NAKED (1 << 3) /* No prologue or epilogue. */ mgl@1371: +#define AVR32_FT_VOLATILE (1 << 4) /* Does not return. */ mgl@1371: +#define AVR32_FT_NESTED (1 << 5) /* Embedded inside another mgl@1371: + func. */ mgl@1371: + mgl@1371: +/* Some macros to test these flags. */ mgl@1371: +#define AVR32_FUNC_TYPE(t) (t & AVR32_FT_TYPE_MASK) mgl@1371: +#define IS_INTERRUPT(t) (t & AVR32_FT_INTERRUPT) mgl@1371: +#define IS_VOLATILE(t) (t & AVR32_FT_VOLATILE) mgl@1371: +#define IS_NAKED(t) (t & AVR32_FT_NAKED) mgl@1371: +#define IS_NESTED(t) (t & AVR32_FT_NESTED) mgl@1371: + mgl@1371: +#define SYMBOL_FLAG_RMW_ADDR_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT mgl@1371: +#define SYMBOL_REF_RMW_ADDR(RTX) \ mgl@1371: + ((SYMBOL_REF_FLAGS (RTX) & (1 << SYMBOL_FLAG_RMW_ADDR_SHIFT)) != 0) mgl@1371: + mgl@1371: + mgl@1371: +typedef struct minipool_labels mgl@1371: +GTY ((chain_next ("%h.next"), chain_prev ("%h.prev"))) mgl@1371: +{ mgl@1371: + rtx label; mgl@1371: + struct minipool_labels *prev; mgl@1371: + struct minipool_labels *next; mgl@1371: +} minipool_labels; mgl@1371: + mgl@1371: +/* A C structure for machine-specific, per-function data. mgl@1371: + This is added to the cfun structure. */ mgl@1371: + mgl@1371: +typedef struct machine_function mgl@1371: +GTY (()) mgl@1371: +{ mgl@1371: + /* Records the type of the current function. */ mgl@1371: + unsigned long func_type; mgl@1371: + /* List of minipool labels, use for checking if code label is valid in a mgl@1371: + memory expression */ mgl@1371: + minipool_labels *minipool_label_head; mgl@1371: + minipool_labels *minipool_label_tail; mgl@1371: + int ifcvt_after_reload; mgl@1371: +} machine_function; mgl@1371: + mgl@1371: +/* Initialize data used by insn expanders. This is called from insn_emit, mgl@1371: + once for every function before code is generated. */ mgl@1371: +#define INIT_EXPANDERS avr32_init_expanders () mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * SPECS mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +#ifndef ASM_SPEC mgl@1371: +#define ASM_SPEC "%{fpic:--pic} %{mrelax|O*:%{mno-relax|O0|O1: ;:--linkrelax}} %{march=ucr2nomul:-march=ucr2;:%{march=*:-march=%*}} %{mpart=uc3a3revd:-mpart=uc3a3256s;:%{mpart=*:-mpart=%*}}" mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifndef MULTILIB_DEFAULTS mgl@1371: +#define MULTILIB_DEFAULTS { "march=ap", "" } mgl@1371: +#endif mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Run-time Target Specification mgl@1371: + *****************************************************************************/ mgl@1371: +#ifndef TARGET_VERSION mgl@1371: +#define TARGET_VERSION fprintf(stderr, " (AVR32, GNU assembler syntax)"); mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +/* Part types. Keep this in sync with the order of avr32_part_types in avr32.c*/ mgl@1371: +enum part_type mgl@1371: +{ mgl@1371: + PART_TYPE_AVR32_NONE, mgl@1371: + PART_TYPE_AVR32_AP7000, mgl@1371: + PART_TYPE_AVR32_AP7001, mgl@1371: + PART_TYPE_AVR32_AP7002, mgl@1371: + PART_TYPE_AVR32_AP7200, mgl@1371: + PART_TYPE_AVR32_UC3A0128, mgl@1371: + PART_TYPE_AVR32_UC3A0256, mgl@1371: + PART_TYPE_AVR32_UC3A0512, mgl@1371: + PART_TYPE_AVR32_UC3A0512ES, mgl@1371: + PART_TYPE_AVR32_UC3A1128, mgl@1371: + PART_TYPE_AVR32_UC3A1256, mgl@1371: + PART_TYPE_AVR32_UC3A1512, mgl@1371: + PART_TYPE_AVR32_UC3A1512ES, mgl@1371: + PART_TYPE_AVR32_UC3A3REVD, mgl@1371: + PART_TYPE_AVR32_UC3A364, mgl@1371: + PART_TYPE_AVR32_UC3A364S, mgl@1371: + PART_TYPE_AVR32_UC3A3128, mgl@1371: + PART_TYPE_AVR32_UC3A3128S, mgl@1371: + PART_TYPE_AVR32_UC3A3256, mgl@1371: + PART_TYPE_AVR32_UC3A3256S, mgl@1371: + PART_TYPE_AVR32_UC3B064, mgl@1371: + PART_TYPE_AVR32_UC3B0128, mgl@1371: + PART_TYPE_AVR32_UC3B0256, mgl@1371: + PART_TYPE_AVR32_UC3B0256ES, mgl@1371: + PART_TYPE_AVR32_UC3B164, mgl@1371: + PART_TYPE_AVR32_UC3B1128, mgl@1371: + PART_TYPE_AVR32_UC3B1256, mgl@1371: + PART_TYPE_AVR32_UC3B1256ES mgl@1371: +}; mgl@1371: + mgl@1371: +/* Microarchitectures. */ mgl@1371: +enum microarchitecture_type mgl@1371: +{ mgl@1371: + UARCH_TYPE_AVR32A, mgl@1371: + UARCH_TYPE_AVR32B, mgl@1371: + UARCH_TYPE_NONE mgl@1371: +}; mgl@1371: + mgl@1371: +/* Architectures types which specifies the pipeline. mgl@1371: + Keep this in sync with avr32_arch_types in avr32.c mgl@1371: + and the pipeline attribute in avr32.md */ mgl@1371: +enum architecture_type mgl@1371: +{ mgl@1371: + ARCH_TYPE_AVR32_AP, mgl@1371: + ARCH_TYPE_AVR32_UCR1, mgl@1371: + ARCH_TYPE_AVR32_UCR2, mgl@1371: + ARCH_TYPE_AVR32_UCR2NOMUL, mgl@1371: + ARCH_TYPE_AVR32_NONE mgl@1371: +}; mgl@1371: + mgl@1371: +/* Flag specifying if the cpu has support for DSP instructions.*/ mgl@1371: +#define FLAG_AVR32_HAS_DSP (1 << 0) mgl@1371: +/* Flag specifying if the cpu has support for Read-Modify-Write mgl@1371: + instructions.*/ mgl@1371: +#define FLAG_AVR32_HAS_RMW (1 << 1) mgl@1371: +/* Flag specifying if the cpu has support for SIMD instructions. */ mgl@1371: +#define FLAG_AVR32_HAS_SIMD (1 << 2) mgl@1371: +/* Flag specifying if the cpu has support for unaligned memory word access. */ mgl@1371: +#define FLAG_AVR32_HAS_UNALIGNED_WORD (1 << 3) mgl@1371: +/* Flag specifying if the cpu has support for branch prediction. */ mgl@1371: +#define FLAG_AVR32_HAS_BRANCH_PRED (1 << 4) mgl@1371: +/* Flag specifying if the cpu has support for a return stack. */ mgl@1371: +#define FLAG_AVR32_HAS_RETURN_STACK (1 << 5) mgl@1371: +/* Flag specifying if the cpu has caches. */ mgl@1371: +#define FLAG_AVR32_HAS_CACHES (1 << 6) mgl@1371: +/* Flag specifying if the cpu has support for v2 insns. */ mgl@1371: +#define FLAG_AVR32_HAS_V2_INSNS (1 << 7) mgl@1371: +/* Flag specifying that the cpu has buggy mul insns. */ mgl@1371: +#define FLAG_AVR32_HAS_NO_MUL_INSNS (1 << 8) mgl@1371: + mgl@1371: +/* Structure for holding information about different avr32 CPUs/parts */ mgl@1371: +struct part_type_s mgl@1371: +{ mgl@1371: + const char *const name; mgl@1371: + enum part_type part_type; mgl@1371: + enum architecture_type arch_type; mgl@1371: + /* Must lie outside user's namespace. NULL == no macro. */ mgl@1371: + const char *const macro; mgl@1371: +}; mgl@1371: + mgl@1371: +/* Structure for holding information about different avr32 pipeline mgl@1371: + architectures. */ mgl@1371: +struct arch_type_s mgl@1371: +{ mgl@1371: + const char *const name; mgl@1371: + enum architecture_type arch_type; mgl@1371: + enum microarchitecture_type uarch_type; mgl@1371: + const unsigned long feature_flags; mgl@1371: + /* Must lie outside user's namespace. NULL == no macro. */ mgl@1371: + const char *const macro; mgl@1371: +}; mgl@1371: + mgl@1371: +extern const struct part_type_s *avr32_part; mgl@1371: +extern const struct arch_type_s *avr32_arch; mgl@1371: + mgl@1371: +#define TARGET_SIMD (avr32_arch->feature_flags & FLAG_AVR32_HAS_SIMD) mgl@1371: +#define TARGET_DSP (avr32_arch->feature_flags & FLAG_AVR32_HAS_DSP) mgl@1371: +#define TARGET_RMW (avr32_arch->feature_flags & FLAG_AVR32_HAS_RMW) mgl@1371: +#define TARGET_UNALIGNED_WORD (avr32_arch->feature_flags & FLAG_AVR32_HAS_UNALIGNED_WORD) mgl@1371: +#define TARGET_BRANCH_PRED (avr32_arch->feature_flags & FLAG_AVR32_HAS_BRANCH_PRED) mgl@1371: +#define TARGET_RETURN_STACK (avr32_arch->feature_flags & FLAG_AVR32_HAS_RETURN_STACK) mgl@1371: +#define TARGET_V2_INSNS (avr32_arch->feature_flags & FLAG_AVR32_HAS_V2_INSNS) mgl@1371: +#define TARGET_CACHES (avr32_arch->feature_flags & FLAG_AVR32_HAS_CACHES) mgl@1371: +#define TARGET_NO_MUL_INSNS (avr32_arch->feature_flags & FLAG_AVR32_HAS_NO_MUL_INSNS) mgl@1371: +#define TARGET_ARCH_AP (avr32_arch->arch_type == ARCH_TYPE_AVR32_AP) mgl@1371: +#define TARGET_ARCH_UCR1 (avr32_arch->arch_type == ARCH_TYPE_AVR32_UCR1) mgl@1371: +#define TARGET_ARCH_UCR2 (avr32_arch->arch_type == ARCH_TYPE_AVR32_UCR2) mgl@1371: +#define TARGET_ARCH_UC (TARGET_ARCH_UCR1 || TARGET_ARCH_UCR2) mgl@1371: +#define TARGET_UARCH_AVR32A (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) mgl@1371: +#define TARGET_UARCH_AVR32B (avr32_arch->uarch_type == UARCH_TYPE_AVR32B) mgl@1371: + mgl@1371: +#define CAN_DEBUG_WITHOUT_FP mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Storage Layout mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to have the value 1 if the most significant bit in a mgl@1371: +byte has the lowest number; otherwise define it to have the value zero. mgl@1371: +This means that bit-field instructions count from the most significant mgl@1371: +bit. If the machine has no bit-field instructions, then this must still mgl@1371: +be defined, but it doesn't matter which value it is defined to. This mgl@1371: +macro need not be a constant. mgl@1371: + mgl@1371: +This macro does not affect the way structure fields are packed into mgl@1371: +bytes or words; that is controlled by BYTES_BIG_ENDIAN. mgl@1371: +*/ mgl@1371: +#define BITS_BIG_ENDIAN 0 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to have the value 1 if the most significant byte in a mgl@1371: +word has the lowest number. This macro need not be a constant. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + Data is stored in an big-endian way. mgl@1371: +*/ mgl@1371: +#define BYTES_BIG_ENDIAN 1 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to have the value 1 if, in a multiword object, the mgl@1371: +most significant word has the lowest number. This applies to both mgl@1371: +memory locations and registers; GCC fundamentally assumes that the mgl@1371: +order of words in memory is the same as the order in registers. This mgl@1371: +macro need not be a constant. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + Data is stored in an bin-endian way. mgl@1371: +*/ mgl@1371: +#define WORDS_BIG_ENDIAN 1 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro if WORDS_BIG_ENDIAN is not constant. This must be a mgl@1371: +constant value with the same meaning as WORDS_BIG_ENDIAN, which will be mgl@1371: +used only when compiling libgcc2.c. Typically the value will be set mgl@1371: +based on preprocessor defines. mgl@1371: +*/ mgl@1371: +#define LIBGCC2_WORDS_BIG_ENDIAN WORDS_BIG_ENDIAN mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to have the value 1 if DFmode, XFmode or mgl@1371: +TFmode floating point numbers are stored in memory with the word mgl@1371: +containing the sign bit at the lowest address; otherwise define it to mgl@1371: +have the value 0. This macro need not be a constant. mgl@1371: + mgl@1371: +You need not define this macro if the ordering is the same as for mgl@1371: +multi-word integers. mgl@1371: +*/ mgl@1371: +/* #define FLOAT_WORDS_BIG_ENDIAN 1 */ mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to be the number of bits in an addressable storage mgl@1371: +unit (byte); normally 8. mgl@1371: +*/ mgl@1371: +#define BITS_PER_UNIT 8 mgl@1371: + mgl@1371: +/* mgl@1371: +Number of bits in a word; normally 32. mgl@1371: +*/ mgl@1371: +#define BITS_PER_WORD 32 mgl@1371: + mgl@1371: +/* mgl@1371: +Maximum number of bits in a word. If this is undefined, the default is mgl@1371: +BITS_PER_WORD. Otherwise, it is the constant value that is the mgl@1371: +largest value that BITS_PER_WORD can have at run-time. mgl@1371: +*/ mgl@1371: +/* MAX_BITS_PER_WORD not defined*/ mgl@1371: + mgl@1371: +/* mgl@1371: +Number of storage units in a word; normally 4. mgl@1371: +*/ mgl@1371: +#define UNITS_PER_WORD 4 mgl@1371: + mgl@1371: +/* mgl@1371: +Minimum number of units in a word. If this is undefined, the default is mgl@1371: +UNITS_PER_WORD. Otherwise, it is the constant value that is the mgl@1371: +smallest value that UNITS_PER_WORD can have at run-time. mgl@1371: +*/ mgl@1371: +/* MIN_UNITS_PER_WORD not defined */ mgl@1371: + mgl@1371: +/* mgl@1371: +Width of a pointer, in bits. You must specify a value no wider than the mgl@1371: +width of Pmode. If it is not equal to the width of Pmode, mgl@1371: +you must define POINTERS_EXTEND_UNSIGNED. mgl@1371: +*/ mgl@1371: +#define POINTER_SIZE 32 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is greater than zero if pointers that need to be mgl@1371: +extended from being POINTER_SIZE bits wide to Pmode are to mgl@1371: +be zero-extended and zero if they are to be sign-extended. If the value mgl@1371: +is less then zero then there must be an "ptr_extend" instruction that mgl@1371: +extends a pointer from POINTER_SIZE to Pmode. mgl@1371: + mgl@1371: +You need not define this macro if the POINTER_SIZE is equal mgl@1371: +to the width of Pmode. mgl@1371: +*/ mgl@1371: +/* #define POINTERS_EXTEND_UNSIGNED */ mgl@1371: + mgl@1371: +/* mgl@1371: +A Macro to update M and UNSIGNEDP when an object whose type mgl@1371: +is TYPE and which has the specified mode and signedness is to be mgl@1371: +stored in a register. This macro is only called when TYPE is a mgl@1371: +scalar type. mgl@1371: + mgl@1371: +On most RISC machines, which only have operations that operate on a full mgl@1371: +register, define this macro to set M to word_mode if mgl@1371: +M is an integer mode narrower than BITS_PER_WORD. In most mgl@1371: +cases, only integer modes should be widened because wider-precision mgl@1371: +floating-point operations are usually more expensive than their narrower mgl@1371: +counterparts. mgl@1371: + mgl@1371: +For most machines, the macro definition does not change UNSIGNEDP. mgl@1371: +However, some machines, have instructions that preferentially handle mgl@1371: +either signed or unsigned quantities of certain modes. For example, on mgl@1371: +the DEC Alpha, 32-bit loads from memory and 32-bit add instructions mgl@1371: +sign-extend the result to 64 bits. On such machines, set mgl@1371: +UNSIGNEDP according to which kind of extension is more efficient. mgl@1371: + mgl@1371: +Do not define this macro if it would never modify M. mgl@1371: +*/ mgl@1371: +#define PROMOTE_MODE(M, UNSIGNEDP, TYPE) \ mgl@1371: + { \ mgl@1371: + if (GET_MODE_CLASS (M) == MODE_INT \ mgl@1371: + && GET_MODE_SIZE (M) < 4) \ mgl@1371: + { \ mgl@1371: + if (M == QImode) \ mgl@1371: + UNSIGNEDP = 1; \ mgl@1371: + else if (M == SImode) \ mgl@1371: + UNSIGNEDP = 0; \ mgl@1371: + (M) = SImode; \ mgl@1371: + } \ mgl@1371: + } mgl@1371: + mgl@1371: +#define PROMOTE_FUNCTION_MODE(M, UNSIGNEDP, TYPE) \ mgl@1371: + { \ mgl@1371: + if (GET_MODE_CLASS (M) == MODE_INT \ mgl@1371: + && GET_MODE_SIZE (M) < 4) \ mgl@1371: + { \ mgl@1371: + (M) = SImode; \ mgl@1371: + } \ mgl@1371: + } mgl@1371: + mgl@1371: +/* Define if operations between registers always perform the operation mgl@1371: + on the full register even if a narrower mode is specified. */ mgl@1371: +#define WORD_REGISTER_OPERATIONS mgl@1371: + mgl@1371: +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD mgl@1371: + will either zero-extend or sign-extend. The value of this macro should mgl@1371: + be the code that says which one of the two operations is implicitly mgl@1371: + done, UNKNOWN if not known. */ mgl@1371: +#define LOAD_EXTEND_OP(MODE) \ mgl@1371: + (((MODE) == QImode) ? ZERO_EXTEND \ mgl@1371: + : ((MODE) == HImode) ? SIGN_EXTEND : UNKNOWN) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro if the promotion described by PROMOTE_MODE mgl@1371: +should only be performed for outgoing function arguments or mgl@1371: +function return values, as specified by PROMOTE_FUNCTION_ARGS mgl@1371: +and PROMOTE_FUNCTION_RETURN, respectively. mgl@1371: +*/ mgl@1371: +/* #define PROMOTE_FOR_CALL_ONLY */ mgl@1371: + mgl@1371: +/* mgl@1371: +Normal alignment required for function parameters on the stack, in mgl@1371: +bits. All stack parameters receive at least this much alignment mgl@1371: +regardless of data type. On most machines, this is the same as the mgl@1371: +size of an integer. mgl@1371: +*/ mgl@1371: +#define PARM_BOUNDARY 32 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to the minimum alignment enforced by hardware for the mgl@1371: +stack pointer on this machine. The definition is a C expression for the mgl@1371: +desired alignment (measured in bits). This value is used as a default mgl@1371: +if PREFERRED_STACK_BOUNDARY is not defined. On most machines, mgl@1371: +this should be the same as PARM_BOUNDARY. mgl@1371: +*/ mgl@1371: +#define STACK_BOUNDARY 32 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro if you wish to preserve a certain alignment for the mgl@1371: +stack pointer, greater than what the hardware enforces. The definition mgl@1371: +is a C expression for the desired alignment (measured in bits). This mgl@1371: +macro must evaluate to a value equal to or larger than mgl@1371: +STACK_BOUNDARY. mgl@1371: +*/ mgl@1371: +#define PREFERRED_STACK_BOUNDARY (TARGET_FORCE_DOUBLE_ALIGN ? 64 : 32 ) mgl@1371: + mgl@1371: +/* mgl@1371: +Alignment required for a function entry point, in bits. mgl@1371: +*/ mgl@1371: +#define FUNCTION_BOUNDARY 16 mgl@1371: + mgl@1371: +/* mgl@1371: +Biggest alignment that any data type can require on this machine, in bits. mgl@1371: +*/ mgl@1371: +#define BIGGEST_ALIGNMENT (TARGET_FORCE_DOUBLE_ALIGN ? 64 : 32 ) mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, the smallest alignment, in bits, that can be given to an mgl@1371: +object that can be referenced in one operation, without disturbing any mgl@1371: +nearby object. Normally, this is BITS_PER_UNIT, but may be larger mgl@1371: +on machines that don't have byte or half-word store operations. mgl@1371: +*/ mgl@1371: +#define MINIMUM_ATOMIC_ALIGNMENT BITS_PER_UNIT mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +An integer expression for the size in bits of the largest integer machine mode that mgl@1371: +should actually be used. All integer machine modes of this size or smaller can be mgl@1371: +used for structures and unions with the appropriate sizes. If this macro is undefined, mgl@1371: +GET_MODE_BITSIZE (DImode) is assumed.*/ mgl@1371: +#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (DImode) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression to compute the alignment given to a constant mgl@1371: +that is being placed in memory. CONSTANT is the constant and mgl@1371: +BASIC_ALIGN is the alignment that the object would ordinarily mgl@1371: +have. The value of this macro is used instead of that alignment to mgl@1371: +align the object. mgl@1371: + mgl@1371: +If this macro is not defined, then BASIC_ALIGN is used. mgl@1371: + mgl@1371: +The typical use of this macro is to increase alignment for string mgl@1371: +constants to be word aligned so that strcpy calls that copy mgl@1371: +constants can be done inline. mgl@1371: +*/ mgl@1371: +#define CONSTANT_ALIGNMENT(CONSTANT, BASIC_ALIGN) \ mgl@1371: + ((TREE_CODE(CONSTANT) == STRING_CST) ? BITS_PER_WORD : BASIC_ALIGN) mgl@1371: + mgl@1371: +/* Try to align string to a word. */ mgl@1371: +#define DATA_ALIGNMENT(TYPE, ALIGN) \ mgl@1371: + ({(TREE_CODE (TYPE) == ARRAY_TYPE \ mgl@1371: + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ mgl@1371: + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN));}) mgl@1371: + mgl@1371: +/* Try to align local store strings to a word. */ mgl@1371: +#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ mgl@1371: + ({(TREE_CODE (TYPE) == ARRAY_TYPE \ mgl@1371: + && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ mgl@1371: + && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN));}) mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to be the value 1 if instructions will fail to work mgl@1371: +if given data not on the nominal alignment. If instructions will merely mgl@1371: +go slower in that case, define this macro as 0. mgl@1371: +*/ mgl@1371: +#define STRICT_ALIGNMENT 1 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this if you wish to imitate the way many other C compilers handle mgl@1371: +alignment of bit-fields and the structures that contain them. mgl@1371: + mgl@1371: +The behavior is that the type written for a bit-field (int, mgl@1371: +short, or other integer type) imposes an alignment for the mgl@1371: +entire structure, as if the structure really did contain an ordinary mgl@1371: +field of that type. In addition, the bit-field is placed within the mgl@1371: +structure so that it would fit within such a field, not crossing a mgl@1371: +boundary for it. mgl@1371: + mgl@1371: +Thus, on most machines, a bit-field whose type is written as int mgl@1371: +would not cross a four-byte boundary, and would force four-byte mgl@1371: +alignment for the whole structure. (The alignment used may not be four mgl@1371: +bytes; it is controlled by the other alignment parameters.) mgl@1371: + mgl@1371: +If the macro is defined, its definition should be a C expression; mgl@1371: +a nonzero value for the expression enables this behavior. mgl@1371: + mgl@1371: +Note that if this macro is not defined, or its value is zero, some mgl@1371: +bit-fields may cross more than one alignment boundary. The compiler can mgl@1371: +support such references if there are insv, extv, and mgl@1371: +extzv insns that can directly reference memory. mgl@1371: + mgl@1371: +The other known way of making bit-fields work is to define mgl@1371: +STRUCTURE_SIZE_BOUNDARY as large as BIGGEST_ALIGNMENT. mgl@1371: +Then every structure can be accessed with fullwords. mgl@1371: + mgl@1371: +Unless the machine has bit-field instructions or you define mgl@1371: +STRUCTURE_SIZE_BOUNDARY that way, you must define mgl@1371: +PCC_BITFIELD_TYPE_MATTERS to have a nonzero value. mgl@1371: + mgl@1371: +If your aim is to make GCC use the same conventions for laying out mgl@1371: +bit-fields as are used by another compiler, here is how to investigate mgl@1371: +what the other compiler does. Compile and run this program: mgl@1371: + mgl@1371: +struct foo1 mgl@1371: +{ mgl@1371: + char x; mgl@1371: + char :0; mgl@1371: + char y; mgl@1371: +}; mgl@1371: + mgl@1371: +struct foo2 mgl@1371: +{ mgl@1371: + char x; mgl@1371: + int :0; mgl@1371: + char y; mgl@1371: +}; mgl@1371: + mgl@1371: +main () mgl@1371: +{ mgl@1371: + printf ("Size of foo1 is %d\n", mgl@1371: + sizeof (struct foo1)); mgl@1371: + printf ("Size of foo2 is %d\n", mgl@1371: + sizeof (struct foo2)); mgl@1371: + exit (0); mgl@1371: +} mgl@1371: + mgl@1371: +If this prints 2 and 5, then the compiler's behavior is what you would mgl@1371: +get from PCC_BITFIELD_TYPE_MATTERS. mgl@1371: +*/ mgl@1371: +#define PCC_BITFIELD_TYPE_MATTERS 1 mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Layout of Source Language Data Types mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the type int on the mgl@1371: +target machine. If you don't define this, the default is one word. mgl@1371: +*/ mgl@1371: +#define INT_TYPE_SIZE 32 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the type short on the mgl@1371: +target machine. If you don't define this, the default is half a word. (If mgl@1371: +this would be less than one storage unit, it is rounded up to one unit.) mgl@1371: +*/ mgl@1371: +#define SHORT_TYPE_SIZE 16 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the type long on the mgl@1371: +target machine. If you don't define this, the default is one word. mgl@1371: +*/ mgl@1371: +#define LONG_TYPE_SIZE 32 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the type long long on the mgl@1371: +target machine. If you don't define this, the default is two mgl@1371: +words. If you want to support GNU Ada on your machine, the value of this mgl@1371: +macro must be at least 64. mgl@1371: +*/ mgl@1371: +#define LONG_LONG_TYPE_SIZE 64 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the type char on the mgl@1371: +target machine. If you don't define this, the default is mgl@1371: +BITS_PER_UNIT. mgl@1371: +*/ mgl@1371: +#define CHAR_TYPE_SIZE 8 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the C++ type bool and mgl@1371: +C99 type _Bool on the target machine. If you don't define mgl@1371: +this, and you probably shouldn't, the default is CHAR_TYPE_SIZE. mgl@1371: +*/ mgl@1371: +#define BOOL_TYPE_SIZE 8 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +An expression whose value is 1 or 0, according to whether the type mgl@1371: +char should be signed or unsigned by default. The user can mgl@1371: +always override this default with the options -fsigned-char mgl@1371: +and -funsigned-char. mgl@1371: +*/ mgl@1371: +/* We are using unsigned char */ mgl@1371: +#define DEFAULT_SIGNED_CHAR 0 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for a string describing the name of the data type to use mgl@1371: +for size values. The typedef name size_t is defined using the mgl@1371: +contents of the string. mgl@1371: + mgl@1371: +The string can contain more than one keyword. If so, separate them with mgl@1371: +spaces, and write first any length keyword, then unsigned if mgl@1371: +appropriate, and finally int. The string must exactly match one mgl@1371: +of the data type names defined in the function mgl@1371: +init_decl_processing in the file c-decl.c. You may not mgl@1371: +omit int or change the order - that would cause the compiler to mgl@1371: +crash on startup. mgl@1371: + mgl@1371: +If you don't define this macro, the default is "long unsigned int". mgl@1371: +*/ mgl@1371: +#define SIZE_TYPE "long unsigned int" mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for a string describing the name of the data type to use mgl@1371: +for the result of subtracting two pointers. The typedef name mgl@1371: +ptrdiff_t is defined using the contents of the string. See mgl@1371: +SIZE_TYPE above for more information. mgl@1371: + mgl@1371: +If you don't define this macro, the default is "long int". mgl@1371: +*/ mgl@1371: +#define PTRDIFF_TYPE "long int" mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bits of the data type for wide mgl@1371: +characters. This is used in cpp, which cannot make use of mgl@1371: +WCHAR_TYPE. mgl@1371: +*/ mgl@1371: +#define WCHAR_TYPE_SIZE 32 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for a string describing the name of the data type to mgl@1371: +use for wide characters passed to printf and returned from mgl@1371: +getwc. The typedef name wint_t is defined using the mgl@1371: +contents of the string. See SIZE_TYPE above for more mgl@1371: +information. mgl@1371: + mgl@1371: +If you don't define this macro, the default is "unsigned int". mgl@1371: +*/ mgl@1371: +#define WINT_TYPE "unsigned int" mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for a string describing the name of the data type that mgl@1371: +can represent any value of any standard or extended signed integer type. mgl@1371: +The typedef name intmax_t is defined using the contents of the mgl@1371: +string. See SIZE_TYPE above for more information. mgl@1371: + mgl@1371: +If you don't define this macro, the default is the first of mgl@1371: +"int", "long int", or "long long int" that has as mgl@1371: +much precision as long long int. mgl@1371: +*/ mgl@1371: +#define INTMAX_TYPE "long long int" mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for a string describing the name of the data type that mgl@1371: +can represent any value of any standard or extended unsigned integer mgl@1371: +type. The typedef name uintmax_t is defined using the contents mgl@1371: +of the string. See SIZE_TYPE above for more information. mgl@1371: + mgl@1371: +If you don't define this macro, the default is the first of mgl@1371: +"unsigned int", "long unsigned int", or "long long unsigned int" mgl@1371: +that has as much precision as long long unsigned int. mgl@1371: +*/ mgl@1371: +#define UINTMAX_TYPE "long long unsigned int" mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Register Usage mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* Convert from gcc internal register number to register number mgl@1371: + used in assembly code */ mgl@1371: +#define ASM_REGNUM(reg) (LAST_REGNUM - (reg)) mgl@1371: +#define ASM_FP_REGNUM(reg) (LAST_FP_REGNUM - (reg)) mgl@1371: + mgl@1371: +/* Convert between register number used in assembly to gcc mgl@1371: + internal register number */ mgl@1371: +#define INTERNAL_REGNUM(reg) (LAST_REGNUM - (reg)) mgl@1371: +#define INTERNAL_FP_REGNUM(reg) (LAST_FP_REGNUM - (reg)) mgl@1371: + mgl@1371: +/** Basic Characteristics of Registers **/ mgl@1371: + mgl@1371: +/* mgl@1371: +Number of hardware registers known to the compiler. They receive mgl@1371: +numbers 0 through FIRST_PSEUDO_REGISTER-1; thus, the first mgl@1371: +pseudo register's number really is assigned the number mgl@1371: +FIRST_PSEUDO_REGISTER. mgl@1371: +*/ mgl@1371: +#define FIRST_PSEUDO_REGISTER (LAST_FP_REGNUM + 1) mgl@1371: + mgl@1371: +#define FIRST_REGNUM 0 mgl@1371: +#define LAST_REGNUM 15 mgl@1371: +#define NUM_FP_REGS 16 mgl@1371: +#define FIRST_FP_REGNUM 16 mgl@1371: +#define LAST_FP_REGNUM (16+NUM_FP_REGS-1) mgl@1371: + mgl@1371: +/* mgl@1371: +An initializer that says which registers are used for fixed purposes mgl@1371: +all throughout the compiled code and are therefore not available for mgl@1371: +general allocation. These would include the stack pointer, the frame mgl@1371: +pointer (except on machines where that can be used as a general mgl@1371: +register when no frame pointer is needed), the program counter on mgl@1371: +machines where that is considered one of the addressable registers, mgl@1371: +and any other numbered register with a standard use. mgl@1371: + mgl@1371: +This information is expressed as a sequence of numbers, separated by mgl@1371: +commas and surrounded by braces. The nth number is 1 if mgl@1371: +register n is fixed, 0 otherwise. mgl@1371: + mgl@1371: +The table initialized from this macro, and the table initialized by mgl@1371: +the following one, may be overridden at run time either automatically, mgl@1371: +by the actions of the macro CONDITIONAL_REGISTER_USAGE, or by mgl@1371: +the user with the command options -ffixed-[reg], mgl@1371: +-fcall-used-[reg] and -fcall-saved-[reg]. mgl@1371: +*/ mgl@1371: + mgl@1371: +/* The internal gcc register numbers are reversed mgl@1371: + compared to the real register numbers since mgl@1371: + gcc expects data types stored over multiple mgl@1371: + registers in the register file to be big endian mgl@1371: + if the memory layout is big endian. But this mgl@1371: + is not the case for avr32 so we fake a big mgl@1371: + endian register file. */ mgl@1371: + mgl@1371: +#define FIXED_REGISTERS { \ mgl@1371: + 1, /* Program Counter */ \ mgl@1371: + 0, /* Link Register */ \ mgl@1371: + 1, /* Stack Pointer */ \ mgl@1371: + 0, /* r12 */ \ mgl@1371: + 0, /* r11 */ \ mgl@1371: + 0, /* r10 */ \ mgl@1371: + 0, /* r9 */ \ mgl@1371: + 0, /* r8 */ \ mgl@1371: + 0, /* r7 */ \ mgl@1371: + 0, /* r6 */ \ mgl@1371: + 0, /* r5 */ \ mgl@1371: + 0, /* r4 */ \ mgl@1371: + 0, /* r3 */ \ mgl@1371: + 0, /* r2 */ \ mgl@1371: + 0, /* r1 */ \ mgl@1371: + 0, /* r0 */ \ mgl@1371: + 0, /* f15 */ \ mgl@1371: + 0, /* f14 */ \ mgl@1371: + 0, /* f13 */ \ mgl@1371: + 0, /* f12 */ \ mgl@1371: + 0, /* f11 */ \ mgl@1371: + 0, /* f10 */ \ mgl@1371: + 0, /* f9 */ \ mgl@1371: + 0, /* f8 */ \ mgl@1371: + 0, /* f7 */ \ mgl@1371: + 0, /* f6 */ \ mgl@1371: + 0, /* f5 */ \ mgl@1371: + 0, /* f4 */ \ mgl@1371: + 0, /* f3 */ \ mgl@1371: + 0, /* f2*/ \ mgl@1371: + 0, /* f1 */ \ mgl@1371: + 0 /* f0 */ \ mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: +Like FIXED_REGISTERS but has 1 for each register that is mgl@1371: +clobbered (in general) by function calls as well as for fixed mgl@1371: +registers. This macro therefore identifies the registers that are not mgl@1371: +available for general allocation of values that must live across mgl@1371: +function calls. mgl@1371: + mgl@1371: +If a register has 0 in CALL_USED_REGISTERS, the compiler mgl@1371: +automatically saves it on function entry and restores it on function mgl@1371: +exit, if the register is used within the function. mgl@1371: +*/ mgl@1371: +#define CALL_USED_REGISTERS { \ mgl@1371: + 1, /* Program Counter */ \ mgl@1371: + 0, /* Link Register */ \ mgl@1371: + 1, /* Stack Pointer */ \ mgl@1371: + 1, /* r12 */ \ mgl@1371: + 1, /* r11 */ \ mgl@1371: + 1, /* r10 */ \ mgl@1371: + 1, /* r9 */ \ mgl@1371: + 1, /* r8 */ \ mgl@1371: + 0, /* r7 */ \ mgl@1371: + 0, /* r6 */ \ mgl@1371: + 0, /* r5 */ \ mgl@1371: + 0, /* r4 */ \ mgl@1371: + 0, /* r3 */ \ mgl@1371: + 0, /* r2 */ \ mgl@1371: + 0, /* r1 */ \ mgl@1371: + 0, /* r0 */ \ mgl@1371: + 1, /* f15 */ \ mgl@1371: + 1, /* f14 */ \ mgl@1371: + 1, /* f13 */ \ mgl@1371: + 1, /* f12 */ \ mgl@1371: + 1, /* f11 */ \ mgl@1371: + 1, /* f10 */ \ mgl@1371: + 1, /* f9 */ \ mgl@1371: + 1, /* f8 */ \ mgl@1371: + 0, /* f7 */ \ mgl@1371: + 0, /* f6 */ \ mgl@1371: + 0, /* f5 */ \ mgl@1371: + 0, /* f4 */ \ mgl@1371: + 0, /* f3 */ \ mgl@1371: + 0, /* f2*/ \ mgl@1371: + 0, /* f1*/ \ mgl@1371: + 0, /* f0 */ \ mgl@1371: +} mgl@1371: + mgl@1371: +/* Interrupt functions can only use registers that have already been mgl@1371: + saved by the prologue, even if they would normally be mgl@1371: + call-clobbered. */ mgl@1371: +#define HARD_REGNO_RENAME_OK(SRC, DST) \ mgl@1371: + (! IS_INTERRUPT (cfun->machine->func_type) || \ mgl@1371: + regs_ever_live[DST]) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Zero or more C statements that may conditionally modify five variables mgl@1371: +fixed_regs, call_used_regs, global_regs, mgl@1371: +reg_names, and reg_class_contents, to take into account mgl@1371: +any dependence of these register sets on target flags. The first three mgl@1371: +of these are of type char [] (interpreted as Boolean vectors). mgl@1371: +global_regs is a const char *[], and mgl@1371: +reg_class_contents is a HARD_REG_SET. Before the macro is mgl@1371: +called, fixed_regs, call_used_regs, mgl@1371: +reg_class_contents, and reg_names have been initialized mgl@1371: +from FIXED_REGISTERS, CALL_USED_REGISTERS, mgl@1371: +REG_CLASS_CONTENTS, and REGISTER_NAMES, respectively. mgl@1371: +global_regs has been cleared, and any -ffixed-[reg], mgl@1371: +-fcall-used-[reg] and -fcall-saved-[reg] mgl@1371: +command options have been applied. mgl@1371: + mgl@1371: +You need not define this macro if it has no work to do. mgl@1371: + mgl@1371: +If the usage of an entire class of registers depends on the target mgl@1371: +flags, you may indicate this to GCC by using this macro to modify mgl@1371: +fixed_regs and call_used_regs to 1 for each of the mgl@1371: +registers in the classes which should not be used by GCC. Also define mgl@1371: +the macro REG_CLASS_FROM_LETTER to return NO_REGS if it mgl@1371: +is called with a letter for a class that shouldn't be used. mgl@1371: + mgl@1371: + (However, if this class is not included in GENERAL_REGS and all mgl@1371: +of the insn patterns whose constraints permit this class are mgl@1371: +controlled by target switches, then GCC will automatically avoid using mgl@1371: +these registers when the target switches are opposed to them.) mgl@1371: +*/ mgl@1371: +#define CONDITIONAL_REGISTER_USAGE \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + int regno; \ mgl@1371: + \ mgl@1371: + if (TARGET_SOFT_FLOAT) \ mgl@1371: + { \ mgl@1371: + for (regno = FIRST_FP_REGNUM; \ mgl@1371: + regno <= LAST_FP_REGNUM; ++regno) \ mgl@1371: + fixed_regs[regno] = call_used_regs[regno] = 1; \ mgl@1371: + } \ mgl@1371: + if (flag_pic) \ mgl@1371: + { \ mgl@1371: + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ mgl@1371: + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ mgl@1371: + } \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +If the program counter has a register number, define this as that mgl@1371: +register number. Otherwise, do not define it. mgl@1371: +*/ mgl@1371: + mgl@1371: +#define LAST_AVR32_REGNUM 16 mgl@1371: + mgl@1371: + mgl@1371: +/** Order of Allocation of Registers **/ mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, an initializer for a vector of integers, containing the mgl@1371: +numbers of hard registers in the order in which GCC should prefer mgl@1371: +to use them (from most preferred to least). mgl@1371: + mgl@1371: +If this macro is not defined, registers are used lowest numbered first mgl@1371: +(all else being equal). mgl@1371: + mgl@1371: +One use of this macro is on machines where the highest numbered mgl@1371: +registers must always be saved and the save-multiple-registers mgl@1371: +instruction supports only sequences of consecutive registers. On such mgl@1371: +machines, define REG_ALLOC_ORDER to be an initializer that lists mgl@1371: +the highest numbered allocable register first. mgl@1371: +*/ mgl@1371: +#define REG_ALLOC_ORDER \ mgl@1371: +{ \ mgl@1371: + INTERNAL_REGNUM(8), \ mgl@1371: + INTERNAL_REGNUM(9), \ mgl@1371: + INTERNAL_REGNUM(10), \ mgl@1371: + INTERNAL_REGNUM(11), \ mgl@1371: + INTERNAL_REGNUM(12), \ mgl@1371: + LR_REGNUM, \ mgl@1371: + INTERNAL_REGNUM(7), \ mgl@1371: + INTERNAL_REGNUM(6), \ mgl@1371: + INTERNAL_REGNUM(5), \ mgl@1371: + INTERNAL_REGNUM(4), \ mgl@1371: + INTERNAL_REGNUM(3), \ mgl@1371: + INTERNAL_REGNUM(2), \ mgl@1371: + INTERNAL_REGNUM(1), \ mgl@1371: + INTERNAL_REGNUM(0), \ mgl@1371: + INTERNAL_FP_REGNUM(15), \ mgl@1371: + INTERNAL_FP_REGNUM(14), \ mgl@1371: + INTERNAL_FP_REGNUM(13), \ mgl@1371: + INTERNAL_FP_REGNUM(12), \ mgl@1371: + INTERNAL_FP_REGNUM(11), \ mgl@1371: + INTERNAL_FP_REGNUM(10), \ mgl@1371: + INTERNAL_FP_REGNUM(9), \ mgl@1371: + INTERNAL_FP_REGNUM(8), \ mgl@1371: + INTERNAL_FP_REGNUM(7), \ mgl@1371: + INTERNAL_FP_REGNUM(6), \ mgl@1371: + INTERNAL_FP_REGNUM(5), \ mgl@1371: + INTERNAL_FP_REGNUM(4), \ mgl@1371: + INTERNAL_FP_REGNUM(3), \ mgl@1371: + INTERNAL_FP_REGNUM(2), \ mgl@1371: + INTERNAL_FP_REGNUM(1), \ mgl@1371: + INTERNAL_FP_REGNUM(0), \ mgl@1371: + SP_REGNUM, \ mgl@1371: + PC_REGNUM \ mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/** How Values Fit in Registers **/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the number of consecutive hard registers, starting mgl@1371: +at register number REGNO, required to hold a value of mode mgl@1371: +MODE. mgl@1371: + mgl@1371: +On a machine where all registers are exactly one word, a suitable mgl@1371: +definition of this macro is mgl@1371: + mgl@1371: +#define HARD_REGNO_NREGS(REGNO, MODE) \ mgl@1371: + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) \ mgl@1371: + / UNITS_PER_WORD) mgl@1371: +*/ mgl@1371: +#define HARD_REGNO_NREGS(REGNO, MODE) \ mgl@1371: + ((unsigned int)((GET_MODE_SIZE(MODE) + UNITS_PER_WORD -1 ) / UNITS_PER_WORD)) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if it is permissible to store a value mgl@1371: +of mode MODE in hard register number REGNO (or in several mgl@1371: +registers starting with that one). For a machine where all registers mgl@1371: +are equivalent, a suitable definition is mgl@1371: + mgl@1371: + #define HARD_REGNO_MODE_OK(REGNO, MODE) 1 mgl@1371: + mgl@1371: +You need not include code to check for the numbers of fixed registers, mgl@1371: +because the allocation mechanism considers them to be always occupied. mgl@1371: + mgl@1371: +On some machines, double-precision values must be kept in even/odd mgl@1371: +register pairs. You can implement that by defining this macro to reject mgl@1371: +odd register numbers for such modes. mgl@1371: + mgl@1371: +The minimum requirement for a mode to be OK in a register is that the mgl@1371: +mov[mode] instruction pattern support moves between the mgl@1371: +register and other hard register in the same class and that moving a mgl@1371: +value into the register and back out not alter it. mgl@1371: + mgl@1371: +Since the same instruction used to move word_mode will work for mgl@1371: +all narrower integer modes, it is not necessary on any machine for mgl@1371: +HARD_REGNO_MODE_OK to distinguish between these modes, provided mgl@1371: +you define patterns movhi, etc., to take advantage of this. This mgl@1371: +is useful because of the interaction between HARD_REGNO_MODE_OK mgl@1371: +and MODES_TIEABLE_P; it is very desirable for all integer modes mgl@1371: +to be tieable. mgl@1371: + mgl@1371: +Many machines have special registers for floating point arithmetic. mgl@1371: +Often people assume that floating point machine modes are allowed only mgl@1371: +in floating point registers. This is not true. Any registers that mgl@1371: +can hold integers can safely hold a floating point machine mgl@1371: +mode, whether or not floating arithmetic can be done on it in those mgl@1371: +registers. Integer move instructions can be used to move the values. mgl@1371: + mgl@1371: +On some machines, though, the converse is true: fixed-point machine mgl@1371: +modes may not go in floating registers. This is true if the floating mgl@1371: +registers normalize any value stored in them, because storing a mgl@1371: +non-floating value there would garble it. In this case, mgl@1371: +HARD_REGNO_MODE_OK should reject fixed-point machine modes in mgl@1371: +floating registers. But if the floating registers do not automatically mgl@1371: +normalize, if you can store any bit pattern in one and retrieve it mgl@1371: +unchanged without a trap, then any machine mode may go in a floating mgl@1371: +register, so you can define this macro to say so. mgl@1371: + mgl@1371: +The primary significance of special floating registers is rather that mgl@1371: +they are the registers acceptable in floating point arithmetic mgl@1371: +instructions. However, this is of no concern to mgl@1371: +HARD_REGNO_MODE_OK. You handle it by writing the proper mgl@1371: +constraints for those instructions. mgl@1371: + mgl@1371: +On some machines, the floating registers are especially slow to access, mgl@1371: +so that it is better to store a value in a stack frame than in such a mgl@1371: +register if floating point arithmetic is not being done. As long as the mgl@1371: +floating registers are not in class GENERAL_REGS, they will not mgl@1371: +be used unless some pattern's constraint asks for one. mgl@1371: +*/ mgl@1371: +#define HARD_REGNO_MODE_OK(REGNO, MODE) avr32_hard_regno_mode_ok(REGNO, MODE) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if a value of mode mgl@1371: +MODE1 is accessible in mode MODE2 without copying. mgl@1371: + mgl@1371: +If HARD_REGNO_MODE_OK(R, MODE1) and mgl@1371: +HARD_REGNO_MODE_OK(R, MODE2) are always the same for mgl@1371: +any R, then MODES_TIEABLE_P(MODE1, MODE2) mgl@1371: +should be nonzero. If they differ for any R, you should define mgl@1371: +this macro to return zero unless some other mechanism ensures the mgl@1371: +accessibility of the value in a narrower mode. mgl@1371: + mgl@1371: +You should define this macro to return nonzero in as many cases as mgl@1371: +possible since doing so will allow GCC to perform better register mgl@1371: +allocation. mgl@1371: +*/ mgl@1371: +#define MODES_TIEABLE_P(MODE1, MODE2) \ mgl@1371: + (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Register Classes mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +An enumeral type that must be defined with all the register class names mgl@1371: +as enumeral values. NO_REGS must be first. ALL_REGS mgl@1371: +must be the last register class, followed by one more enumeral value, mgl@1371: +LIM_REG_CLASSES, which is not a register class but rather mgl@1371: +tells how many classes there are. mgl@1371: + mgl@1371: +Each register class has a number, which is the value of casting mgl@1371: +the class name to type int. The number serves as an index mgl@1371: +in many of the tables described below. mgl@1371: +*/ mgl@1371: +enum reg_class mgl@1371: +{ mgl@1371: + NO_REGS, mgl@1371: + GENERAL_REGS, mgl@1371: + FP_REGS, mgl@1371: + ALL_REGS, mgl@1371: + LIM_REG_CLASSES mgl@1371: +}; mgl@1371: + mgl@1371: +/* mgl@1371: +The number of distinct register classes, defined as follows: mgl@1371: + #define N_REG_CLASSES (int) LIM_REG_CLASSES mgl@1371: +*/ mgl@1371: +#define N_REG_CLASSES (int)LIM_REG_CLASSES mgl@1371: + mgl@1371: +/* mgl@1371: +An initializer containing the names of the register classes as C string mgl@1371: +constants. These names are used in writing some of the debugging dumps. mgl@1371: +*/ mgl@1371: +#define REG_CLASS_NAMES \ mgl@1371: +{ \ mgl@1371: + "NO_REGS", \ mgl@1371: + "GENERAL_REGS", \ mgl@1371: + "FLOATING_POINT_REGS", \ mgl@1371: + "ALL_REGS" \ mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: +An initializer containing the contents of the register classes, as integers mgl@1371: +which are bit masks. The nth integer specifies the contents of class mgl@1371: +n. The way the integer mask is interpreted is that mgl@1371: +register r is in the class if mask & (1 << r) is 1. mgl@1371: + mgl@1371: +When the machine has more than 32 registers, an integer does not suffice. mgl@1371: +Then the integers are replaced by sub-initializers, braced groupings containing mgl@1371: +several integers. Each sub-initializer must be suitable as an initializer mgl@1371: +for the type HARD_REG_SET which is defined in hard-reg-set.h. mgl@1371: +In this situation, the first integer in each sub-initializer corresponds to mgl@1371: +registers 0 through 31, the second integer to registers 32 through 63, and mgl@1371: +so on. mgl@1371: +*/ mgl@1371: +#define REG_CLASS_CONTENTS { \ mgl@1371: + {0x00000000}, /* NO_REGS */ \ mgl@1371: + {0x0000FFFF}, /* GENERAL_REGS */ \ mgl@1371: + {0xFFFF0000}, /* FP_REGS */ \ mgl@1371: + {0x7FFFFFFF}, /* ALL_REGS */ \ mgl@1371: +} mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is a register class containing hard register mgl@1371: +REGNO. In general there is more than one such class; choose a class mgl@1371: +which is minimal, meaning that no smaller class also contains the mgl@1371: +register. mgl@1371: +*/ mgl@1371: +#define REGNO_REG_CLASS(REGNO) ((REGNO < 16) ? GENERAL_REGS : FP_REGS) mgl@1371: + mgl@1371: +/* mgl@1371: +A macro whose definition is the name of the class to which a valid mgl@1371: +base register must belong. A base register is one used in an address mgl@1371: +which is the register value plus a displacement. mgl@1371: +*/ mgl@1371: +#define BASE_REG_CLASS GENERAL_REGS mgl@1371: + mgl@1371: +/* mgl@1371: +This is a variation of the BASE_REG_CLASS macro which allows mgl@1371: +the selection of a base register in a mode depenedent manner. If mgl@1371: +mode is VOIDmode then it should return the same value as mgl@1371: +BASE_REG_CLASS. mgl@1371: +*/ mgl@1371: +#define MODE_BASE_REG_CLASS(MODE) BASE_REG_CLASS mgl@1371: + mgl@1371: +/* mgl@1371: +A macro whose definition is the name of the class to which a valid mgl@1371: +index register must belong. An index register is one used in an mgl@1371: +address where its value is either multiplied by a scale factor or mgl@1371: +added to another register (as well as added to a displacement). mgl@1371: +*/ mgl@1371: +#define INDEX_REG_CLASS BASE_REG_CLASS mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which defines the machine-dependent operand constraint mgl@1371: +letters for register classes. If CHAR is such a letter, the mgl@1371: +value should be the register class corresponding to it. Otherwise, mgl@1371: +the value should be NO_REGS. The register letter r, mgl@1371: +corresponding to class GENERAL_REGS, will not be passed mgl@1371: +to this macro; you do not need to handle it. mgl@1371: +*/ mgl@1371: +#define REG_CLASS_FROM_LETTER(CHAR) ((CHAR) == 'f' ? FP_REGS : NO_REGS) mgl@1371: + mgl@1371: + mgl@1371: +/* These assume that REGNO is a hard or pseudo reg number. mgl@1371: + They give nonzero only if REGNO is a hard reg of the suitable class mgl@1371: + or a pseudo reg currently allocated to a suitable hard reg. mgl@1371: + Since they use reg_renumber, they are safe only once reg_renumber mgl@1371: + has been allocated, which happens in local-alloc.c. */ mgl@1371: +#define TEST_REGNO(R, TEST, VALUE) \ mgl@1371: + ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which is nonzero if register number num is suitable for use as a base mgl@1371: +register in operand addresses. It may be either a suitable hard register or a pseudo mgl@1371: +register that has been allocated such a hard register. mgl@1371: +*/ mgl@1371: +#define REGNO_OK_FOR_BASE_P(NUM) TEST_REGNO(NUM, <=, LAST_REGNUM) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which is nonzero if register number NUM is mgl@1371: +suitable for use as an index register in operand addresses. It may be mgl@1371: +either a suitable hard register or a pseudo register that has been mgl@1371: +allocated such a hard register. mgl@1371: + mgl@1371: +The difference between an index register and a base register is that mgl@1371: +the index register may be scaled. If an address involves the sum of mgl@1371: +two registers, neither one of them scaled, then either one may be mgl@1371: +labeled the ``base'' and the other the ``index''; but whichever mgl@1371: +labeling is used must fit the machine's constraints of which registers mgl@1371: +may serve in each capacity. The compiler will try both labelings, mgl@1371: +looking for one that is valid, and will reload one or both registers mgl@1371: +only if neither labeling works. mgl@1371: +*/ mgl@1371: +#define REGNO_OK_FOR_INDEX_P(NUM) TEST_REGNO(NUM, <=, LAST_REGNUM) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that places additional restrictions on the register class mgl@1371: +to use when it is necessary to copy value X into a register in class mgl@1371: +CLASS. The value is a register class; perhaps CLASS, or perhaps mgl@1371: +another, smaller class. On many machines, the following definition is mgl@1371: +safe: #define PREFERRED_RELOAD_CLASS(X,CLASS) CLASS mgl@1371: + mgl@1371: +Sometimes returning a more restrictive class makes better code. For mgl@1371: +example, on the 68000, when X is an integer constant that is in range mgl@1371: +for a 'moveq' instruction, the value of this macro is always mgl@1371: +DATA_REGS as long as CLASS includes the data registers. mgl@1371: +Requiring a data register guarantees that a 'moveq' will be used. mgl@1371: + mgl@1371: +If X is a const_double, by returning NO_REGS mgl@1371: +you can force X into a memory constant. This is useful on mgl@1371: +certain machines where immediate floating values cannot be loaded into mgl@1371: +certain kinds of registers. mgl@1371: +*/ mgl@1371: +#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the maximum number of consecutive registers mgl@1371: +of class CLASS needed to hold a value of mode MODE. mgl@1371: + mgl@1371: +This is closely related to the macro HARD_REGNO_NREGS. In fact, mgl@1371: +the value of the macro CLASS_MAX_NREGS(CLASS, MODE) mgl@1371: +should be the maximum value of HARD_REGNO_NREGS(REGNO, MODE) mgl@1371: +for all REGNO values in the class CLASS. mgl@1371: + mgl@1371: +This macro helps control the handling of multiple-word values mgl@1371: +in the reload pass. mgl@1371: +*/ mgl@1371: +#define CLASS_MAX_NREGS(CLASS, MODE) /* ToDo:fixme */ \ mgl@1371: + (unsigned int)((GET_MODE_SIZE(MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + Using CONST_OK_FOR_CONSTRAINT_P instead of CONS_OK_FOR_LETTER_P mgl@1371: + in order to support constraints with more than one letter. mgl@1371: + Only two letters are then used for constant constraints, mgl@1371: + the letter 'K' and the letter 'I'. The constraint starting with mgl@1371: + these letters must consist of four characters. The character following mgl@1371: + 'K' or 'I' must be either 'u' (unsigned) or 's' (signed) to specify mgl@1371: + if the constant is zero or sign extended. The last two characters specify mgl@1371: + the length in bits of the constant. The base constraint letter 'I' means mgl@1371: + that this is an negated constant, meaning that actually -VAL should be mgl@1371: + checked to lie withing the valid range instead of VAL which is used when mgl@1371: + 'K' is the base constraint letter. mgl@1371: + mgl@1371: +*/ mgl@1371: + mgl@1371: +#define CONSTRAINT_LEN(C, STR) \ mgl@1371: + ( ((C) == 'K' || (C) == 'I') ? 4 : \ mgl@1371: + ((C) == 'R') ? 5 : \ mgl@1371: + ((C) == 'P') ? -1 : \ mgl@1371: + DEFAULT_CONSTRAINT_LEN((C), (STR)) ) mgl@1371: + mgl@1371: +#define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \ mgl@1371: + avr32_const_ok_for_constraint_p(VALUE, C, STR) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that defines the machine-dependent operand constraint mgl@1371: +letters that specify particular ranges of const_double values ('G' or 'H'). mgl@1371: + mgl@1371: +If C is one of those letters, the expression should check that mgl@1371: +VALUE, an RTX of code const_double, is in the appropriate mgl@1371: +range and return 1 if so, 0 otherwise. If C is not one of those mgl@1371: +letters, the value should be 0 regardless of VALUE. mgl@1371: + mgl@1371: +const_double is used for all floating-point constants and for mgl@1371: +DImode fixed-point constants. A given letter can accept either mgl@1371: +or both kinds of values. It can use GET_MODE to distinguish mgl@1371: +between these kinds. mgl@1371: +*/ mgl@1371: +#define CONST_DOUBLE_OK_FOR_LETTER_P(OP, C) \ mgl@1371: + ((C) == 'G' ? avr32_const_double_immediate(OP) : 0) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that defines the optional machine-dependent constraint mgl@1371: +letters that can be used to segregate specific types of operands, usually mgl@1371: +memory references, for the target machine. Any letter that is not mgl@1371: +elsewhere defined and not matched by REG_CLASS_FROM_LETTER mgl@1371: +may be used. Normally this macro will not be defined. mgl@1371: + mgl@1371: +If it is required for a particular target machine, it should return 1 mgl@1371: +if VALUE corresponds to the operand type represented by the mgl@1371: +constraint letter C. If C is not defined as an extra mgl@1371: +constraint, the value returned should be 0 regardless of VALUE. mgl@1371: + mgl@1371: +For example, on the ROMP, load instructions cannot have their output mgl@1371: +in r0 if the memory reference contains a symbolic address. Constraint mgl@1371: +letter 'Q' is defined as representing a memory address that does mgl@1371: +not contain a symbolic address. An alternative is specified with mgl@1371: +a 'Q' constraint on the input and 'r' on the output. The next mgl@1371: +alternative specifies 'm' on the input and a register class that mgl@1371: +does not include r0 on the output. mgl@1371: +*/ mgl@1371: +#define EXTRA_CONSTRAINT_STR(OP, C, STR) \ mgl@1371: + ((C) == 'W' ? avr32_address_operand(OP, GET_MODE(OP)) : \ mgl@1371: + (C) == 'R' ? (avr32_indirect_register_operand(OP, GET_MODE(OP)) || \ mgl@1371: + (avr32_imm_disp_memory_operand(OP, GET_MODE(OP)) \ mgl@1371: + && avr32_const_ok_for_constraint_p( \ mgl@1371: + INTVAL(XEXP(XEXP(OP, 0), 1)), \ mgl@1371: + (STR)[1], &(STR)[1]))) : \ mgl@1371: + (C) == 'S' ? avr32_indexed_memory_operand(OP, GET_MODE(OP)) : \ mgl@1371: + (C) == 'T' ? avr32_const_pool_ref_operand(OP, GET_MODE(OP)) : \ mgl@1371: + (C) == 'U' ? SYMBOL_REF_RCALL_FUNCTION_P(OP) : \ mgl@1371: + (C) == 'Z' ? avr32_cop_memory_operand(OP, GET_MODE(OP)) : \ mgl@1371: + (C) == 'Q' ? avr32_non_rmw_memory_operand(OP, GET_MODE(OP)) : \ mgl@1371: + (C) == 'Y' ? avr32_rmw_memory_operand(OP, GET_MODE(OP)) : \ mgl@1371: + 0) mgl@1371: + mgl@1371: + mgl@1371: +#define EXTRA_MEMORY_CONSTRAINT(C, STR) ( ((C) == 'R') || \ mgl@1371: + ((C) == 'Q') || \ mgl@1371: + ((C) == 'S') || \ mgl@1371: + ((C) == 'Y') || \ mgl@1371: + ((C) == 'Z') ) mgl@1371: + mgl@1371: + mgl@1371: +/* Returns nonzero if op is a function SYMBOL_REF which mgl@1371: + can be called using an rcall instruction */ mgl@1371: +#define SYMBOL_REF_RCALL_FUNCTION_P(op) \ mgl@1371: + ( GET_CODE(op) == SYMBOL_REF \ mgl@1371: + && SYMBOL_REF_FUNCTION_P(op) \ mgl@1371: + && SYMBOL_REF_LOCAL_P(op) \ mgl@1371: + && !SYMBOL_REF_EXTERNAL_P(op) \ mgl@1371: + && !TARGET_HAS_ASM_ADDR_PSEUDOS ) mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Stack Layout and Calling Conventions mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/** Basic Stack Layout **/ mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro if pushing a word onto the stack moves the stack mgl@1371: +pointer to a smaller address. mgl@1371: + mgl@1371: +When we say, ``define this macro if ...,'' it means that the mgl@1371: +compiler checks this macro only with #ifdef so the precise mgl@1371: +definition used does not matter. mgl@1371: +*/ mgl@1371: +/* pushm decrece SP: *(--SP) <-- Rx */ mgl@1371: +#define STACK_GROWS_DOWNWARD mgl@1371: + mgl@1371: +/* mgl@1371: +This macro defines the operation used when something is pushed mgl@1371: +on the stack. In RTL, a push operation will be mgl@1371: +(set (mem (STACK_PUSH_CODE (reg sp))) ...) mgl@1371: + mgl@1371: +The choices are PRE_DEC, POST_DEC, PRE_INC, mgl@1371: +and POST_INC. Which of these is correct depends on mgl@1371: +the stack direction and on whether the stack pointer points mgl@1371: +to the last item on the stack or whether it points to the mgl@1371: +space for the next item on the stack. mgl@1371: + mgl@1371: +The default is PRE_DEC when STACK_GROWS_DOWNWARD is mgl@1371: +defined, which is almost always right, and PRE_INC otherwise, mgl@1371: +which is often wrong. mgl@1371: +*/ mgl@1371: +/* pushm: *(--SP) <-- Rx */ mgl@1371: +#define STACK_PUSH_CODE PRE_DEC mgl@1371: + mgl@1371: +/* Define this to nonzero if the nominal address of the stack frame mgl@1371: + is at the high-address end of the local variables; mgl@1371: + that is, each additional local variable allocated mgl@1371: + goes at a more negative offset in the frame. */ mgl@1371: +#define FRAME_GROWS_DOWNWARD 1 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Offset from the frame pointer to the first local variable slot to be allocated. mgl@1371: + mgl@1371: +If FRAME_GROWS_DOWNWARD, find the next slot's offset by mgl@1371: +subtracting the first slot's length from STARTING_FRAME_OFFSET. mgl@1371: +Otherwise, it is found by adding the length of the first slot to the mgl@1371: +value STARTING_FRAME_OFFSET. mgl@1371: + (i'm not sure if the above is still correct.. had to change it to get mgl@1371: + rid of an overfull. --mew 2feb93 ) mgl@1371: +*/ mgl@1371: +#define STARTING_FRAME_OFFSET 0 mgl@1371: + mgl@1371: +/* mgl@1371: +Offset from the stack pointer register to the first location at which mgl@1371: +outgoing arguments are placed. If not specified, the default value of mgl@1371: +zero is used. This is the proper value for most machines. mgl@1371: + mgl@1371: +If ARGS_GROW_DOWNWARD, this is the offset to the location above mgl@1371: +the first location at which outgoing arguments are placed. mgl@1371: +*/ mgl@1371: +#define STACK_POINTER_OFFSET 0 mgl@1371: + mgl@1371: +/* mgl@1371: +Offset from the argument pointer register to the first argument's mgl@1371: +address. On some machines it may depend on the data type of the mgl@1371: +function. mgl@1371: + mgl@1371: +If ARGS_GROW_DOWNWARD, this is the offset to the location above mgl@1371: +the first argument's address. mgl@1371: +*/ mgl@1371: +#define FIRST_PARM_OFFSET(FUNDECL) 0 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is RTL representing the address in a stack mgl@1371: +frame where the pointer to the caller's frame is stored. Assume that mgl@1371: +FRAMEADDR is an RTL expression for the address of the stack frame mgl@1371: +itself. mgl@1371: + mgl@1371: +If you don't define this macro, the default is to return the value mgl@1371: +of FRAMEADDR - that is, the stack frame address is also the mgl@1371: +address of the stack word that points to the previous frame. mgl@1371: +*/ mgl@1371: +#define DYNAMIC_CHAIN_ADDRESS(FRAMEADDR) plus_constant ((FRAMEADDR), 4) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is RTL representing the value of the return mgl@1371: +address for the frame COUNT steps up from the current frame, after mgl@1371: +the prologue. FRAMEADDR is the frame pointer of the COUNT mgl@1371: +frame, or the frame pointer of the COUNT - 1 frame if mgl@1371: +RETURN_ADDR_IN_PREVIOUS_FRAME is defined. mgl@1371: + mgl@1371: +The value of the expression must always be the correct address when mgl@1371: +COUNT is zero, but may be NULL_RTX if there is not way to mgl@1371: +determine the return address of other frames. mgl@1371: +*/ mgl@1371: +#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) avr32_return_addr(COUNT, FRAMEADDR) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is RTL representing the location of the mgl@1371: +incoming return address at the beginning of any function, before the mgl@1371: +prologue. This RTL is either a REG, indicating that the return mgl@1371: +value is saved in 'REG', or a MEM representing a location in mgl@1371: +the stack. mgl@1371: + mgl@1371: +You only need to define this macro if you want to support call frame mgl@1371: +debugging information like that provided by DWARF 2. mgl@1371: + mgl@1371: +If this RTL is a REG, you should also define mgl@1371: +DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). mgl@1371: +*/ mgl@1371: +#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is an integer giving the offset, in bytes, mgl@1371: +from the value of the stack pointer register to the top of the stack mgl@1371: +frame at the beginning of any function, before the prologue. The top of mgl@1371: +the frame is defined to be the value of the stack pointer in the mgl@1371: +previous frame, just before the call instruction. mgl@1371: + mgl@1371: +You only need to define this macro if you want to support call frame mgl@1371: +debugging information like that provided by DWARF 2. mgl@1371: +*/ mgl@1371: +#define INCOMING_FRAME_SP_OFFSET 0 mgl@1371: + mgl@1371: + mgl@1371: +/** Exception Handling Support **/ mgl@1371: + mgl@1371: +/* Use setjump/longjump for exception handling. */ mgl@1371: +#define DWARF2_UNWIND_INFO 0 mgl@1371: +#define MUST_USE_SJLJ_EXCEPTIONS 1 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is the Nth register number used for mgl@1371: +data by exception handlers, or INVALID_REGNUM if fewer than mgl@1371: +N registers are usable. mgl@1371: + mgl@1371: +The exception handling library routines communicate with the exception mgl@1371: +handlers via a set of agreed upon registers. Ideally these registers mgl@1371: +should be call-clobbered; it is possible to use call-saved registers, mgl@1371: +but may negatively impact code size. The target must support at least mgl@1371: +2 data registers, but should define 4 if there are enough free registers. mgl@1371: + mgl@1371: +You must define this macro if you want to support call frame exception mgl@1371: +handling like that provided by DWARF 2. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + Use r9-r11 mgl@1371: +*/ mgl@1371: +#define EH_RETURN_DATA_REGNO(N) \ mgl@1371: + ((N<3) ? INTERNAL_REGNUM(N+9) : INVALID_REGNUM) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is RTL representing a location in which mgl@1371: +to store a stack adjustment to be applied before function return. mgl@1371: +This is used to unwind the stack to an exception handler's call frame. mgl@1371: +It will be assigned zero on code paths that return normally. mgl@1371: + mgl@1371: +Typically this is a call-clobbered hard register that is otherwise mgl@1371: +untouched by the epilogue, but could also be a stack slot. mgl@1371: + mgl@1371: +You must define this macro if you want to support call frame exception mgl@1371: +handling like that provided by DWARF 2. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + Use r8 mgl@1371: +*/ mgl@1371: +#define EH_RETURN_STACKADJ_REGNO INTERNAL_REGNUM(8) mgl@1371: +#define EH_RETURN_STACKADJ_RTX gen_rtx_REG(SImode, EH_RETURN_STACKADJ_REGNO) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is RTL representing a location in which mgl@1371: +to store the address of an exception handler to which we should mgl@1371: +return. It will not be assigned on code paths that return normally. mgl@1371: + mgl@1371: +Typically this is the location in the call frame at which the normal mgl@1371: +return address is stored. For targets that return by popping an mgl@1371: +address off the stack, this might be a memory address just below mgl@1371: +the target call frame rather than inside the current call mgl@1371: +frame. EH_RETURN_STACKADJ_RTX will have already been assigned, mgl@1371: +so it may be used to calculate the location of the target call frame. mgl@1371: + mgl@1371: +Some targets have more complex requirements than storing to an mgl@1371: +address calculable during initial code generation. In that case mgl@1371: +the eh_return instruction pattern should be used instead. mgl@1371: + mgl@1371: +If you want to support call frame exception handling, you must mgl@1371: +define either this macro or the eh_return instruction pattern. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + We define the eh_return instruction pattern, so this isn't needed. mgl@1371: +*/ mgl@1371: +/* #define EH_RETURN_HANDLER_RTX gen_rtx_REG(Pmode, RET_REGISTER) */ mgl@1371: + mgl@1371: +/* mgl@1371: + This macro chooses the encoding of pointers embedded in the mgl@1371: + exception handling sections. If at all possible, this should be mgl@1371: + defined such that the exception handling section will not require mgl@1371: + dynamic relocations, and so may be read-only. mgl@1371: + mgl@1371: + code is 0 for data, 1 for code labels, 2 for function mgl@1371: + pointers. global is true if the symbol may be affected by dynamic mgl@1371: + relocations. The macro should return a combination of the DW_EH_PE_* mgl@1371: + defines as found in dwarf2.h. mgl@1371: + mgl@1371: + If this macro is not defined, pointers will not be encoded but mgl@1371: + represented directly. mgl@1371: +*/ mgl@1371: +#define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ mgl@1371: + ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ mgl@1371: + | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr) \ mgl@1371: + | DW_EH_PE_sdata4) mgl@1371: + mgl@1371: +/* ToDo: The rest of this subsection */ mgl@1371: + mgl@1371: +/** Specifying How Stack Checking is Done **/ mgl@1371: +/* ToDo: All in this subsection */ mgl@1371: + mgl@1371: +/** Registers That Address the Stack Frame **/ mgl@1371: + mgl@1371: +/* mgl@1371: +The register number of the stack pointer register, which must also be a mgl@1371: +fixed register according to FIXED_REGISTERS. On most machines, mgl@1371: +the hardware determines which register this is. mgl@1371: +*/ mgl@1371: +/* Using r13 as stack pointer. */ mgl@1371: +#define STACK_POINTER_REGNUM INTERNAL_REGNUM(13) mgl@1371: + mgl@1371: +/* mgl@1371: +The register number of the frame pointer register, which is used to mgl@1371: +access automatic variables in the stack frame. On some machines, the mgl@1371: +hardware determines which register this is. On other machines, you can mgl@1371: +choose any register you wish for this purpose. mgl@1371: +*/ mgl@1371: +/* Use r7 */ mgl@1371: +#define FRAME_POINTER_REGNUM INTERNAL_REGNUM(7) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +The register number of the arg pointer register, which is used to access mgl@1371: +the function's argument list. On some machines, this is the same as the mgl@1371: +frame pointer register. On some machines, the hardware determines which mgl@1371: +register this is. On other machines, you can choose any register you mgl@1371: +wish for this purpose. If this is not the same register as the frame mgl@1371: +pointer register, then you must mark it as a fixed register according to mgl@1371: +FIXED_REGISTERS, or arrange to be able to eliminate it (see Section mgl@1371: +10.10.5 [Elimination], page 224). mgl@1371: +*/ mgl@1371: +/* Using r5 */ mgl@1371: +#define ARG_POINTER_REGNUM INTERNAL_REGNUM(4) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Register numbers used for passing a function's static chain pointer. If mgl@1371: +register windows are used, the register number as seen by the called mgl@1371: +function is STATIC_CHAIN_INCOMING_REGNUM, while the register mgl@1371: +number as seen by the calling function is STATIC_CHAIN_REGNUM. If mgl@1371: +these registers are the same, STATIC_CHAIN_INCOMING_REGNUM need mgl@1371: +not be defined. mgl@1371: + mgl@1371: +The static chain register need not be a fixed register. mgl@1371: + mgl@1371: +If the static chain is passed in memory, these macros should not be mgl@1371: +defined; instead, the next two macros should be defined. mgl@1371: +*/ mgl@1371: +/* Using r0 */ mgl@1371: +#define STATIC_CHAIN_REGNUM INTERNAL_REGNUM(0) mgl@1371: + mgl@1371: + mgl@1371: +/** Eliminating Frame Pointer and Arg Pointer **/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which is nonzero if a function must have and use a frame mgl@1371: +pointer. This expression is evaluated in the reload pass. If its value is mgl@1371: +nonzero the function will have a frame pointer. mgl@1371: + mgl@1371: +The expression can in principle examine the current function and decide mgl@1371: +according to the facts, but on most machines the constant 0 or the mgl@1371: +constant 1 suffices. Use 0 when the machine allows code to be generated mgl@1371: +with no frame pointer, and doing so saves some time or space. Use 1 mgl@1371: +when there is no possible advantage to avoiding a frame pointer. mgl@1371: + mgl@1371: +In certain cases, the compiler does not know how to produce valid code mgl@1371: +without a frame pointer. The compiler recognizes those cases and mgl@1371: +automatically gives the function a frame pointer regardless of what mgl@1371: +FRAME_POINTER_REQUIRED says. You don't need to worry about mgl@1371: +them. mgl@1371: + mgl@1371: +In a function that does not require a frame pointer, the frame pointer mgl@1371: +register can be allocated for ordinary usage, unless you mark it as a mgl@1371: +fixed register. See FIXED_REGISTERS for more information. mgl@1371: +*/ mgl@1371: +/* We need the frame pointer when compiling for profiling */ mgl@1371: +#define FRAME_POINTER_REQUIRED (current_function_profile) mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement to store in the variable DEPTH_VAR the difference mgl@1371: +between the frame pointer and the stack pointer values immediately after mgl@1371: +the function prologue. The value would be computed from information mgl@1371: +such as the result of get_frame_size () and the tables of mgl@1371: +registers regs_ever_live and call_used_regs. mgl@1371: + mgl@1371: +If ELIMINABLE_REGS is defined, this macro will be not be used and mgl@1371: +need not be defined. Otherwise, it must be defined even if mgl@1371: +FRAME_POINTER_REQUIRED is defined to always be true; in that mgl@1371: +case, you may set DEPTH_VAR to anything. mgl@1371: +*/ mgl@1371: +#define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) ((DEPTH_VAR) = get_frame_size()) mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, this macro specifies a table of register pairs used to mgl@1371: +eliminate unneeded registers that point into the stack frame. If it is not mgl@1371: +defined, the only elimination attempted by the compiler is to replace mgl@1371: +references to the frame pointer with references to the stack pointer. mgl@1371: + mgl@1371: +The definition of this macro is a list of structure initializations, each mgl@1371: +of which specifies an original and replacement register. mgl@1371: + mgl@1371: +On some machines, the position of the argument pointer is not known until mgl@1371: +the compilation is completed. In such a case, a separate hard register mgl@1371: +must be used for the argument pointer. This register can be eliminated by mgl@1371: +replacing it with either the frame pointer or the argument pointer, mgl@1371: +depending on whether or not the frame pointer has been eliminated. mgl@1371: + mgl@1371: +In this case, you might specify: mgl@1371: + #define ELIMINABLE_REGS \ mgl@1371: + {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ mgl@1371: + {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ mgl@1371: + {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} mgl@1371: + mgl@1371: +Note that the elimination of the argument pointer with the stack pointer is mgl@1371: +specified first since that is the preferred elimination. mgl@1371: +*/ mgl@1371: +#define ELIMINABLE_REGS \ mgl@1371: +{ \ mgl@1371: + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ mgl@1371: + { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ mgl@1371: + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM } \ mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that returns nonzero if the compiler is allowed to try mgl@1371: +to replace register number FROM with register number mgl@1371: +TO. This macro need only be defined if ELIMINABLE_REGS mgl@1371: +is defined, and will usually be the constant 1, since most of the cases mgl@1371: +preventing register elimination are things that the compiler already mgl@1371: +knows about. mgl@1371: +*/ mgl@1371: +#define CAN_ELIMINATE(FROM, TO) 1 mgl@1371: + mgl@1371: +/* mgl@1371: +This macro is similar to INITIAL_FRAME_POINTER_OFFSET. It mgl@1371: +specifies the initial difference between the specified pair of mgl@1371: +registers. This macro must be defined if ELIMINABLE_REGS is mgl@1371: +defined. mgl@1371: +*/ mgl@1371: +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ mgl@1371: + ((OFFSET) = avr32_initial_elimination_offset(FROM, TO)) mgl@1371: + mgl@1371: +/** Passing Function Arguments on the Stack **/ mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression. If nonzero, push insns will be used to pass mgl@1371: +outgoing arguments. mgl@1371: +If the target machine does not have a push instruction, set it to zero. mgl@1371: +That directs GCC to use an alternate strategy: to mgl@1371: +allocate the entire argument block and then store the arguments into mgl@1371: +it. When PUSH_ARGS is nonzero, PUSH_ROUNDING must be defined too. mgl@1371: +*/ mgl@1371: +#define PUSH_ARGS 1 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is the number of bytes actually pushed onto the mgl@1371: +stack when an instruction attempts to push NPUSHED bytes. mgl@1371: + mgl@1371: +On some machines, the definition mgl@1371: + mgl@1371: + #define PUSH_ROUNDING(BYTES) (BYTES) mgl@1371: + mgl@1371: +will suffice. But on other machines, instructions that appear mgl@1371: +to push one byte actually push two bytes in an attempt to maintain mgl@1371: +alignment. Then the definition should be mgl@1371: + mgl@1371: + #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) mgl@1371: +*/ mgl@1371: +/* Push 4 bytes at the time. */ mgl@1371: +#define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression. If nonzero, the maximum amount of space required for mgl@1371: +outgoing arguments will be computed and placed into the variable mgl@1371: +current_function_outgoing_args_size. No space will be pushed mgl@1371: +onto the stack for each call; instead, the function prologue should mgl@1371: +increase the stack frame size by this amount. mgl@1371: + mgl@1371: +Setting both PUSH_ARGS and ACCUMULATE_OUTGOING_ARGS is not proper. mgl@1371: +*/ mgl@1371: +#define ACCUMULATE_OUTGOING_ARGS 0 mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that should indicate the number of bytes of its own mgl@1371: +arguments that a function pops on returning, or 0 if the mgl@1371: +function pops no arguments and the caller must therefore pop them all mgl@1371: +after the function returns. mgl@1371: + mgl@1371: +FUNDECL is a C variable whose value is a tree node that describes mgl@1371: +the function in question. Normally it is a node of type mgl@1371: +FUNCTION_DECL that describes the declaration of the function. mgl@1371: +From this you can obtain the DECL_ATTRIBUTES of the function. mgl@1371: + mgl@1371: +FUNTYPE is a C variable whose value is a tree node that mgl@1371: +describes the function in question. Normally it is a node of type mgl@1371: +FUNCTION_TYPE that describes the data type of the function. mgl@1371: +From this it is possible to obtain the data types of the value and mgl@1371: +arguments (if known). mgl@1371: + mgl@1371: +When a call to a library function is being considered, FUNDECL mgl@1371: +will contain an identifier node for the library function. Thus, if mgl@1371: +you need to distinguish among various library functions, you can do so mgl@1371: +by their names. Note that ``library function'' in this context means mgl@1371: +a function used to perform arithmetic, whose name is known specially mgl@1371: +in the compiler and was not mentioned in the C code being compiled. mgl@1371: + mgl@1371: +STACK_SIZE is the number of bytes of arguments passed on the mgl@1371: +stack. If a variable number of bytes is passed, it is zero, and mgl@1371: +argument popping will always be the responsibility of the calling function. mgl@1371: + mgl@1371: +On the VAX, all functions always pop their arguments, so the definition mgl@1371: +of this macro is STACK_SIZE. On the 68000, using the standard mgl@1371: +calling convention, no functions pop their arguments, so the value of mgl@1371: +the macro is always 0 in this case. But an alternative calling mgl@1371: +convention is available in which functions that take a fixed number of mgl@1371: +arguments pop them but other functions (such as printf) pop mgl@1371: +nothing (the caller pops all). When this convention is in use, mgl@1371: +FUNTYPE is examined to determine whether a function takes a fixed mgl@1371: +number of arguments. mgl@1371: +*/ mgl@1371: +#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 mgl@1371: + mgl@1371: + mgl@1371: +/*Return true if this function can we use a single return instruction*/ mgl@1371: +#define USE_RETURN_INSN(ISCOND) avr32_use_return_insn(ISCOND) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that should indicate the number of bytes a call sequence mgl@1371: +pops off the stack. It is added to the value of RETURN_POPS_ARGS mgl@1371: +when compiling a function call. mgl@1371: + mgl@1371: +CUM is the variable in which all arguments to the called function mgl@1371: +have been accumulated. mgl@1371: + mgl@1371: +On certain architectures, such as the SH5, a call trampoline is used mgl@1371: +that pops certain registers off the stack, depending on the arguments mgl@1371: +that have been passed to the function. Since this is a property of the mgl@1371: +call site, not of the called function, RETURN_POPS_ARGS is not mgl@1371: +appropriate. mgl@1371: +*/ mgl@1371: +#define CALL_POPS_ARGS(CUM) 0 mgl@1371: + mgl@1371: +/* Passing Arguments in Registers */ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that controls whether a function argument is passed mgl@1371: +in a register, and which register. mgl@1371: + mgl@1371: +The arguments are CUM, which summarizes all the previous mgl@1371: +arguments; MODE, the machine mode of the argument; TYPE, mgl@1371: +the data type of the argument as a tree node or 0 if that is not known mgl@1371: +(which happens for C support library functions); and NAMED, mgl@1371: +which is 1 for an ordinary argument and 0 for nameless arguments that mgl@1371: +correspond to '...' in the called function's prototype. mgl@1371: +TYPE can be an incomplete type if a syntax error has previously mgl@1371: +occurred. mgl@1371: + mgl@1371: +The value of the expression is usually either a reg RTX for the mgl@1371: +hard register in which to pass the argument, or zero to pass the mgl@1371: +argument on the stack. mgl@1371: + mgl@1371: +For machines like the VAX and 68000, where normally all arguments are mgl@1371: +pushed, zero suffices as a definition. mgl@1371: + mgl@1371: +The value of the expression can also be a parallel RTX. This is mgl@1371: +used when an argument is passed in multiple locations. The mode of the mgl@1371: +of the parallel should be the mode of the entire argument. The mgl@1371: +parallel holds any number of expr_list pairs; each one mgl@1371: +describes where part of the argument is passed. In each mgl@1371: +expr_list the first operand must be a reg RTX for the hard mgl@1371: +register in which to pass this part of the argument, and the mode of the mgl@1371: +register RTX indicates how large this part of the argument is. The mgl@1371: +second operand of the expr_list is a const_int which gives mgl@1371: +the offset in bytes into the entire argument of where this part starts. mgl@1371: +As a special exception the first expr_list in the parallel mgl@1371: +RTX may have a first operand of zero. This indicates that the entire mgl@1371: +argument is also stored on the stack. mgl@1371: + mgl@1371: +The last time this macro is called, it is called with MODE == VOIDmode, mgl@1371: +and its result is passed to the call or call_value mgl@1371: +pattern as operands 2 and 3 respectively. mgl@1371: + mgl@1371: +The usual way to make the ISO library 'stdarg.h' work on a machine mgl@1371: +where some arguments are usually passed in registers, is to cause mgl@1371: +nameless arguments to be passed on the stack instead. This is done mgl@1371: +by making FUNCTION_ARG return 0 whenever NAMED is 0. mgl@1371: + mgl@1371: +You may use the macro MUST_PASS_IN_STACK (MODE, TYPE) mgl@1371: +in the definition of this macro to determine if this argument is of a mgl@1371: +type that must be passed in the stack. If REG_PARM_STACK_SPACE mgl@1371: +is not defined and FUNCTION_ARG returns nonzero for such an mgl@1371: +argument, the compiler will abort. If REG_PARM_STACK_SPACE is mgl@1371: +defined, the argument will be computed in the stack and then loaded into mgl@1371: +a register. */ mgl@1371: + mgl@1371: +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ mgl@1371: + avr32_function_arg(&(CUM), MODE, TYPE, NAMED) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C type for declaring a variable that is used as the first argument of mgl@1371: +FUNCTION_ARG and other related values. For some target machines, mgl@1371: +the type int suffices and can hold the number of bytes of mgl@1371: +argument so far. mgl@1371: + mgl@1371: +There is no need to record in CUMULATIVE_ARGS anything about the mgl@1371: +arguments that have been passed on the stack. The compiler has other mgl@1371: +variables to keep track of that. For target machines on which all mgl@1371: +arguments are passed on the stack, there is no need to store anything in mgl@1371: +CUMULATIVE_ARGS; however, the data structure must exist and mgl@1371: +should not be empty, so use int. mgl@1371: +*/ mgl@1371: +typedef struct avr32_args mgl@1371: +{ mgl@1371: + /* Index representing the argument register the current function argument mgl@1371: + will occupy */ mgl@1371: + int index; mgl@1371: + /* A mask with bits representing the argument registers: if a bit is set mgl@1371: + then this register is used for an arguemnt */ mgl@1371: + int used_index; mgl@1371: + /* TRUE if this function has anonymous arguments */ mgl@1371: + int uses_anonymous_args; mgl@1371: + /* The size in bytes of the named arguments pushed on the stack */ mgl@1371: + int stack_pushed_args_size; mgl@1371: + /* Set to true if this function needs a Return Value Pointer */ mgl@1371: + int use_rvp; mgl@1371: + mgl@1371: +} CUMULATIVE_ARGS; mgl@1371: + mgl@1371: + mgl@1371: +#define FIRST_CUM_REG_INDEX 0 mgl@1371: +#define LAST_CUM_REG_INDEX 4 mgl@1371: +#define GET_REG_INDEX(CUM) ((CUM)->index) mgl@1371: +#define SET_REG_INDEX(CUM, INDEX) ((CUM)->index = (INDEX)); mgl@1371: +#define GET_USED_INDEX(CUM, INDEX) ((CUM)->used_index & (1 << (INDEX))) mgl@1371: +#define SET_USED_INDEX(CUM, INDEX) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if (INDEX >= 0) \ mgl@1371: + (CUM)->used_index |= (1 << (INDEX)); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: +#define SET_INDEXES_UNUSED(CUM) ((CUM)->used_index = 0) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + A C statement (sans semicolon) for initializing the variable cum for the mgl@1371: + state at the beginning of the argument list. The variable has type mgl@1371: + CUMULATIVE_ARGS. The value of FNTYPE is the tree node for the data type of mgl@1371: + the function which will receive the args, or 0 if the args are to a compiler mgl@1371: + support library function. For direct calls that are not libcalls, FNDECL mgl@1371: + contain the declaration node of the function. FNDECL is also set when mgl@1371: + INIT_CUMULATIVE_ARGS is used to find arguments for the function being mgl@1371: + compiled. N_NAMED_ARGS is set to the number of named arguments, including a mgl@1371: + structure return address if it is passed as a parameter, when making a call. mgl@1371: + When processing incoming arguments, N_NAMED_ARGS is set to -1. mgl@1371: + mgl@1371: + When processing a call to a compiler support library function, LIBNAME mgl@1371: + identifies which one. It is a symbol_ref rtx which contains the name of the mgl@1371: + function, as a string. LIBNAME is 0 when an ordinary C function call is mgl@1371: + being processed. Thus, each time this macro is called, either LIBNAME or mgl@1371: + FNTYPE is nonzero, but never both of them at once. mgl@1371: +*/ mgl@1371: +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ mgl@1371: + avr32_init_cumulative_args(&(CUM), FNTYPE, LIBNAME, FNDECL) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement (sans semicolon) to update the summarizer variable mgl@1371: +CUM to advance past an argument in the argument list. The mgl@1371: +values MODE, TYPE and NAMED describe that argument. mgl@1371: +Once this is done, the variable CUM is suitable for analyzing mgl@1371: +the following argument with FUNCTION_ARG, etc. mgl@1371: + mgl@1371: +This macro need not do anything if the argument in question was passed mgl@1371: +on the stack. The compiler knows how to track the amount of stack space mgl@1371: +used for arguments without any special help. mgl@1371: +*/ mgl@1371: +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ mgl@1371: + avr32_function_arg_advance(&(CUM), MODE, TYPE, NAMED) mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression which determines whether, and in which direction, mgl@1371: +to pad out an argument with extra space. The value should be of type mgl@1371: +enum direction: either 'upward' to pad above the argument, mgl@1371: +'downward' to pad below, or 'none' to inhibit padding. mgl@1371: + mgl@1371: +The amount of padding is always just enough to reach the next mgl@1371: +multiple of FUNCTION_ARG_BOUNDARY; this macro does not control mgl@1371: +it. mgl@1371: + mgl@1371: +This macro has a default definition which is right for most systems. mgl@1371: +For little-endian machines, the default is to pad upward. For mgl@1371: +big-endian machines, the default is to pad downward for an argument of mgl@1371: +constant size shorter than an int, and upward otherwise. mgl@1371: +*/ mgl@1371: +#define FUNCTION_ARG_PADDING(MODE, TYPE) \ mgl@1371: + avr32_function_arg_padding(MODE, TYPE) mgl@1371: + mgl@1371: +/* mgl@1371: + Specify padding for the last element of a block move between registers mgl@1371: + and memory. First is nonzero if this is the only element. Defining mgl@1371: + this macro allows better control of register function parameters on mgl@1371: + big-endian machines, without using PARALLEL rtl. In particular, mgl@1371: + MUST_PASS_IN_STACK need not test padding and mode of types in registers, mgl@1371: + as there is no longer a "wrong" part of a register; For example, a three mgl@1371: + byte aggregate may be passed in the high part of a register if so required. mgl@1371: +*/ mgl@1371: +#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ mgl@1371: + avr32_function_arg_padding(MODE, TYPE) mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression which determines whether the default mgl@1371: +implementation of va_arg will attempt to pad down before reading the mgl@1371: +next argument, if that argument is smaller than its aligned space as mgl@1371: +controlled by PARM_BOUNDARY. If this macro is not defined, all such mgl@1371: +arguments are padded down if BYTES_BIG_ENDIAN is true. mgl@1371: +*/ mgl@1371: +#define PAD_VARARGS_DOWN \ mgl@1371: + (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if REGNO is the number of a hard mgl@1371: +register in which function arguments are sometimes passed. This does mgl@1371: +not include implicit arguments such as the static chain and mgl@1371: +the structure-value address. On many machines, no registers can be mgl@1371: +used for this purpose since all function arguments are pushed on the mgl@1371: +stack. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + Use r8 - r12 for function arguments. mgl@1371: +*/ mgl@1371: +#define FUNCTION_ARG_REGNO_P(REGNO) \ mgl@1371: + (REGNO >= 3 && REGNO <= 7) mgl@1371: + mgl@1371: +/* Number of registers used for passing function arguments */ mgl@1371: +#define NUM_ARG_REGS 5 mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, the order in which arguments are loaded into their mgl@1371: +respective argument registers is reversed so that the last mgl@1371: +argument is loaded first. This macro only affects arguments mgl@1371: +passed in registers. mgl@1371: +*/ mgl@1371: +/* #define LOAD_ARGS_REVERSED */ mgl@1371: + mgl@1371: +/** How Scalar Function Values Are Returned **/ mgl@1371: + mgl@1371: +/* AVR32 is using r12 as return register. */ mgl@1371: +#define RET_REGISTER (15 - 12) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression to create an RTX representing the place where a library mgl@1371: +function returns a value of mode MODE. If the precise function mgl@1371: +being called is known, FUNC is a tree node mgl@1371: +(FUNCTION_DECL) for it; otherwise, func is a null mgl@1371: +pointer. This makes it possible to use a different value-returning mgl@1371: +convention for specific functions when all their calls are mgl@1371: +known. mgl@1371: + mgl@1371: +Note that "library function" in this context means a compiler mgl@1371: +support routine, used to perform arithmetic, whose name is known mgl@1371: +specially by the compiler and was not mentioned in the C code being mgl@1371: +compiled. mgl@1371: + mgl@1371: +The definition of LIBRARY_VALUE need not be concerned aggregate mgl@1371: +data types, because none of the library functions returns such types. mgl@1371: +*/ mgl@1371: +#define LIBCALL_VALUE(MODE) avr32_libcall_value(MODE) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if REGNO is the number of a hard mgl@1371: +register in which the values of called function may come back. mgl@1371: + mgl@1371: +A register whose use for returning values is limited to serving as the mgl@1371: +second of a pair (for a value of type double, say) need not be mgl@1371: +recognized by this macro. So for most machines, this definition mgl@1371: +suffices: mgl@1371: + #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) mgl@1371: + mgl@1371: +If the machine has register windows, so that the caller and the called mgl@1371: +function use different registers for the return value, this macro mgl@1371: +should recognize only the caller's register numbers. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + When returning a value of mode DImode, r11:r10 is used, else r12 is used. mgl@1371: +*/ mgl@1371: +#define FUNCTION_VALUE_REGNO_P(REGNO) ((REGNO) == RET_REGISTER \ mgl@1371: + || (REGNO) == INTERNAL_REGNUM(11)) mgl@1371: + mgl@1371: + mgl@1371: +/** How Large Values Are Returned **/ mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to be 1 if all structure and union return values must be mgl@1371: +in memory. Since this results in slower code, this should be defined mgl@1371: +only if needed for compatibility with other compilers or with an ABI. mgl@1371: +If you define this macro to be 0, then the conventions used for structure mgl@1371: +and union return values are decided by the RETURN_IN_MEMORY macro. mgl@1371: + mgl@1371: +If not defined, this defaults to the value 1. mgl@1371: +*/ mgl@1371: +#define DEFAULT_PCC_STRUCT_RETURN 0 mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/** Generating Code for Profiling **/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement or compound statement to output to FILE some mgl@1371: +assembler code to call the profiling subroutine mcount. mgl@1371: + mgl@1371: +The details of how mcount expects to be called are determined by mgl@1371: +your operating system environment, not by GCC. To figure them out, mgl@1371: +compile a small program for profiling using the system's installed C mgl@1371: +compiler and look at the assembler code that results. mgl@1371: + mgl@1371: +Older implementations of mcount expect the address of a counter mgl@1371: +variable to be loaded into some register. The name of this variable is mgl@1371: +'LP' followed by the number LABELNO, so you would generate mgl@1371: +the name using 'LP%d' in a fprintf. mgl@1371: +*/ mgl@1371: +/* ToDo: fixme */ mgl@1371: +#ifndef FUNCTION_PROFILER mgl@1371: +#define FUNCTION_PROFILER(FILE, LABELNO) \ mgl@1371: + fprintf((FILE), "/* profiler %d */", (LABELNO)) mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +/***************************************************************************** mgl@1371: + * Trampolines for Nested Functions * mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement to output, on the stream FILE, assembler code for a mgl@1371: +block of data that contains the constant parts of a trampoline. This mgl@1371: +code should not include a label - the label is taken care of mgl@1371: +automatically. mgl@1371: + mgl@1371: +If you do not define this macro, it means no template is needed mgl@1371: +for the target. Do not define this macro on systems where the block move mgl@1371: +code to copy the trampoline into place would be larger than the code mgl@1371: +to generate it on the spot. mgl@1371: +*/ mgl@1371: +/* ToDo: correct? */ mgl@1371: +#define TRAMPOLINE_TEMPLATE(FILE) avr32_trampoline_template(FILE); mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the size in bytes of the trampoline, as an integer. mgl@1371: +*/ mgl@1371: +/* ToDo: fixme */ mgl@1371: +#define TRAMPOLINE_SIZE 0x0C mgl@1371: + mgl@1371: +/* mgl@1371: +Alignment required for trampolines, in bits. mgl@1371: + mgl@1371: +If you don't define this macro, the value of BIGGEST_ALIGNMENT mgl@1371: +is used for aligning trampolines. mgl@1371: +*/ mgl@1371: +#define TRAMPOLINE_ALIGNMENT 16 mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement to initialize the variable parts of a trampoline. mgl@1371: +ADDR is an RTX for the address of the trampoline; FNADDR is mgl@1371: +an RTX for the address of the nested function; STATIC_CHAIN is an mgl@1371: +RTX for the static chain value that should be passed to the function mgl@1371: +when it is called. mgl@1371: +*/ mgl@1371: +#define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \ mgl@1371: + avr32_initialize_trampoline(ADDR, FNADDR, STATIC_CHAIN) mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Implicit Calls to Library Routines mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* Tail calling. */ mgl@1371: + mgl@1371: +/* A C expression that evaluates to true if it is ok to perform a sibling mgl@1371: + call to DECL. */ mgl@1371: +#define FUNCTION_OK_FOR_SIBCALL(DECL) 0 mgl@1371: + mgl@1371: +#define OVERRIDE_OPTIONS avr32_override_options () mgl@1371: + mgl@1371: +#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) avr32_optimization_options (LEVEL, SIZE) mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Addressing Modes mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if the machine supports pre-increment, mgl@1371: +pre-decrement, post-increment, or post-decrement addressing respectively. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + AVR32 supports Rp++ and --Rp mgl@1371: +*/ mgl@1371: +#define HAVE_PRE_INCREMENT 0 mgl@1371: +#define HAVE_PRE_DECREMENT 1 mgl@1371: +#define HAVE_POST_INCREMENT 1 mgl@1371: +#define HAVE_POST_DECREMENT 0 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if the machine supports pre- or mgl@1371: +post-address side-effect generation involving constants other than mgl@1371: +the size of the memory operand. mgl@1371: +*/ mgl@1371: +#define HAVE_PRE_MODIFY_DISP 0 mgl@1371: +#define HAVE_POST_MODIFY_DISP 0 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if the machine supports pre- or mgl@1371: +post-address side-effect generation involving a register displacement. mgl@1371: +*/ mgl@1371: +#define HAVE_PRE_MODIFY_REG 0 mgl@1371: +#define HAVE_POST_MODIFY_REG 0 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is 1 if the RTX X is a constant which mgl@1371: +is a valid address. On most machines, this can be defined as mgl@1371: +CONSTANT_P (X), but a few machines are more restrictive mgl@1371: +in which constant addresses are supported. mgl@1371: + mgl@1371: +CONSTANT_P accepts integer-values expressions whose values are mgl@1371: +not explicitly known, such as symbol_ref, label_ref, and mgl@1371: +high expressions and const arithmetic expressions, in mgl@1371: +addition to const_int and const_double expressions. mgl@1371: +*/ mgl@1371: +#define CONSTANT_ADDRESS_P(X) CONSTANT_P(X) mgl@1371: + mgl@1371: +/* mgl@1371: +A number, the maximum number of registers that can appear in a valid mgl@1371: +memory address. Note that it is up to you to specify a value equal to mgl@1371: +the maximum number that GO_IF_LEGITIMATE_ADDRESS would ever mgl@1371: +accept. mgl@1371: +*/ mgl@1371: +#define MAX_REGS_PER_ADDRESS 2 mgl@1371: + mgl@1371: +/* mgl@1371: +A C compound statement with a conditional goto LABEL; mgl@1371: +executed if X (an RTX) is a legitimate memory address on the mgl@1371: +target machine for a memory operand of mode MODE. mgl@1371: + mgl@1371: +It usually pays to define several simpler macros to serve as mgl@1371: +subroutines for this one. Otherwise it may be too complicated to mgl@1371: +understand. mgl@1371: + mgl@1371: +This macro must exist in two variants: a strict variant and a mgl@1371: +non-strict one. The strict variant is used in the reload pass. It mgl@1371: +must be defined so that any pseudo-register that has not been mgl@1371: +allocated a hard register is considered a memory reference. In mgl@1371: +contexts where some kind of register is required, a pseudo-register mgl@1371: +with no hard register must be rejected. mgl@1371: + mgl@1371: +The non-strict variant is used in other passes. It must be defined to mgl@1371: +accept all pseudo-registers in every context where some kind of mgl@1371: +register is required. mgl@1371: + mgl@1371: +Compiler source files that want to use the strict variant of this mgl@1371: +macro define the macro REG_OK_STRICT. You should use an mgl@1371: +#ifdef REG_OK_STRICT conditional to define the strict variant mgl@1371: +in that case and the non-strict variant otherwise. mgl@1371: + mgl@1371: +Subroutines to check for acceptable registers for various purposes (one mgl@1371: +for base registers, one for index registers, and so on) are typically mgl@1371: +among the subroutines used to define GO_IF_LEGITIMATE_ADDRESS. mgl@1371: +Then only these subroutine macros need have two variants; the higher mgl@1371: +levels of macros may be the same whether strict or not. mgl@1371: + mgl@1371: +Normally, constant addresses which are the sum of a symbol_ref mgl@1371: +and an integer are stored inside a const RTX to mark them as mgl@1371: +constant. Therefore, there is no need to recognize such sums mgl@1371: +specifically as legitimate addresses. Normally you would simply mgl@1371: +recognize any const as legitimate. mgl@1371: + mgl@1371: +Usually PRINT_OPERAND_ADDRESS is not prepared to handle constant mgl@1371: +sums that are not marked with const. It assumes that a naked mgl@1371: +plus indicates indexing. If so, then you must reject such mgl@1371: +naked constant sums as illegitimate addresses, so that none of them will mgl@1371: +be given to PRINT_OPERAND_ADDRESS. mgl@1371: + mgl@1371: +On some machines, whether a symbolic address is legitimate depends on mgl@1371: +the section that the address refers to. On these machines, define the mgl@1371: +macro ENCODE_SECTION_INFO to store the information into the mgl@1371: +symbol_ref, and then check for it here. When you see a mgl@1371: +const, you will have to look inside it to find the mgl@1371: +symbol_ref in order to determine the section. mgl@1371: + mgl@1371: +The best way to modify the name string is by adding text to the mgl@1371: +beginning, with suitable punctuation to prevent any ambiguity. Allocate mgl@1371: +the new name in saveable_obstack. You will have to modify mgl@1371: +ASM_OUTPUT_LABELREF to remove and decode the added text and mgl@1371: +output the name accordingly, and define STRIP_NAME_ENCODING to mgl@1371: +access the original name string. mgl@1371: + mgl@1371: +You can check the information stored here into the symbol_ref in mgl@1371: +the definitions of the macros GO_IF_LEGITIMATE_ADDRESS and mgl@1371: +PRINT_OPERAND_ADDRESS. mgl@1371: +*/ mgl@1371: +#ifdef REG_OK_STRICT mgl@1371: +# define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if (avr32_legitimate_address(MODE, X, 1)) \ mgl@1371: + goto LABEL; \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: +#else mgl@1371: +# define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if (avr32_legitimate_address(MODE, X, 0)) \ mgl@1371: + goto LABEL; \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C compound statement that attempts to replace X with a valid mgl@1371: +memory address for an operand of mode MODE. win will be a mgl@1371: +C statement label elsewhere in the code; the macro definition may use mgl@1371: + mgl@1371: + GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); mgl@1371: + mgl@1371: +to avoid further processing if the address has become legitimate. mgl@1371: + mgl@1371: +X will always be the result of a call to break_out_memory_refs, mgl@1371: +and OLDX will be the operand that was given to that function to produce mgl@1371: +X. mgl@1371: + mgl@1371: +The code generated by this macro should not alter the substructure of mgl@1371: +X. If it transforms X into a more legitimate form, it mgl@1371: +should assign X (which will always be a C variable) a new value. mgl@1371: + mgl@1371: +It is not necessary for this macro to come up with a legitimate mgl@1371: +address. The compiler has standard ways of doing so in all cases. In mgl@1371: +fact, it is safe for this macro to do nothing. But often a mgl@1371: +machine-dependent strategy can generate better code. mgl@1371: +*/ mgl@1371: +#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if (GET_CODE(X) == PLUS \ mgl@1371: + && GET_CODE(XEXP(X, 0)) == REG \ mgl@1371: + && GET_CODE(XEXP(X, 1)) == CONST_INT \ mgl@1371: + && !CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(X, 1)), \ mgl@1371: + 'K', "Ks16")) \ mgl@1371: + { \ mgl@1371: + rtx index = force_reg(SImode, XEXP(X, 1)); \ mgl@1371: + X = gen_rtx_PLUS( SImode, XEXP(X, 0), index); \ mgl@1371: + } \ mgl@1371: + GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN); \ mgl@1371: + } \ mgl@1371: + while(0) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement or compound statement with a conditional mgl@1371: +goto LABEL; executed if memory address X (an RTX) can have mgl@1371: +different meanings depending on the machine mode of the memory mgl@1371: +reference it is used for or if the address is valid for some modes mgl@1371: +but not others. mgl@1371: + mgl@1371: +Autoincrement and autodecrement addresses typically have mode-dependent mgl@1371: +effects because the amount of the increment or decrement is the size mgl@1371: +of the operand being addressed. Some machines have other mode-dependent mgl@1371: +addresses. Many RISC machines have no mode-dependent addresses. mgl@1371: + mgl@1371: +You may assume that ADDR is a valid address for the machine. mgl@1371: +*/ mgl@1371: +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if (GET_CODE (ADDR) == POST_INC \ mgl@1371: + || GET_CODE (ADDR) == PRE_DEC) \ mgl@1371: + goto LABEL; \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if X is a legitimate constant for mgl@1371: +an immediate operand on the target machine. You can assume that mgl@1371: +X satisfies CONSTANT_P, so you need not check this. In fact, mgl@1371: +'1' is a suitable definition for this macro on machines where mgl@1371: +anything CONSTANT_P is valid. mgl@1371: +*/ mgl@1371: +#define LEGITIMATE_CONSTANT_P(X) avr32_legitimate_constant_p(X) mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Condition Code Status mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +C code for a data type which is used for declaring the mdep mgl@1371: +component of cc_status. It defaults to int. mgl@1371: + mgl@1371: +This macro is not used on machines that do not use cc0. mgl@1371: +*/ mgl@1371: + mgl@1371: +typedef struct mgl@1371: +{ mgl@1371: + int flags; mgl@1371: + rtx value; mgl@1371: + int fpflags; mgl@1371: + rtx fpvalue; mgl@1371: + int cond_exec_cmp_clobbered; mgl@1371: +} avr32_status_reg; mgl@1371: + mgl@1371: + mgl@1371: +#define CC_STATUS_MDEP avr32_status_reg mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression to initialize the mdep field to "empty". mgl@1371: +The default definition does nothing, since most machines don't use mgl@1371: +the field anyway. If you want to use the field, you should probably mgl@1371: +define this macro to initialize it. mgl@1371: + mgl@1371: +This macro is not used on machines that do not use cc0. mgl@1371: +*/ mgl@1371: + mgl@1371: +#define CC_STATUS_MDEP_INIT \ mgl@1371: + (cc_status.mdep.flags = CC_NONE , cc_status.mdep.cond_exec_cmp_clobbered = 0, cc_status.mdep.value = 0) mgl@1371: + mgl@1371: +#define FPCC_STATUS_INIT \ mgl@1371: + (cc_status.mdep.fpflags = CC_NONE , cc_status.mdep.fpvalue = 0) mgl@1371: + mgl@1371: +/* mgl@1371: +A C compound statement to set the components of cc_status mgl@1371: +appropriately for an insn INSN whose body is EXP. It is mgl@1371: +this macro's responsibility to recognize insns that set the condition mgl@1371: +code as a byproduct of other activity as well as those that explicitly mgl@1371: +set (cc0). mgl@1371: + mgl@1371: +This macro is not used on machines that do not use cc0. mgl@1371: + mgl@1371: +If there are insns that do not set the condition code but do alter mgl@1371: +other machine registers, this macro must check to see whether they mgl@1371: +invalidate the expressions that the condition code is recorded as mgl@1371: +reflecting. For example, on the 68000, insns that store in address mgl@1371: +registers do not set the condition code, which means that usually mgl@1371: +NOTICE_UPDATE_CC can leave cc_status unaltered for such mgl@1371: +insns. But suppose that the previous insn set the condition code mgl@1371: +based on location 'a4@@(102)' and the current insn stores a new mgl@1371: +value in 'a4'. Although the condition code is not changed by mgl@1371: +this, it will no longer be true that it reflects the contents of mgl@1371: +'a4@@(102)'. Therefore, NOTICE_UPDATE_CC must alter mgl@1371: +cc_status in this case to say that nothing is known about the mgl@1371: +condition code value. mgl@1371: + mgl@1371: +The definition of NOTICE_UPDATE_CC must be prepared to deal mgl@1371: +with the results of peephole optimization: insns whose patterns are mgl@1371: +parallel RTXs containing various reg, mem or mgl@1371: +constants which are just the operands. The RTL structure of these mgl@1371: +insns is not sufficient to indicate what the insns actually do. What mgl@1371: +NOTICE_UPDATE_CC should do when it sees one is just to run mgl@1371: +CC_STATUS_INIT. mgl@1371: + mgl@1371: +A possible definition of NOTICE_UPDATE_CC is to call a function mgl@1371: +that looks at an attribute (see Insn Attributes) named, for example, mgl@1371: +'cc'. This avoids having detailed information about patterns in mgl@1371: +two places, the 'md' file and in NOTICE_UPDATE_CC. mgl@1371: +*/ mgl@1371: + mgl@1371: +#define NOTICE_UPDATE_CC(EXP, INSN) avr32_notice_update_cc(EXP, INSN) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Describing Relative Costs of Operations mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the cost of moving data of mode MODE from a mgl@1371: +register in class FROM to one in class TO. The classes are mgl@1371: +expressed using the enumeration values such as GENERAL_REGS. A mgl@1371: +value of 2 is the default; other values are interpreted relative to mgl@1371: +that. mgl@1371: + mgl@1371: +It is not required that the cost always equal 2 when FROM is the mgl@1371: +same as TO; on some machines it is expensive to move between mgl@1371: +registers if they are not general registers. mgl@1371: + mgl@1371: +If reload sees an insn consisting of a single set between two mgl@1371: +hard registers, and if REGISTER_MOVE_COST applied to their mgl@1371: +classes returns a value of 2, reload does not check to ensure that the mgl@1371: +constraints of the insn are met. Setting a cost of other than 2 will mgl@1371: +allow reload to verify that the constraints are met. You should do this mgl@1371: +if the movm pattern's constraints do not allow such copying. mgl@1371: +*/ mgl@1371: +#define REGISTER_MOVE_COST(MODE, FROM, TO) \ mgl@1371: + ((GET_MODE_SIZE(MODE) <= 4) ? 2: \ mgl@1371: + (GET_MODE_SIZE(MODE) <= 8) ? 3: \ mgl@1371: + 4) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the cost of moving data of mode MODE between a mgl@1371: +register of class CLASS and memory; IN is zero if the value mgl@1371: +is to be written to memory, nonzero if it is to be read in. This cost mgl@1371: +is relative to those in REGISTER_MOVE_COST. If moving between mgl@1371: +registers and memory is more expensive than between two registers, you mgl@1371: +should define this macro to express the relative cost. mgl@1371: + mgl@1371: +If you do not define this macro, GCC uses a default cost of 4 plus mgl@1371: +the cost of copying via a secondary reload register, if one is mgl@1371: +needed. If your machine requires a secondary reload register to copy mgl@1371: +between memory and a register of CLASS but the reload mechanism is mgl@1371: +more complex than copying via an intermediate, define this macro to mgl@1371: +reflect the actual cost of the move. mgl@1371: + mgl@1371: +GCC defines the function memory_move_secondary_cost if mgl@1371: +secondary reloads are needed. It computes the costs due to copying via mgl@1371: +a secondary register. If your machine copies from memory using a mgl@1371: +secondary register in the conventional way but the default base value of mgl@1371: +4 is not correct for your machine, define this macro to add some other mgl@1371: +value to the result of that function. The arguments to that function mgl@1371: +are the same as to this macro. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + Memory moves are costly mgl@1371: +*/ mgl@1371: +#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ mgl@1371: + (((IN) ? ((GET_MODE_SIZE(MODE) < 4) ? 4 : \ mgl@1371: + (GET_MODE_SIZE(MODE) > 8) ? 6 : \ mgl@1371: + 3) \ mgl@1371: + : ((GET_MODE_SIZE(MODE) > 8) ? 6 : 3))) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression for the cost of a branch instruction. A value of 1 is mgl@1371: +the default; other values are interpreted relative to that. mgl@1371: +*/ mgl@1371: + /* Try to use conditionals as much as possible */ mgl@1371: +#define BRANCH_COST (TARGET_BRANCH_PRED ? 3 : 4) mgl@1371: + mgl@1371: +/*A C expression for the maximum number of instructions to execute via conditional mgl@1371: + execution instructions instead of a branch. A value of BRANCH_COST+1 is the default mgl@1371: + if the machine does not use cc0, and 1 if it does use cc0.*/ mgl@1371: +#define MAX_CONDITIONAL_EXECUTE 4 mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro as a C expression which is nonzero if accessing less mgl@1371: +than a word of memory (i.e.: a char or a short) is no mgl@1371: +faster than accessing a word of memory, i.e., if such access mgl@1371: +require more than one instruction or if there is no difference in cost mgl@1371: +between byte and (aligned) word loads. mgl@1371: + mgl@1371: +When this macro is not defined, the compiler will access a field by mgl@1371: +finding the smallest containing object; when it is defined, a fullword mgl@1371: +load will be used if alignment permits. Unless bytes accesses are mgl@1371: +faster than word accesses, using word accesses is preferable since it mgl@1371: +may eliminate subsequent memory access if subsequent accesses occur to mgl@1371: +other fields in the same word of the structure, but to different bytes. mgl@1371: +*/ mgl@1371: +#define SLOW_BYTE_ACCESS 1 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro if it is as good or better to call a constant mgl@1371: +function address than to call an address kept in a register. mgl@1371: +*/ mgl@1371: +#define NO_FUNCTION_CSE mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Adjusting the Instruction Scheduler mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/***************************************************************************** mgl@1371: + * Dividing the Output into Sections (Texts, Data, ...) * mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is a string, including spacing, containing the mgl@1371: +assembler operation that should precede instructions and read-only data. mgl@1371: +Normally "\t.text" is right. mgl@1371: +*/ mgl@1371: +#define TEXT_SECTION_ASM_OP "\t.text" mgl@1371: +/* mgl@1371: +A C statement that switches to the default section containing instructions. mgl@1371: +Normally this is not needed, as simply defining TEXT_SECTION_ASM_OP mgl@1371: +is enough. The MIPS port uses this to sort all functions after all data mgl@1371: +declarations. mgl@1371: +*/ mgl@1371: +/* #define TEXT_SECTION */ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is a string, including spacing, containing the mgl@1371: +assembler operation to identify the following data as writable initialized mgl@1371: +data. Normally "\t.data" is right. mgl@1371: +*/ mgl@1371: +#define DATA_SECTION_ASM_OP "\t.data" mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression whose value is a string, including spacing, mgl@1371: +containing the assembler operation to identify the following data as mgl@1371: +shared data. If not defined, DATA_SECTION_ASM_OP will be used. mgl@1371: +*/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression whose value is a string, including spacing, containing mgl@1371: +the assembler operation to identify the following data as read-only mgl@1371: +initialized data. mgl@1371: +*/ mgl@1371: +#undef READONLY_DATA_SECTION_ASM_OP mgl@1371: +#define READONLY_DATA_SECTION_ASM_OP \ mgl@1371: + ((TARGET_USE_RODATA_SECTION) ? \ mgl@1371: + "\t.section\t.rodata" : \ mgl@1371: + TEXT_SECTION_ASM_OP ) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression whose value is a string, including spacing, mgl@1371: +containing the assembler operation to identify the following data as mgl@1371: +uninitialized global data. If not defined, and neither mgl@1371: +ASM_OUTPUT_BSS nor ASM_OUTPUT_ALIGNED_BSS are defined, mgl@1371: +uninitialized global data will be output in the data section if mgl@1371: +-fno-common is passed, otherwise ASM_OUTPUT_COMMON will be mgl@1371: +used. mgl@1371: +*/ mgl@1371: +#define BSS_SECTION_ASM_OP "\t.section\t.bss" mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression whose value is a string, including spacing, mgl@1371: +containing the assembler operation to identify the following data as mgl@1371: +uninitialized global shared data. If not defined, and mgl@1371: +BSS_SECTION_ASM_OP is, the latter will be used. mgl@1371: +*/ mgl@1371: +/*#define SHARED_BSS_SECTION_ASM_OP "\trseg\tshared_bbs_section:data:noroot(0)\n"*/ mgl@1371: +/* mgl@1371: +If defined, a C expression whose value is a string, including spacing, mgl@1371: +containing the assembler operation to identify the following data as mgl@1371: +initialization code. If not defined, GCC will assume such a section does mgl@1371: +not exist. mgl@1371: +*/ mgl@1371: +#undef INIT_SECTION_ASM_OP mgl@1371: +#define INIT_SECTION_ASM_OP "\t.section\t.init" mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, a C expression whose value is a string, including spacing, mgl@1371: +containing the assembler operation to identify the following data as mgl@1371: +finalization code. If not defined, GCC will assume such a section does mgl@1371: +not exist. mgl@1371: +*/ mgl@1371: +#undef FINI_SECTION_ASM_OP mgl@1371: +#define FINI_SECTION_ASM_OP "\t.section\t.fini" mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, an ASM statement that switches to a different section mgl@1371: +via SECTION_OP, calls FUNCTION, and switches back to mgl@1371: +the text section. This is used in crtstuff.c if mgl@1371: +INIT_SECTION_ASM_OP or FINI_SECTION_ASM_OP to calls mgl@1371: +to initialization and finalization functions from the init and fini mgl@1371: +sections. By default, this macro uses a simple function call. Some mgl@1371: +ports need hand-crafted assembly code to avoid dependencies on mgl@1371: +registers initialized in the function prologue or to ensure that mgl@1371: +constant pools don't end up too far way in the text section. mgl@1371: +*/ mgl@1371: +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ mgl@1371: + asm ( SECTION_OP "\n" \ mgl@1371: + "mcall r6[" USER_LABEL_PREFIX #FUNC "@got]\n" \ mgl@1371: + TEXT_SECTION_ASM_OP); mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to be an expression with a nonzero value if jump mgl@1371: +tables (for tablejump insns) should be output in the text mgl@1371: +section, along with the assembler instructions. Otherwise, the mgl@1371: +readonly data section is used. mgl@1371: + mgl@1371: +This macro is irrelevant if there is no separate readonly data section. mgl@1371: +*/ mgl@1371: +/* Put jump tables in text section if we have caches. Otherwise assume that mgl@1371: + loading data from code memory is slow. */ mgl@1371: +#define JUMP_TABLES_IN_TEXT_SECTION \ mgl@1371: + (TARGET_CACHES ? 1 : 0) mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Position Independent Code (PIC) mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +#ifndef AVR32_ALWAYS_PIC mgl@1371: +#define AVR32_ALWAYS_PIC 0 mgl@1371: +#endif mgl@1371: + mgl@1371: +/* GOT is set to r6 */ mgl@1371: +#define PIC_OFFSET_TABLE_REGNUM INTERNAL_REGNUM(6) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression that is nonzero if X is a legitimate immediate mgl@1371: +operand on the target machine when generating position independent code. mgl@1371: +You can assume that X satisfies CONSTANT_P, so you need not mgl@1371: +check this. You can also assume flag_pic is true, so you need not mgl@1371: +check it either. You need not define this macro if all constants mgl@1371: +(including SYMBOL_REF) can be immediate operands when generating mgl@1371: +position independent code. mgl@1371: +*/ mgl@1371: +/* We can't directly access anything that contains a symbol, mgl@1371: + nor can we indirect via the constant pool. */ mgl@1371: +#define LEGITIMATE_PIC_OPERAND_P(X) avr32_legitimate_pic_operand_p(X) mgl@1371: + mgl@1371: + mgl@1371: +/* We need to know when we are making a constant pool; this determines mgl@1371: + whether data needs to be in the GOT or can be referenced via a GOT mgl@1371: + offset. */ mgl@1371: +extern int making_const_table; mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Defining the Output Assembler Language mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C string constant describing how to begin a comment in the target mgl@1371: +assembler language. The compiler assumes that the comment will end at mgl@1371: +the end of the line. mgl@1371: +*/ mgl@1371: +#define ASM_COMMENT_START "# " mgl@1371: + mgl@1371: +/* mgl@1371: +A C string constant for text to be output before each asm mgl@1371: +statement or group of consecutive ones. Normally this is mgl@1371: +"#APP", which is a comment that has no effect on most mgl@1371: +assemblers but tells the GNU assembler that it must check the lines mgl@1371: +that follow for all valid assembler constructs. mgl@1371: +*/ mgl@1371: +#undef ASM_APP_ON mgl@1371: +#define ASM_APP_ON "#APP\n" mgl@1371: + mgl@1371: +/* mgl@1371: +A C string constant for text to be output after each asm mgl@1371: +statement or group of consecutive ones. Normally this is mgl@1371: +"#NO_APP", which tells the GNU assembler to resume making the mgl@1371: +time-saving assumptions that are valid for ordinary compiler output. mgl@1371: +*/ mgl@1371: +#undef ASM_APP_OFF mgl@1371: +#define ASM_APP_OFF "#NO_APP\n" mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +#define FILE_ASM_OP "\t.file\n" mgl@1371: +#define IDENT_ASM_OP "\t.ident\t" mgl@1371: +#define SET_ASM_OP "\t.set\t" mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: + * Output assembly directives to switch to section name. The section mgl@1371: + * should have attributes as specified by flags, which is a bit mask mgl@1371: + * of the SECTION_* flags defined in 'output.h'. If align is nonzero, mgl@1371: + * it contains an alignment in bytes to be used for the section, mgl@1371: + * otherwise some target default should be used. Only targets that mgl@1371: + * must specify an alignment within the section directive need pay mgl@1371: + * attention to align -- we will still use ASM_OUTPUT_ALIGN. mgl@1371: + * mgl@1371: + * NOTE: This one must not be moved to avr32.c mgl@1371: + */ mgl@1371: +#undef TARGET_ASM_NAMED_SECTION mgl@1371: +#define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +You may define this macro as a C expression. You should define the mgl@1371: +expression to have a nonzero value if GCC should output the constant mgl@1371: +pool for a function before the code for the function, or a zero value if mgl@1371: +GCC should output the constant pool after the function. If you do mgl@1371: +not define this macro, the usual case, GCC will output the constant mgl@1371: +pool before the function. mgl@1371: +*/ mgl@1371: +#define CONSTANT_POOL_BEFORE_FUNCTION 0 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro as a C expression which is nonzero if the constant mgl@1371: +EXP, of type tree, should be output after the code for a mgl@1371: +function. The compiler will normally output all constants before the mgl@1371: +function; you need not define this macro if this is OK. mgl@1371: +*/ mgl@1371: +#define CONSTANT_AFTER_FUNCTION_P(EXP) 1 mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro as a C expression which is nonzero if C is mgl@1371: +used as a logical line separator by the assembler. mgl@1371: + mgl@1371: +If you do not define this macro, the default is that only mgl@1371: +the character ';' is treated as a logical line separator. mgl@1371: +*/ mgl@1371: +#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '\n') mgl@1371: + mgl@1371: + mgl@1371: +/** Output of Uninitialized Variables **/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement (sans semicolon) to output to the stdio stream mgl@1371: +STREAM the assembler definition of a common-label named mgl@1371: +NAME whose size is SIZE bytes. The variable ROUNDED mgl@1371: +is the size rounded up to whatever alignment the caller wants. mgl@1371: + mgl@1371: +Use the expression assemble_name(STREAM, NAME) to mgl@1371: +output the name itself; before and after that, output the additional mgl@1371: +assembler syntax for defining the name, and a newline. mgl@1371: + mgl@1371: +This macro controls how the assembler definitions of uninitialized mgl@1371: +common global variables are output. mgl@1371: +*/ mgl@1371: +/* mgl@1371: +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ mgl@1371: + avr32_asm_output_common(STREAM, NAME, SIZE, ROUNDED) mgl@1371: +*/ mgl@1371: + mgl@1371: +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + fputs ("\t.comm ", (FILE)); \ mgl@1371: + assemble_name ((FILE), (NAME)); \ mgl@1371: + fprintf ((FILE), ",%d\n", (SIZE)); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: +/* mgl@1371: + * Like ASM_OUTPUT_BSS except takes the required alignment as a mgl@1371: + * separate, explicit argument. If you define this macro, it is used mgl@1371: + * in place of ASM_OUTPUT_BSS, and gives you more flexibility in mgl@1371: + * handling the required alignment of the variable. The alignment is mgl@1371: + * specified as the number of bits. mgl@1371: + * mgl@1371: + * Try to use function asm_output_aligned_bss defined in file varasm.c mgl@1371: + * when defining this macro. mgl@1371: + */ mgl@1371: +#define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ mgl@1371: + asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGNMENT) mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement (sans semicolon) to output to the stdio stream mgl@1371: +STREAM the assembler definition of a local-common-label named mgl@1371: +NAME whose size is SIZE bytes. The variable ROUNDED mgl@1371: +is the size rounded up to whatever alignment the caller wants. mgl@1371: + mgl@1371: +Use the expression assemble_name(STREAM, NAME) to mgl@1371: +output the name itself; before and after that, output the additional mgl@1371: +assembler syntax for defining the name, and a newline. mgl@1371: + mgl@1371: +This macro controls how the assembler definitions of uninitialized mgl@1371: +static variables are output. mgl@1371: +*/ mgl@1371: +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + fputs ("\t.lcomm ", (FILE)); \ mgl@1371: + assemble_name ((FILE), (NAME)); \ mgl@1371: + fprintf ((FILE), ",%d, %d\n", (SIZE), 2); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement (sans semicolon) to output to the stdio stream mgl@1371: +STREAM the assembler definition of a label named NAME. mgl@1371: +Use the expression assemble_name(STREAM, NAME) to mgl@1371: +output the name itself; before and after that, output the additional mgl@1371: +assembler syntax for defining the name, and a newline. mgl@1371: +*/ mgl@1371: +#define ASM_OUTPUT_LABEL(STREAM, NAME) avr32_asm_output_label(STREAM, NAME) mgl@1371: + mgl@1371: +/* A C string containing the appropriate assembler directive to mgl@1371: + * specify the size of a symbol, without any arguments. On systems mgl@1371: + * that use ELF, the default (in 'config/elfos.h') is '"\t.size\t"'; mgl@1371: + * on other systems, the default is not to define this macro. mgl@1371: + * mgl@1371: + * Define this macro only if it is correct to use the default mgl@1371: + * definitions of ASM_ OUTPUT_SIZE_DIRECTIVE and mgl@1371: + * ASM_OUTPUT_MEASURED_SIZE for your system. If you need your own mgl@1371: + * custom definitions of those macros, or if you do not need explicit mgl@1371: + * symbol sizes at all, do not define this macro. mgl@1371: + */ mgl@1371: +#define SIZE_ASM_OP "\t.size\t" mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement (sans semicolon) to output to the stdio stream mgl@1371: +STREAM some commands that will make the label NAME global; mgl@1371: +that is, available for reference from other files. Use the expression mgl@1371: +assemble_name(STREAM, NAME) to output the name mgl@1371: +itself; before and after that, output the additional assembler syntax mgl@1371: +for making that name global, and a newline. mgl@1371: +*/ mgl@1371: +#define GLOBAL_ASM_OP "\t.globl\t" mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which evaluates to true if the target supports weak symbols. mgl@1371: + mgl@1371: +If you don't define this macro, defaults.h provides a default mgl@1371: +definition. If either ASM_WEAKEN_LABEL or ASM_WEAKEN_DECL mgl@1371: +is defined, the default definition is '1'; otherwise, it is mgl@1371: +'0'. Define this macro if you want to control weak symbol support mgl@1371: +with a compiler flag such as -melf. mgl@1371: +*/ mgl@1371: +#define SUPPORTS_WEAK 1 mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement (sans semicolon) to output to the stdio stream mgl@1371: +STREAM a reference in assembler syntax to a label named mgl@1371: +NAME. This should add '_' to the front of the name, if that mgl@1371: +is customary on your operating system, as it is in most Berkeley Unix mgl@1371: +systems. This macro is used in assemble_name. mgl@1371: +*/ mgl@1371: +#define ASM_OUTPUT_LABELREF(STREAM, NAME) \ mgl@1371: + avr32_asm_output_labelref(STREAM, NAME) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression to assign to OUTVAR (which is a variable of type mgl@1371: +char *) a newly allocated string made from the string mgl@1371: +NAME and the number NUMBER, with some suitable punctuation mgl@1371: +added. Use alloca to get space for the string. mgl@1371: + mgl@1371: +The string will be used as an argument to ASM_OUTPUT_LABELREF to mgl@1371: +produce an assembler label for an internal static variable whose name is mgl@1371: +NAME. Therefore, the string must be such as to result in valid mgl@1371: +assembler code. The argument NUMBER is different each time this mgl@1371: +macro is executed; it prevents conflicts between similarly-named mgl@1371: +internal static variables in different scopes. mgl@1371: + mgl@1371: +Ideally this string should not be a valid C identifier, to prevent any mgl@1371: +conflict with the user's own symbols. Most assemblers allow periods mgl@1371: +or percent signs in assembler symbols; putting at least one of these mgl@1371: +between the name and the number will suffice. mgl@1371: +*/ mgl@1371: +#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + (OUTVAR) = (char *) alloca (strlen ((NAME)) + 10); \ mgl@1371: + sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER)); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: + mgl@1371: +/** Macros Controlling Initialization Routines **/ mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +If defined, main will not call __main as described above. mgl@1371: +This macro should be defined for systems that control start-up code mgl@1371: +on a symbol-by-symbol basis, such as OSF/1, and should not mgl@1371: +be defined explicitly for systems that support INIT_SECTION_ASM_OP. mgl@1371: +*/ mgl@1371: +/* mgl@1371: + __main is not defined when debugging. mgl@1371: +*/ mgl@1371: +#define HAS_INIT_SECTION mgl@1371: + mgl@1371: + mgl@1371: +/** Output of Assembler Instructions **/ mgl@1371: + mgl@1371: +/* mgl@1371: +A C initializer containing the assembler's names for the machine mgl@1371: +registers, each one as a C string constant. This is what translates mgl@1371: +register numbers in the compiler into assembler language. mgl@1371: +*/ mgl@1371: + mgl@1371: +#define REGISTER_NAMES \ mgl@1371: +{ \ mgl@1371: + "pc", "lr", \ mgl@1371: + "sp", "r12", \ mgl@1371: + "r11", "r10", \ mgl@1371: + "r9", "r8", \ mgl@1371: + "r7", "r6", \ mgl@1371: + "r5", "r4", \ mgl@1371: + "r3", "r2", \ mgl@1371: + "r1", "r0", \ mgl@1371: + "f15","f14", \ mgl@1371: + "f13","f12", \ mgl@1371: + "f11","f10", \ mgl@1371: + "f9", "f8", \ mgl@1371: + "f7", "f6", \ mgl@1371: + "f5", "f4", \ mgl@1371: + "f3", "f2", \ mgl@1371: + "f1", "f0" \ mgl@1371: +} mgl@1371: + mgl@1371: +/* mgl@1371: +A C compound statement to output to stdio stream STREAM the mgl@1371: +assembler syntax for an instruction operand X. X is an mgl@1371: +RTL expression. mgl@1371: + mgl@1371: +CODE is a value that can be used to specify one of several ways mgl@1371: +of printing the operand. It is used when identical operands must be mgl@1371: +printed differently depending on the context. CODE comes from mgl@1371: +the '%' specification that was used to request printing of the mgl@1371: +operand. If the specification was just '%digit' then mgl@1371: +CODE is 0; if the specification was '%ltr digit' mgl@1371: +then CODE is the ASCII code for ltr. mgl@1371: + mgl@1371: +If X is a register, this macro should print the register's name. mgl@1371: +The names can be found in an array reg_names whose type is mgl@1371: +char *[]. reg_names is initialized from REGISTER_NAMES. mgl@1371: + mgl@1371: +When the machine description has a specification '%punct' mgl@1371: +(a '%' followed by a punctuation character), this macro is called mgl@1371: +with a null pointer for X and the punctuation character for mgl@1371: +CODE. mgl@1371: +*/ mgl@1371: +#define PRINT_OPERAND(STREAM, X, CODE) avr32_print_operand(STREAM, X, CODE) mgl@1371: + mgl@1371: +/* A C statement to be executed just prior to the output of mgl@1371: + assembler code for INSN, to modify the extracted operands so mgl@1371: + they will be output differently. mgl@1371: + mgl@1371: + Here the argument OPVEC is the vector containing the operands mgl@1371: + extracted from INSN, and NOPERANDS is the number of elements of mgl@1371: + the vector which contain meaningful data for this insn. mgl@1371: + The contents of this vector are what will be used to convert the insn mgl@1371: + template into assembler code, so you can change the assembler output mgl@1371: + by changing the contents of the vector. */ mgl@1371: +#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ mgl@1371: + avr32_final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which evaluates to true if CODE is a valid mgl@1371: +punctuation character for use in the PRINT_OPERAND macro. If mgl@1371: +PRINT_OPERAND_PUNCT_VALID_P is not defined, it means that no mgl@1371: +punctuation characters (except for the standard one, '%') are used mgl@1371: +in this way. mgl@1371: +*/ mgl@1371: +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ mgl@1371: + (((CODE) == '?') \ mgl@1371: + || ((CODE) == '!')) mgl@1371: + mgl@1371: +/* mgl@1371: +A C compound statement to output to stdio stream STREAM the mgl@1371: +assembler syntax for an instruction operand that is a memory reference mgl@1371: +whose address is X. X is an RTL expression. mgl@1371: + mgl@1371: +On some machines, the syntax for a symbolic address depends on the mgl@1371: +section that the address refers to. On these machines, define the macro mgl@1371: +ENCODE_SECTION_INFO to store the information into the mgl@1371: +symbol_ref, and then check for it here. (see Assembler Format.) mgl@1371: +*/ mgl@1371: +#define PRINT_OPERAND_ADDRESS(STREAM, X) avr32_print_operand_address(STREAM, X) mgl@1371: + mgl@1371: + mgl@1371: +/** Output of Dispatch Tables **/ mgl@1371: + mgl@1371: +/* mgl@1371: + * A C statement to output to the stdio stream stream an assembler mgl@1371: + * pseudo-instruction to generate a difference between two mgl@1371: + * labels. value and rel are the numbers of two internal labels. The mgl@1371: + * definitions of these labels are output using mgl@1371: + * (*targetm.asm_out.internal_label), and they must be printed in the mgl@1371: + * same way here. For example, mgl@1371: + * mgl@1371: + * fprintf (stream, "\t.word L%d-L%d\n", mgl@1371: + * value, rel) mgl@1371: + * mgl@1371: + * You must provide this macro on machines where the addresses in a mgl@1371: + * dispatch table are relative to the table's own address. If defined, mgl@1371: + * GCC will also use this macro on all machines when producing mgl@1371: + * PIC. body is the body of the ADDR_DIFF_VEC; it is provided so that mgl@1371: + * the mode and flags can be read. mgl@1371: + */ mgl@1371: +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ mgl@1371: + fprintf(STREAM, "\tbral\t%sL%d\n", LOCAL_LABEL_PREFIX, VALUE) mgl@1371: + mgl@1371: +/* mgl@1371: +This macro should be provided on machines where the addresses mgl@1371: +in a dispatch table are absolute. mgl@1371: + mgl@1371: +The definition should be a C statement to output to the stdio stream mgl@1371: +STREAM an assembler pseudo-instruction to generate a reference to mgl@1371: +a label. VALUE is the number of an internal label whose mgl@1371: +definition is output using ASM_OUTPUT_INTERNAL_LABEL. mgl@1371: +For example, mgl@1371: + mgl@1371: +fprintf(STREAM, "\t.word L%d\n", VALUE) mgl@1371: +*/ mgl@1371: + mgl@1371: +#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ mgl@1371: + fprintf(STREAM, "\t.long %sL%d\n", LOCAL_LABEL_PREFIX, VALUE) mgl@1371: + mgl@1371: +/** Assembler Commands for Exception Regions */ mgl@1371: + mgl@1371: +/* ToDo: All of this subsection */ mgl@1371: + mgl@1371: +/** Assembler Commands for Alignment */ mgl@1371: + mgl@1371: + mgl@1371: +/* mgl@1371: +A C statement to output to the stdio stream STREAM an assembler mgl@1371: +command to advance the location counter to a multiple of 2 to the mgl@1371: +POWER bytes. POWER will be a C expression of type int. mgl@1371: +*/ mgl@1371: +#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + if ((POWER) != 0) \ mgl@1371: + fprintf(STREAM, "\t.align\t%d\n", POWER); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: +/* mgl@1371: +Like ASM_OUTPUT_ALIGN, except that the \nop" instruction is used for padding, if mgl@1371: +necessary. mgl@1371: +*/ mgl@1371: +#define ASM_OUTPUT_ALIGN_WITH_NOP(STREAM, POWER) \ mgl@1371: + fprintf(STREAM, "\t.balignw\t%d, 0xd703\n", (1 << POWER)) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Controlling Debugging Information Format mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* How to renumber registers for dbx and gdb. */ mgl@1371: +#define DBX_REGISTER_NUMBER(REGNO) ASM_REGNUM (REGNO) mgl@1371: + mgl@1371: +/* The DWARF 2 CFA column which tracks the return address. */ mgl@1371: +#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM(LR_REGNUM) mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro if GCC should produce dwarf version 2 format mgl@1371: +debugging output in response to the -g option. mgl@1371: + mgl@1371: +To support optional call frame debugging information, you must also mgl@1371: +define INCOMING_RETURN_ADDR_RTX and either set mgl@1371: +RTX_FRAME_RELATED_P on the prologue insns if you use RTL for the mgl@1371: +prologue, or call dwarf2out_def_cfa and dwarf2out_reg_save mgl@1371: +as appropriate from TARGET_ASM_FUNCTION_PROLOGUE if you don't. mgl@1371: +*/ mgl@1371: +#define DWARF2_DEBUGGING_INFO 1 mgl@1371: + mgl@1371: + mgl@1371: +#define DWARF2_ASM_LINE_DEBUG_INFO 1 mgl@1371: +#define DWARF2_FRAME_INFO 1 mgl@1371: + mgl@1371: + mgl@1371: +/****************************************************************************** mgl@1371: + * Miscellaneous Parameters mgl@1371: + *****************************************************************************/ mgl@1371: + mgl@1371: +/* ToDo: a lot */ mgl@1371: + mgl@1371: +/* mgl@1371: +An alias for a machine mode name. This is the machine mode that mgl@1371: +elements of a jump-table should have. mgl@1371: +*/ mgl@1371: +#define CASE_VECTOR_MODE SImode mgl@1371: + mgl@1371: +/* mgl@1371: +Define this macro to be a C expression to indicate when jump-tables mgl@1371: +should contain relative addresses. If jump-tables never contain mgl@1371: +relative addresses, then you need not define this macro. mgl@1371: +*/ mgl@1371: +#define CASE_VECTOR_PC_RELATIVE 0 mgl@1371: + mgl@1371: +/* Increase the threshold for using table jumps on the UC arch. */ mgl@1371: +#define CASE_VALUES_THRESHOLD (TARGET_BRANCH_PRED ? 4 : 7) mgl@1371: + mgl@1371: +/* mgl@1371: +The maximum number of bytes that a single instruction can move quickly mgl@1371: +between memory and registers or between two memory locations. mgl@1371: +*/ mgl@1371: +#define MOVE_MAX (2*UNITS_PER_WORD) mgl@1371: + mgl@1371: + mgl@1371: +/* A C expression that is nonzero if on this machine the number of bits actually used mgl@1371: + for the count of a shift operation is equal to the number of bits needed to represent mgl@1371: + the size of the object being shifted. When this macro is nonzero, the compiler will mgl@1371: + assume that it is safe to omit a sign-extend, zero-extend, and certain bitwise 'and' mgl@1371: + instructions that truncates the count of a shift operation. On machines that have mgl@1371: + instructions that act on bit-fields at variable positions, which may include 'bit test' mgl@1371: + 378 GNU Compiler Collection (GCC) Internals mgl@1371: + instructions, a nonzero SHIFT_COUNT_TRUNCATED also enables deletion of truncations mgl@1371: + of the values that serve as arguments to bit-field instructions. mgl@1371: + If both types of instructions truncate the count (for shifts) and position (for bit-field mgl@1371: + operations), or if no variable-position bit-field instructions exist, you should define mgl@1371: + this macro. mgl@1371: + However, on some machines, such as the 80386 and the 680x0, truncation only applies mgl@1371: + to shift operations and not the (real or pretended) bit-field operations. Define SHIFT_ mgl@1371: + COUNT_TRUNCATED to be zero on such machines. Instead, add patterns to the 'md' file mgl@1371: + that include the implied truncation of the shift instructions. mgl@1371: + You need not de ne this macro if it would always have the value of zero. */ mgl@1371: +#define SHIFT_COUNT_TRUNCATED 1 mgl@1371: + mgl@1371: +/* mgl@1371: +A C expression which is nonzero if on this machine it is safe to mgl@1371: +convert an integer of INPREC bits to one of OUTPREC mgl@1371: +bits (where OUTPREC is smaller than INPREC) by merely mgl@1371: +operating on it as if it had only OUTPREC bits. mgl@1371: + mgl@1371: +On many machines, this expression can be 1. mgl@1371: + mgl@1371: +When TRULY_NOOP_TRUNCATION returns 1 for a pair of sizes for mgl@1371: +modes for which MODES_TIEABLE_P is 0, suboptimal code can result. mgl@1371: +If this is the case, making TRULY_NOOP_TRUNCATION return 0 in mgl@1371: +such cases may improve things. mgl@1371: +*/ mgl@1371: +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 mgl@1371: + mgl@1371: +/* mgl@1371: +An alias for the machine mode for pointers. On most machines, define mgl@1371: +this to be the integer mode corresponding to the width of a hardware mgl@1371: +pointer; SImode on 32-bit machine or DImode on 64-bit machines. mgl@1371: +On some machines you must define this to be one of the partial integer mgl@1371: +modes, such as PSImode. mgl@1371: + mgl@1371: +The width of Pmode must be at least as large as the value of mgl@1371: +POINTER_SIZE. If it is not equal, you must define the macro mgl@1371: +POINTERS_EXTEND_UNSIGNED to specify how pointers are extended mgl@1371: +to Pmode. mgl@1371: +*/ mgl@1371: +#define Pmode SImode mgl@1371: + mgl@1371: +/* mgl@1371: +An alias for the machine mode used for memory references to functions mgl@1371: +being called, in call RTL expressions. On most machines this mgl@1371: +should be QImode. mgl@1371: +*/ mgl@1371: +#define FUNCTION_MODE SImode mgl@1371: + mgl@1371: + mgl@1371: +#define REG_S_P(x) \ mgl@1371: + (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (XEXP (x, 0)))) mgl@1371: + mgl@1371: + mgl@1371: +/* If defined, modifies the length assigned to instruction INSN as a mgl@1371: + function of the context in which it is used. LENGTH is an lvalue mgl@1371: + that contains the initially computed length of the insn and should mgl@1371: + be updated with the correct length of the insn. */ mgl@1371: +#define ADJUST_INSN_LENGTH(INSN, LENGTH) \ mgl@1371: + ((LENGTH) = avr32_adjust_insn_length ((INSN), (LENGTH))) mgl@1371: + mgl@1371: + mgl@1371: +#define CLZ_DEFINED_VALUE_AT_ZERO(mode, value) \ mgl@1371: + (value = 32, (mode == SImode)) mgl@1371: + mgl@1371: +#define CTZ_DEFINED_VALUE_AT_ZERO(mode, value) \ mgl@1371: + (value = 32, (mode == SImode)) mgl@1371: + mgl@1371: +#define UNITS_PER_SIMD_WORD UNITS_PER_WORD mgl@1371: + mgl@1371: +#define STORE_FLAG_VALUE 1 mgl@1371: + mgl@1371: + mgl@1371: +/* IF-conversion macros. */ mgl@1371: +#define IFCVT_MODIFY_INSN( CE_INFO, PATTERN, INSN ) \ mgl@1371: + { \ mgl@1371: + (PATTERN) = avr32_ifcvt_modify_insn (CE_INFO, PATTERN, INSN, &num_true_changes); \ mgl@1371: + } mgl@1371: + mgl@1371: +#define IFCVT_EXTRA_FIELDS \ mgl@1371: + int num_cond_clobber_insns; \ mgl@1371: + int num_extra_move_insns; \ mgl@1371: + rtx extra_move_insns[MAX_CONDITIONAL_EXECUTE]; \ mgl@1371: + rtx moved_insns[MAX_CONDITIONAL_EXECUTE]; mgl@1371: + mgl@1371: +#define IFCVT_INIT_EXTRA_FIELDS( CE_INFO ) \ mgl@1371: + { \ mgl@1371: + (CE_INFO)->num_cond_clobber_insns = 0; \ mgl@1371: + (CE_INFO)->num_extra_move_insns = 0; \ mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: +#define IFCVT_MODIFY_CANCEL( CE_INFO ) avr32_ifcvt_modify_cancel (CE_INFO, &num_true_changes) mgl@1371: + mgl@1371: +#define IFCVT_ALLOW_MODIFY_TEST_IN_INSN 1 mgl@1371: +#define IFCVT_COND_EXEC_BEFORE_RELOAD (TARGET_COND_EXEC_BEFORE_RELOAD) mgl@1371: + mgl@1371: +enum avr32_builtins mgl@1371: +{ mgl@1371: + AVR32_BUILTIN_MTSR, mgl@1371: + AVR32_BUILTIN_MFSR, mgl@1371: + AVR32_BUILTIN_MTDR, mgl@1371: + AVR32_BUILTIN_MFDR, mgl@1371: + AVR32_BUILTIN_CACHE, mgl@1371: + AVR32_BUILTIN_SYNC, mgl@1371: + AVR32_BUILTIN_SSRF, mgl@1371: + AVR32_BUILTIN_CSRF, mgl@1371: + AVR32_BUILTIN_TLBR, mgl@1371: + AVR32_BUILTIN_TLBS, mgl@1371: + AVR32_BUILTIN_TLBW, mgl@1371: + AVR32_BUILTIN_BREAKPOINT, mgl@1371: + AVR32_BUILTIN_XCHG, mgl@1371: + AVR32_BUILTIN_LDXI, mgl@1371: + AVR32_BUILTIN_BSWAP16, mgl@1371: + AVR32_BUILTIN_BSWAP32, mgl@1371: + AVR32_BUILTIN_COP, mgl@1371: + AVR32_BUILTIN_MVCR_W, mgl@1371: + AVR32_BUILTIN_MVRC_W, mgl@1371: + AVR32_BUILTIN_MVCR_D, mgl@1371: + AVR32_BUILTIN_MVRC_D, mgl@1371: + AVR32_BUILTIN_MULSATHH_H, mgl@1371: + AVR32_BUILTIN_MULSATHH_W, mgl@1371: + AVR32_BUILTIN_MULSATRNDHH_H, mgl@1371: + AVR32_BUILTIN_MULSATRNDWH_W, mgl@1371: + AVR32_BUILTIN_MULSATWH_W, mgl@1371: + AVR32_BUILTIN_MACSATHH_W, mgl@1371: + AVR32_BUILTIN_SATADD_H, mgl@1371: + AVR32_BUILTIN_SATSUB_H, mgl@1371: + AVR32_BUILTIN_SATADD_W, mgl@1371: + AVR32_BUILTIN_SATSUB_W, mgl@1371: + AVR32_BUILTIN_MULWH_D, mgl@1371: + AVR32_BUILTIN_MULNWH_D, mgl@1371: + AVR32_BUILTIN_MACWH_D, mgl@1371: + AVR32_BUILTIN_MACHH_D, mgl@1371: + AVR32_BUILTIN_MUSFR, mgl@1371: + AVR32_BUILTIN_MUSTR, mgl@1371: + AVR32_BUILTIN_SATS, mgl@1371: + AVR32_BUILTIN_SATU, mgl@1371: + AVR32_BUILTIN_SATRNDS, mgl@1371: + AVR32_BUILTIN_SATRNDU, mgl@1371: + AVR32_BUILTIN_MEMS, mgl@1371: + AVR32_BUILTIN_MEMC, mgl@1371: + AVR32_BUILTIN_MEMT mgl@1371: +}; mgl@1371: + mgl@1371: + mgl@1371: +#define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) \ mgl@1371: + ((MODE == SFmode) || (MODE == DFmode)) mgl@1371: + mgl@1371: +#define RENAME_LIBRARY_SET ".set" mgl@1371: + mgl@1371: +/* Make ABI_NAME an alias for __GCC_NAME. */ mgl@1371: +#define RENAME_LIBRARY(GCC_NAME, ABI_NAME) \ mgl@1371: + __asm__ (".globl\t__avr32_" #ABI_NAME "\n" \ mgl@1371: + ".set\t__avr32_" #ABI_NAME \ mgl@1371: + ", __" #GCC_NAME "\n"); mgl@1371: + mgl@1371: +/* Give libgcc functions avr32 ABI name. */ mgl@1371: +#ifdef L_muldi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, mul64) mgl@1371: +#endif mgl@1371: +#ifdef L_divdi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divdi3, sdiv64) mgl@1371: +#endif mgl@1371: +#ifdef L_udivdi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivdi3, udiv64) mgl@1371: +#endif mgl@1371: +#ifdef L_moddi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (moddi3, smod64) mgl@1371: +#endif mgl@1371: +#ifdef L_umoddi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (umoddi3, umod64) mgl@1371: +#endif mgl@1371: +#ifdef L_ashldi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashldi3, lsl64) mgl@1371: +#endif mgl@1371: +#ifdef L_lshrdi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (lshrdi3, lsr64) mgl@1371: +#endif mgl@1371: +#ifdef L_ashrdi3 mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashrdi3, asr64) mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_fixsfdi mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, f32_to_s64) mgl@1371: +#endif mgl@1371: +#ifdef L_fixunssfdi mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, f32_to_u64) mgl@1371: +#endif mgl@1371: +#ifdef L_floatdidf mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, s64_to_f64) mgl@1371: +#endif mgl@1371: +#ifdef L_floatdisf mgl@1371: +#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, s64_to_f32) mgl@1371: +#endif mgl@1371: + mgl@1371: +#endif mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32.md mgl@1371: @@ -0,0 +1,4893 @@ mgl@1371: +;; AVR32 machine description file. mgl@1371: +;; Copyright 2003-2006 Atmel Corporation. mgl@1371: +;; mgl@1371: +;; Written by Ronny Pedersen, Atmel Norway, mgl@1371: +;; mgl@1371: +;; This file is part of GCC. mgl@1371: +;; mgl@1371: +;; This program is free software; you can redistribute it and/or modify mgl@1371: +;; it under the terms of the GNU General Public License as published by mgl@1371: +;; the Free Software Foundation; either version 2 of the License, or mgl@1371: +;; (at your option) any later version. mgl@1371: +;; mgl@1371: +;; This program is distributed in the hope that it will be useful, mgl@1371: +;; but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: +;; GNU General Public License for more details. mgl@1371: +;; mgl@1371: +;; You should have received a copy of the GNU General Public License mgl@1371: +;; along with this program; if not, write to the Free Software mgl@1371: +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. mgl@1371: + mgl@1371: +;; -*- Mode: Scheme -*- mgl@1371: + mgl@1371: +(define_attr "type" "alu,alu2,alu_sat,mulhh,mulwh,mulww_w,mulww_d,div,machh_w,macww_w,macww_d,branch,call,load,load_rm,store,load2,load4,store2,store4,fmul,fcmps,fcmpd,fcast,fmv,fmvcpu,fldd,fstd,flds,fsts,fstm" mgl@1371: + (const_string "alu")) mgl@1371: + mgl@1371: + mgl@1371: +(define_attr "cc" "none,set_vncz,set_ncz,set_cz,set_z,set_z_if_not_v2,bld,compare,cmp_cond_insn,clobber,call_set,fpcompare,from_fpcc" mgl@1371: + (const_string "none")) mgl@1371: + mgl@1371: + mgl@1371: +; NB! Keep this in sync with enum architecture_type in avr32.h mgl@1371: +(define_attr "pipeline" "ap,ucr1,ucr2,ucr2nomul" mgl@1371: + (const (symbol_ref "avr32_arch->arch_type"))) mgl@1371: + mgl@1371: +; Insn length in bytes mgl@1371: +(define_attr "length" "" mgl@1371: + (const_int 4)) mgl@1371: + mgl@1371: +; Signal if an insn is predicable and hence can be conditionally executed. mgl@1371: +(define_attr "predicable" "no,yes" (const_string "no")) mgl@1371: + mgl@1371: +;; Uses of UNSPEC in this file: mgl@1371: +(define_constants mgl@1371: + [(UNSPEC_PUSHM 0) mgl@1371: + (UNSPEC_POPM 1) mgl@1371: + (UNSPEC_UDIVMODSI4_INTERNAL 2) mgl@1371: + (UNSPEC_DIVMODSI4_INTERNAL 3) mgl@1371: + (UNSPEC_STM 4) mgl@1371: + (UNSPEC_LDM 5) mgl@1371: + (UNSPEC_MOVSICC 6) mgl@1371: + (UNSPEC_ADDSICC 7) mgl@1371: + (UNSPEC_COND_MI 8) mgl@1371: + (UNSPEC_COND_PL 9) mgl@1371: + (UNSPEC_PIC_SYM 10) mgl@1371: + (UNSPEC_PIC_BASE 11) mgl@1371: + (UNSPEC_STORE_MULTIPLE 12) mgl@1371: + (UNSPEC_STMFP 13) mgl@1371: + (UNSPEC_FPCC_TO_REG 14) mgl@1371: + (UNSPEC_REG_TO_CC 15) mgl@1371: + (UNSPEC_FORCE_MINIPOOL 16) mgl@1371: + (UNSPEC_SATS 17) mgl@1371: + (UNSPEC_SATU 18) mgl@1371: + (UNSPEC_SATRNDS 19) mgl@1371: + (UNSPEC_SATRNDU 20) mgl@1371: + ]) mgl@1371: + mgl@1371: +(define_constants mgl@1371: + [(VUNSPEC_EPILOGUE 0) mgl@1371: + (VUNSPEC_CACHE 1) mgl@1371: + (VUNSPEC_MTSR 2) mgl@1371: + (VUNSPEC_MFSR 3) mgl@1371: + (VUNSPEC_BLOCKAGE 4) mgl@1371: + (VUNSPEC_SYNC 5) mgl@1371: + (VUNSPEC_TLBR 6) mgl@1371: + (VUNSPEC_TLBW 7) mgl@1371: + (VUNSPEC_TLBS 8) mgl@1371: + (VUNSPEC_BREAKPOINT 9) mgl@1371: + (VUNSPEC_MTDR 10) mgl@1371: + (VUNSPEC_MFDR 11) mgl@1371: + (VUNSPEC_MVCR 12) mgl@1371: + (VUNSPEC_MVRC 13) mgl@1371: + (VUNSPEC_COP 14) mgl@1371: + (VUNSPEC_ALIGN 15) mgl@1371: + (VUNSPEC_POOL_START 16) mgl@1371: + (VUNSPEC_POOL_END 17) mgl@1371: + (VUNSPEC_POOL_4 18) mgl@1371: + (VUNSPEC_POOL_8 19) mgl@1371: + (VUNSPEC_POOL_16 20) mgl@1371: + (VUNSPEC_MUSFR 21) mgl@1371: + (VUNSPEC_MUSTR 22) mgl@1371: + (VUNSPEC_SYNC_CMPXCHG 23) mgl@1371: + (VUNSPEC_SYNC_SET_LOCK_AND_LOAD 24) mgl@1371: + (VUNSPEC_SYNC_STORE_IF_LOCK 25) mgl@1371: + (VUNSPEC_EH_RETURN 26) mgl@1371: + (VUNSPEC_FRS 27) mgl@1371: + (VUNSPEC_CSRF 28) mgl@1371: + (VUNSPEC_SSRF 29) mgl@1371: + ]) mgl@1371: + mgl@1371: +(define_constants mgl@1371: + [ mgl@1371: + ;; R7 = 15-7 = 8 mgl@1371: + (FP_REGNUM 8) mgl@1371: + ;; Return Register = R12 = 15 - 12 = 3 mgl@1371: + (RETVAL_REGNUM 3) mgl@1371: + ;; SP = R13 = 15 - 13 = 2 mgl@1371: + (SP_REGNUM 2) mgl@1371: + ;; LR = R14 = 15 - 14 = 1 mgl@1371: + (LR_REGNUM 1) mgl@1371: + ;; PC = R15 = 15 - 15 = 0 mgl@1371: + (PC_REGNUM 0) mgl@1371: + ;; FPSR = GENERAL_REGS + 1 = 17 mgl@1371: + (FPCC_REGNUM 17) mgl@1371: + ]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;****************************************************************************** mgl@1371: +;; Macros mgl@1371: +;;****************************************************************************** mgl@1371: + mgl@1371: +;; Integer Modes for basic alu insns mgl@1371: +(define_mode_macro INTM [SI HI QI]) mgl@1371: +(define_mode_attr alu_cc_attr [(SI "set_vncz") (HI "clobber") (QI "clobber")]) mgl@1371: + mgl@1371: +;; Move word modes mgl@1371: +(define_mode_macro MOVM [SI V2HI V4QI]) mgl@1371: + mgl@1371: +;; For mov/addcc insns mgl@1371: +(define_mode_macro ADDCC [SI HI QI]) mgl@1371: +(define_mode_macro MOVCC [SF SI HI QI]) mgl@1371: +(define_mode_macro CMP [DI SI HI QI]) mgl@1371: +(define_mode_attr store_postfix [(SF ".w") (SI ".w") (HI ".h") (QI ".b")]) mgl@1371: +(define_mode_attr load_postfix [(SF ".w") (SI ".w") (HI ".sh") (QI ".ub")]) mgl@1371: +(define_mode_attr load_postfix_s [(SI ".w") (HI ".sh") (QI ".sb")]) mgl@1371: +(define_mode_attr load_postfix_u [(SI ".w") (HI ".uh") (QI ".ub")]) mgl@1371: +(define_mode_attr pred_mem_constraint [(SF "RKu11") (SI "RKu11") (HI "RKu10") (QI "RKu09")]) mgl@1371: +(define_mode_attr cmp_constraint [(DI "rKu20") (SI "rKs21") (HI "r") (QI "r")]) mgl@1371: +(define_mode_attr cmp_predicate [(DI "register_immediate_operand") mgl@1371: + (SI "register_const_int_operand") mgl@1371: + (HI "register_operand") mgl@1371: + (QI "register_operand")]) mgl@1371: +(define_mode_attr cmp_length [(DI "6") mgl@1371: + (SI "4") mgl@1371: + (HI "4") mgl@1371: + (QI "4")]) mgl@1371: + mgl@1371: +;; For all conditional insns mgl@1371: +(define_code_macro any_cond [eq ne gt ge lt le gtu geu ltu leu]) mgl@1371: +(define_code_attr cond [(eq "eq") (ne "ne") (gt "gt") (ge "ge") (lt "lt") (le "le") mgl@1371: + (gtu "hi") (geu "hs") (ltu "lo") (leu "ls")]) mgl@1371: +(define_code_attr invcond [(eq "ne") (ne "eq") (gt "le") (ge "lt") (lt "ge") (le "gt") mgl@1371: + (gtu "ls") (geu "lo") (ltu "hs") (leu "hi")]) mgl@1371: + mgl@1371: +;; For logical operations mgl@1371: +(define_code_macro logical [and ior xor]) mgl@1371: +(define_code_attr logical_insn [(and "and") (ior "or") (xor "eor")]) mgl@1371: + mgl@1371: +;; Predicable operations with three register operands mgl@1371: +(define_code_macro predicable_op3 [and ior xor plus minus]) mgl@1371: +(define_code_attr predicable_insn3 [(and "and") (ior "or") (xor "eor") (plus "add") (minus "sub")]) mgl@1371: +(define_code_attr predicable_commutative3 [(and "%") (ior "%") (xor "%") (plus "%") (minus "")]) mgl@1371: + mgl@1371: +;; Load the predicates mgl@1371: +(include "predicates.md") mgl@1371: + mgl@1371: + mgl@1371: +;;****************************************************************************** mgl@1371: +;; Automaton pipeline description for avr32 mgl@1371: +;;****************************************************************************** mgl@1371: + mgl@1371: +(define_automaton "avr32_ap") mgl@1371: + mgl@1371: + mgl@1371: +(define_cpu_unit "is" "avr32_ap") mgl@1371: +(define_cpu_unit "a1,m1,da" "avr32_ap") mgl@1371: +(define_cpu_unit "a2,m2,d" "avr32_ap") mgl@1371: + mgl@1371: +;;Alu instructions mgl@1371: +(define_insn_reservation "alu_op" 1 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "alu")) mgl@1371: + "is,a1,a2") mgl@1371: + mgl@1371: +(define_insn_reservation "alu2_op" 2 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "alu2")) mgl@1371: + "is,is+a1,a1+a2,a2") mgl@1371: + mgl@1371: +(define_insn_reservation "alu_sat_op" 2 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "alu_sat")) mgl@1371: + "is,a1,a2") mgl@1371: + mgl@1371: + mgl@1371: +;;Mul instructions mgl@1371: +(define_insn_reservation "mulhh_op" 2 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "mulhh,mulwh")) mgl@1371: + "is,m1,m2") mgl@1371: + mgl@1371: +(define_insn_reservation "mulww_w_op" 3 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "mulww_w")) mgl@1371: + "is,m1,m1+m2,m2") mgl@1371: + mgl@1371: +(define_insn_reservation "mulww_d_op" 5 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "mulww_d")) mgl@1371: + "is,m1,m1+m2,m1+m2,m2,m2") mgl@1371: + mgl@1371: +(define_insn_reservation "div_op" 33 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "div")) mgl@1371: + "is,m1,m1*31 + m2*31,m2") mgl@1371: + mgl@1371: +(define_insn_reservation "machh_w_op" 3 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "machh_w")) mgl@1371: + "is*2,m1,m2") mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_reservation "macww_w_op" 4 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "macww_w")) mgl@1371: + "is*2,m1,m1,m2") mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_reservation "macww_d_op" 6 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "macww_d")) mgl@1371: + "is*2,m1,m1+m2,m1+m2,m2") mgl@1371: + mgl@1371: +;;Bypasses for Mac instructions, because of accumulator cache. mgl@1371: +;;Set latency as low as possible in order to let the compiler let mgl@1371: +;;mul -> mac and mac -> mac combinations which use the same mgl@1371: +;;accumulator cache be placed close together to avoid any mgl@1371: +;;instructions which can ruin the accumulator cache come inbetween. mgl@1371: +(define_bypass 4 "machh_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass") mgl@1371: +(define_bypass 5 "macww_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass") mgl@1371: +(define_bypass 7 "macww_d_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass") mgl@1371: + mgl@1371: +(define_bypass 3 "mulhh_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass") mgl@1371: +(define_bypass 4 "mulww_w_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass") mgl@1371: +(define_bypass 6 "mulww_d_op" "alu_op,alu2_op,alu_sat_op,load_op" "avr32_mul_waw_bypass") mgl@1371: + mgl@1371: + mgl@1371: +;;Bypasses for all mul/mac instructions followed by an instruction mgl@1371: +;;which reads the output AND writes the result to the same register. mgl@1371: +;;This will generate an Write After Write hazard which gives an mgl@1371: +;;extra cycle before the result is ready. mgl@1371: +(define_bypass 0 "machh_w_op" "machh_w_op" "avr32_valid_macmac_bypass") mgl@1371: +(define_bypass 0 "macww_w_op" "macww_w_op" "avr32_valid_macmac_bypass") mgl@1371: +(define_bypass 0 "macww_d_op" "macww_d_op" "avr32_valid_macmac_bypass") mgl@1371: + mgl@1371: +(define_bypass 0 "mulhh_op" "machh_w_op" "avr32_valid_mulmac_bypass") mgl@1371: +(define_bypass 0 "mulww_w_op" "macww_w_op" "avr32_valid_mulmac_bypass") mgl@1371: +(define_bypass 0 "mulww_d_op" "macww_d_op" "avr32_valid_mulmac_bypass") mgl@1371: + mgl@1371: +;;Branch and call instructions mgl@1371: +;;We assume that all branches and rcalls are predicted correctly :-) mgl@1371: +;;while calls use a lot of cycles. mgl@1371: +(define_insn_reservation "branch_op" 0 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "branch")) mgl@1371: + "nothing") mgl@1371: + mgl@1371: +(define_insn_reservation "call_op" 10 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "call")) mgl@1371: + "nothing") mgl@1371: + mgl@1371: + mgl@1371: +;;Load store instructions mgl@1371: +(define_insn_reservation "load_op" 2 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "load")) mgl@1371: + "is,da,d") mgl@1371: + mgl@1371: +(define_insn_reservation "load_rm_op" 3 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "load_rm")) mgl@1371: + "is,da,d") mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_reservation "store_op" 0 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "store")) mgl@1371: + "is,da,d") mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_reservation "load_double_op" 3 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "load2")) mgl@1371: + "is,da,da+d,d") mgl@1371: + mgl@1371: +(define_insn_reservation "load_quad_op" 4 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "load4")) mgl@1371: + "is,da,da+d,da+d,d") mgl@1371: + mgl@1371: +(define_insn_reservation "store_double_op" 0 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "store2")) mgl@1371: + "is,da,da+d,d") mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_reservation "store_quad_op" 0 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "store4")) mgl@1371: + "is,da,da+d,da+d,d") mgl@1371: + mgl@1371: +;;For store the operand to write to memory is read in d and mgl@1371: +;;the real latency between any instruction and a store is therefore mgl@1371: +;;one less than for the instructions which reads the operands in the first mgl@1371: +;;excecution stage mgl@1371: +(define_bypass 2 "load_double_op" "store_double_op" "avr32_store_bypass") mgl@1371: +(define_bypass 3 "load_quad_op" "store_quad_op" "avr32_store_bypass") mgl@1371: +(define_bypass 1 "load_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 2 "load_rm_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 1 "alu_sat_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 1 "alu2_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 1 "mulhh_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 2 "mulww_w_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 4 "mulww_d_op" "store_op" "avr32_store_bypass" ) mgl@1371: +(define_bypass 2 "machh_w_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 3 "macww_w_op" "store_op" "avr32_store_bypass") mgl@1371: +(define_bypass 5 "macww_d_op" "store_op" "avr32_store_bypass") mgl@1371: + mgl@1371: + mgl@1371: +; Bypass for load double operation. If only the first loaded word is needed mgl@1371: +; then the latency is 2 mgl@1371: +(define_bypass 2 "load_double_op" mgl@1371: + "load_op,load_rm_op,alu_sat_op, alu2_op, alu_op, mulhh_op, mulww_w_op, mgl@1371: + mulww_d_op, machh_w_op, macww_w_op, macww_d_op" mgl@1371: + "avr32_valid_load_double_bypass") mgl@1371: + mgl@1371: +; Bypass for load quad operation. If only the first or second loaded word is needed mgl@1371: +; we set the latency to 2 mgl@1371: +(define_bypass 2 "load_quad_op" mgl@1371: + "load_op,load_rm_op,alu_sat_op, alu2_op, alu_op, mulhh_op, mulww_w_op, mgl@1371: + mulww_d_op, machh_w_op, macww_w_op, macww_d_op" mgl@1371: + "avr32_valid_load_quad_bypass") mgl@1371: + mgl@1371: + mgl@1371: +;;****************************************************************************** mgl@1371: +;; End of Automaton pipeline description for avr32 mgl@1371: +;;****************************************************************************** mgl@1371: + mgl@1371: +(define_cond_exec mgl@1371: + [(match_operator 0 "avr32_comparison_operator" mgl@1371: + [(match_operand:CMP 1 "register_operand" "r") mgl@1371: + (match_operand:CMP 2 "" "")])] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "%!" mgl@1371: +) mgl@1371: + mgl@1371: +(define_cond_exec mgl@1371: + [(match_operator 0 "avr32_comparison_operator" mgl@1371: + [(and:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "one_bit_set_operand" "i")) mgl@1371: + (const_int 0)])] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "%!" mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; move mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: + mgl@1371: + mgl@1371: +;;== char - 8 bits ============================================================ mgl@1371: +(define_expand "movqi" mgl@1371: + [(set (match_operand:QI 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:QI 1 "general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( !no_new_pseudos ){ mgl@1371: + if (GET_CODE (operands[1]) == MEM && optimize){ mgl@1371: + rtx reg = gen_reg_rtx (SImode); mgl@1371: + mgl@1371: + emit_insn (gen_zero_extendqisi2 (reg, operands[1])); mgl@1371: + operands[1] = gen_lowpart (QImode, reg); mgl@1371: + } mgl@1371: + mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) == MEM) mgl@1371: + operands[1] = force_reg (QImode, operands[1]); mgl@1371: + } mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: +(define_insn "*movqi_internal" mgl@1371: + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r") mgl@1371: + (match_operand:QI 1 "general_operand" "rKs08,m,r,i"))] mgl@1371: + "register_operand (operands[0], QImode) mgl@1371: + || register_operand (operands[1], QImode)" mgl@1371: + "@ mgl@1371: + mov\t%0, %1 mgl@1371: + ld.ub\t%0, %1 mgl@1371: + st.b\t%0, %1 mgl@1371: + mov\t%0, %1" mgl@1371: + [(set_attr "length" "2,4,4,4") mgl@1371: + (set_attr "type" "alu,load_rm,store,alu")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;== short - 16 bits ========================================================== mgl@1371: +(define_expand "movhi" mgl@1371: + [(set (match_operand:HI 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:HI 1 "general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( !no_new_pseudos ){ mgl@1371: + if (GET_CODE (operands[1]) == MEM && optimize){ mgl@1371: + rtx reg = gen_reg_rtx (SImode); mgl@1371: + mgl@1371: + emit_insn (gen_extendhisi2 (reg, operands[1])); mgl@1371: + operands[1] = gen_lowpart (HImode, reg); mgl@1371: + } mgl@1371: + mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) == MEM) mgl@1371: + operands[1] = force_reg (HImode, operands[1]); mgl@1371: + } mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "*movhi_internal" mgl@1371: + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") mgl@1371: + (match_operand:HI 1 "general_operand" "rKs08,m,r,i"))] mgl@1371: + "register_operand (operands[0], HImode) mgl@1371: + || register_operand (operands[1], HImode)" mgl@1371: + "@ mgl@1371: + mov\t%0, %1 mgl@1371: + ld.sh\t%0, %1 mgl@1371: + st.h\t%0, %1 mgl@1371: + mov\t%0, %1" mgl@1371: + [(set_attr "length" "2,4,4,4") mgl@1371: + (set_attr "type" "alu,load_rm,store,alu")]) mgl@1371: + mgl@1371: + mgl@1371: +;;== int - 32 bits ============================================================ mgl@1371: + mgl@1371: +(define_expand "movmisalignsi" mgl@1371: + [(set (match_operand:SI 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:SI 1 "nonimmediate_operand" ""))] mgl@1371: + "TARGET_UNALIGNED_WORD" mgl@1371: + { mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "mov" mgl@1371: + [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "") mgl@1371: + (match_operand:MOVM 1 "avr32_non_rmw_general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) == MEM) mgl@1371: + operands[1] = force_reg (mode, operands[1]); mgl@1371: + mgl@1371: + mgl@1371: + /* Check for out of range immediate constants as these may mgl@1371: + occur during reloading, since it seems like reload does mgl@1371: + not check if the immediate is legitimate. Don't know if mgl@1371: + this is a bug? */ mgl@1371: + if ( reload_in_progress mgl@1371: + && avr32_imm_in_const_pool mgl@1371: + && GET_CODE(operands[1]) == CONST_INT mgl@1371: + && !avr32_const_ok_for_constraint_p(INTVAL(operands[1]), 'K', "Ks21") ){ mgl@1371: + operands[1] = force_const_mem(SImode, operands[1]); mgl@1371: + } mgl@1371: + mgl@1371: + /* Check for RMW memory operands. They are not allowed for mov operations mgl@1371: + only the atomic memc/s/t operations */ mgl@1371: + if ( !reload_in_progress mgl@1371: + && avr32_rmw_memory_operand (operands[0], mode) ){ mgl@1371: + operands[0] = copy_rtx (operands[0]); mgl@1371: + XEXP(operands[0], 0) = force_reg (mode, XEXP(operands[0], 0)); mgl@1371: + } mgl@1371: + mgl@1371: + if ( !reload_in_progress mgl@1371: + && avr32_rmw_memory_operand (operands[1], mode) ){ mgl@1371: + operands[1] = copy_rtx (operands[1]); mgl@1371: + XEXP(operands[1], 0) = force_reg (mode, XEXP(operands[1], 0)); mgl@1371: + } mgl@1371: + mgl@1371: + if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS) mgl@1371: + && !avr32_legitimate_pic_operand_p(operands[1]) ) mgl@1371: + operands[1] = legitimize_pic_address (operands[1], mode, mgl@1371: + (no_new_pseudos ? operands[0] : 0)); mgl@1371: + else if ( flag_pic && avr32_address_operand(operands[1], GET_MODE(operands[1])) ) mgl@1371: + /* If we have an address operand then this function uses the pic register. */ mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mov_internal" mgl@1371: + [(set (match_operand:MOVM 0 "avr32_non_rmw_nonimmediate_operand" "=r, r, r,r,r,Q,r") mgl@1371: + (match_operand:MOVM 1 "avr32_non_rmw_general_operand" "rKs08,Ks21,J,n,Q,r,W"))] mgl@1371: + "(register_operand (operands[0], mode) mgl@1371: + || register_operand (operands[1], mode)) mgl@1371: + && !avr32_rmw_memory_operand (operands[0], mode) mgl@1371: + && !avr32_rmw_memory_operand (operands[1], mode)" mgl@1371: + { mgl@1371: + switch (which_alternative) { mgl@1371: + case 0: mgl@1371: + case 1: return "mov\t%0, %1"; mgl@1371: + case 2: mgl@1371: + if ( TARGET_V2_INSNS ) mgl@1371: + return "movh\t%0, hi(%1)"; mgl@1371: + /* Fallthrough */ mgl@1371: + case 3: return "mov\t%0, lo(%1)\;orh\t%0,hi(%1)"; mgl@1371: + case 4: mgl@1371: + if ( (REG_P(XEXP(operands[1], 0)) mgl@1371: + && REGNO(XEXP(operands[1], 0)) == SP_REGNUM) mgl@1371: + || (GET_CODE(XEXP(operands[1], 0)) == PLUS mgl@1371: + && REGNO(XEXP(XEXP(operands[1], 0), 0)) == SP_REGNUM mgl@1371: + && GET_CODE(XEXP(XEXP(operands[1], 0), 1)) == CONST_INT mgl@1371: + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) % 4 == 0 mgl@1371: + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) <= 0x1FC) ) mgl@1371: + return "lddsp\t%0, %1"; mgl@1371: + else if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])) ) mgl@1371: + return "lddpc\t%0, %1"; mgl@1371: + else mgl@1371: + return "ld.w\t%0, %1"; mgl@1371: + case 5: mgl@1371: + if ( (REG_P(XEXP(operands[0], 0)) mgl@1371: + && REGNO(XEXP(operands[0], 0)) == SP_REGNUM) mgl@1371: + || (GET_CODE(XEXP(operands[0], 0)) == PLUS mgl@1371: + && REGNO(XEXP(XEXP(operands[0], 0), 0)) == SP_REGNUM mgl@1371: + && GET_CODE(XEXP(XEXP(operands[0], 0), 1)) == CONST_INT mgl@1371: + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) % 4 == 0 mgl@1371: + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) <= 0x1FC) ) mgl@1371: + return "stdsp\t%0, %1"; mgl@1371: + else mgl@1371: + return "st.w\t%0, %1"; mgl@1371: + case 6: mgl@1371: + if ( TARGET_HAS_ASM_ADDR_PSEUDOS ) mgl@1371: + return "lda.w\t%0, %1"; mgl@1371: + else mgl@1371: + return "ld.w\t%0, r6[%1@got]"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "length" "2,4,4,8,4,4,8") mgl@1371: + (set_attr "type" "alu,alu,alu,alu2,load,store,load") mgl@1371: + (set_attr "cc" "none,none,set_z_if_not_v2,set_z,none,none,clobber")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "reload_out_rmw_memory_operand" mgl@1371: + [(set (match_operand:SI 2 "register_operand" "=r") mgl@1371: + (match_operand:SI 0 "address_operand" "")) mgl@1371: + (set (mem:SI (match_dup 2)) mgl@1371: + (match_operand:SI 1 "register_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + operands[0] = XEXP(operands[0], 0); mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +(define_expand "reload_in_rmw_memory_operand" mgl@1371: + [(set (match_operand:SI 2 "register_operand" "=r") mgl@1371: + (match_operand:SI 1 "address_operand" "")) mgl@1371: + (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (mem:SI (match_dup 2)))] mgl@1371: + "" mgl@1371: + { mgl@1371: + operands[1] = XEXP(operands[1], 0); mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;; These instructions are for loading constants which cannot be loaded mgl@1371: +;; directly from the constant pool because the offset is too large mgl@1371: +;; high and lo_sum are used even tough for our case it should be mgl@1371: +;; low and high sum :-) mgl@1371: +(define_insn "mov_symbol_lo" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (high:SI (match_operand:SI 1 "immediate_operand" "i" )))] mgl@1371: + "" mgl@1371: + "mov\t%0, lo(%1)" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "add_symbol_hi" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (lo_sum:SI (match_dup 0) mgl@1371: + (match_operand:SI 1 "immediate_operand" "i" )))] mgl@1371: + "" mgl@1371: + "orh\t%0, hi(%1)" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;; When generating pic, we need to load the symbol offset into a register. mgl@1371: +;; So that the optimizer does not confuse this with a normal symbol load mgl@1371: +;; we use an unspec. The offset will be loaded from a constant pool entry, mgl@1371: +;; since that is the only type of relocation we can use. mgl@1371: +(define_insn "pic_load_addr" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec:SI [(match_operand:SI 1 "" "")] UNSPEC_PIC_SYM))] mgl@1371: + "flag_pic && CONSTANT_POOL_ADDRESS_P(XEXP(operands[1], 0))" mgl@1371: + "lddpc\t%0, %1" mgl@1371: + [(set_attr "type" "load") mgl@1371: + (set_attr "length" "4")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "pic_compute_got_from_pc" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (unspec:SI [(minus:SI (pc) mgl@1371: + (match_dup 0))] UNSPEC_PIC_BASE)) mgl@1371: + (use (label_ref (match_operand 1 "" "")))] mgl@1371: + "flag_pic" mgl@1371: + { mgl@1371: + (*targetm.asm_out.internal_label) (asm_out_file, "L", mgl@1371: + CODE_LABEL_NUMBER (operands[1])); mgl@1371: + return \"rsub\t%0, pc\"; mgl@1371: + } mgl@1371: + [(set_attr "cc" "clobber") mgl@1371: + (set_attr "length" "2")] mgl@1371: +) mgl@1371: + mgl@1371: +;;== long long int - 64 bits ================================================== mgl@1371: + mgl@1371: +(define_expand "movdi" mgl@1371: + [(set (match_operand:DI 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:DI 1 "general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) != REG) mgl@1371: + operands[1] = force_reg (DImode, operands[1]); mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_and_split "*movdi_internal" mgl@1371: + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r, r, r,r,r,m") mgl@1371: + (match_operand:DI 1 "general_operand" "r, Ks08,Ks21,G,n,m,r"))] mgl@1371: + "register_operand (operands[0], DImode) mgl@1371: + || register_operand (operands[1], DImode)" mgl@1371: + { mgl@1371: + switch (which_alternative ){ mgl@1371: + case 0: mgl@1371: + case 1: mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + case 4: mgl@1371: + return "#"; mgl@1371: + case 5: mgl@1371: + if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1]))) mgl@1371: + return "ld.d\t%0, pc[%1 - .]"; mgl@1371: + else mgl@1371: + return "ld.d\t%0, %1"; mgl@1371: + case 6: mgl@1371: + return "st.d\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: +;; Lets split all reg->reg or imm->reg transfers into two SImode transfers mgl@1371: + "reload_completed && mgl@1371: + (REG_P (operands[0]) && mgl@1371: + (REG_P (operands[1]) mgl@1371: + || GET_CODE (operands[1]) == CONST_INT mgl@1371: + || GET_CODE (operands[1]) == CONST_DOUBLE))" mgl@1371: + [(set (match_dup 0) (match_dup 1)) mgl@1371: + (set (match_dup 2) (match_dup 3))] mgl@1371: + { mgl@1371: + operands[2] = gen_highpart (SImode, operands[0]); mgl@1371: + operands[0] = gen_lowpart (SImode, operands[0]); mgl@1371: + if ( REG_P(operands[1]) ){ mgl@1371: + operands[3] = gen_highpart(SImode, operands[1]); mgl@1371: + operands[1] = gen_lowpart(SImode, operands[1]); mgl@1371: + } else if ( GET_CODE(operands[1]) == CONST_DOUBLE mgl@1371: + || GET_CODE(operands[1]) == CONST_INT ){ mgl@1371: + rtx split_const[2]; mgl@1371: + avr32_split_const_expr (DImode, SImode, operands[1], split_const); mgl@1371: + operands[3] = split_const[1]; mgl@1371: + operands[1] = split_const[0]; mgl@1371: + } else { mgl@1371: + internal_error("Illegal operand[1] for movdi split!"); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "length" "*,*,*,*,*,4,4") mgl@1371: + (set_attr "type" "*,*,*,*,*,load2,store2") mgl@1371: + (set_attr "cc" "*,*,*,*,*,none,none")]) mgl@1371: + mgl@1371: + mgl@1371: +;;== 128 bits ================================================== mgl@1371: +(define_expand "movti" mgl@1371: + [(set (match_operand:TI 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:TI 1 "nonimmediate_operand" ""))] mgl@1371: + "TARGET_ARCH_AP" mgl@1371: + { mgl@1371: + mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) != REG) mgl@1371: + operands[1] = force_reg (TImode, operands[1]); mgl@1371: + mgl@1371: + /* We must fix any pre_dec for loads and post_inc stores */ mgl@1371: + if ( GET_CODE (operands[0]) == MEM mgl@1371: + && GET_CODE (XEXP(operands[0],0)) == POST_INC ){ mgl@1371: + emit_move_insn(gen_rtx_MEM(TImode, XEXP(XEXP(operands[0],0),0)), operands[1]); mgl@1371: + emit_insn(gen_addsi3(XEXP(XEXP(operands[0],0),0), XEXP(XEXP(operands[0],0),0), GEN_INT(GET_MODE_SIZE(TImode)))); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + mgl@1371: + if ( GET_CODE (operands[1]) == MEM mgl@1371: + && GET_CODE (XEXP(operands[1],0)) == PRE_DEC ){ mgl@1371: + emit_insn(gen_addsi3(XEXP(XEXP(operands[1],0),0), XEXP(XEXP(operands[1],0),0), GEN_INT(-GET_MODE_SIZE(TImode)))); mgl@1371: + emit_move_insn(operands[0], gen_rtx_MEM(TImode, XEXP(XEXP(operands[1],0),0))); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_and_split "*movti_internal" mgl@1371: + [(set (match_operand:TI 0 "avr32_movti_dst_operand" "=r,&r, r, ,RKu00,r, n,T"))] mgl@1371: + "(register_operand (operands[0], TImode) mgl@1371: + || register_operand (operands[1], TImode))" mgl@1371: + { mgl@1371: + switch (which_alternative ){ mgl@1371: + case 0: mgl@1371: + case 2: mgl@1371: + case 4: mgl@1371: + return "#"; mgl@1371: + case 1: mgl@1371: + return "ldm\t%p1, %0"; mgl@1371: + case 3: mgl@1371: + return "stm\t%p0, %1"; mgl@1371: + case 5: mgl@1371: + return "ld.d\t%U0, pc[%1 - .]\;ld.d\t%B0, pc[%1 - . + 8]"; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + "reload_completed && mgl@1371: + (REG_P (operands[0]) && mgl@1371: + (REG_P (operands[1]) mgl@1371: + /* If this is a load from the constant pool we split it into mgl@1371: + two double loads. */ mgl@1371: + || (GET_CODE (operands[1]) == MEM mgl@1371: + && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF mgl@1371: + && CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0))) mgl@1371: + /* If this is a load where the pointer register is a part mgl@1371: + of the register list, we must split it into two double mgl@1371: + loads in order for it to be exception safe. */ mgl@1371: + || (GET_CODE (operands[1]) == MEM mgl@1371: + && register_operand (XEXP (operands[1], 0), SImode) mgl@1371: + && reg_overlap_mentioned_p (operands[0], XEXP (operands[1], 0))) mgl@1371: + || GET_CODE (operands[1]) == CONST_INT mgl@1371: + || GET_CODE (operands[1]) == CONST_DOUBLE))" mgl@1371: + [(set (match_dup 0) (match_dup 1)) mgl@1371: + (set (match_dup 2) (match_dup 3))] mgl@1371: + { mgl@1371: + operands[2] = simplify_gen_subreg ( DImode, operands[0], mgl@1371: + TImode, 0 ); mgl@1371: + operands[0] = simplify_gen_subreg ( DImode, operands[0], mgl@1371: + TImode, 8 ); mgl@1371: + if ( REG_P(operands[1]) ){ mgl@1371: + operands[3] = simplify_gen_subreg ( DImode, operands[1], mgl@1371: + TImode, 0 ); mgl@1371: + operands[1] = simplify_gen_subreg ( DImode, operands[1], mgl@1371: + TImode, 8 ); mgl@1371: + } else if ( GET_CODE(operands[1]) == CONST_DOUBLE mgl@1371: + || GET_CODE(operands[1]) == CONST_INT ){ mgl@1371: + rtx split_const[2]; mgl@1371: + avr32_split_const_expr (TImode, DImode, operands[1], split_const); mgl@1371: + operands[3] = split_const[1]; mgl@1371: + operands[1] = split_const[0]; mgl@1371: + } else if (avr32_const_pool_ref_operand (operands[1], GET_MODE(operands[1]))){ mgl@1371: + rtx split_const[2]; mgl@1371: + rtx cop = avoid_constant_pool_reference (operands[1]); mgl@1371: + if (operands[1] == cop) mgl@1371: + cop = get_pool_constant (XEXP (operands[1], 0)); mgl@1371: + avr32_split_const_expr (TImode, DImode, cop, split_const); mgl@1371: + operands[3] = force_const_mem (DImode, split_const[1]); mgl@1371: + operands[1] = force_const_mem (DImode, split_const[0]); mgl@1371: + } else { mgl@1371: + rtx ptr_reg = XEXP (operands[1], 0); mgl@1371: + operands[1] = gen_rtx_MEM (DImode, mgl@1371: + gen_rtx_PLUS ( SImode, mgl@1371: + ptr_reg, mgl@1371: + GEN_INT (8) )); mgl@1371: + operands[3] = gen_rtx_MEM (DImode, mgl@1371: + ptr_reg); mgl@1371: + mgl@1371: + /* Check if the first load will clobber the pointer. mgl@1371: + If so, we must switch the order of the operations. */ mgl@1371: + if ( reg_overlap_mentioned_p (operands[0], ptr_reg) ) mgl@1371: + { mgl@1371: + /* We need to switch the order of the operations mgl@1371: + so that the pointer register does not get clobbered mgl@1371: + after the first double word load. */ mgl@1371: + rtx tmp; mgl@1371: + tmp = operands[0]; mgl@1371: + operands[0] = operands[2]; mgl@1371: + operands[2] = tmp; mgl@1371: + tmp = operands[1]; mgl@1371: + operands[1] = operands[3]; mgl@1371: + operands[3] = tmp; mgl@1371: + } mgl@1371: + mgl@1371: + mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "*,*,4,4,*,8") mgl@1371: + (set_attr "type" "*,*,load4,store4,*,load4")]) mgl@1371: + mgl@1371: + mgl@1371: +;;== float - 32 bits ========================================================== mgl@1371: +(define_expand "movsf" mgl@1371: + [(set (match_operand:SF 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:SF 1 "general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + mgl@1371: + mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) != REG) mgl@1371: + operands[1] = force_reg (SFmode, operands[1]); mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: +(define_insn "*movsf_internal" mgl@1371: + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,r,r,m") mgl@1371: + (match_operand:SF 1 "general_operand" "r, G,F,m,r"))] mgl@1371: + "(register_operand (operands[0], SFmode) mgl@1371: + || register_operand (operands[1], SFmode))" mgl@1371: + { mgl@1371: + switch (which_alternative) { mgl@1371: + case 0: mgl@1371: + case 1: return "mov\t%0, %1"; mgl@1371: + case 2: mgl@1371: + { mgl@1371: + HOST_WIDE_INT target_float[2]; mgl@1371: + real_to_target (target_float, CONST_DOUBLE_REAL_VALUE (operands[1]), SFmode); mgl@1371: + if ( TARGET_V2_INSNS mgl@1371: + && avr32_hi16_immediate_operand (GEN_INT (target_float[0]), VOIDmode) ) mgl@1371: + return "movh\t%0, hi(%1)"; mgl@1371: + else mgl@1371: + return "mov\t%0, lo(%1)\;orh\t%0, hi(%1)"; mgl@1371: + } mgl@1371: + case 3: mgl@1371: + if ( (REG_P(XEXP(operands[1], 0)) mgl@1371: + && REGNO(XEXP(operands[1], 0)) == SP_REGNUM) mgl@1371: + || (GET_CODE(XEXP(operands[1], 0)) == PLUS mgl@1371: + && REGNO(XEXP(XEXP(operands[1], 0), 0)) == SP_REGNUM mgl@1371: + && GET_CODE(XEXP(XEXP(operands[1], 0), 1)) == CONST_INT mgl@1371: + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) % 4 == 0 mgl@1371: + && INTVAL(XEXP(XEXP(operands[1], 0), 1)) <= 0x1FC) ) mgl@1371: + return "lddsp\t%0, %1"; mgl@1371: + else if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1])) ) mgl@1371: + return "lddpc\t%0, %1"; mgl@1371: + else mgl@1371: + return "ld.w\t%0, %1"; mgl@1371: + case 4: mgl@1371: + if ( (REG_P(XEXP(operands[0], 0)) mgl@1371: + && REGNO(XEXP(operands[0], 0)) == SP_REGNUM) mgl@1371: + || (GET_CODE(XEXP(operands[0], 0)) == PLUS mgl@1371: + && REGNO(XEXP(XEXP(operands[0], 0), 0)) == SP_REGNUM mgl@1371: + && GET_CODE(XEXP(XEXP(operands[0], 0), 1)) == CONST_INT mgl@1371: + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) % 4 == 0 mgl@1371: + && INTVAL(XEXP(XEXP(operands[0], 0), 1)) <= 0x1FC) ) mgl@1371: + return "stdsp\t%0, %1"; mgl@1371: + else mgl@1371: + return "st.w\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "length" "2,4,8,4,4") mgl@1371: + (set_attr "type" "alu,alu,alu2,load,store") mgl@1371: + (set_attr "cc" "none,none,clobber,none,none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;== double - 64 bits ========================================================= mgl@1371: +(define_expand "movdf" mgl@1371: + [(set (match_operand:DF 0 "nonimmediate_operand" "") mgl@1371: + (match_operand:DF 1 "general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if (GET_CODE (operands[0]) != REG){ mgl@1371: + operands[1] = force_reg (DFmode, operands[1]); mgl@1371: + } mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn_and_split "*movdf_internal" mgl@1371: + [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,r,r,m") mgl@1371: + (match_operand:DF 1 "general_operand" " r,G,F,m,r"))] mgl@1371: + "TARGET_SOFT_FLOAT mgl@1371: + && (register_operand (operands[0], DFmode) mgl@1371: + || register_operand (operands[1], DFmode))" mgl@1371: + { mgl@1371: + switch (which_alternative ){ mgl@1371: + case 0: mgl@1371: + case 1: mgl@1371: + case 2: mgl@1371: + return "#"; mgl@1371: + case 3: mgl@1371: + if ( avr32_const_pool_ref_operand(operands[1], GET_MODE(operands[1]))) mgl@1371: + return "ld.d\t%0, pc[%1 - .]"; mgl@1371: + else mgl@1371: + return "ld.d\t%0, %1"; mgl@1371: + case 4: mgl@1371: + return "st.d\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + "TARGET_SOFT_FLOAT mgl@1371: + && reload_completed mgl@1371: + && (REG_P (operands[0]) mgl@1371: + && (REG_P (operands[1]) mgl@1371: + || GET_CODE (operands[1]) == CONST_DOUBLE))" mgl@1371: + [(set (match_dup 0) (match_dup 1)) mgl@1371: + (set (match_dup 2) (match_dup 3))] mgl@1371: + " mgl@1371: + { mgl@1371: + operands[2] = gen_highpart (SImode, operands[0]); mgl@1371: + operands[0] = gen_lowpart (SImode, operands[0]); mgl@1371: + operands[3] = gen_highpart(SImode, operands[1]); mgl@1371: + operands[1] = gen_lowpart(SImode, operands[1]); mgl@1371: + } mgl@1371: + " mgl@1371: + mgl@1371: + [(set_attr "length" "*,*,*,4,4") mgl@1371: + (set_attr "type" "*,*,*,load2,store2") mgl@1371: + (set_attr "cc" "*,*,*,none,none")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Conditional Moves mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "ld_predicable" mgl@1371: + [(set (match_operand:MOVCC 0 "register_operand" "=r") mgl@1371: + (match_operand:MOVCC 1 "avr32_non_rmw_memory_operand" ""))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "ld%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "load") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "st_predicable" mgl@1371: + [(set (match_operand:MOVCC 0 "avr32_non_rmw_memory_operand" "=") mgl@1371: + (match_operand:MOVCC 1 "register_operand" "r"))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "st%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "store") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "mov_predicable" mgl@1371: + [(set (match_operand:MOVCC 0 "register_operand" "=r") mgl@1371: + (match_operand:MOVCC 1 "avr32_cond_register_immediate_operand" "rKs08"))] mgl@1371: + "" mgl@1371: + "mov%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "alu") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Move chunks of memory mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_expand "movmemsi" mgl@1371: + [(match_operand:BLK 0 "general_operand" "") mgl@1371: + (match_operand:BLK 1 "general_operand" "") mgl@1371: + (match_operand:SI 2 "const_int_operand" "") mgl@1371: + (match_operand:SI 3 "const_int_operand" "")] mgl@1371: + "" mgl@1371: + " mgl@1371: + if (avr32_gen_movmemsi (operands)) mgl@1371: + DONE; mgl@1371: + FAIL; mgl@1371: + " mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Bit field instructions mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Instructions to insert or extract bit-fields mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "insv" mgl@1371: + [ (set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (match_operand:SI 1 "immediate_operand" "Ku05") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku05")) mgl@1371: + (match_operand 3 "register_operand" "r"))] mgl@1371: + "" mgl@1371: + "bfins\t%0, %3, %2, %1" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "set_ncz")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "extv" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (sign_extract:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" "") mgl@1371: + (match_operand:SI 3 "immediate_operand" "")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( INTVAL(operands[2]) >= 32 ) mgl@1371: + FAIL; mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +(define_expand "extzv" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extract:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" "") mgl@1371: + (match_operand:SI 3 "immediate_operand" "")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( INTVAL(operands[2]) >= 32 ) mgl@1371: + FAIL; mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "extv_internal" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (sign_extract:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku05") mgl@1371: + (match_operand:SI 3 "immediate_operand" "Ku05")))] mgl@1371: + "INTVAL(operands[2]) < 32" mgl@1371: + "bfexts\t%0, %1, %3, %2" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "set_ncz")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "extzv_internal" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (zero_extract:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku05") mgl@1371: + (match_operand:SI 3 "immediate_operand" "Ku05")))] mgl@1371: + "INTVAL(operands[2]) < 32" mgl@1371: + "bfextu\t%0, %1, %3, %2" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "set_ncz")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Some peepholes for avoiding unnecessary cast instructions mgl@1371: +;; followed by bfins. mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) mgl@1371: + (set (zero_extract:SI (match_operand 2 "register_operand" "") mgl@1371: + (match_operand:SI 3 "immediate_operand" "") mgl@1371: + (match_operand:SI 4 "immediate_operand" "")) mgl@1371: + (match_dup 0))] mgl@1371: + "((peep2_reg_dead_p(2, operands[0]) && mgl@1371: + (INTVAL(operands[3]) <= 8)))" mgl@1371: + [(set (zero_extract:SI (match_dup 2) mgl@1371: + (match_dup 3) mgl@1371: + (match_dup 4)) mgl@1371: + (match_dup 1))] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extend:SI (match_operand:HI 1 "register_operand" ""))) mgl@1371: + (set (zero_extract:SI (match_operand 2 "register_operand" "") mgl@1371: + (match_operand:SI 3 "immediate_operand" "") mgl@1371: + (match_operand:SI 4 "immediate_operand" "")) mgl@1371: + (match_dup 0))] mgl@1371: + "((peep2_reg_dead_p(2, operands[0]) && mgl@1371: + (INTVAL(operands[3]) <= 16)))" mgl@1371: + [(set (zero_extract:SI (match_dup 2) mgl@1371: + (match_dup 3) mgl@1371: + (match_dup 4)) mgl@1371: + (match_dup 1))] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; push bytes mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Implements the push instruction mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "pushm" mgl@1371: + [(set (mem:BLK (pre_dec:BLK (reg:SI SP_REGNUM))) mgl@1371: + (unspec:BLK [(match_operand 0 "const_int_operand" "")] mgl@1371: + UNSPEC_PUSHM))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if (INTVAL(operands[0])) { mgl@1371: + return "pushm\t%r0"; mgl@1371: + } else { mgl@1371: + return ""; mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "store") mgl@1371: + (set_attr "length" "2") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "stm" mgl@1371: + [(unspec [(match_operand 0 "register_operand" "r") mgl@1371: + (match_operand 1 "const_int_operand" "") mgl@1371: + (match_operand 2 "const_int_operand" "")] mgl@1371: + UNSPEC_STM)] mgl@1371: + "" mgl@1371: + { mgl@1371: + if (INTVAL(operands[1])) { mgl@1371: + if (INTVAL(operands[2]) != 0) mgl@1371: + return "stm\t--%0, %s1"; mgl@1371: + else mgl@1371: + return "stm\t%0, %s1"; mgl@1371: + } else { mgl@1371: + return ""; mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "store") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "popm" mgl@1371: + [(unspec [(match_operand 0 "const_int_operand" "")] mgl@1371: + UNSPEC_POPM)] mgl@1371: + "" mgl@1371: + { mgl@1371: + if (INTVAL(operands[0])) { mgl@1371: + return "popm %r0"; mgl@1371: + } else { mgl@1371: + return ""; mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "load") mgl@1371: + (set_attr "length" "2")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; add mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Adds reg1 with reg2 and puts the result in reg0. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "add3" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r,r,r,r,r") mgl@1371: + (plus:INTM (match_operand:INTM 1 "register_operand" "%0,r,0,r,0") mgl@1371: + (match_operand:INTM 2 "avr32_add_operand" "r,r,Is08,Is16,Is21")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + add %0, %2 mgl@1371: + add %0, %1, %2 mgl@1371: + sub %0, %n2 mgl@1371: + sub %0, %1, %n2 mgl@1371: + sub %0, %n2" mgl@1371: + mgl@1371: + [(set_attr "length" "2,4,2,4,4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: +(define_insn "add3_lsl" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (plus:INTM (ashift:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (match_operand:INTM 3 "avr32_add_shift_immediate_operand" "Ku02")) mgl@1371: + (match_operand:INTM 2 "register_operand" "r")))] mgl@1371: + "" mgl@1371: + "add %0, %2, %1 << %3" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: +(define_insn "add3_lsl2" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (plus:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (ashift:INTM (match_operand:INTM 2 "register_operand" "r") mgl@1371: + (match_operand:INTM 3 "avr32_add_shift_immediate_operand" "Ku02"))))] mgl@1371: + "" mgl@1371: + "add %0, %1, %2 << %3" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "add3_mul" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (plus:INTM (mult:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (match_operand:INTM 3 "immediate_operand" "Ku04" )) mgl@1371: + (match_operand:INTM 2 "register_operand" "r")))] mgl@1371: + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) || mgl@1371: + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)" mgl@1371: + "add %0, %2, %1 << %p3" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: +(define_insn "add3_mul2" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (plus:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (mult:INTM (match_operand:INTM 2 "register_operand" "r") mgl@1371: + (match_operand:INTM 3 "immediate_operand" "Ku04" ))))] mgl@1371: + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) || mgl@1371: + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)" mgl@1371: + "add %0, %1, %2 << %p3" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (ashift:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (plus:SI (match_dup 0) mgl@1371: + (match_operand:SI 4 "register_operand" "")))] mgl@1371: + "(peep2_reg_dead_p(2, operands[0]) && mgl@1371: + (INTVAL(operands[2]) < 4 && INTVAL(operands[2]) > 0))" mgl@1371: + [(set (match_dup 3) mgl@1371: + (plus:SI (ashift:SI (match_dup 1) mgl@1371: + (match_dup 2)) mgl@1371: + (match_dup 4)))] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (ashift:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (plus:SI (match_operand:SI 4 "register_operand" "") mgl@1371: + (match_dup 0)))] mgl@1371: + "(peep2_reg_dead_p(2, operands[0]) && mgl@1371: + (INTVAL(operands[2]) < 4 && INTVAL(operands[2]) > 0))" mgl@1371: + [(set (match_dup 3) mgl@1371: + (plus:SI (ashift:SI (match_dup 1) mgl@1371: + (match_dup 2)) mgl@1371: + (match_dup 4)))] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "adddi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r,r") mgl@1371: + (plus:DI (match_operand:DI 1 "register_operand" "%0,r") mgl@1371: + (match_operand:DI 2 "register_operand" "r,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + add %0, %2\;adc %m0, %m0, %m2 mgl@1371: + add %0, %1, %2\;adc %m0, %m1, %m2" mgl@1371: + [(set_attr "length" "6,8") mgl@1371: + (set_attr "type" "alu2") mgl@1371: + (set_attr "cc" "set_vncz")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "add_imm_predicable" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "+r") mgl@1371: + (plus:INTM (match_dup 0) mgl@1371: + (match_operand:INTM 1 "avr32_cond_immediate_operand" "%Is08")))] mgl@1371: + "" mgl@1371: + "sub%?\t%0, -%1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; subtract mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Subtract reg2 or immediate value from reg0 and puts the result in reg0. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "sub3" mgl@1371: + [(set (match_operand:INTM 0 "general_operand" "=r,r,r,r,r,r,r") mgl@1371: + (minus:INTM (match_operand:INTM 1 "nonmemory_operand" "0,r,0,r,0,r,Ks08") mgl@1371: + (match_operand:INTM 2 "nonmemory_operand" "r,r,Ks08,Ks16,Ks21,0,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + sub %0, %2 mgl@1371: + sub %0, %1, %2 mgl@1371: + sub %0, %2 mgl@1371: + sub %0, %1, %2 mgl@1371: + sub %0, %2 mgl@1371: + rsub %0, %1 mgl@1371: + rsub %0, %2, %1" mgl@1371: + [(set_attr "length" "2,4,2,4,4,2,4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: +(define_insn "*sub3_mul" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (minus:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (mult:INTM (match_operand:INTM 2 "register_operand" "r") mgl@1371: + (match_operand:SI 3 "immediate_operand" "Ku04" ))))] mgl@1371: + "(INTVAL(operands[3]) == 0) || (INTVAL(operands[3]) == 2) || mgl@1371: + (INTVAL(operands[3]) == 4) || (INTVAL(operands[3]) == 8)" mgl@1371: + "sub %0, %1, %2 << %p3" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: +(define_insn "*sub3_lsl" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (minus:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (ashift:INTM (match_operand:INTM 2 "register_operand" "r") mgl@1371: + (match_operand:SI 3 "avr32_add_shift_immediate_operand" "Ku02"))))] mgl@1371: + "" mgl@1371: + "sub %0, %1, %2 << %3" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "subdi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r,r") mgl@1371: + (minus:DI (match_operand:DI 1 "register_operand" "%0,r") mgl@1371: + (match_operand:DI 2 "register_operand" "r,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + sub %0, %2\;sbc %m0, %m0, %m2 mgl@1371: + sub %0, %1, %2\;sbc %m0, %m1, %m2" mgl@1371: + [(set_attr "length" "6,8") mgl@1371: + (set_attr "type" "alu2") mgl@1371: + (set_attr "cc" "set_vncz")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "sub_imm_predicable" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "+r") mgl@1371: + (minus:INTM (match_dup 0) mgl@1371: + (match_operand:INTM 1 "avr32_cond_immediate_operand" "Ks08")))] mgl@1371: + "" mgl@1371: + "sub%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: +(define_insn "rsub_imm_predicable" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "+r") mgl@1371: + (minus:INTM (match_operand:INTM 1 "avr32_cond_immediate_operand" "Ks08") mgl@1371: + (match_dup 0)))] mgl@1371: + "" mgl@1371: + "rsub%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; multiply mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Multiply op1 and op2 and put the value in op0. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mulqi3" mgl@1371: + [(set (match_operand:QI 0 "register_operand" "=r,r,r") mgl@1371: + (mult:QI (match_operand:QI 1 "register_operand" "%0,r,r") mgl@1371: + (match_operand:QI 2 "avr32_mul_operand" "r,r,Ks08")))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + { mgl@1371: + switch (which_alternative){ mgl@1371: + case 0: mgl@1371: + return "mul %0, %2"; mgl@1371: + case 1: mgl@1371: + return "mul %0, %1, %2"; mgl@1371: + case 2: mgl@1371: + return "mul %0, %1, %2"; mgl@1371: + default: mgl@1371: + gcc_unreachable(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "mulww_w,mulww_w,mulwh") mgl@1371: + (set_attr "length" "2,4,4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "mulsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r") mgl@1371: + (mult:SI (match_operand:SI 1 "register_operand" "%0,r,r") mgl@1371: + (match_operand:SI 2 "avr32_mul_operand" "r,r,Ks08")))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + { mgl@1371: + switch (which_alternative){ mgl@1371: + case 0: mgl@1371: + return "mul %0, %2"; mgl@1371: + case 1: mgl@1371: + return "mul %0, %1, %2"; mgl@1371: + case 2: mgl@1371: + return "mul %0, %1, %2"; mgl@1371: + default: mgl@1371: + gcc_unreachable(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "mulww_w,mulww_w,mulwh") mgl@1371: + (set_attr "length" "2,4,4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mulhisi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulhh.w %0, %1:b, %2:b" mgl@1371: + [(set_attr "type" "mulhh") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(match_scratch:DI 6 "r") mgl@1371: + (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (match_operand:HI 1 "register_operand" "")) mgl@1371: + (sign_extend:SI (match_operand:HI 2 "register_operand" "")))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (ashiftrt:SI (match_dup 0) mgl@1371: + (const_int 16)))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP mgl@1371: + && (peep2_reg_dead_p(1, operands[0]) || (REGNO(operands[0]) == REGNO(operands[3])))" mgl@1371: + [(set (match_dup 4) (sign_extend:SI (match_dup 1))) mgl@1371: + (set (match_dup 6) mgl@1371: + (ashift:DI (mult:DI (sign_extend:DI (match_dup 4)) mgl@1371: + (sign_extend:DI (match_dup 2))) mgl@1371: + (const_int 16))) mgl@1371: + (set (match_dup 3) (match_dup 5))] mgl@1371: + mgl@1371: + "{ mgl@1371: + operands[4] = gen_rtx_REG(SImode, REGNO(operands[1])); mgl@1371: + operands[5] = gen_highpart (SImode, operands[4]); mgl@1371: + }" mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mulnhisi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (neg:HI (match_operand:HI 1 "register_operand" "r"))) mgl@1371: + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulnhh.w %0, %1:b, %2:b" mgl@1371: + [(set_attr "type" "mulhh") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "machisi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (plus:SI (mult:SI mgl@1371: + (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (match_dup 0)))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "machh.w %0, %1:b, %2:b" mgl@1371: + [(set_attr "type" "machh_w") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mulsidi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r") mgl@1371: + (mult:DI mgl@1371: + (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + "muls.d %0, %1, %2" mgl@1371: + [(set_attr "type" "mulww_d") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "umulsidi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r") mgl@1371: + (mult:DI mgl@1371: + (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) mgl@1371: + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + "mulu.d %0, %1, %2" mgl@1371: + [(set_attr "type" "mulww_d") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "*mulaccsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "%r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")) mgl@1371: + (match_dup 0)))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + "mac %0, %1, %2" mgl@1371: + [(set_attr "type" "macww_w") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "*mulaccsidi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "+r") mgl@1371: + (plus:DI (mult:DI mgl@1371: + (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))) mgl@1371: + (match_dup 0)))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + "macs.d %0, %1, %2" mgl@1371: + [(set_attr "type" "macww_d") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "*umulaccsidi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "+r") mgl@1371: + (plus:DI (mult:DI mgl@1371: + (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) mgl@1371: + (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))) mgl@1371: + (match_dup 0)))] mgl@1371: + "!TARGET_NO_MUL_INSNS" mgl@1371: + "macu.d %0, %1, %2" mgl@1371: + [(set_attr "type" "macww_d") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;; Try to avoid Write-After-Write hazards for mul operations mgl@1371: +;; if it can be done mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (match_operand 1 "general_operand" "")) mgl@1371: + (sign_extend:SI (match_operand 2 "general_operand" "")))) mgl@1371: + (set (match_dup 0) mgl@1371: + (match_operator:SI 3 "alu_operator" [(match_dup 0) mgl@1371: + (match_operand 4 "general_operand" "")]))] mgl@1371: + "peep2_reg_dead_p(1, operands[2])" mgl@1371: + [(set (match_dup 5) mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (match_dup 1)) mgl@1371: + (sign_extend:SI (match_dup 2)))) mgl@1371: + (set (match_dup 0) mgl@1371: + (match_op_dup 3 [(match_dup 5) mgl@1371: + (match_dup 4)]))] mgl@1371: + "{operands[5] = gen_rtx_REG(SImode, REGNO(operands[2]));}" mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; DSP instructions mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "mulsathh_h" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (ss_truncate:HI (ashiftrt:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 15))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulsathh.h\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulhh")]) mgl@1371: + mgl@1371: +(define_insn "mulsatrndhh_h" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (ss_truncate:HI (ashiftrt:SI mgl@1371: + (plus:SI (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:SI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 1073741824)) mgl@1371: + (const_int 15))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulsatrndhh.h\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulhh")]) mgl@1371: + mgl@1371: +(define_insn "mulsathh_w" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ss_truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 1))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulsathh.w\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulhh")]) mgl@1371: + mgl@1371: +(define_insn "mulsatwh_w" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ss_truncate:SI (ashiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 15))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulsatwh.w\t%0, %1, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulwh")]) mgl@1371: + mgl@1371: +(define_insn "mulsatrndwh_w" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ss_truncate:SI (ashiftrt:DI (plus:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 1073741824)) mgl@1371: + (const_int 15))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulsatrndwh.w\t%0, %1, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulwh")]) mgl@1371: + mgl@1371: +(define_insn "macsathh_w" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (plus:SI (match_dup 0) mgl@1371: + (ss_truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 1)))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "macsathh.w\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulhh")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mulwh_d" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r") mgl@1371: + (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 16)))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulwh.d\t%0, %1, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulwh")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mulnwh_d" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r") mgl@1371: + (ashift:DI (mult:DI (not:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 16)))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "mulnwh.d\t%0, %1, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulwh")]) mgl@1371: + mgl@1371: +(define_insn "macwh_d" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "+r") mgl@1371: + (plus:DI (match_dup 0) mgl@1371: + (ashift:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r"))) mgl@1371: + (const_int 16))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "macwh.d\t%0, %1, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulwh")]) mgl@1371: + mgl@1371: +(define_insn "machh_d" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "+r") mgl@1371: + (plus:DI (match_dup 0) mgl@1371: + (mult:DI (sign_extend:DI (match_operand:HI 1 "register_operand" "%r")) mgl@1371: + (sign_extend:DI (match_operand:HI 2 "register_operand" "r")))))] mgl@1371: + "!TARGET_NO_MUL_INSNS && TARGET_DSP" mgl@1371: + "machh.d\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "mulwh")]) mgl@1371: + mgl@1371: +(define_insn "satadd_w" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ss_plus:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")))] mgl@1371: + "TARGET_DSP" mgl@1371: + "satadd.w\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "alu_sat")]) mgl@1371: + mgl@1371: +(define_insn "satsub_w" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ss_minus:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")))] mgl@1371: + "TARGET_DSP" mgl@1371: + "satsub.w\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "alu_sat")]) mgl@1371: + mgl@1371: +(define_insn "satadd_h" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (ss_plus:HI (match_operand:HI 1 "register_operand" "r") mgl@1371: + (match_operand:HI 2 "register_operand" "r")))] mgl@1371: + "TARGET_DSP" mgl@1371: + "satadd.h\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "alu_sat")]) mgl@1371: + mgl@1371: +(define_insn "satsub_h" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (ss_minus:HI (match_operand:HI 1 "register_operand" "r") mgl@1371: + (match_operand:HI 2 "register_operand" "r")))] mgl@1371: + "TARGET_DSP" mgl@1371: + "satsub.h\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "alu_sat")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; smin mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Set reg0 to the smallest value of reg1 and reg2. It is used for signed mgl@1371: +;; values in the registers. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "sminsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (smin:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")))] mgl@1371: + "" mgl@1371: + "min %0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; smax mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Set reg0 to the largest value of reg1 and reg2. It is used for signed mgl@1371: +;; values in the registers. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "smaxsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (smax:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")))] mgl@1371: + "" mgl@1371: + "max %0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Logical operations mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: + mgl@1371: + mgl@1371: +;; Split up simple DImode logical operations. Simply perform the logical mgl@1371: +;; operation on the upper and lower halves of the registers. mgl@1371: +(define_split mgl@1371: + [(set (match_operand:DI 0 "register_operand" "") mgl@1371: + (match_operator:DI 6 "logical_binary_operator" mgl@1371: + [(match_operand:DI 1 "register_operand" "") mgl@1371: + (match_operand:DI 2 "register_operand" "")]))] mgl@1371: + "reload_completed" mgl@1371: + [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) mgl@1371: + (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] mgl@1371: + " mgl@1371: + { mgl@1371: + operands[3] = gen_highpart (SImode, operands[0]); mgl@1371: + operands[0] = gen_lowpart (SImode, operands[0]); mgl@1371: + operands[4] = gen_highpart (SImode, operands[1]); mgl@1371: + operands[1] = gen_lowpart (SImode, operands[1]); mgl@1371: + operands[5] = gen_highpart (SImode, operands[2]); mgl@1371: + operands[2] = gen_lowpart (SImode, operands[2]); mgl@1371: + }" mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Logical operations with shifted operand mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "si_lshift" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (logical:SI (match_operator:SI 4 "logical_shift_operator" mgl@1371: + [(match_operand:SI 2 "register_operand" "r") mgl@1371: + (match_operand:SI 3 "immediate_operand" "Ku05")]) mgl@1371: + (match_operand:SI 1 "register_operand" "r")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( GET_CODE(operands[4]) == ASHIFT ) mgl@1371: + return "\t%0, %1, %2 << %3"; mgl@1371: + else mgl@1371: + return "\t%0, %1, %2 >> %3"; mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "cc" "set_z")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;;************************************************ mgl@1371: +;; Peepholes for detecting logical operantions mgl@1371: +;; with shifted operands mgl@1371: +;;************************************************ mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 3 "register_operand" "") mgl@1371: + (match_operator:SI 5 "logical_shift_operator" mgl@1371: + [(match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" "")])) mgl@1371: + (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (logical:SI (match_operand:SI 4 "register_operand" "") mgl@1371: + (match_dup 3)))] mgl@1371: + "(dead_or_set_p(insn, operands[3])) || (REGNO(operands[3]) == REGNO(operands[0]))" mgl@1371: + { mgl@1371: + if ( GET_CODE(operands[5]) == ASHIFT ) mgl@1371: + return "\t%0, %4, %1 << %2"; mgl@1371: + else mgl@1371: + return "\t%0, %4, %1 >> %2"; mgl@1371: + } mgl@1371: + [(set_attr "cc" "set_z")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 3 "register_operand" "") mgl@1371: + (match_operator:SI 5 "logical_shift_operator" mgl@1371: + [(match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" "")])) mgl@1371: + (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (logical:SI (match_dup 3) mgl@1371: + (match_operand:SI 4 "register_operand" "")))] mgl@1371: + "(dead_or_set_p(insn, operands[3])) || (REGNO(operands[3]) == REGNO(operands[0]))" mgl@1371: + { mgl@1371: + if ( GET_CODE(operands[5]) == ASHIFT ) mgl@1371: + return "\t%0, %4, %1 << %2"; mgl@1371: + else mgl@1371: + return "\t%0, %4, %1 >> %2"; mgl@1371: + } mgl@1371: + [(set_attr "cc" "set_z")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (match_operator:SI 5 "logical_shift_operator" mgl@1371: + [(match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" "")])) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (logical:SI (match_operand:SI 4 "register_operand" "") mgl@1371: + (match_dup 0)))] mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[3]) == REGNO(operands[0]))" mgl@1371: + mgl@1371: + [(set (match_dup 3) mgl@1371: + (logical:SI (match_op_dup:SI 5 [(match_dup 1) (match_dup 2)]) mgl@1371: + (match_dup 4)))] mgl@1371: + mgl@1371: + "" mgl@1371: +) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (match_operator:SI 5 "logical_shift_operator" mgl@1371: + [(match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" "")])) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (logical:SI (match_dup 0) mgl@1371: + (match_operand:SI 4 "register_operand" "")))] mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[3]) == REGNO(operands[0]))" mgl@1371: + mgl@1371: + [(set (match_dup 3) mgl@1371: + (logical:SI (match_op_dup:SI 5 [(match_dup 1) (match_dup 2)]) mgl@1371: + (match_dup 4)))] mgl@1371: + mgl@1371: + "" mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; and mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Store the result after a bitwise logical-and between reg0 and reg2 in reg0. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "andnsi" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (and:SI (match_dup 0) mgl@1371: + (not:SI (match_operand:SI 1 "register_operand" "r"))))] mgl@1371: + "" mgl@1371: + "andn %0, %1" mgl@1371: + [(set_attr "cc" "set_z") mgl@1371: + (set_attr "length" "2")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "andsi3" mgl@1371: + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r,r, r, r,r,r,r,r") mgl@1371: + (and:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,r,0,0, 0, 0,0,0,0,r" ) mgl@1371: + (match_operand:SI 2 "nonmemory_operand" " N,M,N,Ku16,Ks17,J,L,r,i,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + memc\t%0, %z2 mgl@1371: + bfextu\t%0, %1, 0, %z2 mgl@1371: + cbr\t%0, %z2 mgl@1371: + andl\t%0, %2, COH mgl@1371: + andl\t%0, lo(%2) mgl@1371: + andh\t%0, hi(%2), COH mgl@1371: + andh\t%0, hi(%2) mgl@1371: + and\t%0, %2 mgl@1371: + andh\t%0, hi(%2)\;andl\t%0, lo(%2) mgl@1371: + and\t%0, %1, %2" mgl@1371: + mgl@1371: + [(set_attr "length" "4,4,2,4,4,4,4,2,8,4") mgl@1371: + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z,set_z")]) mgl@1371: + mgl@1371: +(define_insn "anddi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=&r,&r") mgl@1371: + (and:DI (match_operand:DI 1 "register_operand" "%0,r") mgl@1371: + (match_operand:DI 2 "register_operand" "r,r")))] mgl@1371: + "" mgl@1371: + "#" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; or mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Store the result after a bitwise inclusive-or between reg0 and reg2 in reg0. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "iorsi3" mgl@1371: + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r,r, r,r,r,r") mgl@1371: + (ior:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0,0, 0,0,0,r" ) mgl@1371: + (match_operand:SI 2 "nonmemory_operand" " O,O,Ku16,J,r,i,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + mems\t%0, %p2 mgl@1371: + sbr\t%0, %p2 mgl@1371: + orl\t%0, %2 mgl@1371: + orh\t%0, hi(%2) mgl@1371: + or\t%0, %2 mgl@1371: + orh\t%0, hi(%2)\;orl\t%0, lo(%2) mgl@1371: + or\t%0, %1, %2" mgl@1371: + mgl@1371: + [(set_attr "length" "4,2,4,4,2,8,4") mgl@1371: + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z,set_z")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "iordi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=&r,&r") mgl@1371: + (ior:DI (match_operand:DI 1 "register_operand" "%0,r") mgl@1371: + (match_operand:DI 2 "register_operand" "r,r")))] mgl@1371: + "" mgl@1371: + "#" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; xor bytes mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Store the result after a bitwise exclusive-or between reg0 and reg2 in reg0. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "xorsi3" mgl@1371: + [(set (match_operand:SI 0 "avr32_rmw_memory_or_register_operand" "=Y,r, r,r,r,r") mgl@1371: + (xor:SI (match_operand:SI 1 "avr32_rmw_memory_or_register_operand" "%0,0, 0,0,0,r" ) mgl@1371: + (match_operand:SI 2 "nonmemory_operand" " O,Ku16,J,r,i,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + memt\t%0, %p2 mgl@1371: + eorl\t%0, %2 mgl@1371: + eorh\t%0, hi(%2) mgl@1371: + eor\t%0, %2 mgl@1371: + eorh\t%0, hi(%2)\;eorl\t%0, lo(%2) mgl@1371: + eor\t%0, %1, %2" mgl@1371: + mgl@1371: + [(set_attr "length" "4,4,4,2,8,4") mgl@1371: + (set_attr "cc" "none,set_z,set_z,set_z,set_z,set_z")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "xordi3" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=&r,&r") mgl@1371: + (xor:DI (match_operand:DI 1 "register_operand" "%0,r") mgl@1371: + (match_operand:DI 2 "register_operand" "r,r")))] mgl@1371: + "" mgl@1371: + "#" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Three operand predicable insns mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "_predicable" mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (predicable_op3:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (match_operand:INTM 2 "register_operand" "r")))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "%?\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn_and_split "_imm_clobber_predicable" mgl@1371: + [(parallel mgl@1371: + [(set (match_operand:INTM 0 "register_operand" "=r") mgl@1371: + (predicable_op3:INTM (match_operand:INTM 1 "register_operand" "r") mgl@1371: + (match_operand:INTM 2 "avr32_mov_immediate_operand" "JKs21"))) mgl@1371: + (clobber (match_operand:INTM 3 "register_operand" "=&r"))])] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + { mgl@1371: + if ( current_insn_predicate != NULL_RTX ) mgl@1371: + { mgl@1371: + if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks08") ) mgl@1371: + return "%! mov%?\t%3, %2\;%?\t%0, %1, %3"; mgl@1371: + else if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21") ) mgl@1371: + return "%! mov\t%3, %2\;%?\t%0, %1, %3"; mgl@1371: + else mgl@1371: + return "%! movh\t%3, hi(%2)\;%?\t%0, %1, %3"; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + if ( !avr32_cond_imm_clobber_splittable (insn, operands) ) mgl@1371: + { mgl@1371: + if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks08") ) mgl@1371: + return "mov%?\t%3, %2\;%?\t%0, %1, %3"; mgl@1371: + else if ( avr32_const_ok_for_constraint_p (INTVAL (operands[2]), 'K', "Ks21") ) mgl@1371: + return "mov\t%3, %2\;%?\t%0, %1, %3"; mgl@1371: + else mgl@1371: + return "movh\t%3, hi(%2)\;%?\t%0, %1, %3"; mgl@1371: + } mgl@1371: + return "#"; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + ;; If we find out that we could not actually do if-conversion on the block mgl@1371: + ;; containing this insn we convert it back to normal immediate format mgl@1371: + ;; to avoid outputing a redundant move insn mgl@1371: + ;; Do not split until after we have checked if we can make the insn mgl@1371: + ;; conditional. mgl@1371: + "(GET_CODE (PATTERN (insn)) != COND_EXEC mgl@1371: + && cfun->machine->ifcvt_after_reload mgl@1371: + && avr32_cond_imm_clobber_splittable (insn, operands))" mgl@1371: + [(set (match_dup 0) mgl@1371: + (predicable_op3:INTM (match_dup 1) mgl@1371: + (match_dup 2)))] mgl@1371: + "" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Zero extend predicable insns mgl@1371: +;;============================================================================= mgl@1371: +(define_insn_and_split "zero_extendhisi_clobber_predicable" mgl@1371: + [(parallel mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))) mgl@1371: + (clobber (match_operand:SI 2 "register_operand" "=&r"))])] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + { mgl@1371: + if ( current_insn_predicate != NULL_RTX ) mgl@1371: + { mgl@1371: + return "%! mov\t%2, 0xffff\;and%?\t%0, %1, %2"; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + return "#"; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + ;; If we find out that we could not actually do if-conversion on the block mgl@1371: + ;; containing this insn we convert it back to normal immediate format mgl@1371: + ;; to avoid outputing a redundant move insn mgl@1371: + ;; Do not split until after we have checked if we can make the insn mgl@1371: + ;; conditional. mgl@1371: + "(GET_CODE (PATTERN (insn)) != COND_EXEC mgl@1371: + && cfun->machine->ifcvt_after_reload)" mgl@1371: + [(set (match_dup 0) mgl@1371: + (zero_extend:SI (match_dup 1)))] mgl@1371: + "" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn_and_split "zero_extendqisi_clobber_predicable" mgl@1371: + [(parallel mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (zero_extend:SI (match_operand:QI 1 "register_operand" "r"))) mgl@1371: + (clobber (match_operand:SI 2 "register_operand" "=&r"))])] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + { mgl@1371: + if ( current_insn_predicate != NULL_RTX ) mgl@1371: + { mgl@1371: + return "%! mov\t%2, 0xff\;and%?\t%0, %1, %2"; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + return "#"; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + ;; If we find out that we could not actually do if-conversion on the block mgl@1371: + ;; containing this insn we convert it back to normal immediate format mgl@1371: + ;; to avoid outputing a redundant move insn mgl@1371: + ;; Do not split until after we have checked if we can make the insn mgl@1371: + ;; conditional. mgl@1371: + "(GET_CODE (PATTERN (insn)) != COND_EXEC mgl@1371: + && cfun->machine->ifcvt_after_reload)" mgl@1371: + [(set (match_dup 0) mgl@1371: + (zero_extend:SI (match_dup 1)))] mgl@1371: + "" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn_and_split "zero_extendqihi_clobber_predicable" mgl@1371: + [(parallel mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (zero_extend:HI (match_operand:QI 1 "register_operand" "r"))) mgl@1371: + (clobber (match_operand:SI 2 "register_operand" "=&r"))])] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + { mgl@1371: + if ( current_insn_predicate != NULL_RTX ) mgl@1371: + { mgl@1371: + return "%! mov\t%2, 0xff\;and%?\t%0, %1, %2"; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + return "#"; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + ;; If we find out that we could not actually do if-conversion on the block mgl@1371: + ;; containing this insn we convert it back to normal immediate format mgl@1371: + ;; to avoid outputing a redundant move insn mgl@1371: + ;; Do not split until after we have checked if we can make the insn mgl@1371: + ;; conditional. mgl@1371: + "(GET_CODE (PATTERN (insn)) != COND_EXEC mgl@1371: + && cfun->machine->ifcvt_after_reload)" mgl@1371: + [(set (match_dup 0) mgl@1371: + (zero_extend:HI (match_dup 1)))] mgl@1371: + "" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: + ) mgl@1371: +;;============================================================================= mgl@1371: +;; divmod mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Signed division that produces both a quotient and a remainder. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "divmodsi4" mgl@1371: + [(parallel [ mgl@1371: + (parallel [ mgl@1371: + (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (div:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r"))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "=r") mgl@1371: + (mod:SI (match_dup 1) mgl@1371: + (match_dup 2)))]) mgl@1371: + (use (match_dup 4))])] mgl@1371: + "" mgl@1371: + { mgl@1371: + if (! no_new_pseudos) { mgl@1371: + operands[4] = gen_reg_rtx (DImode); mgl@1371: + mgl@1371: + emit_insn(gen_divmodsi4_internal(operands[4],operands[1],operands[2])); mgl@1371: + emit_move_insn(operands[0], gen_rtx_SUBREG( SImode, operands[4], 4)); mgl@1371: + emit_move_insn(operands[3], gen_rtx_SUBREG( SImode, operands[4], 0)); mgl@1371: + mgl@1371: + DONE; mgl@1371: + } else { mgl@1371: + FAIL; mgl@1371: + } mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "divmodsi4_internal" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r") mgl@1371: + (unspec:DI [(match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")] mgl@1371: + UNSPEC_DIVMODSI4_INTERNAL))] mgl@1371: + "" mgl@1371: + "divs %0, %1, %2" mgl@1371: + [(set_attr "type" "div") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; udivmod mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Unsigned division that produces both a quotient and a remainder. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "udivmodsi4" mgl@1371: + [(parallel [ mgl@1371: + (parallel [ mgl@1371: + (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (udiv:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r"))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "=r") mgl@1371: + (umod:SI (match_dup 1) mgl@1371: + (match_dup 2)))]) mgl@1371: + (use (match_dup 4))])] mgl@1371: + "" mgl@1371: + { mgl@1371: + if (! no_new_pseudos) { mgl@1371: + operands[4] = gen_reg_rtx (DImode); mgl@1371: + mgl@1371: + emit_insn(gen_udivmodsi4_internal(operands[4],operands[1],operands[2])); mgl@1371: + emit_move_insn(operands[0], gen_rtx_SUBREG( SImode, operands[4], 4)); mgl@1371: + emit_move_insn(operands[3], gen_rtx_SUBREG( SImode, operands[4], 0)); mgl@1371: + mgl@1371: + DONE; mgl@1371: + } else { mgl@1371: + FAIL; mgl@1371: + } mgl@1371: + }) mgl@1371: + mgl@1371: +(define_insn "udivmodsi4_internal" mgl@1371: + [(set (match_operand:DI 0 "register_operand" "=r") mgl@1371: + (unspec:DI [(match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "register_operand" "r")] mgl@1371: + UNSPEC_UDIVMODSI4_INTERNAL))] mgl@1371: + "" mgl@1371: + "divu %0, %1, %2" mgl@1371: + [(set_attr "type" "div") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Arithmetic-shift left mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Arithmetic-shift reg0 left by reg2 or immediate value. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "ashlsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r") mgl@1371: + (ashift:SI (match_operand:SI 1 "register_operand" "r,0,r") mgl@1371: + (match_operand:SI 2 "nonmemory_operand" "r,Ku05,Ku05")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + lsl %0, %1, %2 mgl@1371: + lsl %0, %2 mgl@1371: + lsl %0, %1, %2" mgl@1371: + [(set_attr "length" "4,2,4") mgl@1371: + (set_attr "cc" "set_ncz")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Arithmetic-shift right mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Arithmetic-shift reg0 right by an immediate value. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "ashrsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r") mgl@1371: + (ashiftrt:SI (match_operand:SI 1 "register_operand" "r,0,r") mgl@1371: + (match_operand:SI 2 "nonmemory_operand" "r,Ku05,Ku05")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + asr %0, %1, %2 mgl@1371: + asr %0, %2 mgl@1371: + asr %0, %1, %2" mgl@1371: + [(set_attr "length" "4,2,4") mgl@1371: + (set_attr "cc" "set_ncz")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Logical shift right mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Logical shift reg0 right by an immediate value. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "lshrsi3" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r") mgl@1371: + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,0,r") mgl@1371: + (match_operand:SI 2 "nonmemory_operand" "r,Ku05,Ku05")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + lsr %0, %1, %2 mgl@1371: + lsr %0, %2 mgl@1371: + lsr %0, %1, %2" mgl@1371: + [(set_attr "length" "4,2,4") mgl@1371: + (set_attr "cc" "set_ncz")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; neg mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Negate operand 1 and store the result in operand 0. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "negsi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r") mgl@1371: + (neg:SI (match_operand:SI 1 "register_operand" "0,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + neg\t%0 mgl@1371: + rsub\t%0, %1, 0" mgl@1371: + [(set_attr "length" "2,4") mgl@1371: + (set_attr "cc" "set_vncz")]) mgl@1371: + mgl@1371: +(define_insn "negsi2_predicable" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (neg:SI (match_dup 0)))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "rsub%?\t%0, 0" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; abs mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Store the absolute value of operand 1 into operand 0. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "abssi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (abs:SI (match_operand:SI 1 "register_operand" "0")))] mgl@1371: + "" mgl@1371: + "abs\t%0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "set_z")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; one_cmpl mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Store the bitwise-complement of operand 1 into operand 0. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "one_cmplsi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r") mgl@1371: + (not:SI (match_operand:SI 1 "register_operand" "0,r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + com\t%0 mgl@1371: + rsub\t%0, %1, -1" mgl@1371: + [(set_attr "length" "2,4") mgl@1371: + (set_attr "cc" "set_z")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "one_cmplsi2_predicable" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (not:SI (match_dup 0)))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "rsub%?\t%0, -1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Bit load mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Load a bit into Z and C flags mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "bldsi" mgl@1371: + [(set (cc0) mgl@1371: + (and:SI (match_operand:SI 0 "register_operand" "r") mgl@1371: + (match_operand:SI 1 "one_bit_set_operand" "i")))] mgl@1371: + "" mgl@1371: + "bld\t%0, %p1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "bld")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Compare mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Compare reg0 with reg1 or an immediate value. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_expand "cmp" mgl@1371: + [(set (cc0) mgl@1371: + (compare:CMP mgl@1371: + (match_operand:CMP 0 "register_operand" "") mgl@1371: + (match_operand:CMP 1 "" "")))] mgl@1371: + "" mgl@1371: + "{ mgl@1371: + avr32_compare_op0 = operands[0]; mgl@1371: + avr32_compare_op1 = operands[1]; mgl@1371: + }" mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "cmp_internal" mgl@1371: + [(set (cc0) mgl@1371: + (compare:CMP mgl@1371: + (match_operand:CMP 0 "register_operand" "r") mgl@1371: + (match_operand:CMP 1 "" "")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + set_next_insn_cond(insn, mgl@1371: + avr32_output_cmp(get_next_insn_cond(insn), GET_MODE (operands[0]), operands[0], operands[1])); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "compare")]) mgl@1371: + mgl@1371: + mgl@1371: +;;;============================================================================= mgl@1371: +;; Test if zero mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Compare reg against zero and set the condition codes. mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "tstsi" mgl@1371: + [(set (cc0) mgl@1371: + (match_operand:SI 0 "register_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + avr32_compare_op0 = operands[0]; mgl@1371: + avr32_compare_op1 = const0_rtx; mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "tstsi_internal" mgl@1371: + [(set (cc0) mgl@1371: + (match_operand:SI 0 "register_operand" "r"))] mgl@1371: + "" mgl@1371: + { mgl@1371: + set_next_insn_cond(insn, mgl@1371: + avr32_output_cmp(get_next_insn_cond(insn), SImode, operands[0], const0_rtx)); mgl@1371: + mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "compare")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "tstdi" mgl@1371: + [(set (cc0) mgl@1371: + (match_operand:DI 0 "register_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + avr32_compare_op0 = operands[0]; mgl@1371: + avr32_compare_op1 = const0_rtx; mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "tstdi_internal" mgl@1371: + [(set (cc0) mgl@1371: + (match_operand:DI 0 "register_operand" "r"))] mgl@1371: + "" mgl@1371: + { mgl@1371: + set_next_insn_cond(insn, mgl@1371: + avr32_output_cmp(get_next_insn_cond(insn), DImode, operands[0], const0_rtx)); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu2") mgl@1371: + (set_attr "cc" "compare")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Convert operands mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "truncdisi2" mgl@1371: + [(set (match_operand:SI 0 "general_operand" "") mgl@1371: + (truncate:SI (match_operand:DI 1 "general_operand" "")))] mgl@1371: + "" mgl@1371: + "truncdisi2") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Extend mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "extendhisi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") mgl@1371: + (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,,m")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "casts.h\t%0"; mgl@1371: + case 1: mgl@1371: + return "bfexts\t%0, %1, 0, 16"; mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + return "ld.sh\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "2,4,2,4") mgl@1371: + (set_attr "cc" "set_ncz,set_ncz,none,none") mgl@1371: + (set_attr "type" "alu,alu,load_rm,load_rm")]) mgl@1371: + mgl@1371: +(define_insn "extendqisi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") mgl@1371: + (sign_extend:SI (match_operand:QI 1 "extendqi_operand" "0,r,RKu00,m")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "casts.b\t%0"; mgl@1371: + case 1: mgl@1371: + return "bfexts\t%0, %1, 0, 8"; mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + return "ld.sb\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "2,4,2,4") mgl@1371: + (set_attr "cc" "set_ncz,set_ncz,none,none") mgl@1371: + (set_attr "type" "alu,alu,load_rm,load_rm")]) mgl@1371: + mgl@1371: +(define_insn "extendqihi2" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") mgl@1371: + (sign_extend:HI (match_operand:QI 1 "extendqi_operand" "0,r,RKu00,m")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "casts.b\t%0"; mgl@1371: + case 1: mgl@1371: + return "bfexts\t%0, %1, 0, 8"; mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + return "ld.sb\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "2,4,2,4") mgl@1371: + (set_attr "cc" "set_ncz,set_ncz,none,none") mgl@1371: + (set_attr "type" "alu,alu,load_rm,load_rm")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Zero-extend mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "zero_extendhisi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") mgl@1371: + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "0,r,,m")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "castu.h\t%0"; mgl@1371: + case 1: mgl@1371: + return "bfextu\t%0, %1, 0, 16"; mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + return "ld.uh\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "length" "2,4,2,4") mgl@1371: + (set_attr "cc" "set_ncz,set_ncz,none,none") mgl@1371: + (set_attr "type" "alu,alu,load_rm,load_rm")]) mgl@1371: + mgl@1371: +(define_insn "zero_extendqisi2" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") mgl@1371: + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,r,,m")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "castu.b\t%0"; mgl@1371: + case 1: mgl@1371: + return "bfextu\t%0, %1, 0, 8"; mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + return "ld.ub\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "2,4,2,4") mgl@1371: + (set_attr "cc" "set_ncz, set_ncz, none, none") mgl@1371: + (set_attr "type" "alu, alu, load_rm, load_rm")]) mgl@1371: + mgl@1371: +(define_insn "zero_extendqihi2" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r,r,r,r") mgl@1371: + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,r,,m")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "castu.b\t%0"; mgl@1371: + case 1: mgl@1371: + return "bfextu\t%0, %1, 0, 8"; mgl@1371: + case 2: mgl@1371: + case 3: mgl@1371: + return "ld.ub\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "2,4,2,4") mgl@1371: + (set_attr "cc" "set_ncz, set_ncz, none, none") mgl@1371: + (set_attr "type" "alu, alu, load_rm, load_rm")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Conditional load and extend insns mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "ldsi_predicable_se" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (sign_extend:SI mgl@1371: + (match_operand:INTM 1 "memory_operand" "")))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "ld%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "load") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "ldsi_predicable_ze" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (zero_extend:SI mgl@1371: + (match_operand:INTM 1 "memory_operand" "")))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "ld%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "load") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "ldhi_predicable_ze" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (zero_extend:HI mgl@1371: + (match_operand:QI 1 "memory_operand" "RKs10")))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "ld.ub%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "load") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "ldhi_predicable_se" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (sign_extend:HI mgl@1371: + (match_operand:QI 1 "memory_operand" "RKs10")))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + "ld.sb%?\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "cmp_cond_insn") mgl@1371: + (set_attr "type" "load") mgl@1371: + (set_attr "predicable" "yes")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Conditional set register mgl@1371: +;; sr{cond4} rd mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: + mgl@1371: +;;Because of the same issue as with conditional moves and adds we must mgl@1371: +;;not separate the compare instrcution from the scc instruction as mgl@1371: +;;they might be sheduled "badly". mgl@1371: + mgl@1371: +(define_insn "s" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (any_cond:SI (cc0) mgl@1371: + (const_int 0)))] mgl@1371: + "" mgl@1371: + "sr\t%0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "smi" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec:SI [(cc0) mgl@1371: + (const_int 0)] UNSPEC_COND_MI))] mgl@1371: + "" mgl@1371: + "srmi\t%0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "spl" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec:SI [(cc0) mgl@1371: + (const_int 0)] UNSPEC_COND_PL))] mgl@1371: + "" mgl@1371: + "srpl\t%0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Conditional branch mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Branch to label if the specified condition codes are set. mgl@1371: +;;============================================================================= mgl@1371: +; branch if negative mgl@1371: +(define_insn "bmi" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_MI) mgl@1371: + (label_ref (match_operand 0 "" "")) mgl@1371: + (pc)))] mgl@1371: + "" mgl@1371: + "brmi %0" mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 256))) mgl@1371: + (const_int 2)] ; use compact branch mgl@1371: + (const_int 4))) ; use extended branch mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "*bmi-reverse" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_MI) mgl@1371: + (pc) mgl@1371: + (label_ref (match_operand 0 "" ""))))] mgl@1371: + "" mgl@1371: + "brpl %0" mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 256))) mgl@1371: + (const_int 2)] ; use compact branch mgl@1371: + (const_int 4))) ; use extended branch mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +; branch if positive mgl@1371: +(define_insn "bpl" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_PL) mgl@1371: + (label_ref (match_operand 0 "" "")) mgl@1371: + (pc)))] mgl@1371: + "" mgl@1371: + "brpl %0" mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 256))) mgl@1371: + (const_int 2)] ; use compact branch mgl@1371: + (const_int 4))) ; use extended branch mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_insn "*bpl-reverse" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (unspec:CC [(cc0) (const_int 0)] UNSPEC_COND_PL) mgl@1371: + (pc) mgl@1371: + (label_ref (match_operand 0 "" ""))))] mgl@1371: + "" mgl@1371: + "brmi %0" mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 256))) mgl@1371: + (const_int 2)] ; use compact branch mgl@1371: + (const_int 4))) ; use extended branch mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +; branch if equal mgl@1371: +(define_insn "b" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (any_cond:CC (cc0) mgl@1371: + (const_int 0)) mgl@1371: + (label_ref (match_operand 0 "" "")) mgl@1371: + (pc)))] mgl@1371: + "" mgl@1371: + "br %0 " mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 256))) mgl@1371: + (const_int 2)] ; use compact branch mgl@1371: + (const_int 4))) ; use extended branch mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "*b-reverse" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (any_cond:CC (cc0) mgl@1371: + (const_int 0)) mgl@1371: + (pc) mgl@1371: + (label_ref (match_operand 0 "" ""))))] mgl@1371: + "" mgl@1371: + "br %0 " mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 254)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 256))) mgl@1371: + (const_int 2)] ; use compact branch mgl@1371: + (const_int 4))) ; use extended branch mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;============================================================================= mgl@1371: +; Conditional Add/Subtract mgl@1371: +;----------------------------------------------------------------------------- mgl@1371: +; sub{cond4} Rd, imm mgl@1371: +;============================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "addcc" mgl@1371: + [(set (match_operand:ADDCC 0 "register_operand" "") mgl@1371: + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(match_dup 4) mgl@1371: + (match_dup 5)]) mgl@1371: + (match_operand:ADDCC 2 "register_operand" "") mgl@1371: + (plus:ADDCC mgl@1371: + (match_dup 2) mgl@1371: + (match_operand:ADDCC 3 "" ""))))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( !(GET_CODE (operands[3]) == CONST_INT mgl@1371: + || (TARGET_V2_INSNS && REG_P(operands[3]))) ){ mgl@1371: + FAIL; mgl@1371: + } mgl@1371: + mgl@1371: + /* Delete compare instruction as it is merged into this instruction */ mgl@1371: + remove_insn (get_last_insn_anywhere ()); mgl@1371: + mgl@1371: + operands[4] = avr32_compare_op0; mgl@1371: + operands[5] = avr32_compare_op1; mgl@1371: + mgl@1371: + if ( TARGET_V2_INSNS mgl@1371: + && REG_P(operands[3]) mgl@1371: + && REGNO(operands[0]) != REGNO(operands[2]) ){ mgl@1371: + emit_move_insn (operands[0], operands[2]); mgl@1371: + operands[2] = operands[0]; mgl@1371: + } mgl@1371: + } mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "addcc_cmp_reg" mgl@1371: + [(set (match_operand:ADDCC 0 "register_operand" "=r") mgl@1371: + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(match_operand:CMP 4 "register_operand" "r") mgl@1371: + (match_operand:CMP 5 "" "")]) mgl@1371: + (match_dup 0) mgl@1371: + (plus:ADDCC mgl@1371: + (match_operand:ADDCC 2 "register_operand" "r") mgl@1371: + (match_operand:ADDCC 3 "register_operand" "r"))))] mgl@1371: + "TARGET_V2_INSNS" mgl@1371: + { mgl@1371: + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]); mgl@1371: + return "add%i1\t%0, %2, %3"; mgl@1371: + } mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "cmp_cond_insn")]) mgl@1371: + mgl@1371: +(define_insn "addcc_cmp" mgl@1371: + [(set (match_operand:ADDCC 0 "register_operand" "=r") mgl@1371: + (if_then_else:ADDCC (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(match_operand:CMP 4 "register_operand" "r") mgl@1371: + (match_operand:CMP 5 "" "")]) mgl@1371: + (match_operand:ADDCC 2 "register_operand" "0") mgl@1371: + (plus:ADDCC mgl@1371: + (match_dup 2) mgl@1371: + (match_operand:ADDCC 3 "avr32_cond_immediate_operand" "Is08"))))] mgl@1371: + "" mgl@1371: + { mgl@1371: + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]); mgl@1371: + return "sub%i1\t%0, -%3"; mgl@1371: + } mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "cmp_cond_insn")]) mgl@1371: + mgl@1371: +;============================================================================= mgl@1371: +; Conditional Move mgl@1371: +;----------------------------------------------------------------------------- mgl@1371: +; mov{cond4} Rd, (Rs/imm) mgl@1371: +;============================================================================= mgl@1371: +(define_expand "movcc" mgl@1371: + [(set (match_operand:MOVCC 0 "register_operand" "") mgl@1371: + (if_then_else:MOVCC (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(match_dup 4) mgl@1371: + (match_dup 5)]) mgl@1371: + (match_operand:MOVCC 2 "avr32_cond_register_immediate_operand" "") mgl@1371: + (match_operand:MOVCC 3 "avr32_cond_register_immediate_operand" "")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + /* Delete compare instruction as it is merged into this instruction */ mgl@1371: + remove_insn (get_last_insn_anywhere ()); mgl@1371: + mgl@1371: + operands[4] = avr32_compare_op0; mgl@1371: + operands[5] = avr32_compare_op1; mgl@1371: + } mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "movcc_cmp" mgl@1371: + [(set (match_operand:MOVCC 0 "register_operand" "=r,r,r") mgl@1371: + (if_then_else:MOVCC (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(match_operand:CMP 4 "register_operand" "r,r,r") mgl@1371: + (match_operand:CMP 5 "" ",,")]) mgl@1371: + (match_operand:MOVCC 2 "avr32_cond_register_immediate_operand" "0, rKs08,rKs08") mgl@1371: + (match_operand:MOVCC 3 "avr32_cond_register_immediate_operand" "rKs08,0,rKs08")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]); mgl@1371: + mgl@1371: + switch( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "mov%i1 %0, %3"; mgl@1371: + case 1: mgl@1371: + return "mov%1 %0, %2"; mgl@1371: + case 2: mgl@1371: + return "mov%1 %0, %2\;mov%i1 %0, %3"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + [(set_attr "length" "8,8,12") mgl@1371: + (set_attr "cc" "cmp_cond_insn")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; jump mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Jump inside a function; an unconditional branch to a label. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "jump" mgl@1371: + [(set (pc) mgl@1371: + (label_ref (match_operand 0 "" "")))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if (get_attr_length(insn) > 4) mgl@1371: + return "Can't jump this far"; mgl@1371: + return (get_attr_length(insn) == 2 ? mgl@1371: + "rjmp %0" : "bral %0"); mgl@1371: + } mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set (attr "length") mgl@1371: + (cond [(and (le (minus (match_dup 0) (pc)) (const_int 1022)) mgl@1371: + (le (minus (pc) (match_dup 0)) (const_int 1024))) mgl@1371: + (const_int 2) ; use rjmp mgl@1371: + (le (match_dup 0) (const_int 1048575)) mgl@1371: + (const_int 4)] ; use bral mgl@1371: + (const_int 8))) ; do something else mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; call mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Subroutine call instruction returning no value. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "call_internal" mgl@1371: + [(parallel [(call (mem:SI (match_operand:SI 0 "avr32_call_operand" "r,U,T,W")) mgl@1371: + (match_operand 1 "" "")) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch (which_alternative){ mgl@1371: + case 0: mgl@1371: + return "icall\t%0"; mgl@1371: + case 1: mgl@1371: + return "rcall\t%0"; mgl@1371: + case 2: mgl@1371: + return "mcall\t%0"; mgl@1371: + case 3: mgl@1371: + if ( TARGET_HAS_ASM_ADDR_PSEUDOS ) mgl@1371: + return "call\t%0"; mgl@1371: + else mgl@1371: + return "mcall\tr6[%0@got]"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "length" "2,4,4,10") mgl@1371: + (set_attr "cc" "clobber")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "call" mgl@1371: + [(parallel [(call (match_operand:SI 0 "" "") mgl@1371: + (match_operand 1 "" "")) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "" mgl@1371: + { mgl@1371: + rtx call_address; mgl@1371: + if ( GET_CODE(operands[0]) != MEM ) mgl@1371: + FAIL; mgl@1371: + mgl@1371: + call_address = XEXP(operands[0], 0); mgl@1371: + mgl@1371: + /* If assembler supports call pseudo insn and the call mgl@1371: + address is a symbol then nothing special needs to be done. */ mgl@1371: + if ( TARGET_HAS_ASM_ADDR_PSEUDOS mgl@1371: + && (GET_CODE(call_address) == SYMBOL_REF) ){ mgl@1371: + /* We must however mark the function as using the GOT if mgl@1371: + flag_pic is set, since the call insn might turn into mgl@1371: + a mcall using the GOT ptr register. */ mgl@1371: + if ( flag_pic ){ mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + emit_call_insn(gen_call_internal(call_address, operands[1])); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + } else { mgl@1371: + if ( flag_pic && mgl@1371: + GET_CODE(call_address) == SYMBOL_REF ){ mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + emit_call_insn(gen_call_internal(call_address, operands[1])); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + mgl@1371: + if ( !SYMBOL_REF_RCALL_FUNCTION_P(operands[0]) ){ mgl@1371: + if ( optimize_size && mgl@1371: + GET_CODE(call_address) == SYMBOL_REF ){ mgl@1371: + call_address = force_const_mem(SImode, call_address); mgl@1371: + } else { mgl@1371: + call_address = force_reg(SImode, call_address); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + emit_call_insn(gen_call_internal(call_address, operands[1])); mgl@1371: + DONE; mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; call_value mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Subrutine call instruction returning a value. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "call_value" mgl@1371: + [(parallel [(set (match_operand:SI 0 "" "") mgl@1371: + (call (match_operand:SI 1 "" "") mgl@1371: + (match_operand 2 "" ""))) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "" mgl@1371: + { mgl@1371: + rtx call_address; mgl@1371: + if ( GET_CODE(operands[1]) != MEM ) mgl@1371: + FAIL; mgl@1371: + mgl@1371: + call_address = XEXP(operands[1], 0); mgl@1371: + mgl@1371: + /* If assembler supports call pseudo insn and the call mgl@1371: + address is a symbol then nothing special needs to be done. */ mgl@1371: + if ( TARGET_HAS_ASM_ADDR_PSEUDOS mgl@1371: + && (GET_CODE(call_address) == SYMBOL_REF) ){ mgl@1371: + /* We must however mark the function as using the GOT if mgl@1371: + flag_pic is set, since the call insn might turn into mgl@1371: + a mcall using the GOT ptr register. */ mgl@1371: + if ( flag_pic ) { mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + emit_call_insn(gen_call_value_internal(operands[0], call_address, operands[2])); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + } else { mgl@1371: + if ( flag_pic && mgl@1371: + GET_CODE(call_address) == SYMBOL_REF ){ mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + emit_call_insn(gen_call_value_internal(operands[0], call_address, operands[2])); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + mgl@1371: + if ( !SYMBOL_REF_RCALL_FUNCTION_P(operands[1]) ){ mgl@1371: + if ( optimize_size && mgl@1371: + GET_CODE(call_address) == SYMBOL_REF){ mgl@1371: + call_address = force_const_mem(SImode, call_address); mgl@1371: + } else { mgl@1371: + call_address = force_reg(SImode, call_address); mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + emit_call_insn(gen_call_value_internal(operands[0], call_address, mgl@1371: + operands[2])); mgl@1371: + DONE; mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: +(define_insn "call_value_internal" mgl@1371: + [(parallel [(set (match_operand 0 "register_operand" "=r,r,r,r") mgl@1371: + (call (mem:SI (match_operand:SI 1 "avr32_call_operand" "r,U,T,W")) mgl@1371: + (match_operand 2 "" ""))) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + ;; Operand 2 not used on the AVR32. mgl@1371: + "" mgl@1371: + { mgl@1371: + switch (which_alternative){ mgl@1371: + case 0: mgl@1371: + return "icall\t%1"; mgl@1371: + case 1: mgl@1371: + return "rcall\t%1"; mgl@1371: + case 2: mgl@1371: + return "mcall\t%1"; mgl@1371: + case 3: mgl@1371: + if ( TARGET_HAS_ASM_ADDR_PSEUDOS ) mgl@1371: + return "call\t%1"; mgl@1371: + else mgl@1371: + return "mcall\tr6[%1@got]"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "length" "2,4,4,10") mgl@1371: + (set_attr "cc" "call_set")]) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; untyped_call mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Subrutine call instruction returning a value of any type. mgl@1371: +;; The code is copied from m68k.md (except gen_blockage is removed) mgl@1371: +;; Fixme! mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "untyped_call" mgl@1371: + [(parallel [(call (match_operand 0 "avr32_call_operand" "") mgl@1371: + (const_int 0)) mgl@1371: + (match_operand 1 "" "") mgl@1371: + (match_operand 2 "" "")])] mgl@1371: + "" mgl@1371: + { mgl@1371: + int i; mgl@1371: + mgl@1371: + emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); mgl@1371: + mgl@1371: + for (i = 0; i < XVECLEN (operands[2], 0); i++) { mgl@1371: + rtx set = XVECEXP (operands[2], 0, i); mgl@1371: + emit_move_insn (SET_DEST (set), SET_SRC (set)); mgl@1371: + } mgl@1371: + mgl@1371: + /* The optimizer does not know that the call sets the function value mgl@1371: + registers we stored in the result block. We avoid problems by mgl@1371: + claiming that all hard registers are used and clobbered at this mgl@1371: + point. */ mgl@1371: + emit_insn (gen_blockage ()); mgl@1371: + mgl@1371: + DONE; mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; return mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: +(define_insn "return" mgl@1371: + [(return)] mgl@1371: + "USE_RETURN_INSN (FALSE)" mgl@1371: + { mgl@1371: + avr32_output_return_instruction(TRUE, FALSE, NULL, NULL); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "call")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "return_cond" mgl@1371: + [(set (pc) mgl@1371: + (if_then_else (match_operand 0 "avr32_comparison_operand" "") mgl@1371: + (return) mgl@1371: + (pc)))] mgl@1371: + "USE_RETURN_INSN (TRUE)" mgl@1371: + "ret%0\tr12"; mgl@1371: + [(set_attr "type" "call")]) mgl@1371: + mgl@1371: +(define_insn "return_cond_predicable" mgl@1371: + [(return)] mgl@1371: + "USE_RETURN_INSN (TRUE)" mgl@1371: + "ret%?\tr12"; mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "return_imm" mgl@1371: + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (return)])] mgl@1371: + "USE_RETURN_INSN (FALSE) && mgl@1371: + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))" mgl@1371: + { mgl@1371: + avr32_output_return_instruction(TRUE, FALSE, NULL, operands[0]); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "call")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "return_imm_cond" mgl@1371: + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (set (pc) mgl@1371: + (if_then_else (match_operand 1 "avr32_comparison_operand" "") mgl@1371: + (return) mgl@1371: + (pc)))])] mgl@1371: + "USE_RETURN_INSN (TRUE) && mgl@1371: + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))" mgl@1371: + "ret%1\t%0"; mgl@1371: + [(set_attr "type" "call")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "return_imm_predicable" mgl@1371: + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (return)])] mgl@1371: + "USE_RETURN_INSN (TRUE) && mgl@1371: + ((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))" mgl@1371: + "ret%?\t%0"; mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: +(define_insn "return_reg" mgl@1371: + [(set (reg RETVAL_REGNUM) (match_operand:MOVM 0 "register_operand" "r")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (return)] mgl@1371: + "USE_RETURN_INSN (TRUE)" mgl@1371: + "ret%?\t%0"; mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "predicable" "yes")]) mgl@1371: + mgl@1371: +(define_insn "return_reg_cond" mgl@1371: + [(set (reg RETVAL_REGNUM) (match_operand:MOVM 0 "register_operand" "r")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (set (pc) mgl@1371: + (if_then_else (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(cc0) (const_int 0)]) mgl@1371: + (return) mgl@1371: + (pc)))] mgl@1371: + "USE_RETURN_INSN (TRUE)" mgl@1371: + "ret%1\t%0"; mgl@1371: + [(set_attr "type" "call")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; nop mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; No-op instruction. mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "nop" mgl@1371: + [(const_int 0)] mgl@1371: + "" mgl@1371: + "nop" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "type" "alu") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; nonlocal_goto_receiver mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; For targets with a return stack we must make sure to flush the return stack mgl@1371: +;; since it will be corrupt after a nonlocal goto. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "nonlocal_goto_receiver" mgl@1371: + [(const_int 0)] mgl@1371: + "TARGET_RETURN_STACK" mgl@1371: + " mgl@1371: + { mgl@1371: + emit_insn ( gen_frs() ); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + " mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; builtin_setjmp_receiver mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; For pic code we need to reload the pic register. mgl@1371: +;; For targets with a return stack we must make sure to flush the return stack mgl@1371: +;; since it will probably be corrupted. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "builtin_setjmp_receiver" mgl@1371: + [(label_ref (match_operand 0 "" ""))] mgl@1371: + "flag_pic" mgl@1371: + " mgl@1371: + { mgl@1371: + if ( TARGET_RETURN_STACK ) mgl@1371: + emit_insn ( gen_frs() ); mgl@1371: + mgl@1371: + avr32_load_pic_register (); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + " mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; indirect_jump mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Jump to an address in reg or memory. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "indirect_jump" mgl@1371: + [(set (pc) mgl@1371: + (match_operand:SI 0 "general_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + /* One of the ops has to be in a register. */ mgl@1371: + if ( (flag_pic || TARGET_HAS_ASM_ADDR_PSEUDOS ) mgl@1371: + && !avr32_legitimate_pic_operand_p(operands[0]) ) mgl@1371: + operands[0] = legitimize_pic_address (operands[0], SImode, 0); mgl@1371: + else if ( flag_pic && avr32_address_operand(operands[0], GET_MODE(operands[0])) ) mgl@1371: + /* If we have an address operand then this function uses the pic register. */ mgl@1371: + current_function_uses_pic_offset_table = 1; mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "indirect_jump_internal" mgl@1371: + [(set (pc) mgl@1371: + (match_operand:SI 0 "avr32_non_rmw_general_operand" "r,m,W"))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch( which_alternative ){ mgl@1371: + case 0: mgl@1371: + return "mov\tpc, %0"; mgl@1371: + case 1: mgl@1371: + if ( avr32_const_pool_ref_operand(operands[0], GET_MODE(operands[0])) ) mgl@1371: + return "lddpc\tpc, %0"; mgl@1371: + else mgl@1371: + return "ld.w\tpc, %0"; mgl@1371: + case 2: mgl@1371: + if ( flag_pic ) mgl@1371: + return "ld.w\tpc, r6[%0@got]"; mgl@1371: + else mgl@1371: + return "lda.w\tpc, %0"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "2,4,8") mgl@1371: + (set_attr "type" "call,call,call") mgl@1371: + (set_attr "cc" "none,none,clobber")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; casesi and tablejump mgl@1371: +;;============================================================================= mgl@1371: +(define_insn "tablejump_add" mgl@1371: + [(set (pc) mgl@1371: + (plus:SI (match_operand:SI 0 "register_operand" "r") mgl@1371: + (mult:SI (match_operand:SI 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku04" )))) mgl@1371: + (use (label_ref (match_operand 3 "" "")))] mgl@1371: + "flag_pic && mgl@1371: + ((INTVAL(operands[2]) == 0) || (INTVAL(operands[2]) == 2) || mgl@1371: + (INTVAL(operands[2]) == 4) || (INTVAL(operands[2]) == 8))" mgl@1371: + "add\tpc, %0, %1 << %p2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")]) mgl@1371: + mgl@1371: +(define_insn "tablejump_insn" mgl@1371: + [(set (pc) (match_operand:SI 0 "memory_operand" "m")) mgl@1371: + (use (label_ref (match_operand 1 "" "")))] mgl@1371: + "!flag_pic" mgl@1371: + "ld.w\tpc, %0" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "call") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: +(define_expand "casesi" mgl@1371: + [(match_operand:SI 0 "register_operand" "") ; index to jump on mgl@1371: + (match_operand:SI 1 "const_int_operand" "") ; lower bound mgl@1371: + (match_operand:SI 2 "const_int_operand" "") ; total range mgl@1371: + (match_operand:SI 3 "" "") ; table label mgl@1371: + (match_operand:SI 4 "" "")] ; Out of range label mgl@1371: + "" mgl@1371: + " mgl@1371: + { mgl@1371: + rtx reg; mgl@1371: + rtx index = operands[0]; mgl@1371: + rtx low_bound = operands[1]; mgl@1371: + rtx range = operands[2]; mgl@1371: + rtx table_label = operands[3]; mgl@1371: + rtx oor_label = operands[4]; mgl@1371: + mgl@1371: + index = force_reg ( SImode, index ); mgl@1371: + if (low_bound != const0_rtx) mgl@1371: + { mgl@1371: + if (!avr32_const_ok_for_constraint_p(INTVAL (low_bound), 'I', \"Is21\")){ mgl@1371: + reg = force_reg(SImode, GEN_INT (INTVAL (low_bound))); mgl@1371: + emit_insn (gen_subsi3 (reg, index, mgl@1371: + reg)); mgl@1371: + } else { mgl@1371: + reg = gen_reg_rtx (SImode); mgl@1371: + emit_insn (gen_addsi3 (reg, index, mgl@1371: + GEN_INT (-INTVAL (low_bound)))); mgl@1371: + } mgl@1371: + index = reg; mgl@1371: + } mgl@1371: + mgl@1371: + if (!avr32_const_ok_for_constraint_p (INTVAL (range), 'K', \"Ks21\")) mgl@1371: + range = force_reg (SImode, range); mgl@1371: + mgl@1371: + emit_cmp_and_jump_insns ( index, range, GTU, NULL_RTX, SImode, 1, oor_label ); mgl@1371: + reg = gen_reg_rtx (SImode); mgl@1371: + emit_move_insn ( reg, gen_rtx_LABEL_REF (VOIDmode, table_label)); mgl@1371: + mgl@1371: + if ( flag_pic ) mgl@1371: + emit_jump_insn ( gen_tablejump_add ( reg, index, GEN_INT(4), table_label)); mgl@1371: + else mgl@1371: + emit_jump_insn ( mgl@1371: + gen_tablejump_insn ( gen_rtx_MEM ( SImode, mgl@1371: + gen_rtx_PLUS ( SImode, mgl@1371: + reg, mgl@1371: + gen_rtx_MULT ( SImode, mgl@1371: + index, mgl@1371: + GEN_INT(4)))), mgl@1371: + table_label)); mgl@1371: + DONE; mgl@1371: + }" mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "prefetch" mgl@1371: + [(prefetch (match_operand:SI 0 "avr32_ks16_address_operand" "p") mgl@1371: + (match_operand 1 "const_int_operand" "") mgl@1371: + (match_operand 2 "const_int_operand" ""))] mgl@1371: + "" mgl@1371: + { mgl@1371: + return "pref\t%0"; mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "load") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; prologue mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; This pattern, if defined, emits RTL for entry to a function. The function mgl@1371: +;; entry i responsible for setting up the stack frame, initializing the frame mgl@1371: +;; pointer register, saving callee saved registers, etc. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "prologue" mgl@1371: + [(clobber (const_int 0))] mgl@1371: + "" mgl@1371: + " mgl@1371: + avr32_expand_prologue(); mgl@1371: + DONE; mgl@1371: + " mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; eh_return mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; This pattern, if defined, affects the way __builtin_eh_return, and mgl@1371: +;; thence the call frame exception handling library routines, are mgl@1371: +;; built. It is intended to handle non-trivial actions needed along mgl@1371: +;; the abnormal return path. mgl@1371: +;; mgl@1371: +;; The address of the exception handler to which the function should mgl@1371: +;; return is passed as operand to this pattern. It will normally need mgl@1371: +;; to copied by the pattern to some special register or memory mgl@1371: +;; location. If the pattern needs to determine the location of the mgl@1371: +;; target call frame in order to do so, it may use mgl@1371: +;; EH_RETURN_STACKADJ_RTX, if defined; it will have already been mgl@1371: +;; assigned. mgl@1371: +;; mgl@1371: +;; If this pattern is not defined, the default action will be to mgl@1371: +;; simply copy the return address to EH_RETURN_HANDLER_RTX. Either mgl@1371: +;; that macro or this pattern needs to be defined if call frame mgl@1371: +;; exception handling is to be used. mgl@1371: + mgl@1371: +;; We can't expand this before we know where the link register is stored. mgl@1371: +(define_insn_and_split "eh_return" mgl@1371: + [(unspec_volatile [(match_operand:SI 0 "register_operand" "r")] mgl@1371: + VUNSPEC_EH_RETURN) mgl@1371: + (clobber (match_scratch:SI 1 "=&r"))] mgl@1371: + "" mgl@1371: + "#" mgl@1371: + "reload_completed" mgl@1371: + [(const_int 0)] mgl@1371: + " mgl@1371: + { mgl@1371: + avr32_set_return_address (operands[0], operands[1]); mgl@1371: + DONE; mgl@1371: + }" mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; ffssi2 mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "ffssi2" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ffs:SI (match_operand:SI 1 "register_operand" "r"))) ] mgl@1371: + "" mgl@1371: + "mov %0, %1 mgl@1371: + brev %0 mgl@1371: + clz %0, %0 mgl@1371: + sub %0, -1 mgl@1371: + cp %0, 33 mgl@1371: + moveq %0, 0" mgl@1371: + [(set_attr "length" "18") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; swap_h mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "*swap_h" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (ior:SI (ashift:SI (match_dup 0) (const_int 16)) mgl@1371: + (lshiftrt:SI (match_dup 0) (const_int 16))))] mgl@1371: + "" mgl@1371: + "swap.h %0" mgl@1371: + [(set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn_and_split "bswap_16" mgl@1371: + [ (set (match_operand:HI 0 "avr32_bswap_operand" "=r,RKs13,r") mgl@1371: + (ior:HI (and:HI (lshiftrt:HI (match_operand:HI 1 "avr32_bswap_operand" "r,r,RKs13") mgl@1371: + (const_int 8)) mgl@1371: + (const_int 255)) mgl@1371: + (ashift:HI (and:HI (match_dup 1) mgl@1371: + (const_int 255)) mgl@1371: + (const_int 8))))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + if ( REGNO(operands[0]) == REGNO(operands[1])) mgl@1371: + return "swap.bh\t%0"; mgl@1371: + else mgl@1371: + return "mov\t%0, %1\;swap.bh\t%0"; mgl@1371: + case 1: mgl@1371: + return "stswp.h\t%0, %1"; mgl@1371: + case 2: mgl@1371: + return "ldswp.sh\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + "(reload_completed && mgl@1371: + REG_P(operands[0]) && REG_P(operands[1]) mgl@1371: + && (REGNO(operands[0]) != REGNO(operands[1])))" mgl@1371: + [(set (match_dup 0) (match_dup 1)) mgl@1371: + (set (match_dup 0) mgl@1371: + (ior:HI (and:HI (lshiftrt:HI (match_dup 0) mgl@1371: + (const_int 8)) mgl@1371: + (const_int 255)) mgl@1371: + (ashift:HI (and:HI (match_dup 0) mgl@1371: + (const_int 255)) mgl@1371: + (const_int 8))))] mgl@1371: + "" mgl@1371: + mgl@1371: + [(set_attr "length" "4,4,4") mgl@1371: + (set_attr "type" "alu,store,load_rm")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn_and_split "bswap_32" mgl@1371: + [ (set (match_operand:SI 0 "avr32_bswap_operand" "=r,RKs14,r") mgl@1371: + (ior:SI (ior:SI (lshiftrt:SI (and:SI (match_operand:SI 1 "avr32_bswap_operand" "r,r,RKs14") mgl@1371: + (const_int -16777216)) mgl@1371: + (const_int 24)) mgl@1371: + (lshiftrt:SI (and:SI (match_dup 1) mgl@1371: + (const_int 16711680)) mgl@1371: + (const_int 8))) mgl@1371: + (ior:SI (ashift:SI (and:SI (match_dup 1) mgl@1371: + (const_int 65280)) mgl@1371: + (const_int 8)) mgl@1371: + (ashift:SI (and:SI (match_dup 1) mgl@1371: + (const_int 255)) mgl@1371: + (const_int 24)))))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( which_alternative ){ mgl@1371: + case 0: mgl@1371: + if ( REGNO(operands[0]) == REGNO(operands[1])) mgl@1371: + return "swap.b\t%0"; mgl@1371: + else mgl@1371: + return "#"; mgl@1371: + case 1: mgl@1371: + return "stswp.w\t%0, %1"; mgl@1371: + case 2: mgl@1371: + return "ldswp.w\t%0, %1"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + "(reload_completed && mgl@1371: + REG_P(operands[0]) && REG_P(operands[1]) mgl@1371: + && (REGNO(operands[0]) != REGNO(operands[1])))" mgl@1371: + [(set (match_dup 0) (match_dup 1)) mgl@1371: + (set (match_dup 0) mgl@1371: + (ior:SI (ior:SI (lshiftrt:SI (and:SI (match_dup 0) mgl@1371: + (const_int -16777216)) mgl@1371: + (const_int 24)) mgl@1371: + (lshiftrt:SI (and:SI (match_dup 0) mgl@1371: + (const_int 16711680)) mgl@1371: + (const_int 8))) mgl@1371: + (ior:SI (ashift:SI (and:SI (match_dup 0) mgl@1371: + (const_int 65280)) mgl@1371: + (const_int 8)) mgl@1371: + (ashift:SI (and:SI (match_dup 0) mgl@1371: + (const_int 255)) mgl@1371: + (const_int 24)))))] mgl@1371: + "" mgl@1371: + mgl@1371: + [(set_attr "length" "4,4,4") mgl@1371: + (set_attr "type" "alu,store,load_rm")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; blockage mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and mgl@1371: +;; all of memory. This blocks insns from being moved across this point. mgl@1371: + mgl@1371: +(define_insn "blockage" mgl@1371: + [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)] mgl@1371: + "" mgl@1371: + "" mgl@1371: + [(set_attr "length" "0")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; clzsi2 mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "clzsi2" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (clz:SI (match_operand:SI 1 "register_operand" "r"))) ] mgl@1371: + "" mgl@1371: + "clz %0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "set_z")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; ctzsi2 mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "ctzsi2" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r,r") mgl@1371: + (ctz:SI (match_operand:SI 1 "register_operand" "0,r"))) ] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + brev\t%0\;clz\t%0, %0 mgl@1371: + mov\t%0, %1\;brev\t%0\;clz\t%0, %0" mgl@1371: + [(set_attr "length" "8") mgl@1371: + (set_attr "cc" "set_z")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; cache instructions mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "cache" mgl@1371: + [ (unspec_volatile [(match_operand:SI 0 "avr32_ks11_address_operand" "p") mgl@1371: + (match_operand:SI 1 "immediate_operand" "Ku05")] VUNSPEC_CACHE)] mgl@1371: + "" mgl@1371: + "cache %0, %1" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "sync" mgl@1371: + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku08")] VUNSPEC_SYNC)] mgl@1371: + "" mgl@1371: + "sync %0" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; TLB instructions mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "tlbr" mgl@1371: + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBR)] mgl@1371: + "" mgl@1371: + "tlbr" mgl@1371: + [(set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "tlbw" mgl@1371: + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBW)] mgl@1371: + "" mgl@1371: + "tlbw" mgl@1371: + [(set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "tlbs" mgl@1371: + [ (unspec_volatile [(const_int 0)] VUNSPEC_TLBS)] mgl@1371: + "" mgl@1371: + "tlbs" mgl@1371: + [(set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Breakpoint instruction mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "breakpoint" mgl@1371: + [ (unspec_volatile [(const_int 0)] VUNSPEC_BREAKPOINT)] mgl@1371: + "" mgl@1371: + "breakpoint" mgl@1371: + [(set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; mtsr/mfsr instruction mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "mtsr" mgl@1371: + [ (unspec_volatile [(match_operand 0 "immediate_operand" "i") mgl@1371: + (match_operand:SI 1 "register_operand" "r")] VUNSPEC_MTSR)] mgl@1371: + "" mgl@1371: + "mtsr\t%0, %1" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mfsr" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "i")] VUNSPEC_MFSR)) ] mgl@1371: + "" mgl@1371: + "mfsr\t%0, %1" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; mtdr/mfdr instruction mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "mtdr" mgl@1371: + [ (unspec_volatile [(match_operand 0 "immediate_operand" "i") mgl@1371: + (match_operand:SI 1 "register_operand" "r")] VUNSPEC_MTDR)] mgl@1371: + "" mgl@1371: + "mtdr\t%0, %1" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mfdr" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "i")] VUNSPEC_MFDR)) ] mgl@1371: + "" mgl@1371: + "mfdr\t%0, %1" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; musfr mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "musfr" mgl@1371: + [ (unspec_volatile [(match_operand:SI 0 "register_operand" "r")] VUNSPEC_MUSFR)] mgl@1371: + "" mgl@1371: + "musfr\t%0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mustr" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec_volatile:SI [(const_int 0)] VUNSPEC_MUSTR)) ] mgl@1371: + "" mgl@1371: + "mustr\t%0" mgl@1371: + [(set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "ssrf" mgl@1371: + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku05")] VUNSPEC_SSRF)] mgl@1371: + "" mgl@1371: + "ssrf %0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "csrf" mgl@1371: + [ (unspec_volatile [(match_operand:SI 0 "immediate_operand" "Ku05")] VUNSPEC_CSRF)] mgl@1371: + "" mgl@1371: + "csrf %0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Flush Return Stack instruction mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "frs" mgl@1371: + [ (unspec_volatile [(const_int 0)] VUNSPEC_FRS)] mgl@1371: + "" mgl@1371: + "frs" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "cc" "none")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Saturation Round Scale instruction mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "sats" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (unspec:SI [(match_dup 0) mgl@1371: + (match_operand 1 "immediate_operand" "Ku05") mgl@1371: + (match_operand 2 "immediate_operand" "Ku05")] mgl@1371: + UNSPEC_SATS)) ] mgl@1371: + "TARGET_DSP" mgl@1371: + "sats\t%0 >> %1, %2" mgl@1371: + [(set_attr "type" "alu_sat") mgl@1371: + (set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "satu" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (unspec:SI [(match_dup 0) mgl@1371: + (match_operand 1 "immediate_operand" "Ku05") mgl@1371: + (match_operand 2 "immediate_operand" "Ku05")] mgl@1371: + UNSPEC_SATU)) ] mgl@1371: + "TARGET_DSP" mgl@1371: + "satu\t%0 >> %1, %2" mgl@1371: + [(set_attr "type" "alu_sat") mgl@1371: + (set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "satrnds" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (unspec:SI [(match_dup 0) mgl@1371: + (match_operand 1 "immediate_operand" "Ku05") mgl@1371: + (match_operand 2 "immediate_operand" "Ku05")] mgl@1371: + UNSPEC_SATRNDS)) ] mgl@1371: + "TARGET_DSP" mgl@1371: + "satrnds\t%0 >> %1, %2" mgl@1371: + [(set_attr "type" "alu_sat") mgl@1371: + (set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "satrndu" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (unspec:SI [(match_dup 0) mgl@1371: + (match_operand 1 "immediate_operand" "Ku05") mgl@1371: + (match_operand 2 "immediate_operand" "Ku05")] mgl@1371: + UNSPEC_SATRNDU)) ] mgl@1371: + "TARGET_DSP" mgl@1371: + "sats\t%0 >> %1, %2" mgl@1371: + [(set_attr "type" "alu_sat") mgl@1371: + (set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +;; Special patterns for dealing with the constant pool mgl@1371: + mgl@1371: +(define_insn "align_4" mgl@1371: + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN)] mgl@1371: + "" mgl@1371: + { mgl@1371: + assemble_align (32); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "2")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "consttable_start" mgl@1371: + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_START)] mgl@1371: + "" mgl@1371: + { mgl@1371: + return ".cpool"; mgl@1371: + } mgl@1371: + [(set_attr "length" "0")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "consttable_end" mgl@1371: + [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)] mgl@1371: + "" mgl@1371: + { mgl@1371: + making_const_table = FALSE; mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "0")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "consttable_4" mgl@1371: + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_4)] mgl@1371: + "" mgl@1371: + { mgl@1371: + making_const_table = TRUE; mgl@1371: + switch (GET_MODE_CLASS (GET_MODE (operands[0]))) mgl@1371: + { mgl@1371: + case MODE_FLOAT: mgl@1371: + { mgl@1371: + REAL_VALUE_TYPE r; mgl@1371: + char real_string[1024]; mgl@1371: + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); mgl@1371: + real_to_decimal(real_string, &r, 1024, 0, 1); mgl@1371: + asm_fprintf (asm_out_file, "\t.float\t%s\n", real_string); mgl@1371: + break; mgl@1371: + } mgl@1371: + default: mgl@1371: + assemble_integer (operands[0], 4, 0, 1); mgl@1371: + break; mgl@1371: + } mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "consttable_8" mgl@1371: + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_8)] mgl@1371: + "" mgl@1371: + { mgl@1371: + making_const_table = TRUE; mgl@1371: + switch (GET_MODE_CLASS (GET_MODE (operands[0]))) mgl@1371: + { mgl@1371: + case MODE_FLOAT: mgl@1371: + { mgl@1371: + REAL_VALUE_TYPE r; mgl@1371: + char real_string[1024]; mgl@1371: + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[0]); mgl@1371: + real_to_decimal(real_string, &r, 1024, 0, 1); mgl@1371: + asm_fprintf (asm_out_file, "\t.double\t%s\n", real_string); mgl@1371: + break; mgl@1371: + } mgl@1371: + default: mgl@1371: + assemble_integer(operands[0], 8, 0, 1); mgl@1371: + break; mgl@1371: + } mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "8")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "consttable_16" mgl@1371: + [(unspec_volatile [(match_operand 0 "" "")] VUNSPEC_POOL_16)] mgl@1371: + "" mgl@1371: + { mgl@1371: + making_const_table = TRUE; mgl@1371: + assemble_integer(operands[0], 16, 0, 1); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "16")] mgl@1371: +) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; coprocessor instructions mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +(define_insn "cop" mgl@1371: + [ (unspec_volatile [(match_operand 0 "immediate_operand" "Ku03") mgl@1371: + (match_operand 1 "immediate_operand" "Ku04") mgl@1371: + (match_operand 2 "immediate_operand" "Ku04") mgl@1371: + (match_operand 3 "immediate_operand" "Ku04") mgl@1371: + (match_operand 4 "immediate_operand" "Ku07")] VUNSPEC_COP)] mgl@1371: + "" mgl@1371: + "cop\tcp%0, cr%1, cr%2, cr%3, %4" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mvcrsi" mgl@1371: + [ (set (match_operand:SI 0 "avr32_cop_move_operand" "=r,<,Z") mgl@1371: + (unspec_volatile:SI [(match_operand 1 "immediate_operand" "Ku03,Ku03,Ku03") mgl@1371: + (match_operand 2 "immediate_operand" "Ku04,Ku04,Ku04")] mgl@1371: + VUNSPEC_MVCR)) ] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + mvcr.w\tcp%1, %0, cr%2 mgl@1371: + stcm.w\tcp%1, %0, cr%2 mgl@1371: + stc.w\tcp%1, %0, cr%2" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mvcrdi" mgl@1371: + [ (set (match_operand:DI 0 "avr32_cop_move_operand" "=r,<,Z") mgl@1371: + (unspec_volatile:DI [(match_operand 1 "immediate_operand" "Ku03,Ku03,Ku03") mgl@1371: + (match_operand 2 "immediate_operand" "Ku04,Ku04,Ku04")] mgl@1371: + VUNSPEC_MVCR)) ] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + mvcr.d\tcp%1, %0, cr%2 mgl@1371: + stcm.d\tcp%1, %0, cr%2-cr%i2 mgl@1371: + stc.d\tcp%1, %0, cr%2" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mvrcsi" mgl@1371: + [ (unspec_volatile:SI [(match_operand 0 "immediate_operand" "Ku03,Ku03,Ku03") mgl@1371: + (match_operand 1 "immediate_operand" "Ku04,Ku04,Ku04") mgl@1371: + (match_operand:SI 2 "avr32_cop_move_operand" "r,>,Z")] mgl@1371: + VUNSPEC_MVRC)] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch (which_alternative){ mgl@1371: + case 0: mgl@1371: + return "mvrc.w\tcp%0, cr%1, %2"; mgl@1371: + case 1: mgl@1371: + return "ldcm.w\tcp%0, %2, cr%1"; mgl@1371: + case 2: mgl@1371: + return "ldc.w\tcp%0, cr%1, %2"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "mvrcdi" mgl@1371: + [ (unspec_volatile:DI [(match_operand 0 "immediate_operand" "Ku03,Ku03,Ku03") mgl@1371: + (match_operand 1 "immediate_operand" "Ku04,Ku04,Ku04") mgl@1371: + (match_operand:DI 2 "avr32_cop_move_operand" "r,>,Z")] mgl@1371: + VUNSPEC_MVRC)] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch (which_alternative){ mgl@1371: + case 0: mgl@1371: + return "mvrc.d\tcp%0, cr%1, %2"; mgl@1371: + case 1: mgl@1371: + return "ldcm.d\tcp%0, %2, cr%1-cr%i1"; mgl@1371: + case 2: mgl@1371: + return "ldc.d\tcp%0, cr%1, %2"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; epilogue mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; This pattern emits RTL for exit from a function. The function exit is mgl@1371: +;; responsible for deallocating the stack frame, restoring callee saved mgl@1371: +;; registers and emitting the return instruction. mgl@1371: +;; ToDo: using TARGET_ASM_FUNCTION_PROLOGUE instead. mgl@1371: +;;============================================================================= mgl@1371: +(define_expand "epilogue" mgl@1371: + [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)] mgl@1371: + "" mgl@1371: + " mgl@1371: + if (USE_RETURN_INSN (FALSE)){ mgl@1371: + emit_jump_insn (gen_return ()); mgl@1371: + DONE; mgl@1371: + } mgl@1371: + emit_jump_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, mgl@1371: + gen_rtvec (1, mgl@1371: + gen_rtx_RETURN (VOIDmode)), mgl@1371: + VUNSPEC_EPILOGUE)); mgl@1371: + DONE; mgl@1371: + " mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "*epilogue_insns" mgl@1371: + [(unspec_volatile [(return)] VUNSPEC_EPILOGUE)] mgl@1371: + "" mgl@1371: + { mgl@1371: + avr32_output_return_instruction (FALSE, FALSE, NULL, NULL); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + ; Length is absolute worst case mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set_attr "length" "12")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "*epilogue_insns_ret_imm" mgl@1371: + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])] mgl@1371: + "((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))" mgl@1371: + { mgl@1371: + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[0]); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + ; Length is absolute worst case mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set_attr "length" "12")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "sibcall_epilogue" mgl@1371: + [(unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)] mgl@1371: + "" mgl@1371: + { mgl@1371: + avr32_output_return_instruction (FALSE, FALSE, NULL, NULL); mgl@1371: + return ""; mgl@1371: + } mgl@1371: +;; Length is absolute worst case mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set_attr "length" "12")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "*sibcall_epilogue_insns_ret_imm" mgl@1371: + [(parallel [(set (reg RETVAL_REGNUM) (match_operand 0 "immediate_operand" "i")) mgl@1371: + (use (reg RETVAL_REGNUM)) mgl@1371: + (unspec_volatile [(const_int 0)] VUNSPEC_EPILOGUE)])] mgl@1371: + "((INTVAL(operands[0]) == -1) || (INTVAL(operands[0]) == 0) || (INTVAL(operands[0]) == 1))" mgl@1371: + { mgl@1371: + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[0]); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + ; Length is absolute worst case mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set_attr "length" "12")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "ldxi" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (mem:SI (plus:SI mgl@1371: + (match_operand:SI 1 "register_operand" "r") mgl@1371: + (mult:SI (zero_extract:SI (match_operand:SI 2 "register_operand" "r") mgl@1371: + (const_int 8) mgl@1371: + (match_operand:SI 3 "immediate_operand" "Ku05")) mgl@1371: + (const_int 4)))))] mgl@1371: + "(INTVAL(operands[3]) == 24 || INTVAL(operands[3]) == 16 || INTVAL(operands[3]) == 8 mgl@1371: + || INTVAL(operands[3]) == 0)" mgl@1371: + { mgl@1371: + switch ( INTVAL(operands[3]) ){ mgl@1371: + case 0: mgl@1371: + return "ld.w %0, %1[%2:b << 2]"; mgl@1371: + case 8: mgl@1371: + return "ld.w %0, %1[%2:l << 2]"; mgl@1371: + case 16: mgl@1371: + return "ld.w %0, %1[%2:u << 2]"; mgl@1371: + case 24: mgl@1371: + return "ld.w %0, %1[%2:t << 2]"; mgl@1371: + default: mgl@1371: + internal_error("illegal operand for ldxi"); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "load") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; sub r8, r7, 8 mgl@1371: +;; st.w r8[0x0], r12 mgl@1371: +;; to mgl@1371: +;; sub r8, r7, 8 mgl@1371: +;; st.w r7[-0x8], r12 mgl@1371: +;;============================================================================= mgl@1371: +; (set (reg:SI 9 r8) mgl@1371: +; (plus:SI (reg/f:SI 6 r7) mgl@1371: +; (const_int ...))) mgl@1371: +; (set (mem:SI (reg:SI 9 r8)) mgl@1371: +; (reg:SI 12 r12)) mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (plus:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" ""))) mgl@1371: + (set (mem:SI (match_dup 0)) mgl@1371: + (match_operand:SI 3 "register_operand" ""))] mgl@1371: + "REGNO(operands[0]) != REGNO(operands[1]) && avr32_const_ok_for_constraint_p(INTVAL(operands[2]), 'K', \"Ks16\")" mgl@1371: + [(set (match_dup 0) mgl@1371: + (plus:SI (match_dup 1) mgl@1371: + (match_dup 2))) mgl@1371: + (set (mem:SI (plus:SI (match_dup 1) mgl@1371: + (match_dup 2))) mgl@1371: + (match_dup 3))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; sub r6, r7, 4 mgl@1371: +;; ld.w r6, r6[0x0] mgl@1371: +;; to mgl@1371: +;; sub r6, r7, 4 mgl@1371: +;; ld.w r6, r7[-0x4] mgl@1371: +;;============================================================================= mgl@1371: +; (set (reg:SI 7 r6) mgl@1371: +; (plus:SI (reg/f:SI 6 r7) mgl@1371: +; (const_int -4 [0xfffffffc]))) mgl@1371: +; (set (reg:SI 7 r6) mgl@1371: +; (mem:SI (reg:SI 7 r6))) mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (plus:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "immediate_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (mem:SI (match_dup 0)))] mgl@1371: + "REGNO(operands[0]) != REGNO(operands[1]) && avr32_const_ok_for_constraint_p(INTVAL(operands[2]), 'K', \"Ks16\")" mgl@1371: + [(set (match_dup 0) mgl@1371: + (plus:SI (match_dup 1) mgl@1371: + (match_dup 2))) mgl@1371: + (set (match_dup 3) mgl@1371: + (mem:SI (plus:SI (match_dup 1) mgl@1371: + (match_dup 2))))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; ld.sb r0, r7[-0x6] mgl@1371: +;; cashs.b r0 mgl@1371: +;; to mgl@1371: +;; ld.sb r0, r7[-0x6] mgl@1371: +;;============================================================================= mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:QI 0 "register_operand" "") mgl@1371: + (match_operand:QI 1 "load_sb_memory_operand" "")) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (sign_extend:SI (match_dup 0)))] mgl@1371: + "(REGNO(operands[0]) == REGNO(operands[2]) || peep2_reg_dead_p(2, operands[0]))" mgl@1371: + [(set (match_dup 2) mgl@1371: + (sign_extend:SI (match_dup 1)))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; ld.ub r0, r7[-0x6] mgl@1371: +;; cashu.b r0 mgl@1371: +;; to mgl@1371: +;; ld.ub r0, r7[-0x6] mgl@1371: +;;============================================================================= mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:QI 0 "register_operand" "") mgl@1371: + (match_operand:QI 1 "memory_operand" "")) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (zero_extend:SI (match_dup 0)))] mgl@1371: + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 2) mgl@1371: + (zero_extend:SI (match_dup 1)))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; ld.sh r0, r7[-0x6] mgl@1371: +;; casts.h r0 mgl@1371: +;; to mgl@1371: +;; ld.sh r0, r7[-0x6] mgl@1371: +;;============================================================================= mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:HI 0 "register_operand" "") mgl@1371: + (match_operand:HI 1 "memory_operand" "")) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (sign_extend:SI (match_dup 0)))] mgl@1371: + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 2) mgl@1371: + (sign_extend:SI (match_dup 1)))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; ld.uh r0, r7[-0x6] mgl@1371: +;; castu.h r0 mgl@1371: +;; to mgl@1371: +;; ld.uh r0, r7[-0x6] mgl@1371: +;;============================================================================= mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:HI 0 "register_operand" "") mgl@1371: + (match_operand:HI 1 "memory_operand" "")) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (zero_extend:SI (match_dup 0)))] mgl@1371: + "(REGNO(operands[0]) == REGNO(operands[2])) || peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 2) mgl@1371: + (zero_extend:SI (match_dup 1)))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; mul rd, rx, ry mgl@1371: +;; add rd2, rd mgl@1371: +;; or mgl@1371: +;; add rd2, rd, rd2 mgl@1371: +;; to mgl@1371: +;; mac rd2, rx, ry mgl@1371: +;;============================================================================= mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (mult:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (plus:SI (match_dup 3) mgl@1371: + (match_dup 0)))] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 3) mgl@1371: + (plus:SI (mult:SI (match_dup 1) mgl@1371: + (match_dup 2)) mgl@1371: + (match_dup 3)))] mgl@1371: + "") mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (mult:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (plus:SI (match_dup 0) mgl@1371: + (match_dup 3)))] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 3) mgl@1371: + (plus:SI (mult:SI (match_dup 1) mgl@1371: + (match_dup 2)) mgl@1371: + (match_dup 3)))] mgl@1371: + "") mgl@1371: + mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Changing mgl@1371: +;; bfextu rd, rs, k5, 1 or and(h/l) rd, one_bit_set_mask mgl@1371: +;; to mgl@1371: +;; bld rs, k5 mgl@1371: +;; mgl@1371: +;; If rd is dead after the operation. mgl@1371: +;;============================================================================= mgl@1371: +(define_peephole2 mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extract:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (const_int 1) mgl@1371: + (match_operand:SI 2 "immediate_operand" ""))) mgl@1371: + (set (cc0) mgl@1371: + (match_dup 0))] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (cc0) mgl@1371: + (and:SI (match_dup 1) mgl@1371: + (match_dup 2)))] mgl@1371: + "operands[2] = GEN_INT(1 << INTVAL(operands[2]));") mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "") mgl@1371: + (and:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (match_operand:SI 2 "one_bit_set_operand" ""))) mgl@1371: + (set (cc0) mgl@1371: + (match_dup 0))] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (cc0) mgl@1371: + (and:SI (match_dup 1) mgl@1371: + (match_dup 2)))] mgl@1371: + "") mgl@1371: + mgl@1371: +;;============================================================================= mgl@1371: +;; Peephole optimizing mgl@1371: +;;----------------------------------------------------------------------------- mgl@1371: +;; Load with extracted index: ld.w Rd, Rb[Ri:{t/u/b/l} << 2] mgl@1371: +;; mgl@1371: +;;============================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extract:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (const_int 8) mgl@1371: + (match_operand:SI 2 "avr32_extract_shift_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) mgl@1371: + (match_operand:SI 4 "register_operand" ""))))] mgl@1371: + mgl@1371: + "(dead_or_set_p(insn, operands[0]))" mgl@1371: + { mgl@1371: + switch ( INTVAL(operands[2]) ){ mgl@1371: + case 0: mgl@1371: + return "ld.w %3, %4[%1:b << 2]"; mgl@1371: + case 8: mgl@1371: + return "ld.w %3, %4[%1:l << 2]"; mgl@1371: + case 16: mgl@1371: + return "ld.w %3, %4[%1:u << 2]"; mgl@1371: + case 24: mgl@1371: + return "ld.w %3, %4[%1:t << 2]"; mgl@1371: + default: mgl@1371: + internal_error("illegal operand for ldxi"); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "load") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (and:SI (match_operand:SI 1 "register_operand" "") (const_int 255))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) mgl@1371: + (match_operand:SI 3 "register_operand" ""))))] mgl@1371: + mgl@1371: + "(dead_or_set_p(insn, operands[0]))" mgl@1371: + mgl@1371: + "ld.w %2, %3[%1:b << 2]" mgl@1371: + [(set_attr "type" "load") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extract:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (const_int 8) mgl@1371: + (match_operand:SI 2 "avr32_extract_shift_operand" ""))) mgl@1371: + (set (match_operand:SI 3 "register_operand" "") mgl@1371: + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) mgl@1371: + (match_operand:SI 4 "register_operand" ""))))] mgl@1371: + mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) mgl@1371: + || (REGNO(operands[0]) == REGNO(operands[3]))" mgl@1371: + [(set (match_dup 3) mgl@1371: + (mem:SI (plus:SI mgl@1371: + (match_dup 4) mgl@1371: + (mult:SI (zero_extract:SI (match_dup 1) mgl@1371: + (const_int 8) mgl@1371: + (match_dup 2)) mgl@1371: + (const_int 4)))))] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (zero_extend:SI (match_operand:QI 1 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) mgl@1371: + (match_operand:SI 3 "register_operand" ""))))] mgl@1371: + mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) mgl@1371: + || (REGNO(operands[0]) == REGNO(operands[2]))" mgl@1371: + [(set (match_dup 2) mgl@1371: + (mem:SI (plus:SI mgl@1371: + (match_dup 3) mgl@1371: + (mult:SI (zero_extract:SI (match_dup 1) mgl@1371: + (const_int 8) mgl@1371: + (const_int 0)) mgl@1371: + (const_int 4)))))] mgl@1371: + "operands[1] = gen_rtx_REG(SImode, REGNO(operands[1]));" mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (and:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (const_int 255))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) mgl@1371: + (match_operand:SI 3 "register_operand" ""))))] mgl@1371: + mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) mgl@1371: + || (REGNO(operands[0]) == REGNO(operands[2]))" mgl@1371: + [(set (match_dup 2) mgl@1371: + (mem:SI (plus:SI mgl@1371: + (match_dup 3) mgl@1371: + (mult:SI (zero_extract:SI (match_dup 1) mgl@1371: + (const_int 8) mgl@1371: + (const_int 0)) mgl@1371: + (const_int 4)))))] mgl@1371: + "" mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (lshiftrt:SI (match_operand:SI 1 "register_operand" "") mgl@1371: + (const_int 24))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) mgl@1371: + (match_operand:SI 3 "register_operand" ""))))] mgl@1371: + mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) mgl@1371: + || (REGNO(operands[0]) == REGNO(operands[2]))" mgl@1371: + [(set (match_dup 2) mgl@1371: + (mem:SI (plus:SI mgl@1371: + (match_dup 3) mgl@1371: + (mult:SI (zero_extract:SI (match_dup 1) mgl@1371: + (const_int 8) mgl@1371: + (const_int 24)) mgl@1371: + (const_int 4)))))] mgl@1371: + "" mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;************************************************ mgl@1371: +;; ANDN mgl@1371: +;; mgl@1371: +;;************************************************ mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (not:SI (match_operand:SI 1 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (and:SI (match_dup 2) mgl@1371: + (match_dup 0)))] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + mgl@1371: + [(set (match_dup 2) mgl@1371: + (and:SI (match_dup 2) mgl@1371: + (not:SI (match_dup 1)) mgl@1371: + ))] mgl@1371: + "" mgl@1371: +) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (not:SI (match_operand:SI 1 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (and:SI (match_dup 0) mgl@1371: + (match_dup 2) mgl@1371: + ))] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + mgl@1371: + [(set (match_dup 2) mgl@1371: + (and:SI (match_dup 2) mgl@1371: + (not:SI (match_dup 1)) mgl@1371: + ))] mgl@1371: + mgl@1371: + "" mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;;================================================================= mgl@1371: +;; Addabs peephole mgl@1371: +;;================================================================= mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 2 "register_operand" "=r") mgl@1371: + (abs:SI (match_operand:SI 1 "register_operand" "r"))) mgl@1371: + (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (plus:SI (match_operand:SI 3 "register_operand" "r") mgl@1371: + (match_dup 2)))] mgl@1371: + "dead_or_set_p(insn, operands[2])" mgl@1371: + "addabs %0, %3, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "set_z")]) mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 2 "register_operand" "=r") mgl@1371: + (abs:SI (match_operand:SI 1 "register_operand" "r"))) mgl@1371: + (set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (plus:SI (match_dup 2) mgl@1371: + (match_operand:SI 3 "register_operand" "r")))] mgl@1371: + "dead_or_set_p(insn, operands[2])" mgl@1371: + "addabs %0, %3, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "cc" "set_z")]) mgl@1371: + mgl@1371: + mgl@1371: +;;================================================================= mgl@1371: +;; Detect roundings mgl@1371: +;;================================================================= mgl@1371: + mgl@1371: +(define_insn "*round" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "+r") mgl@1371: + (ashiftrt:SI (plus:SI (match_dup 0) mgl@1371: + (match_operand:SI 1 "immediate_operand" "i")) mgl@1371: + (match_operand:SI 2 "immediate_operand" "i")))] mgl@1371: + "avr32_rnd_operands(operands[1], operands[2])" mgl@1371: + mgl@1371: + "satrnds %0 >> %2, 31" mgl@1371: + mgl@1371: + [(set_attr "type" "alu_sat") mgl@1371: + (set_attr "length" "4")] mgl@1371: + mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (plus:SI (match_dup 0) mgl@1371: + (match_operand:SI 1 "immediate_operand" ""))) mgl@1371: + (set (match_dup 0) mgl@1371: + (ashiftrt:SI (match_dup 0) mgl@1371: + (match_operand:SI 2 "immediate_operand" "")))] mgl@1371: + "avr32_rnd_operands(operands[1], operands[2])" mgl@1371: + mgl@1371: + [(set (match_dup 0) mgl@1371: + (ashiftrt:SI (plus:SI (match_dup 0) mgl@1371: + (match_dup 1)) mgl@1371: + (match_dup 2)))] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 0 "register_operand" "r") mgl@1371: + (plus:SI (match_dup 0) mgl@1371: + (match_operand:SI 1 "immediate_operand" "i"))) mgl@1371: + (set (match_dup 0) mgl@1371: + (ashiftrt:SI (match_dup 0) mgl@1371: + (match_operand:SI 2 "immediate_operand" "i")))] mgl@1371: + "avr32_rnd_operands(operands[1], operands[2])" mgl@1371: + mgl@1371: + "satrnds %0 >> %2, 31" mgl@1371: + mgl@1371: + [(set_attr "type" "alu_sat") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;;================================================================= mgl@1371: +;; mcall mgl@1371: +;;================================================================= mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (match_operand 1 "avr32_const_pool_ref_operand" "")) mgl@1371: + (parallel [(call (mem:SI (match_dup 0)) mgl@1371: + (match_operand 2 "" "")) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "dead_or_set_p(insn, operands[0])" mgl@1371: + "mcall %1" mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: +) mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand:SI 2 "register_operand" "") mgl@1371: + (match_operand 1 "avr32_const_pool_ref_operand" "")) mgl@1371: + (parallel [(set (match_operand 0 "register_operand" "") mgl@1371: + (call (mem:SI (match_dup 2)) mgl@1371: + (match_operand 3 "" ""))) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "dead_or_set_p(insn, operands[2])" mgl@1371: + "mcall %1" mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "call_set")] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (match_operand 1 "avr32_const_pool_ref_operand" "")) mgl@1371: + (parallel [(call (mem:SI (match_dup 0)) mgl@1371: + (match_operand 2 "" "")) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(parallel [(call (mem:SI (match_dup 1)) mgl@1371: + (match_dup 2)) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "" mgl@1371: +) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (match_operand 1 "avr32_const_pool_ref_operand" "")) mgl@1371: + (parallel [(set (match_operand 2 "register_operand" "") mgl@1371: + (call (mem:SI (match_dup 0)) mgl@1371: + (match_operand 3 "" ""))) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "(peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[2]) == REGNO(operands[0])))" mgl@1371: + [(parallel [(set (match_dup 2) mgl@1371: + (call (mem:SI (match_dup 1)) mgl@1371: + (match_dup 3))) mgl@1371: + (clobber (reg:SI LR_REGNUM))])] mgl@1371: + "" mgl@1371: +) mgl@1371: + mgl@1371: +;;================================================================= mgl@1371: +;; Returning a value mgl@1371: +;;================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand 0 "register_operand" "") mgl@1371: + (match_operand 1 "register_operand" "")) mgl@1371: + (return)] mgl@1371: + "USE_RETURN_INSN (TRUE) && (REGNO(operands[0]) == RETVAL_REGNUM) mgl@1371: + && (REGNO(operands[1]) != LR_REGNUM) mgl@1371: + && (REGNO_REG_CLASS(REGNO(operands[1])) == GENERAL_REGS)" mgl@1371: + "retal %1" mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "length" "2")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand 0 "register_operand" "r") mgl@1371: + (match_operand 1 "immediate_operand" "i")) mgl@1371: + (return)] mgl@1371: + "(USE_RETURN_INSN (FALSE) && (REGNO(operands[0]) == RETVAL_REGNUM) && mgl@1371: + ((INTVAL(operands[1]) == -1) || (INTVAL(operands[1]) == 0) || (INTVAL(operands[1]) == 1)))" mgl@1371: + { mgl@1371: + avr32_output_return_instruction (TRUE, FALSE, NULL, operands[1]); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "type" "call") mgl@1371: + (set_attr "length" "4")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand 0 "register_operand" "r") mgl@1371: + (match_operand 1 "immediate_operand" "i")) mgl@1371: + (unspec_volatile [(return)] VUNSPEC_EPILOGUE)] mgl@1371: + "(REGNO(operands[0]) == RETVAL_REGNUM) && mgl@1371: + ((INTVAL(operands[1]) == -1) || (INTVAL(operands[1]) == 0) || (INTVAL(operands[1]) == 1))" mgl@1371: + { mgl@1371: + avr32_output_return_instruction (FALSE, FALSE, NULL, operands[1]); mgl@1371: + return ""; mgl@1371: + } mgl@1371: + ; Length is absolute worst case mgl@1371: + [(set_attr "type" "branch") mgl@1371: + (set_attr "length" "12")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole mgl@1371: + [(set (match_operand 0 "register_operand" "=r") mgl@1371: + (if_then_else (match_operator 1 "avr32_comparison_operator" mgl@1371: + [(match_operand 4 "register_operand" "r") mgl@1371: + (match_operand 5 "register_immediate_operand" "rKs21")]) mgl@1371: + (match_operand 2 "avr32_cond_register_immediate_operand" "rKs08") mgl@1371: + (match_operand 3 "avr32_cond_register_immediate_operand" "rKs08"))) mgl@1371: + (return)] mgl@1371: + "USE_RETURN_INSN (TRUE) && (REGNO(operands[0]) == RETVAL_REGNUM)" mgl@1371: + { mgl@1371: + operands[1] = avr32_output_cmp(operands[1], GET_MODE(operands[4]), operands[4], operands[5]); mgl@1371: + mgl@1371: + if ( GET_CODE(operands[2]) == REG mgl@1371: + && GET_CODE(operands[3]) == REG mgl@1371: + && REGNO(operands[2]) != LR_REGNUM mgl@1371: + && REGNO(operands[3]) != LR_REGNUM ){ mgl@1371: + return "ret%1 %2\;ret%i1 %3"; mgl@1371: + } else if ( GET_CODE(operands[2]) == REG mgl@1371: + && GET_CODE(operands[3]) == CONST_INT ){ mgl@1371: + if ( INTVAL(operands[3]) == -1 mgl@1371: + || INTVAL(operands[3]) == 0 mgl@1371: + || INTVAL(operands[3]) == 1 ){ mgl@1371: + return "ret%1 %2\;ret%i1 %d3"; mgl@1371: + } else { mgl@1371: + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12"; mgl@1371: + } mgl@1371: + } else if ( GET_CODE(operands[2]) == CONST_INT mgl@1371: + && GET_CODE(operands[3]) == REG ){ mgl@1371: + if ( INTVAL(operands[2]) == -1 mgl@1371: + || INTVAL(operands[2]) == 0 mgl@1371: + || INTVAL(operands[2]) == 1 ){ mgl@1371: + return "ret%1 %d2\;ret%i1 %3"; mgl@1371: + } else { mgl@1371: + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12"; mgl@1371: + } mgl@1371: + } else { mgl@1371: + if ( (INTVAL(operands[2]) == -1 mgl@1371: + || INTVAL(operands[2]) == 0 mgl@1371: + || INTVAL(operands[2]) == 1 ) mgl@1371: + && (INTVAL(operands[3]) == -1 mgl@1371: + || INTVAL(operands[3]) == 0 mgl@1371: + || INTVAL(operands[3]) == 1 )){ mgl@1371: + return "ret%1 %d2\;ret%i1 %d3"; mgl@1371: + } else { mgl@1371: + return "mov%1 r12, %2\;mov%i1 r12, %3\;retal r12"; mgl@1371: + } mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + [(set_attr "length" "10") mgl@1371: + (set_attr "cc" "none") mgl@1371: + (set_attr "type" "call")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;================================================================= mgl@1371: +;; mulnhh.w mgl@1371: +;;================================================================= mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:HI 0 "register_operand" "") mgl@1371: + (neg:HI (match_operand:HI 1 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (match_dup 0)) mgl@1371: + (sign_extend:SI (match_operand:HI 3 "register_operand" ""))))] mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[2]) == REGNO(operands[0]))" mgl@1371: + [ (set (match_dup 2) mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (neg:HI (match_dup 1))) mgl@1371: + (sign_extend:SI (match_dup 3))))] mgl@1371: + "" mgl@1371: + ) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:HI 0 "register_operand" "") mgl@1371: + (neg:HI (match_operand:HI 1 "register_operand" ""))) mgl@1371: + (set (match_operand:SI 2 "register_operand" "") mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (match_operand:HI 3 "register_operand" "")) mgl@1371: + (sign_extend:SI (match_dup 0))))] mgl@1371: + "(peep2_reg_dead_p(2, operands[0])) || (REGNO(operands[2]) == REGNO(operands[0]))" mgl@1371: + [ (set (match_dup 2) mgl@1371: + (mult:SI mgl@1371: + (sign_extend:SI (neg:HI (match_dup 1))) mgl@1371: + (sign_extend:SI (match_dup 3))))] mgl@1371: + "" mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;;================================================================= mgl@1371: +;; Vector set and extract operations mgl@1371: +;;================================================================= mgl@1371: +(define_insn "vec_setv2hi_hi" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "=r") mgl@1371: + (vec_merge:V2HI mgl@1371: + (match_dup 0) mgl@1371: + (vec_duplicate:V2HI mgl@1371: + (match_operand:HI 1 "register_operand" "r")) mgl@1371: + (const_int 1)))] mgl@1371: + "" mgl@1371: + "bfins\t%0, %1, 16, 16" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")]) mgl@1371: + mgl@1371: +(define_insn "vec_setv2hi_lo" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "+r") mgl@1371: + (vec_merge:V2HI mgl@1371: + (match_dup 0) mgl@1371: + (vec_duplicate:V2HI mgl@1371: + (match_operand:HI 1 "register_operand" "r")) mgl@1371: + (const_int 2)))] mgl@1371: + "" mgl@1371: + "bfins\t%0, %1, 0, 16" mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")]) mgl@1371: + mgl@1371: +(define_expand "vec_setv2hi" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "") mgl@1371: + (vec_merge:V2HI mgl@1371: + (match_dup 0) mgl@1371: + (vec_duplicate:V2HI mgl@1371: + (match_operand:HI 1 "register_operand" "")) mgl@1371: + (match_operand 2 "immediate_operand" "")))] mgl@1371: + "" mgl@1371: + { operands[2] = GEN_INT(INTVAL(operands[2]) + 1); } mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "vec_extractv2hi" mgl@1371: + [(set (match_operand:HI 0 "register_operand" "=r") mgl@1371: + (vec_select:HI mgl@1371: + (match_operand:V2HI 1 "register_operand" "r") mgl@1371: + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] mgl@1371: + "" mgl@1371: + { mgl@1371: + if ( INTVAL(operands[2]) == 0 ) mgl@1371: + return "bfextu\t%0, %1, 16, 16"; mgl@1371: + else mgl@1371: + return "bfextu\t%0, %1, 0, 16"; mgl@1371: + } mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")]) mgl@1371: + mgl@1371: +(define_insn "vec_extractv4qi" mgl@1371: + [(set (match_operand:QI 0 "register_operand" "=r") mgl@1371: + (vec_select:QI mgl@1371: + (match_operand:V4QI 1 "register_operand" "r") mgl@1371: + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] mgl@1371: + "" mgl@1371: + { mgl@1371: + switch ( INTVAL(operands[2]) ){ mgl@1371: + case 0: mgl@1371: + return "bfextu\t%0, %1, 24, 8"; mgl@1371: + case 1: mgl@1371: + return "bfextu\t%0, %1, 16, 8"; mgl@1371: + case 2: mgl@1371: + return "bfextu\t%0, %1, 8, 8"; mgl@1371: + case 3: mgl@1371: + return "bfextu\t%0, %1, 0, 8"; mgl@1371: + default: mgl@1371: + abort(); mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "alu") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "clobber")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "concatv2hi" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "=r, r, r") mgl@1371: + (vec_concat:V2HI mgl@1371: + (match_operand:HI 1 "register_operand" "r, r, 0") mgl@1371: + (match_operand:HI 2 "register_operand" "r, 0, r")))] mgl@1371: + "" mgl@1371: + "@ mgl@1371: + mov\t%0, %1\;bfins\t%0, %2, 0, 16 mgl@1371: + bfins\t%0, %2, 0, 16 mgl@1371: + bfins\t%0, %1, 16, 16" mgl@1371: + [(set_attr "length" "6, 4, 4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: + mgl@1371: +;; Load the atomic operation description mgl@1371: +(include "sync.md") mgl@1371: + mgl@1371: +;; Load the SIMD description mgl@1371: +(include "simd.md") mgl@1371: + mgl@1371: +;; Load the FP coprAocessor patterns mgl@1371: +(include "fpcp.md") mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32-modes.def mgl@1371: @@ -0,0 +1 @@ mgl@1371: +VECTOR_MODES (INT, 4); /* V4QI V2HI */ mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32.opt mgl@1371: @@ -0,0 +1,86 @@ mgl@1371: +; Options for the ATMEL AVR32 port of the compiler. mgl@1371: + mgl@1371: +; Copyright 2007 Atmel Corporation. mgl@1371: +; mgl@1371: +; This file is part of GCC. mgl@1371: +; mgl@1371: +; GCC is free software; you can redistribute it and/or modify it under mgl@1371: +; the terms of the GNU General Public License as published by the Free mgl@1371: +; Software Foundation; either version 2, or (at your option) any later mgl@1371: +; version. mgl@1371: +; mgl@1371: +; GCC is distributed in the hope that it will be useful, but WITHOUT ANY mgl@1371: +; WARRANTY; without even the implied warranty of MERCHANTABILITY or mgl@1371: +; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License mgl@1371: +; for more details. mgl@1371: +; mgl@1371: +; You should have received a copy of the GNU General Public License mgl@1371: +; along with GCC; see the file COPYING. If not, write to the Free mgl@1371: +; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA mgl@1371: +; 02110-1301, USA. mgl@1371: + mgl@1371: +muse-rodata-section mgl@1371: +Target Report Mask(USE_RODATA_SECTION) mgl@1371: +Use section .rodata for read-only data instead of .text. mgl@1371: + mgl@1371: +mhard-float mgl@1371: +Target Report Undocumented Mask(HARD_FLOAT) mgl@1371: +Use floating point coprocessor instructions. mgl@1371: + mgl@1371: +msoft-float mgl@1371: +Target Report Undocumented InverseMask(HARD_FLOAT, SOFT_FLOAT) mgl@1371: +Use software floating-point library for floating-point operations. mgl@1371: + mgl@1371: +mforce-double-align mgl@1371: +Target Report RejectNegative Mask(FORCE_DOUBLE_ALIGN) mgl@1371: +Force double-word alignment for double-word memory accesses. mgl@1371: + mgl@1371: +mno-init-got mgl@1371: +Target Report RejectNegative Mask(NO_INIT_GOT) mgl@1371: +Do not initialize GOT register before using it when compiling PIC code. mgl@1371: + mgl@1371: +mrelax mgl@1371: +Target Report Mask(RELAX) mgl@1371: +Let invoked assembler and linker do relaxing (Enabled by default when optimization level is >1). mgl@1371: + mgl@1371: +mmd-reorg-opt mgl@1371: +Target Report Undocumented Mask(MD_REORG_OPTIMIZATION) mgl@1371: +Perform machine dependent optimizations in reorg stage. mgl@1371: + mgl@1371: +masm-addr-pseudos mgl@1371: +Target Report Mask(HAS_ASM_ADDR_PSEUDOS) mgl@1371: +Use assembler pseudo-instructions lda.w and call for handling direct addresses. (Enabled by default) mgl@1371: + mgl@1371: +mpart= mgl@1371: +Target Report RejectNegative Joined Var(avr32_part_name) mgl@1371: +Specify the AVR32 part name mgl@1371: + mgl@1371: +mcpu= mgl@1371: +Target Report RejectNegative Joined Undocumented Var(avr32_part_name) mgl@1371: +Specify the AVR32 part name (deprecated) mgl@1371: + mgl@1371: +march= mgl@1371: +Target Report RejectNegative Joined Var(avr32_arch_name) mgl@1371: +Specify the AVR32 architecture name mgl@1371: + mgl@1371: +mfast-float mgl@1371: +Target Report Mask(FAST_FLOAT) mgl@1371: +Enable fast floating-point library. Enabled by default if the -funsafe-math-optimizations switch is specified. mgl@1371: + mgl@1371: +mimm-in-const-pool mgl@1371: +Target Report Var(avr32_imm_in_const_pool) Init(-1) mgl@1371: +Put large immediates in constant pool. This is enabled by default for archs with insn-cache. mgl@1371: + mgl@1371: +mno-pic mgl@1371: +Target Report RejectNegative Mask(NO_PIC) mgl@1371: +Do not generate position-independent code. (deprecated, use -fno-pic instead) mgl@1371: + mgl@1371: +mcond-exec-before-reload mgl@1371: +Target Report Undocumented Mask(COND_EXEC_BEFORE_RELOAD) mgl@1371: +Enable experimental conditional execution preparation before the reload stage. mgl@1371: + mgl@1371: +mrmw-addressable-data mgl@1371: +Target Report Mask(RMW_ADDRESSABLE_DATA) mgl@1371: +Signal that all data is in range for the Atomic Read-Modify-Write memory instructions, and that mgl@1371: +gcc can safely generate these whenever possible. mgl@1371: + mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/avr32-protos.h mgl@1371: @@ -0,0 +1,196 @@ mgl@1371: +/* mgl@1371: + Prototypes for exported functions defined in avr32.c mgl@1371: + Copyright 2003-2006 Atmel Corporation. mgl@1371: + mgl@1371: + Written by Ronny Pedersen, Atmel Norway, mgl@1371: + Initial porting by Anders �dland. mgl@1371: + mgl@1371: + This file is part of GCC. mgl@1371: + mgl@1371: + This program is free software; you can redistribute it and/or modify mgl@1371: + it under the terms of the GNU General Public License as published by mgl@1371: + the Free Software Foundation; either version 2 of the License, or mgl@1371: + (at your option) any later version. mgl@1371: + mgl@1371: + This program is distributed in the hope that it will be useful, mgl@1371: + but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: + GNU General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; if not, write to the Free Software mgl@1371: + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ mgl@1371: + mgl@1371: + mgl@1371: +#ifndef AVR32_PROTOS_H mgl@1371: +#define AVR32_PROTOS_H mgl@1371: + mgl@1371: +extern const int swap_reg[]; mgl@1371: + mgl@1371: +extern int avr32_valid_macmac_bypass (rtx, rtx); mgl@1371: +extern int avr32_valid_mulmac_bypass (rtx, rtx); mgl@1371: + mgl@1371: +extern int avr32_decode_lcomm_symbol_offset (rtx, int *); mgl@1371: +extern void avr32_encode_lcomm_symbol_offset (tree, char *, int); mgl@1371: + mgl@1371: +extern const char *avr32_strip_name_encoding (const char *); mgl@1371: + mgl@1371: +extern rtx avr32_get_note_reg_equiv (rtx insn); mgl@1371: + mgl@1371: +extern int avr32_use_return_insn (int iscond); mgl@1371: + mgl@1371: +extern void avr32_make_reglist16 (int reglist16_vect, char *reglist16_string); mgl@1371: + mgl@1371: +extern void avr32_make_reglist8 (int reglist8_vect, char *reglist8_string); mgl@1371: +extern void avr32_make_fp_reglist_w (int reglist_mask, char *reglist_string); mgl@1371: +extern void avr32_make_fp_reglist_d (int reglist_mask, char *reglist_string); mgl@1371: + mgl@1371: +extern void avr32_output_return_instruction (int single_ret_inst, mgl@1371: + int iscond, rtx cond, mgl@1371: + rtx r12_imm); mgl@1371: +extern void avr32_expand_prologue (void); mgl@1371: +extern void avr32_set_return_address (rtx source, rtx scratch); mgl@1371: + mgl@1371: +extern int avr32_hard_regno_mode_ok (int regno, enum machine_mode mode); mgl@1371: +extern int avr32_extra_constraint_s (rtx value, const int strict); mgl@1371: +extern int avr32_eh_return_data_regno (const int n); mgl@1371: +extern int avr32_initial_elimination_offset (const int from, const int to); mgl@1371: +extern rtx avr32_function_arg (CUMULATIVE_ARGS * cum, enum machine_mode mode, mgl@1371: + tree type, int named); mgl@1371: +extern void avr32_init_cumulative_args (CUMULATIVE_ARGS * cum, tree fntype, mgl@1371: + rtx libname, tree fndecl); mgl@1371: +extern void avr32_function_arg_advance (CUMULATIVE_ARGS * cum, mgl@1371: + enum machine_mode mode, mgl@1371: + tree type, int named); mgl@1371: +#ifdef ARGS_SIZE_RTX mgl@1371: +/* expr.h defines ARGS_SIZE_RTX and `enum direction'. */ mgl@1371: +extern enum direction avr32_function_arg_padding (enum machine_mode mode, mgl@1371: + tree type); mgl@1371: +#endif /* ARGS_SIZE_RTX */ mgl@1371: +extern rtx avr32_function_value (tree valtype, tree func, bool outgoing); mgl@1371: +extern rtx avr32_libcall_value (enum machine_mode mode); mgl@1371: +extern int avr32_sched_use_dfa_pipeline_interface (void); mgl@1371: +extern bool avr32_return_in_memory (tree type, tree fntype); mgl@1371: +extern void avr32_regs_to_save (char *operand); mgl@1371: +extern void avr32_target_asm_function_prologue (FILE * file, mgl@1371: + HOST_WIDE_INT size); mgl@1371: +extern void avr32_target_asm_function_epilogue (FILE * file, mgl@1371: + HOST_WIDE_INT size); mgl@1371: +extern void avr32_trampoline_template (FILE * file); mgl@1371: +extern void avr32_initialize_trampoline (rtx addr, rtx fnaddr, mgl@1371: + rtx static_chain); mgl@1371: +extern int avr32_legitimate_address (enum machine_mode mode, rtx x, mgl@1371: + int strict); mgl@1371: +extern int avr32_legitimate_constant_p (rtx x); mgl@1371: + mgl@1371: +extern int avr32_legitimate_pic_operand_p (rtx x); mgl@1371: + mgl@1371: +extern rtx avr32_find_symbol (rtx x); mgl@1371: +extern void avr32_select_section (rtx exp, int reloc, int align); mgl@1371: +extern void avr32_encode_section_info (tree decl, rtx rtl, int first); mgl@1371: +extern void avr32_asm_file_end (FILE * stream); mgl@1371: +extern void avr32_asm_output_ascii (FILE * stream, char *ptr, int len); mgl@1371: +extern void avr32_asm_output_common (FILE * stream, const char *name, mgl@1371: + int size, int rounded); mgl@1371: +extern void avr32_asm_output_label (FILE * stream, const char *name); mgl@1371: +extern void avr32_asm_declare_object_name (FILE * stream, char *name, mgl@1371: + tree decl); mgl@1371: +extern void avr32_asm_globalize_label (FILE * stream, const char *name); mgl@1371: +extern void avr32_asm_weaken_label (FILE * stream, const char *name); mgl@1371: +extern void avr32_asm_output_external (FILE * stream, tree decl, mgl@1371: + const char *name); mgl@1371: +extern void avr32_asm_output_external_libcall (FILE * stream, rtx symref); mgl@1371: +extern void avr32_asm_output_labelref (FILE * stream, const char *name); mgl@1371: +extern void avr32_notice_update_cc (rtx exp, rtx insn); mgl@1371: +extern void avr32_print_operand (FILE * stream, rtx x, int code); mgl@1371: +extern void avr32_print_operand_address (FILE * stream, rtx x); mgl@1371: + mgl@1371: +extern int avr32_symbol (rtx x); mgl@1371: + mgl@1371: +extern void avr32_select_rtx_section (enum machine_mode mode, rtx x, mgl@1371: + unsigned HOST_WIDE_INT align); mgl@1371: + mgl@1371: +extern int avr32_load_multiple_operation (rtx op, enum machine_mode mode); mgl@1371: +extern int avr32_store_multiple_operation (rtx op, enum machine_mode mode); mgl@1371: + mgl@1371: +extern int avr32_const_ok_for_constraint_p (HOST_WIDE_INT value, char c, mgl@1371: + const char *str); mgl@1371: + mgl@1371: +extern bool avr32_cannot_force_const_mem (rtx x); mgl@1371: + mgl@1371: +extern void avr32_init_builtins (void); mgl@1371: + mgl@1371: +extern rtx avr32_expand_builtin (tree exp, rtx target, rtx subtarget, mgl@1371: + enum machine_mode mode, int ignore); mgl@1371: + mgl@1371: +extern bool avr32_must_pass_in_stack (enum machine_mode mode, tree type); mgl@1371: + mgl@1371: +extern bool avr32_strict_argument_naming (CUMULATIVE_ARGS * ca); mgl@1371: + mgl@1371: +extern bool avr32_pass_by_reference (CUMULATIVE_ARGS * cum, mgl@1371: + enum machine_mode mode, mgl@1371: + tree type, bool named); mgl@1371: + mgl@1371: +extern rtx avr32_gen_load_multiple (rtx * regs, int count, rtx from, mgl@1371: + int write_back, int in_struct_p, mgl@1371: + int scalar_p); mgl@1371: +extern rtx avr32_gen_store_multiple (rtx * regs, int count, rtx to, mgl@1371: + int in_struct_p, int scalar_p); mgl@1371: +extern int avr32_gen_movmemsi (rtx * operands); mgl@1371: + mgl@1371: +extern int avr32_rnd_operands (rtx add, rtx shift); mgl@1371: +extern int avr32_adjust_insn_length (rtx insn, int length); mgl@1371: + mgl@1371: +extern int symbol_mentioned_p (rtx x); mgl@1371: +extern int label_mentioned_p (rtx x); mgl@1371: +extern rtx legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg); mgl@1371: +extern int avr32_address_register_rtx_p (rtx x, int strict_p); mgl@1371: +extern int avr32_legitimate_index_p (enum machine_mode mode, rtx index, mgl@1371: + int strict_p); mgl@1371: + mgl@1371: +extern int avr32_const_double_immediate (rtx value); mgl@1371: +extern void avr32_init_expanders (void); mgl@1371: +extern rtx avr32_return_addr (int count, rtx frame); mgl@1371: +extern bool avr32_got_mentioned_p (rtx addr); mgl@1371: + mgl@1371: +extern void avr32_final_prescan_insn (rtx insn, rtx * opvec, int noperands); mgl@1371: + mgl@1371: +extern int avr32_expand_movcc (enum machine_mode mode, rtx operands[]); mgl@1371: +extern int avr32_expand_addcc (enum machine_mode mode, rtx operands[]); mgl@1371: +#ifdef RTX_CODE mgl@1371: +extern int avr32_expand_scc (RTX_CODE cond, rtx * operands); mgl@1371: +#endif mgl@1371: + mgl@1371: +extern int avr32_store_bypass (rtx insn_out, rtx insn_in); mgl@1371: +extern int avr32_mul_waw_bypass (rtx insn_out, rtx insn_in); mgl@1371: +extern int avr32_valid_load_double_bypass (rtx insn_out, rtx insn_in); mgl@1371: +extern int avr32_valid_load_quad_bypass (rtx insn_out, rtx insn_in); mgl@1371: +extern rtx avr32_output_cmp (rtx cond, enum machine_mode mode, mgl@1371: + rtx op0, rtx op1); mgl@1371: + mgl@1371: +rtx get_next_insn_cond (rtx cur_insn); mgl@1371: +int set_next_insn_cond (rtx cur_insn, rtx cond); mgl@1371: +void avr32_override_options (void); mgl@1371: +void avr32_load_pic_register (void); mgl@1371: +#ifdef GCC_BASIC_BLOCK_H mgl@1371: +rtx avr32_ifcvt_modify_insn (ce_if_block_t *ce_info, rtx pattern, rtx insn, mgl@1371: + int *num_true_changes); mgl@1371: +rtx avr32_ifcvt_modify_test (ce_if_block_t *ce_info, rtx test ); mgl@1371: +void avr32_ifcvt_modify_cancel ( ce_if_block_t *ce_info, int *num_true_changes); mgl@1371: +#endif mgl@1371: +void avr32_optimization_options (int level, int size); mgl@1371: +int avr32_const_ok_for_move (HOST_WIDE_INT c); mgl@1371: + mgl@1371: +void avr32_split_const_expr (enum machine_mode mode, mgl@1371: + enum machine_mode new_mode, mgl@1371: + rtx expr, mgl@1371: + rtx *split_expr); mgl@1371: +void avr32_get_intval (enum machine_mode mode, mgl@1371: + rtx const_expr, mgl@1371: + HOST_WIDE_INT *val); mgl@1371: + mgl@1371: +int avr32_cond_imm_clobber_splittable (rtx insn, mgl@1371: + rtx operands[]); mgl@1371: + mgl@1371: + mgl@1371: +#endif /* AVR32_PROTOS_H */ mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/crti.asm mgl@1371: @@ -0,0 +1,64 @@ mgl@1371: +/* mgl@1371: + Init/fini stuff for AVR32. mgl@1371: + Copyright 2003-2006 Atmel Corporation. mgl@1371: + mgl@1371: + Written by Ronny Pedersen, Atmel Norway, mgl@1371: + mgl@1371: + This file is part of GCC. mgl@1371: + mgl@1371: + This program is free software; you can redistribute it and/or modify mgl@1371: + it under the terms of the GNU General Public License as published by mgl@1371: + the Free Software Foundation; either version 2 of the License, or mgl@1371: + (at your option) any later version. mgl@1371: + mgl@1371: + This program is distributed in the hope that it will be useful, mgl@1371: + but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: + GNU General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; if not, write to the Free Software mgl@1371: + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ mgl@1371: + mgl@1371: + mgl@1371: +/* The code in sections .init and .fini is supposed to be a single mgl@1371: + regular function. The function in .init is called directly from mgl@1371: + start in crt1.asm. The function in .fini is atexit()ed in crt1.asm mgl@1371: + too. mgl@1371: + mgl@1371: + crti.asm contributes the prologue of a function to these sections, mgl@1371: + and crtn.asm comes up the epilogue. STARTFILE_SPEC should list mgl@1371: + crti.o before any other object files that might add code to .init mgl@1371: + or .fini sections, and ENDFILE_SPEC should list crtn.o after any mgl@1371: + such object files. */ mgl@1371: + mgl@1371: + .file "crti.asm" mgl@1371: + mgl@1371: + .section ".init" mgl@1371: +/* Just load the GOT */ mgl@1371: + .align 2 mgl@1371: + .global _init mgl@1371: +_init: mgl@1371: + stm --sp, r6, lr mgl@1371: + lddpc r6, 1f mgl@1371: +0: mgl@1371: + rsub r6, pc mgl@1371: + rjmp 2f mgl@1371: + .align 2 mgl@1371: +1: .long 0b - _GLOBAL_OFFSET_TABLE_ mgl@1371: +2: mgl@1371: + mgl@1371: + .section ".fini" mgl@1371: +/* Just load the GOT */ mgl@1371: + .align 2 mgl@1371: + .global _fini mgl@1371: +_fini: mgl@1371: + stm --sp, r6, lr mgl@1371: + lddpc r6, 1f mgl@1371: +0: mgl@1371: + rsub r6, pc mgl@1371: + rjmp 2f mgl@1371: + .align 2 mgl@1371: +1: .long 0b - _GLOBAL_OFFSET_TABLE_ mgl@1371: +2: mgl@1371: + mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/crtn.asm mgl@1371: @@ -0,0 +1,44 @@ mgl@1371: +/* Copyright (C) 2001 Free Software Foundation, Inc. mgl@1371: + Written By Nick Clifton mgl@1371: + mgl@1371: + This file is free software; you can redistribute it and/or modify it mgl@1371: + under the terms of the GNU General Public License as published by the mgl@1371: + Free Software Foundation; either version 2, or (at your option) any mgl@1371: + later version. mgl@1371: + mgl@1371: + In addition to the permissions in the GNU General Public License, the mgl@1371: + Free Software Foundation gives you unlimited permission to link the mgl@1371: + compiled version of this file with other programs, and to distribute mgl@1371: + those programs without any restriction coming from the use of this mgl@1371: + file. (The General Public License restrictions do apply in other mgl@1371: + respects; for example, they cover modification of the file, and mgl@1371: + distribution when not linked into another program.) mgl@1371: + mgl@1371: + This file is distributed in the hope that it will be useful, but mgl@1371: + WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU mgl@1371: + General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; see the file COPYING. If not, write to mgl@1371: + the Free Software Foundation, 59 Temple Place - Suite 330, mgl@1371: + Boston, MA 02111-1307, USA. mgl@1371: + mgl@1371: + As a special exception, if you link this library with files mgl@1371: + compiled with GCC to produce an executable, this does not cause mgl@1371: + the resulting executable to be covered by the GNU General Public License. mgl@1371: + This exception does not however invalidate any other reasons why mgl@1371: + the executable file might be covered by the GNU General Public License. mgl@1371: +*/ mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + .file "crtn.asm" mgl@1371: + mgl@1371: + .section ".init" mgl@1371: + ldm sp++, r6, pc mgl@1371: + mgl@1371: + .section ".fini" mgl@1371: + ldm sp++, r6, pc mgl@1371: + mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/fpcp.md mgl@1371: @@ -0,0 +1,551 @@ mgl@1371: +;; AVR32 machine description file for Floating-Point instructions. mgl@1371: +;; Copyright 2003-2006 Atmel Corporation. mgl@1371: +;; mgl@1371: +;; Written by Ronny Pedersen, Atmel Norway, mgl@1371: +;; mgl@1371: +;; This file is part of GCC. mgl@1371: +;; mgl@1371: +;; This program is free software; you can redistribute it and/or modify mgl@1371: +;; it under the terms of the GNU General Public License as published by mgl@1371: +;; the Free Software Foundation; either version 2 of the License, or mgl@1371: +;; (at your option) any later version. mgl@1371: +;; mgl@1371: +;; This program is distributed in the hope that it will be useful, mgl@1371: +;; but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: +;; GNU General Public License for more details. mgl@1371: +;; mgl@1371: +;; You should have received a copy of the GNU General Public License mgl@1371: +;; along with this program; if not, write to the Free Software mgl@1371: +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. mgl@1371: + mgl@1371: +;; -*- Mode: Scheme -*- mgl@1371: + mgl@1371: +;;****************************************************************************** mgl@1371: +;; Automaton pipeline description for floating-point coprocessor insns mgl@1371: +;;****************************************************************************** mgl@1371: +(define_cpu_unit "fid,fm1,fm2,fm3,fm4,fwb,fcmp,fcast" "avr32_ap") mgl@1371: + mgl@1371: +(define_insn_reservation "fmv_op" 1 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fmv")) mgl@1371: + "is,da,d,fid,fwb") mgl@1371: + mgl@1371: +(define_insn_reservation "fmul_op" 5 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fmul")) mgl@1371: + "is,da,d,fid,fm1,fm2,fm3,fm4,fwb") mgl@1371: + mgl@1371: +(define_insn_reservation "fcmps_op" 1 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fcmps")) mgl@1371: + "is,da,d,fid,fcmp") mgl@1371: + mgl@1371: +(define_insn_reservation "fcmpd_op" 2 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fcmpd")) mgl@1371: + "is,da,d,fid*2,fcmp") mgl@1371: + mgl@1371: +(define_insn_reservation "fcast_op" 3 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fcast")) mgl@1371: + "is,da,d,fid,fcmp,fcast,fwb") mgl@1371: + mgl@1371: +(define_insn_reservation "fmvcpu_op" 2 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fmvcpu")) mgl@1371: + "is,da,d") mgl@1371: + mgl@1371: +(define_insn_reservation "fldd_op" 1 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fldd")) mgl@1371: + "is,da,d,fwb") mgl@1371: + mgl@1371: +(define_insn_reservation "flds_op" 1 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "flds")) mgl@1371: + "is,da,d,fwb") mgl@1371: + mgl@1371: +(define_insn_reservation "fsts_op" 0 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fsts")) mgl@1371: + "is,da*2,d") mgl@1371: + mgl@1371: +(define_insn_reservation "fstd_op" 0 mgl@1371: + (and (eq_attr "pipeline" "ap") mgl@1371: + (eq_attr "type" "fstd")) mgl@1371: + "is,da*2,d") mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "*movsf_fpcp" mgl@1371: + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,r,f,m,r,r,r,m") mgl@1371: + (match_operand:SF 1 "general_operand" " f,r,f,m,f,r,G,m,r"))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "@ mgl@1371: + fmov.s\t%0, %1 mgl@1371: + fmov.s\t%0, %1 mgl@1371: + fmov.s\t%0, %1 mgl@1371: + fld.s\t%0, %1 mgl@1371: + fst.s\t%0, %1 mgl@1371: + mov\t%0, %1 mgl@1371: + mov\t%0, %1 mgl@1371: + ld.w\t%0, %1 mgl@1371: + st.w\t%0, %1" mgl@1371: + [(set_attr "length" "4,4,4,4,4,2,4,4,4") mgl@1371: + (set_attr "type" "fmv,flds,fmvcpu,flds,fsts,alu,alu,load,store")]) mgl@1371: + mgl@1371: +(define_insn_and_split "*movdf_fpcp" mgl@1371: + [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,r,f,m,r,r,m") mgl@1371: + (match_operand:DF 1 "general_operand" " f,r,f,m,f,r,m,r"))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "@ mgl@1371: + fmov.d\t%0, %1 mgl@1371: + fmov.d\t%0, %1 mgl@1371: + fmov.d\t%0, %1 mgl@1371: + fld.d\t%0, %1 mgl@1371: + fst.d\t%0, %1 mgl@1371: + mov\t%0, %1\;mov\t%m0, %m1 mgl@1371: + ld.d\t%0, %1 mgl@1371: + st.d\t%0, %1" mgl@1371: + mgl@1371: + "TARGET_HARD_FLOAT mgl@1371: + && reload_completed mgl@1371: + && (REG_P(operands[0]) && (REGNO_REG_CLASS(REGNO(operands[0])) == GENERAL_REGS)) mgl@1371: + && (REG_P(operands[1]) && (REGNO_REG_CLASS(REGNO(operands[1])) == GENERAL_REGS))" mgl@1371: + [(set (match_dup 0) (match_dup 1)) mgl@1371: + (set (match_dup 2) (match_dup 3))] mgl@1371: + " mgl@1371: + { mgl@1371: + operands[2] = gen_highpart (SImode, operands[0]); mgl@1371: + operands[0] = gen_lowpart (SImode, operands[0]); mgl@1371: + operands[3] = gen_highpart(SImode, operands[1]); mgl@1371: + operands[1] = gen_lowpart(SImode, operands[1]); mgl@1371: + } mgl@1371: + " mgl@1371: + mgl@1371: + [(set_attr "length" "4,4,4,4,4,4,4,4") mgl@1371: + (set_attr "type" "fmv,fldd,fmvcpu,fldd,fstd,alu2,load2,store2")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "mulsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmul.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "nmulsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (neg:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f"))))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fnmul.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "") mgl@1371: + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" ""))) mgl@1371: + (set (match_operand:SF 3 "avr32_fp_register_operand" "") mgl@1371: + (neg:SF (match_dup 0)))] mgl@1371: + "TARGET_HARD_FLOAT && mgl@1371: + (peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[3]) == REGNO(operands[0])))" mgl@1371: + [(set (match_dup 3) mgl@1371: + (neg:SF (mult:SF (match_dup 1) mgl@1371: + (match_dup 2))))] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "macsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (plus:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f")) mgl@1371: + (match_operand:SF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmac.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "nmacsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f"))) mgl@1371: + (match_operand:SF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fnmac.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "") mgl@1371: + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" ""))) mgl@1371: + (set (match_operand:SF 3 "avr32_fp_register_operand" "") mgl@1371: + (minus:SF mgl@1371: + (match_dup 3) mgl@1371: + (match_dup 0)))] mgl@1371: + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 3) mgl@1371: + (plus:SF (neg:SF (mult:SF (match_dup 1) mgl@1371: + (match_dup 2))) mgl@1371: + (match_dup 3)))] mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "msubacsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (minus:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f")) mgl@1371: + (match_operand:SF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmsc.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "") mgl@1371: + (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" ""))) mgl@1371: + (set (match_operand:SF 3 "avr32_fp_register_operand" "") mgl@1371: + (minus:SF mgl@1371: + (match_dup 0) mgl@1371: + (match_dup 3)))] mgl@1371: + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 3) mgl@1371: + (minus:SF (mult:SF (match_dup 1) mgl@1371: + (match_dup 2)) mgl@1371: + (match_dup 3)))] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "nmsubacsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (minus:SF (neg:SF (mult:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f"))) mgl@1371: + (match_operand:SF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fnmsc.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "addsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (plus:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fadd.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "subsf3" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (minus:SF (match_operand:SF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 2 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fsub.s\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "negsf2" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (neg:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fneg.s\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmv")]) mgl@1371: + mgl@1371: +(define_insn "abssf2" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (abs:SF (match_operand:SF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fabs.s\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmv")]) mgl@1371: + mgl@1371: +(define_insn "truncdfsf2" mgl@1371: + [(set (match_operand:SF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (float_truncate:SF mgl@1371: + (match_operand:DF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fcastd.s\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fcast")]) mgl@1371: + mgl@1371: +(define_insn "extendsfdf2" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (float_extend:DF mgl@1371: + (match_operand:SF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fcasts.d\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fcast")]) mgl@1371: + mgl@1371: +(define_insn "muldf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmul.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "nmuldf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (neg:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f"))))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fnmul.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "") mgl@1371: + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" ""))) mgl@1371: + (set (match_operand:DF 3 "avr32_fp_register_operand" "") mgl@1371: + (neg:DF (match_dup 0)))] mgl@1371: + "TARGET_HARD_FLOAT && mgl@1371: + (peep2_reg_dead_p(2, operands[0]) || (REGNO(operands[3]) == REGNO(operands[0])))" mgl@1371: + [(set (match_dup 3) mgl@1371: + (neg:DF (mult:DF (match_dup 1) mgl@1371: + (match_dup 2))))] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "macdf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (plus:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f")) mgl@1371: + (match_operand:DF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmac.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "msubacdf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (minus:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f")) mgl@1371: + (match_operand:DF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmsc.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "") mgl@1371: + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" ""))) mgl@1371: + (set (match_operand:DF 3 "avr32_fp_register_operand" "") mgl@1371: + (minus:DF mgl@1371: + (match_dup 0) mgl@1371: + (match_dup 3)))] mgl@1371: + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 3) mgl@1371: + (minus:DF (mult:DF (match_dup 1) mgl@1371: + (match_dup 2)) mgl@1371: + (match_dup 3)))] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "nmsubacdf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (minus:DF (neg:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f"))) mgl@1371: + (match_operand:DF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fnmsc.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "nmacdf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f"))) mgl@1371: + (match_operand:DF 3 "avr32_fp_register_operand" "0")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fnmac.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_peephole2 mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "") mgl@1371: + (mult:DF (match_operand:DF 1 "avr32_fp_register_operand" "") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" ""))) mgl@1371: + (set (match_operand:DF 3 "avr32_fp_register_operand" "") mgl@1371: + (minus:DF mgl@1371: + (match_dup 3) mgl@1371: + (match_dup 0)))] mgl@1371: + "TARGET_HARD_FLOAT && peep2_reg_dead_p(2, operands[0])" mgl@1371: + [(set (match_dup 3) mgl@1371: + (plus:DF (neg:DF (mult:DF (match_dup 1) mgl@1371: + (match_dup 2))) mgl@1371: + (match_dup 3)))] mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "adddf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (plus:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fadd.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "subdf3" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (minus:DF (match_operand:DF 1 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 2 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fsub.d\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmul")]) mgl@1371: + mgl@1371: +(define_insn "negdf2" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (neg:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fneg.d\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmv")]) mgl@1371: + mgl@1371: +(define_insn "absdf2" mgl@1371: + [(set (match_operand:DF 0 "avr32_fp_register_operand" "=f") mgl@1371: + (abs:DF (match_operand:DF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fabs.d\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmv")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "cmpdf" mgl@1371: + [(set (cc0) mgl@1371: + (compare:DF mgl@1371: + (match_operand:DF 0 "general_operand" "") mgl@1371: + (match_operand:DF 1 "general_operand" "")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "{ mgl@1371: + rtx tmpreg; mgl@1371: + if ( !REG_P(operands[0]) ) mgl@1371: + operands[0] = force_reg(DFmode, operands[0]); mgl@1371: + mgl@1371: + if ( !REG_P(operands[1]) ) mgl@1371: + operands[1] = force_reg(DFmode, operands[1]); mgl@1371: + mgl@1371: + avr32_compare_op0 = operands[0]; mgl@1371: + avr32_compare_op1 = operands[1]; mgl@1371: + mgl@1371: + emit_insn(gen_cmpdf_internal(operands[0], operands[1])); mgl@1371: + mgl@1371: + tmpreg = gen_reg_rtx(SImode); mgl@1371: + emit_insn(gen_fpcc_to_reg(tmpreg)); mgl@1371: + emit_insn(gen_reg_to_cc(tmpreg)); mgl@1371: + mgl@1371: + DONE; mgl@1371: + }" mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "cmpdf_internal" mgl@1371: + [(set (reg:CC FPCC_REGNUM) mgl@1371: + (compare:CC mgl@1371: + (match_operand:DF 0 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:DF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + { mgl@1371: + if (!rtx_equal_p(cc_prev_status.mdep.fpvalue, SET_SRC(PATTERN (insn))) ) mgl@1371: + return "fcmp.d\t%0, %1"; mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fcmpd") mgl@1371: + (set_attr "cc" "fpcompare")]) mgl@1371: + mgl@1371: +(define_expand "cmpsf" mgl@1371: + [(set (cc0) mgl@1371: + (compare:SF mgl@1371: + (match_operand:SF 0 "general_operand" "") mgl@1371: + (match_operand:SF 1 "general_operand" "")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "{ mgl@1371: + rtx tmpreg; mgl@1371: + if ( !REG_P(operands[0]) ) mgl@1371: + operands[0] = force_reg(SFmode, operands[0]); mgl@1371: + mgl@1371: + if ( !REG_P(operands[1]) ) mgl@1371: + operands[1] = force_reg(SFmode, operands[1]); mgl@1371: + mgl@1371: + avr32_compare_op0 = operands[0]; mgl@1371: + avr32_compare_op1 = operands[1]; mgl@1371: + mgl@1371: + emit_insn(gen_cmpsf_internal(operands[0], operands[1])); mgl@1371: + mgl@1371: + tmpreg = gen_reg_rtx(SImode); mgl@1371: + emit_insn(gen_fpcc_to_reg(tmpreg)); mgl@1371: + emit_insn(gen_reg_to_cc(tmpreg)); mgl@1371: + mgl@1371: + DONE; mgl@1371: + }" mgl@1371: +) mgl@1371: + mgl@1371: +(define_insn "cmpsf_internal" mgl@1371: + [(set (reg:CC FPCC_REGNUM) mgl@1371: + (compare:CC mgl@1371: + (match_operand:SF 0 "avr32_fp_register_operand" "f") mgl@1371: + (match_operand:SF 1 "avr32_fp_register_operand" "f")))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + { mgl@1371: + if (!rtx_equal_p(cc_prev_status.mdep.fpvalue, SET_SRC(PATTERN (insn))) ) mgl@1371: + return "fcmp.s\t%0, %1"; mgl@1371: + return ""; mgl@1371: + } mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fcmps") mgl@1371: + (set_attr "cc" "fpcompare")]) mgl@1371: + mgl@1371: +(define_insn "fpcc_to_reg" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=r") mgl@1371: + (unspec:SI [(reg:CC FPCC_REGNUM)] mgl@1371: + UNSPEC_FPCC_TO_REG))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "fmov.s\t%0, fsr" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "fmvcpu")]) mgl@1371: + mgl@1371: +(define_insn "reg_to_cc" mgl@1371: + [(set (cc0) mgl@1371: + (unspec:SI [(match_operand:SI 0 "register_operand" "r")] mgl@1371: + UNSPEC_REG_TO_CC))] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + "musfr\t%0" mgl@1371: + [(set_attr "length" "2") mgl@1371: + (set_attr "type" "alu") mgl@1371: + (set_attr "cc" "from_fpcc")]) mgl@1371: + mgl@1371: +(define_insn "stm_fp" mgl@1371: + [(unspec [(match_operand 0 "register_operand" "r") mgl@1371: + (match_operand 1 "const_int_operand" "") mgl@1371: + (match_operand 2 "const_int_operand" "")] mgl@1371: + UNSPEC_STMFP)] mgl@1371: + "TARGET_HARD_FLOAT" mgl@1371: + { mgl@1371: + int cop_reglist = INTVAL(operands[1]); mgl@1371: + mgl@1371: + if (INTVAL(operands[2]) != 0) mgl@1371: + return "stcm.w\tcp0, --%0, %C1"; mgl@1371: + else mgl@1371: + return "stcm.w\tcp0, %0, %C1"; mgl@1371: + mgl@1371: + if ( cop_reglist & ~0xff ){ mgl@1371: + operands[1] = GEN_INT(cop_reglist & ~0xff); mgl@1371: + if (INTVAL(operands[2]) != 0) mgl@1371: + return "stcm.d\tcp0, --%0, %D1"; mgl@1371: + else mgl@1371: + return "stcm.d\tcp0, %0, %D1"; mgl@1371: + } mgl@1371: + } mgl@1371: + [(set_attr "type" "fstm") mgl@1371: + (set_attr "length" "4") mgl@1371: + (set_attr "cc" "none")]) mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/lib1funcs.S mgl@1371: @@ -0,0 +1,2874 @@ mgl@1371: +/* Macro for moving immediate value to register. */ mgl@1371: +.macro mov_imm reg, imm mgl@1371: +.if (((\imm & 0xfffff) == \imm) || ((\imm | 0xfff00000) == \imm)) mgl@1371: + mov \reg, \imm mgl@1371: +#if __AVR32_UC__ >= 2 mgl@1371: +.elseif ((\imm & 0xffff) == 0) mgl@1371: + movh \reg, hi(\imm) mgl@1371: + mgl@1371: +#endif mgl@1371: +.else mgl@1371: + mov \reg, lo(\imm) mgl@1371: + orh \reg, hi(\imm) mgl@1371: +.endif mgl@1371: +.endm mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* Adjust the unpacked double number if it is a subnormal number. mgl@1371: + The exponent and mantissa pair are stored mgl@1371: + in [mant_hi,mant_lo] and [exp]. A register with the correct sign bit in mgl@1371: + the MSB is passed in [sign]. Needs two scratch mgl@1371: + registers [scratch1] and [scratch2]. An adjusted and packed double float mgl@1371: + is present in [mant_hi,mant_lo] after macro has executed */ mgl@1371: +.macro adjust_subnormal_df exp, mant_lo, mant_hi, sign, scratch1, scratch2 mgl@1371: + /* We have an exponent which is <=0 indicating a subnormal number mgl@1371: + As it should be stored as if the exponent was 1 (although the mgl@1371: + exponent field is all zeros to indicate a subnormal number) mgl@1371: + we have to shift down the mantissa to its correct position. */ mgl@1371: + neg \exp mgl@1371: + sub \exp,-1 /* amount to shift down */ mgl@1371: + cp.w \exp,54 mgl@1371: + brlo 50f /* if more than 53 shift steps, the mgl@1371: + entire mantissa will disappear mgl@1371: + without any rounding to occur */ mgl@1371: + mov \mant_hi, 0 mgl@1371: + mov \mant_lo, 0 mgl@1371: + rjmp 52f mgl@1371: +50: mgl@1371: + sub \exp,-10 /* do the shift to position the mgl@1371: + mantissa at the same time mgl@1371: + note! this does not include the mgl@1371: + final 1 step shift to add the sign */ mgl@1371: + mgl@1371: + /* when shifting, save all shifted out bits in [scratch2]. we may need to mgl@1371: + look at them to make correct rounding. */ mgl@1371: + mgl@1371: + rsub \scratch1,\exp,32 /* get inverted shift count */ mgl@1371: + cp.w \exp,32 /* handle shifts >= 32 separately */ mgl@1371: + brhs 51f mgl@1371: + mgl@1371: + /* small (<32) shift amount, both words are part of the shift */ mgl@1371: + lsl \scratch2,\mant_lo,\scratch1 /* save bits to shift out from lsw*/ mgl@1371: + lsl \scratch1,\mant_hi,\scratch1 /* get bits from msw destined for lsw*/ mgl@1371: + lsr \mant_lo,\mant_lo,\exp /* shift down lsw */ mgl@1371: + lsr \mant_hi,\mant_hi,\exp /* shift down msw */ mgl@1371: + or \mant_hi,\scratch1 /* add bits from msw with prepared lsw */ mgl@1371: + rjmp 50f mgl@1371: + mgl@1371: + /* large (>=32) shift amount, only lsw will have bits left after shift. mgl@1371: + note that shift operations will use ((shift count) mod 32) so mgl@1371: + we do not need to subtract 32 from shift count. */ mgl@1371: +51: mgl@1371: + lsl \scratch2,\mant_hi,\scratch1 /* save bits to shift out from msw */ mgl@1371: + or \scratch2,\mant_lo /* also save all bits from lsw */ mgl@1371: + mov \mant_lo,\mant_hi /* msw -> lsw (i.e. "shift 32 first") */ mgl@1371: + mov \mant_hi,0 /* clear msw */ mgl@1371: + lsr \mant_lo,\mant_lo,\exp /* make rest of shift inside lsw */ mgl@1371: + mgl@1371: +50: mgl@1371: + /* result is almost ready to return, except that least significant bit mgl@1371: + and the part we already shifted out may cause the result to be mgl@1371: + rounded */ mgl@1371: + bld \mant_lo,0 /* get bit to be shifted out */ mgl@1371: + brcc 51f /* if bit was 0, no rounding */ mgl@1371: + mgl@1371: + /* msb of part to remove is 1, so rounding depends on rest of bits */ mgl@1371: + tst \scratch2,\scratch2 /* get shifted out tail */ mgl@1371: + brne 50f /* if rest > 0, do round */ mgl@1371: + bld \mant_lo,1 /* we have to look at lsb in result */ mgl@1371: + brcc 51f /* if lsb is 0, don't round */ mgl@1371: + mgl@1371: +50: mgl@1371: + /* subnormal result requires rounding mgl@1371: + rounding may cause subnormal to become smallest normal number mgl@1371: + luckily, smallest normal number has exactly the representation mgl@1371: + we got by rippling a one bit up from mantissa into exponent field. */ mgl@1371: + sub \mant_lo,-1 mgl@1371: + subcc \mant_hi,-1 mgl@1371: + mgl@1371: +51: mgl@1371: + /* shift and return packed double with correct sign */ mgl@1371: + rol \sign mgl@1371: + ror \mant_hi mgl@1371: + ror \mant_lo mgl@1371: +52: mgl@1371: +.endm mgl@1371: + mgl@1371: + mgl@1371: +/* Adjust subnormal single float number with exponent [exp] mgl@1371: + and mantissa [mant] and round. */ mgl@1371: +.macro adjust_subnormal_sf sf, exp, mant, sign, scratch mgl@1371: + /* subnormal number */ mgl@1371: + rsub \exp,\exp, 1 /* shift amount */ mgl@1371: + cp.w \exp, 25 mgl@1371: + movhs \mant, 0 mgl@1371: + brhs 90f /* Return zero */ mgl@1371: + rsub \scratch, \exp, 32 mgl@1371: + lsl \scratch, \mant,\scratch/* Check if there are any bits set mgl@1371: + in the bits discarded in the mantissa */ mgl@1371: + srne \scratch /* If so set the lsb of the shifted mantissa */ mgl@1371: + lsr \mant,\mant,\exp /* Shift the mantissa */ mgl@1371: + or \mant, \scratch /* Round lsb if any bits were shifted out */ mgl@1371: + /* Rounding : For explaination, see round_sf. */ mgl@1371: + mov \scratch, 0x7f /* Set rounding constant */ mgl@1371: + bld \mant, 8 mgl@1371: + subeq \scratch, -1 /* For odd numbers use rounding constant 0x80 */ mgl@1371: + add \mant, \scratch /* Add rounding constant to mantissa */ mgl@1371: + /* We can't overflow because mantissa is at least shifted one position mgl@1371: + to the right so the implicit bit is zero. We can however get the implicit mgl@1371: + bit set after rounding which means that we have the lowest normal number mgl@1371: + but this is ok since this bit has the same position as the LSB of the mgl@1371: + exponent */ mgl@1371: + lsr \sf, \mant, 7 mgl@1371: + /* Rotate in sign */ mgl@1371: + lsl \sign, 1 mgl@1371: + ror \sf mgl@1371: +90: mgl@1371: +.endm mgl@1371: + mgl@1371: + mgl@1371: +/* Round the unpacked df number with exponent [exp] and mgl@1371: + mantissa [mant_hi, mant_lo]. Uses scratch register mgl@1371: + [scratch] */ mgl@1371: +.macro round_df exp, mant_lo, mant_hi, scratch mgl@1371: + mov \scratch, 0x3ff /* Rounding constant */ mgl@1371: + bld \mant_lo,11 /* Check if lsb in the final result is mgl@1371: + set */ mgl@1371: + subeq \scratch, -1 /* Adjust rounding constant to 0x400 mgl@1371: + if rounding 0.5 upwards */ mgl@1371: + add \mant_lo, \scratch /* Round */ mgl@1371: + acr \mant_hi /* If overflowing we know that mgl@1371: + we have all zeros in the bits not mgl@1371: + scaled out so we can leave them mgl@1371: + but we must increase the exponent with mgl@1371: + two since we had an implicit bit mgl@1371: + which is lost + the extra overflow bit */ mgl@1371: + subcs \exp, -2 /* Update exponent */ mgl@1371: +.endm mgl@1371: + mgl@1371: +/* Round single float number stored in [mant] and [exp] */ mgl@1371: +.macro round_sf exp, mant, scratch mgl@1371: + /* Round: mgl@1371: + For 0.5 we round to nearest even integer mgl@1371: + for all other cases we round to nearest integer. mgl@1371: + This means that if the digit left of the "point" (.) mgl@1371: + is 1 we can add 0x80 to the mantissa since the mgl@1371: + corner case 0x180 will round up to 0x200. If the mgl@1371: + digit left of the "point" is 0 we will have to mgl@1371: + add 0x7f since this will give 0xff and hence a mgl@1371: + truncation/rounding downwards for the corner mgl@1371: + case when the 9 lowest bits are 0x080 */ mgl@1371: + mov \scratch, 0x7f /* Set rounding constant */ mgl@1371: + /* Check if the mantissa is even or odd */ mgl@1371: + bld \mant, 8 mgl@1371: + subeq \scratch, -1 /* Rounding constant should be 0x80 */ mgl@1371: + add \mant, \scratch mgl@1371: + subcs \exp, -2 /* Adjust exponent if we overflowed */ mgl@1371: +.endm mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* Pack a single float number stored in [mant] and [exp] mgl@1371: + into a single float number in [sf] */ mgl@1371: +.macro pack_sf sf, exp, mant mgl@1371: + bld \mant,31 /* implicit bit to z */ mgl@1371: + subne \exp,1 /* if subnormal (implicit bit 0) mgl@1371: + adjust exponent to storage format */ mgl@1371: + mgl@1371: + lsr \sf, \mant, 7 mgl@1371: + bfins \sf, \exp, 24, 8 mgl@1371: +.endm mgl@1371: + mgl@1371: +/* Pack exponent [exp] and mantissa [mant_hi, mant_lo] mgl@1371: + into [df_hi, df_lo]. [df_hi] is shifted mgl@1371: + one bit up so the sign bit can be shifted into it */ mgl@1371: + mgl@1371: +.macro pack_df exp, mant_lo, mant_hi, df_lo, df_hi mgl@1371: + bld \mant_hi,31 /* implicit bit to z */ mgl@1371: + subne \exp,1 /* if subnormal (implicit bit 0) mgl@1371: + adjust exponent to storage format */ mgl@1371: + mgl@1371: + lsr \mant_lo,11 /* shift back lsw */ mgl@1371: + or \df_lo,\mant_lo,\mant_hi<<21 /* combine with low bits from msw */ mgl@1371: + lsl \mant_hi,1 /* get rid of implicit bit */ mgl@1371: + lsr \mant_hi,11 /* shift back msw except for one step*/ mgl@1371: + or \df_hi,\mant_hi,\exp<<21 /* combine msw with exponent */ mgl@1371: +.endm mgl@1371: + mgl@1371: +/* Normalize single float number stored in [mant] and [exp] mgl@1371: + using scratch register [scratch] */ mgl@1371: +.macro normalize_sf exp, mant, scratch mgl@1371: + /* Adjust exponent and mantissa */ mgl@1371: + clz \scratch, \mant mgl@1371: + sub \exp, \scratch mgl@1371: + lsl \mant, \mant, \scratch mgl@1371: +.endm mgl@1371: + mgl@1371: +/* Normalize the exponent and mantissa pair stored mgl@1371: + in [mant_hi,mant_lo] and [exp]. Needs two scratch mgl@1371: + registers [scratch1] and [scratch2]. */ mgl@1371: +.macro normalize_df exp, mant_lo, mant_hi, scratch1, scratch2 mgl@1371: + clz \scratch1,\mant_hi /* Check if we have zeros in high bits */ mgl@1371: + breq 80f /* No need for scaling if no zeros in high bits */ mgl@1371: + brcs 81f /* Check for all zeros */ mgl@1371: + mgl@1371: + /* shift amount is smaller than 32, and involves both msw and lsw*/ mgl@1371: + rsub \scratch2,\scratch1,32 /* shift mantissa */ mgl@1371: + lsl \mant_hi,\mant_hi,\scratch1 mgl@1371: + lsr \scratch2,\mant_lo,\scratch2 mgl@1371: + or \mant_hi,\scratch2 mgl@1371: + lsl \mant_lo,\mant_lo,\scratch1 mgl@1371: + sub \exp,\scratch1 /* adjust exponent */ mgl@1371: + rjmp 80f /* Finished */ mgl@1371: +81: mgl@1371: + /* shift amount is greater than 32 */ mgl@1371: + clz \scratch1,\mant_lo /* shift mantissa */ mgl@1371: + movcs \scratch1, 0 mgl@1371: + subcc \scratch1,-32 mgl@1371: + lsl \mant_hi,\mant_lo,\scratch1 mgl@1371: + mov \mant_lo,0 mgl@1371: + sub \exp,\scratch1 /* adjust exponent */ mgl@1371: +80: mgl@1371: +.endm mgl@1371: + mgl@1371: + mgl@1371: +/* Fast but approximate multiply of two 64-bit numbers to give a 64 bit result. mgl@1371: + The multiplication of [al]x[bl] is discarded. mgl@1371: + Operands in [ah], [al], [bh], [bl]. mgl@1371: + Scratch registers in [sh], [sl]. mgl@1371: + Returns results in registers [rh], [rl].*/ mgl@1371: +.macro mul_approx_df ah, al, bh, bl, rh, rl, sh, sl mgl@1371: + mulu.d \sl, \ah, \bl mgl@1371: + macu.d \sl, \al, \bh mgl@1371: + mulu.d \rl, \ah, \bh mgl@1371: + add \rl, \sh mgl@1371: + acr \rh mgl@1371: +.endm mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_mul) || defined(L_avr32_f64_mul_fast) mgl@1371: + .align 2 mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + .global __avr32_f64_mul mgl@1371: + .type __avr32_f64_mul,@function mgl@1371: +__avr32_f64_mul: mgl@1371: +#else mgl@1371: + .global __avr32_f64_mul_fast mgl@1371: + .type __avr32_f64_mul_fast,@function mgl@1371: +__avr32_f64_mul_fast: mgl@1371: +#endif mgl@1371: + or r12, r10, r11 << 1 mgl@1371: + breq __avr32_f64_mul_op1_zero mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + pushm r4-r7, lr mgl@1371: +#else mgl@1371: + stm --sp, r5,r6,r7,lr mgl@1371: +#endif mgl@1371: + mgl@1371: +#define AVR32_F64_MUL_OP1_INT_BITS 1 mgl@1371: +#define AVR32_F64_MUL_OP2_INT_BITS 10 mgl@1371: +#define AVR32_F64_MUL_RES_INT_BITS 11 mgl@1371: + mgl@1371: + /* op1 in {r11,r10}*/ mgl@1371: + /* op2 in {r9,r8}*/ mgl@1371: + eor lr, r11, r9 /* MSB(lr) = Sign(op1) ^ Sign(op2) */ mgl@1371: + mgl@1371: + /* Unpack op1 to 1.63 format*/ mgl@1371: + /* exp: r7 */ mgl@1371: + /* sf: r11, r10 */ mgl@1371: + bfextu r7, r11, 20, 11 /* Extract exponent */ mgl@1371: + mgl@1371: + mov r5, 1 mgl@1371: + mgl@1371: + /* Check if normalization is needed */ mgl@1371: + breq __avr32_f64_mul_op1_subnormal /*If number is subnormal, normalize it */ mgl@1371: + mgl@1371: + lsl r11, (12-AVR32_F64_MUL_OP1_INT_BITS-1) /* Extract mantissa, leave room for implicit bit */ mgl@1371: + or r11, r11, r10>>(32-(12-AVR32_F64_MUL_OP1_INT_BITS-1)) mgl@1371: + lsl r10, (12-AVR32_F64_MUL_OP1_INT_BITS-1) mgl@1371: + bfins r11, r5, 32 - (1 + AVR32_F64_MUL_OP1_INT_BITS), 1 + AVR32_F64_MUL_OP1_INT_BITS /* Insert implicit bit */ mgl@1371: + mgl@1371: + mgl@1371: +22: mgl@1371: + /* Unpack op2 to 10.54 format */ mgl@1371: + /* exp: r6 */ mgl@1371: + /* sf: r9, r8 */ mgl@1371: + bfextu r6, r9, 20, 11 /* Extract exponent */ mgl@1371: + mgl@1371: + /* Check if normalization is needed */ mgl@1371: + breq __avr32_f64_mul_op2_subnormal /*If number is subnormal, normalize it */ mgl@1371: + mgl@1371: + lsl r8, 1 /* Extract mantissa, leave room for implicit bit */ mgl@1371: + rol r9 mgl@1371: + bfins r9, r5, 32 - (1 + AVR32_F64_MUL_OP2_INT_BITS), 1 + AVR32_F64_MUL_OP2_INT_BITS /* Insert implicit bit */ mgl@1371: + mgl@1371: +23: mgl@1371: + mgl@1371: + /* Check if any operands are NaN or INF */ mgl@1371: + cp r7, 0x7ff mgl@1371: + breq __avr32_f64_mul_op_nan_or_inf /* Check op1 for NaN or Inf */ mgl@1371: + cp r6, 0x7ff mgl@1371: + breq __avr32_f64_mul_op_nan_or_inf /* Check op2 for NaN or Inf */ mgl@1371: + mgl@1371: + mgl@1371: + /* Calculate new exponent in r12*/ mgl@1371: + add r12, r7, r6 mgl@1371: + sub r12, (1023-1) mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + /* Do the multiplication. mgl@1371: + Place result in [r11, r10, r7, r6]. The result is in 11.117 format. */ mgl@1371: + mulu.d r4, r11, r8 mgl@1371: + macu.d r4, r10, r9 mgl@1371: + mulu.d r6, r10, r8 mgl@1371: + mulu.d r10, r11, r9 mgl@1371: + add r7, r4 mgl@1371: + adc r10, r10, r5 mgl@1371: + acr r11 mgl@1371: +#else mgl@1371: + /* Do the multiplication using approximate calculation. discard the al x bl mgl@1371: + calculation. mgl@1371: + Place result in [r11, r10, r7]. The result is in 11.85 format. */ mgl@1371: + mgl@1371: + /* Do the multiplication using approximate calculation. mgl@1371: + Place result in r11, r10. Use r7, r6 as scratch registers */ mgl@1371: + mulu.d r6, r11, r8 mgl@1371: + macu.d r6, r10, r9 mgl@1371: + mulu.d r10, r11, r9 mgl@1371: + add r10, r7 mgl@1371: + acr r11 mgl@1371: +#endif mgl@1371: + /* Adjust exponent and mantissa */ mgl@1371: + /* [r12]:exp, [r11, r10]:mant [r7, r6]:sticky bits */ mgl@1371: + /* Mantissa may be of the format 00000000000.0xxx or 00000000000.1xxx. */ mgl@1371: + /* In the first case, shift one pos to left.*/ mgl@1371: + bld r11, 32-AVR32_F64_MUL_RES_INT_BITS-1 mgl@1371: + breq 0f mgl@1371: + lsl r7, 1 mgl@1371: + rol r10 mgl@1371: + rol r11 mgl@1371: + sub r12, 1 mgl@1371: +0: mgl@1371: + cp r12, 0 mgl@1371: + brle __avr32_f64_mul_res_subnormal /*Result was subnormal.*/ mgl@1371: + mgl@1371: + /* Check for Inf. */ mgl@1371: + cp.w r12, 0x7ff mgl@1371: + brge __avr32_f64_mul_res_inf mgl@1371: + mgl@1371: + /* Insert exponent. */ mgl@1371: + bfins r11, r12, 20, 11 mgl@1371: + mgl@1371: + /* Result was not subnormal. Perform rounding. */ mgl@1371: + /* For the fast version we discard the sticky bits and always round mgl@1371: + the halfwaycase up. */ mgl@1371: +24: mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + or r6, r6, r10 << 31 /* Or in parity bit into stickybits */ mgl@1371: + or r7, r7, r6 >> 1 /* Or together sticky and still make the msb mgl@1371: + of r7 represent the halfway bit. */ mgl@1371: + eorh r7, 0x8000 /* Toggle halfway bit. */ mgl@1371: + /* We should now round up by adding one for the following cases: mgl@1371: + mgl@1371: + halfway sticky|parity round-up mgl@1371: + 0 x no mgl@1371: + 1 0 no mgl@1371: + 1 1 yes mgl@1371: + mgl@1371: + Since we have inverted the halfway bit we can use the satu instruction mgl@1371: + by saturating to 1 bit to implement this. mgl@1371: + */ mgl@1371: + satu r7 >> 0, 1 mgl@1371: +#else mgl@1371: + lsr r7, 31 mgl@1371: +#endif mgl@1371: + add r10, r7 mgl@1371: + acr r11 mgl@1371: + mgl@1371: + /* Insert sign bit*/ mgl@1371: + bld lr, 31 mgl@1371: + bst r11, 31 mgl@1371: + mgl@1371: + /* Return result in [r11,r10] */ mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + popm r4-r7, pc mgl@1371: +#else mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_mul_op1_subnormal: mgl@1371: + andh r11, 0x000f /* Remove sign bit and exponent */ mgl@1371: + clz r12, r10 /* Count leading zeros in lsw */ mgl@1371: + clz r6, r11 /* Count leading zeros in msw */ mgl@1371: + subcs r12, -32 + AVR32_F64_MUL_OP1_INT_BITS mgl@1371: + movcs r6, r12 mgl@1371: + subcc r6, AVR32_F64_MUL_OP1_INT_BITS mgl@1371: + cp.w r6, 32 mgl@1371: + brge 0f mgl@1371: + mgl@1371: + /* shifting involves both msw and lsw*/ mgl@1371: + rsub r12, r6, 32 /* shift mantissa */ mgl@1371: + lsl r11, r11, r6 mgl@1371: + lsr r12, r10, r12 mgl@1371: + or r11, r12 mgl@1371: + lsl r10, r10, r6 mgl@1371: + sub r6, 12-AVR32_F64_MUL_OP1_INT_BITS mgl@1371: + sub r7, r6 /* adjust exponent */ mgl@1371: + rjmp 22b /* Finished */ mgl@1371: +0: mgl@1371: + /* msw is zero so only need to consider lsw */ mgl@1371: + lsl r11, r10, r6 mgl@1371: + breq __avr32_f64_mul_res_zero mgl@1371: + mov r10, 0 mgl@1371: + sub r6, 12-AVR32_F64_MUL_OP1_INT_BITS mgl@1371: + sub r7, r6 /* adjust exponent */ mgl@1371: + rjmp 22b mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_mul_op2_subnormal: mgl@1371: + andh r9, 0x000f /* Remove sign bit and exponent */ mgl@1371: + clz r12, r8 /* Count leading zeros in lsw */ mgl@1371: + clz r5, r9 /* Count leading zeros in msw */ mgl@1371: + subcs r12, -32 + AVR32_F64_MUL_OP2_INT_BITS mgl@1371: + movcs r5, r12 mgl@1371: + subcc r5, AVR32_F64_MUL_OP2_INT_BITS mgl@1371: + cp.w r5, 32 mgl@1371: + brge 0f mgl@1371: + mgl@1371: + /* shifting involves both msw and lsw*/ mgl@1371: + rsub r12, r5, 32 /* shift mantissa */ mgl@1371: + lsl r9, r9, r5 mgl@1371: + lsr r12, r8, r12 mgl@1371: + or r9, r12 mgl@1371: + lsl r8, r8, r5 mgl@1371: + sub r5, 12 - AVR32_F64_MUL_OP2_INT_BITS mgl@1371: + sub r6, r5 /* adjust exponent */ mgl@1371: + rjmp 23b /* Finished */ mgl@1371: +0: mgl@1371: + /* msw is zero so only need to consider lsw */ mgl@1371: + lsl r9, r8, r5 mgl@1371: + breq __avr32_f64_mul_res_zero mgl@1371: + mov r8, 0 mgl@1371: + sub r5, 12 - AVR32_F64_MUL_OP2_INT_BITS mgl@1371: + sub r6, r5 /* adjust exponent */ mgl@1371: + rjmp 23b mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_mul_op_nan_or_inf: mgl@1371: + /* Same code for OP1 and OP2*/ mgl@1371: + /* Since we are here, at least one of the OPs were NaN or INF*/ mgl@1371: + andh r9, 0x000f /* Remove sign bit and exponent */ mgl@1371: + andh r11, 0x000f /* Remove sign bit and exponent */ mgl@1371: + /* Merge the regs in each operand to check for zero*/ mgl@1371: + or r11, r10 /* op1 */ mgl@1371: + or r9, r8 /* op2 */ mgl@1371: + /* Check if op1 is NaN or INF */ mgl@1371: + cp r7, 0x7ff mgl@1371: + brne __avr32_f64_mul_op1_not_naninf mgl@1371: + /* op1 was NaN or INF.*/ mgl@1371: + cp r11, 0 mgl@1371: + brne __avr32_f64_mul_res_nan /* op1 was NaN. Result will be NaN*/ mgl@1371: + /*op1 was INF. check if op2 is NaN or INF*/ mgl@1371: + cp r6, 0x7ff mgl@1371: + brne __avr32_f64_mul_res_inf /*op1 was INF, op2 was neither NaN nor INF*/ mgl@1371: + /* op1 is INF, op2 is either NaN or INF*/ mgl@1371: + cp r9, 0 mgl@1371: + breq __avr32_f64_mul_res_inf /*op2 was also INF*/ mgl@1371: + rjmp __avr32_f64_mul_res_nan /*op2 was NaN*/ mgl@1371: + mgl@1371: +__avr32_f64_mul_op1_not_naninf: mgl@1371: + /* op1 was not NaN nor INF. Then op2 must be NaN or INF*/ mgl@1371: + cp r9, 0 mgl@1371: + breq __avr32_f64_mul_res_inf /*op2 was INF, return INF*/ mgl@1371: + rjmp __avr32_f64_mul_res_nan /*else return NaN*/ mgl@1371: + mgl@1371: +__avr32_f64_mul_res_subnormal:/* Multiply result was subnormal. */ mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + /* Check how much we must scale down the mantissa. */ mgl@1371: + neg r12 mgl@1371: + sub r12, -1 /* We do no longer have an implicit bit. */ mgl@1371: + satu r12 >> 0, 6 /* Saturate shift amount to max 63. */ mgl@1371: + cp.w r12, 32 mgl@1371: + brge 0f mgl@1371: + /* Shift amount <32 */ mgl@1371: + rsub r8, r12, 32 mgl@1371: + or r6, r7 mgl@1371: + lsr r7, r7, r12 mgl@1371: + lsl r9, r10, r8 mgl@1371: + or r7, r9 mgl@1371: + lsr r10, r10, r12 mgl@1371: + lsl r9, r11, r8 mgl@1371: + or r10, r9 mgl@1371: + lsr r11, r11, r12 mgl@1371: + rjmp 24b mgl@1371: +0: mgl@1371: + /* Shift amount >=32 */ mgl@1371: + rsub r8, r12, 32 mgl@1371: + moveq r9, 0 mgl@1371: + breq 0f mgl@1371: + lsl r9, r11, r8 mgl@1371: +0: mgl@1371: + or r6, r7 mgl@1371: + or r6, r6, r10 << 1 mgl@1371: + lsr r10, r10, r12 mgl@1371: + or r7, r9, r10 mgl@1371: + lsr r10, r11, r12 mgl@1371: + mov r11, 0 mgl@1371: + rjmp 24b mgl@1371: +#else mgl@1371: + /* Flush to zero for the fast version. */ mgl@1371: + mov r11, lr /*Get correct sign*/ mgl@1371: + andh r11, 0x8000, COH mgl@1371: + mov r10, 0 mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: +#endif mgl@1371: + mgl@1371: +__avr32_f64_mul_res_zero:/* Multiply result is zero. */ mgl@1371: + mov r11, lr /*Get correct sign*/ mgl@1371: + andh r11, 0x8000, COH mgl@1371: + mov r10, 0 mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + popm r4-r7, pc mgl@1371: +#else mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: +#endif mgl@1371: + mgl@1371: +__avr32_f64_mul_res_nan: /* Return NaN. */ mgl@1371: + mov r11, -1 mgl@1371: + mov r10, -1 mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + popm r4-r7, pc mgl@1371: +#else mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: +#endif mgl@1371: + mgl@1371: +__avr32_f64_mul_res_inf: /* Return INF. */ mgl@1371: + mov r11, 0xfff00000 mgl@1371: + bld lr, 31 mgl@1371: + bst r11, 31 mgl@1371: + mov r10, 0 mgl@1371: +#if defined(L_avr32_f64_mul) mgl@1371: + popm r4-r7, pc mgl@1371: +#else mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: +#endif mgl@1371: + mgl@1371: +__avr32_f64_mul_op1_zero: mgl@1371: + /* Get sign */ mgl@1371: + eor r11, r11, r9 mgl@1371: + andh r11, 0x8000, COH mgl@1371: + /* Check if op2 is Inf or NaN. */ mgl@1371: + bfextu r12, r9, 20, 11 mgl@1371: + cp.w r12, 0x7ff mgl@1371: + retne r12 /* Return 0.0 */ mgl@1371: + /* Return NaN */ mgl@1371: + mov r10, -1 mgl@1371: + mov r11, -1 mgl@1371: + ret r12 mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub) || defined(L_avr32_f64_addsub_fast) mgl@1371: + .align 2 mgl@1371: + mgl@1371: +__avr32_f64_sub_from_add: mgl@1371: + /* Switch sign on op2 */ mgl@1371: + eorh r9, 0x8000 mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub_fast) mgl@1371: + .global __avr32_f64_sub_fast mgl@1371: + .type __avr32_f64_sub_fast,@function mgl@1371: +__avr32_f64_sub_fast: mgl@1371: +#else mgl@1371: + .global __avr32_f64_sub mgl@1371: + .type __avr32_f64_sub,@function mgl@1371: +__avr32_f64_sub: mgl@1371: +#endif mgl@1371: + mgl@1371: + /* op1 in {r11,r10}*/ mgl@1371: + /* op2 in {r9,r8}*/ mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub_fast) mgl@1371: + /* If op2 is zero just return op1 */ mgl@1371: + or r12, r8, r9 << 1 mgl@1371: + reteq r12 mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Check signs */ mgl@1371: + eor r12, r11, r9 mgl@1371: + /* Different signs, use addition. */ mgl@1371: + brmi __avr32_f64_add_from_sub mgl@1371: + mgl@1371: + stm --sp, r5, r6, r7, lr mgl@1371: + mgl@1371: + /* Get sign of op1 into r12 */ mgl@1371: + mov r12, r11 mgl@1371: + andh r12, 0x8000, COH mgl@1371: + mgl@1371: + /* Remove sign from operands */ mgl@1371: + cbr r11, 31 mgl@1371: + cbr r9, 31 mgl@1371: + mgl@1371: + /* Put the largest number in [r11, r10] mgl@1371: + and the smallest number in [r9, r8] */ mgl@1371: + cp r10, r8 mgl@1371: + cpc r11, r9 mgl@1371: + brhs 1f /* Skip swap if operands already correctly ordered*/ mgl@1371: + /* Operands were not correctly ordered, swap them*/ mgl@1371: + mov r7, r11 mgl@1371: + mov r11, r9 mgl@1371: + mov r9, r7 mgl@1371: + mov r7, r10 mgl@1371: + mov r10, r8 mgl@1371: + mov r8, r7 mgl@1371: + eorh r12, 0x8000 /* Invert sign in r12*/ mgl@1371: +1: mgl@1371: + /* Unpack largest operand - opH */ mgl@1371: + /* exp: r7 */ mgl@1371: + /* sf: r11, r10 */ mgl@1371: + lsr r7, r11, 20 /* Extract exponent */ mgl@1371: + lsl r11, 11 /* Extract mantissa, leave room for implicit bit */ mgl@1371: + or r11, r11, r10>>21 mgl@1371: + lsl r10, 11 mgl@1371: + sbr r11, 31 /* Insert implicit bit */ mgl@1371: + mgl@1371: + mgl@1371: + /* Unpack smallest operand - opL */ mgl@1371: + /* exp: r6 */ mgl@1371: + /* sf: r9, r8 */ mgl@1371: + lsr r6, r9, 20 /* Extract exponent */ mgl@1371: + breq __avr32_f64_sub_opL_subnormal /* If either zero or subnormal */ mgl@1371: + lsl r9, 11 /* Extract mantissa, leave room for implicit bit */ mgl@1371: + or r9, r9, r8>>21 mgl@1371: + lsl r8, 11 mgl@1371: + sbr r9, 31 /* Insert implicit bit */ mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_sub_opL_subnormal_done: mgl@1371: + /* opH is NaN or Inf. */ mgl@1371: + cp.w r7, 0x7ff mgl@1371: + breq __avr32_f64_sub_opH_nan_or_inf mgl@1371: + mgl@1371: + /* Get shift amount to scale mantissa of op2. */ mgl@1371: + rsub r6, r7 mgl@1371: + breq __avr32_f64_sub_shift_done /* No need to shift, exponents are equal*/ mgl@1371: + mgl@1371: + /* Scale mantissa [r9, r8] with amount [r6]. mgl@1371: + Uses scratch registers [r5] and [lr]. mgl@1371: + In IEEE mode:Must not forget the sticky bits we intend to shift out. */ mgl@1371: + mgl@1371: + rsub r5,r6,32 /* get (32 - shift count) mgl@1371: + (if shift count > 32 we get a mgl@1371: + negative value, but that will mgl@1371: + work as well in the code below.) */ mgl@1371: + mgl@1371: + cp.w r6,32 /* handle shifts >= 32 separately */ mgl@1371: + brhs __avr32_f64_sub_longshift mgl@1371: + mgl@1371: + /* small (<32) shift amount, both words are part of the shift mgl@1371: + first remember whether part that is lost contains any 1 bits ... */ mgl@1371: + lsl lr,r8,r5 /* shift away bits that are part of mgl@1371: + final mantissa. only part that goes mgl@1371: + to lr are bits that will be lost */ mgl@1371: + mgl@1371: + /* ... and now to the actual shift */ mgl@1371: + lsl r5,r9,r5 /* get bits from msw destined for lsw*/ mgl@1371: + lsr r8,r8,r6 /* shift down lsw of mantissa */ mgl@1371: + lsr r9,r9,r6 /* shift down msw of mantissa */ mgl@1371: + or r8,r5 /* combine these bits with prepared lsw*/ mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + cp.w lr,0 /* if any '1' bit in part we lost ...*/ mgl@1371: + srne lr mgl@1371: + or r8, lr /* ... we need to set sticky bit*/ mgl@1371: +#endif mgl@1371: + mgl@1371: +__avr32_f64_sub_shift_done: mgl@1371: + /* Now subtract the mantissas. */ mgl@1371: + sub r10, r8 mgl@1371: + sbc r11, r11, r9 mgl@1371: + mgl@1371: + /* Normalize the exponent and mantissa pair stored in mgl@1371: + [r11,r10] and exponent in [r7]. Needs two scratch registers [r6] and [lr]. */ mgl@1371: + clz r6,r11 /* Check if we have zeros in high bits */ mgl@1371: + breq __avr32_f64_sub_longnormalize_done /* No need for scaling if no zeros in high bits */ mgl@1371: + brcs __avr32_f64_sub_longnormalize mgl@1371: + mgl@1371: + mgl@1371: + /* shift amount is smaller than 32, and involves both msw and lsw*/ mgl@1371: + rsub lr,r6,32 /* shift mantissa */ mgl@1371: + lsl r11,r11,r6 mgl@1371: + lsr lr,r10,lr mgl@1371: + or r11,lr mgl@1371: + lsl r10,r10,r6 mgl@1371: + mgl@1371: + sub r7,r6 /* adjust exponent */ mgl@1371: + brle __avr32_f64_sub_subnormal_result mgl@1371: +__avr32_f64_sub_longnormalize_done: mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + /* Insert the bits we will remove from the mantissa r9[31:21] */ mgl@1371: + lsl r9, r10, (32 - 11) mgl@1371: +#else mgl@1371: + /* Keep the last bit shifted out. */ mgl@1371: + bfextu r9, r10, 10, 1 mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Pack final result*/ mgl@1371: + /* Input: [r7]:exp, [r11, r10]:mant, [r12]:sign in MSB */ mgl@1371: + /* Result in [r11,r10] */ mgl@1371: + /* Insert mantissa */ mgl@1371: + lsr r10, 11 mgl@1371: + or r10, r10, r11<<21 mgl@1371: + lsr r11, 11 mgl@1371: + /* Insert exponent and sign bit*/ mgl@1371: + bfins r11, r7, 20, 11 mgl@1371: + or r11, r12 mgl@1371: + mgl@1371: + /* Round */ mgl@1371: +__avr32_f64_sub_round: mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + mov_imm r7, 0x80000000 mgl@1371: + bld r10, 0 mgl@1371: + subne r7, -1 mgl@1371: + mgl@1371: + cp.w r9, r7 mgl@1371: + srhs r9 mgl@1371: +#endif mgl@1371: + add r10, r9 mgl@1371: + acr r11 mgl@1371: + mgl@1371: + /* Return result in [r11,r10] */ mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_sub_opL_subnormal: mgl@1371: + /* Extract the of mantissa */ mgl@1371: + lsl r9, 11 /* Extract mantissa, leave room for implicit bit */ mgl@1371: + or r9, r9, r8>>21 mgl@1371: + lsl r8, 11 mgl@1371: + mgl@1371: + /* Set exponent to 1 if we do not have a zero. */ mgl@1371: + or lr, r9, r8 mgl@1371: + movne r6,1 mgl@1371: + mgl@1371: + /* Check if opH is also subnormal. If so, clear implicit bit in r11*/ mgl@1371: + rsub lr, r7, 0 mgl@1371: + moveq r7,1 mgl@1371: + bst r11, 31 mgl@1371: + mgl@1371: + /* Check if op1 is zero, if so set exponent to 0. */ mgl@1371: + or lr, r11, r10 mgl@1371: + moveq r7,0 mgl@1371: + mgl@1371: + rjmp __avr32_f64_sub_opL_subnormal_done mgl@1371: + mgl@1371: +__avr32_f64_sub_opH_nan_or_inf: mgl@1371: + /* Check if opH is NaN, if so return NaN */ mgl@1371: + cbr r11, 31 mgl@1371: + or lr, r11, r10 mgl@1371: + brne __avr32_f64_sub_return_nan mgl@1371: + mgl@1371: + /* opH is Inf. */ mgl@1371: + /* Check if opL is Inf. or NaN */ mgl@1371: + cp.w r6, 0x7ff mgl@1371: + breq __avr32_f64_sub_return_nan mgl@1371: + /* Return infinity with correct sign. */ mgl@1371: + or r11, r12, r7 << 20 mgl@1371: + ldm sp++, r5, r6, r7, pc/* opL not Inf or NaN, return opH */ mgl@1371: +__avr32_f64_sub_return_nan: mgl@1371: + mov r10, -1 /* Generate NaN in r11, r10 */ mgl@1371: + mov r11, -1 mgl@1371: + ldm sp++, r5, r6, r7, pc/* opL Inf or NaN, return NaN */ mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_sub_subnormal_result: mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + /* Check how much we must scale down the mantissa. */ mgl@1371: + neg r7 mgl@1371: + sub r7, -1 /* We do no longer have an implicit bit. */ mgl@1371: + satu r7 >> 0, 6 /* Saturate shift amount to max 63. */ mgl@1371: + cp.w r7, 32 mgl@1371: + brge 0f mgl@1371: + /* Shift amount <32 */ mgl@1371: + rsub r8, r7, 32 mgl@1371: + lsl r9, r10, r8 mgl@1371: + srne r6 mgl@1371: + lsr r10, r10, r7 mgl@1371: + or r10, r6 /* Sticky bit from the mgl@1371: + part that was shifted out. */ mgl@1371: + lsl r9, r11, r8 mgl@1371: + or r10, r10, r9 mgl@1371: + lsr r11, r10, r7 mgl@1371: + /* Set exponent */ mgl@1371: + mov r7, 0 mgl@1371: + rjmp __avr32_f64_sub_longnormalize_done mgl@1371: +0: mgl@1371: + /* Shift amount >=32 */ mgl@1371: + rsub r8, r7, 64 mgl@1371: + lsl r9, r11, r8 mgl@1371: + or r9, r10 mgl@1371: + srne r6 mgl@1371: + lsr r10, r11, r7 mgl@1371: + or r10, r6 /* Sticky bit from the mgl@1371: + part that was shifted out. */ mgl@1371: + mov r11, 0 mgl@1371: + /* Set exponent */ mgl@1371: + mov r7, 0 mgl@1371: + rjmp __avr32_f64_sub_longnormalize_done mgl@1371: +#else mgl@1371: + /* Just flush subnormals to zero. */ mgl@1371: + mov r10, 0 mgl@1371: + mov r11, 0 mgl@1371: +#endif mgl@1371: + ldm sp++, r5, r6, r7, pc mgl@1371: + mgl@1371: +__avr32_f64_sub_longshift: mgl@1371: + /* large (>=32) shift amount, only lsw will have bits left after shift. mgl@1371: + note that shift operations will use ((shift count=r6) mod 32) so mgl@1371: + we do not need to subtract 32 from shift count. */ mgl@1371: + /* Saturate the shift amount to 63. If the amount mgl@1371: + is any larger op2 is insignificant. */ mgl@1371: + satu r6 >> 0, 6 mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + /* first remember whether part that is lost contains any 1 bits ... */ mgl@1371: + moveq lr, r8 /* If shift amount is 32, no bits from msw are lost. */ mgl@1371: + breq 0f mgl@1371: + lsl lr,r9,r5 /* save all lost bits from msw */ mgl@1371: + or lr,r8 /* also save lost bits (all) from lsw mgl@1371: + now lr != 0 if we lose any bits */ mgl@1371: +#endif mgl@1371: +0: mgl@1371: + /* ... and now to the actual shift */ mgl@1371: + lsr r8,r9,r6 /* Move msw to lsw and shift. */ mgl@1371: + mov r9,0 /* clear msw */ mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + cp.w lr,0 /* if any '1' bit in part we lost ...*/ mgl@1371: + srne lr mgl@1371: + or r8, lr /* ... we need to set sticky bit*/ mgl@1371: +#endif mgl@1371: + rjmp __avr32_f64_sub_shift_done mgl@1371: + mgl@1371: +__avr32_f64_sub_longnormalize: mgl@1371: + /* shift amount is greater than 32 */ mgl@1371: + clz r6,r10 /* shift mantissa */ mgl@1371: + /* If the resulting mantissa is zero the result is mgl@1371: + zero so force exponent to zero. */ mgl@1371: + movcs r7, 0 mgl@1371: + movcs r6, 0 mgl@1371: + movcs r12, 0 /* Also clear sign bit. A zero result from subtraction mgl@1371: + always is +0.0 */ mgl@1371: + subcc r6,-32 mgl@1371: + lsl r11,r10,r6 mgl@1371: + mov r10,0 mgl@1371: + sub r7,r6 /* adjust exponent */ mgl@1371: + brle __avr32_f64_sub_subnormal_result mgl@1371: + rjmp __avr32_f64_sub_longnormalize_done mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + .align 2 mgl@1371: +__avr32_f64_add_from_sub: mgl@1371: + /* Switch sign on op2 */ mgl@1371: + eorh r9, 0x8000 mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub_fast) mgl@1371: + .global __avr32_f64_add_fast mgl@1371: + .type __avr32_f64_add_fast,@function mgl@1371: +__avr32_f64_add_fast: mgl@1371: +#else mgl@1371: + .global __avr32_f64_add mgl@1371: + .type __avr32_f64_add,@function mgl@1371: +__avr32_f64_add: mgl@1371: +#endif mgl@1371: + mgl@1371: + /* op1 in {r11,r10}*/ mgl@1371: + /* op2 in {r9,r8}*/ mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_addsub_fast) mgl@1371: + /* If op2 is zero just return op1 */ mgl@1371: + or r12, r8, r9 << 1 mgl@1371: + reteq r12 mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Check signs */ mgl@1371: + eor r12, r11, r9 mgl@1371: + /* Different signs, use subtraction. */ mgl@1371: + brmi __avr32_f64_sub_from_add mgl@1371: + mgl@1371: + stm --sp, r5, r6, r7, lr mgl@1371: + mgl@1371: + /* Get sign of op1 into r12 */ mgl@1371: + mov r12, r11 mgl@1371: + andh r12, 0x8000, COH mgl@1371: + mgl@1371: + /* Remove sign from operands */ mgl@1371: + cbr r11, 31 mgl@1371: + cbr r9, 31 mgl@1371: + mgl@1371: + /* Put the number with the largest exponent in [r11, r10] mgl@1371: + and the number with the smallest exponent in [r9, r8] */ mgl@1371: + cp r11, r9 mgl@1371: + brhs 1f /* Skip swap if operands already correctly ordered */ mgl@1371: + /* Operands were not correctly ordered, swap them */ mgl@1371: + mov r7, r11 mgl@1371: + mov r11, r9 mgl@1371: + mov r9, r7 mgl@1371: + mov r7, r10 mgl@1371: + mov r10, r8 mgl@1371: + mov r8, r7 mgl@1371: +1: mgl@1371: + mov lr, 0 /* Set sticky bits to zero */ mgl@1371: + /* Unpack largest operand - opH */ mgl@1371: + /* exp: r7 */ mgl@1371: + /* sf: r11, r10 */ mgl@1371: + bfextu R7, R11, 20, 11 /* Extract exponent */ mgl@1371: + bfextu r11, r11, 0, 20 /* Extract mantissa */ mgl@1371: + sbr r11, 20 /* Insert implicit bit */ mgl@1371: + mgl@1371: + /* Unpack smallest operand - opL */ mgl@1371: + /* exp: r6 */ mgl@1371: + /* sf: r9, r8 */ mgl@1371: + bfextu R6, R9, 20, 11 /* Extract exponent */ mgl@1371: + breq __avr32_f64_add_op2_subnormal mgl@1371: + bfextu r9, r9, 0, 20 /* Extract mantissa */ mgl@1371: + sbr r9, 20 /* Insert implicit bit */ mgl@1371: + mgl@1371: +2: mgl@1371: + /* opH is NaN or Inf. */ mgl@1371: + cp.w r7, 0x7ff mgl@1371: + breq __avr32_f64_add_opH_nan_or_inf mgl@1371: + mgl@1371: + /* Get shift amount to scale mantissa of op2. */ mgl@1371: + rsub r6, r7 mgl@1371: + breq __avr32_f64_add_shift_done /* No need to shift, exponents are equal*/ mgl@1371: + mgl@1371: + /* Scale mantissa [r9, r8] with amount [r6]. mgl@1371: + Uses scratch registers [r5] and [lr]. mgl@1371: + In IEEE mode:Must not forget the sticky bits we intend to shift out. */ mgl@1371: + rsub r5,r6,32 /* get (32 - shift count) mgl@1371: + (if shift count > 32 we get a mgl@1371: + negative value, but that will mgl@1371: + work as well in the code below.) */ mgl@1371: + mgl@1371: + cp.w r6,32 /* handle shifts >= 32 separately */ mgl@1371: + brhs __avr32_f64_add_longshift mgl@1371: + mgl@1371: + /* small (<32) shift amount, both words are part of the shift mgl@1371: + first remember whether part that is lost contains any 1 bits ... */ mgl@1371: + lsl lr,r8,r5 /* shift away bits that are part of mgl@1371: + final mantissa. only part that goes mgl@1371: + to lr are bits that will be lost */ mgl@1371: + mgl@1371: + /* ... and now to the actual shift */ mgl@1371: + lsl r5,r9,r5 /* get bits from msw destined for lsw*/ mgl@1371: + lsr r8,r8,r6 /* shift down lsw of mantissa */ mgl@1371: + lsr r9,r9,r6 /* shift down msw of mantissa */ mgl@1371: + or r8,r5 /* combine these bits with prepared lsw*/ mgl@1371: + mgl@1371: +__avr32_f64_add_shift_done: mgl@1371: + /* Now add the mantissas. */ mgl@1371: + add r10, r8 mgl@1371: + adc r11, r11, r9 mgl@1371: + mgl@1371: + /* Check if we overflowed. */ mgl@1371: + bld r11, 21 mgl@1371: + breq __avr32_f64_add_res_of: mgl@1371: + mgl@1371: +__avr32_f64_add_res_of_done: mgl@1371: + mgl@1371: + /* Pack final result*/ mgl@1371: + /* Input: [r7]:exp, [r11, r10]:mant, [r12]:sign in MSB */ mgl@1371: + /* Result in [r11,r10] */ mgl@1371: + /* Insert exponent and sign bit*/ mgl@1371: + bfins r11, r7, 20, 11 mgl@1371: + or r11, r12 mgl@1371: + mgl@1371: + /* Round */ mgl@1371: +__avr32_f64_add_round: mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + bfextu r12, r10, 0, 1 /* Extract parity bit.*/ mgl@1371: + or lr, r12 /* or it together with the sticky bits. */ mgl@1371: + eorh lr, 0x8000 /* Toggle round bit. */ mgl@1371: + /* We should now round up by adding one for the following cases: mgl@1371: + mgl@1371: + halfway sticky|parity round-up mgl@1371: + 0 x no mgl@1371: + 1 0 no mgl@1371: + 1 1 yes mgl@1371: + mgl@1371: + Since we have inverted the halfway bit we can use the satu instruction mgl@1371: + by saturating to 1 bit to implement this. mgl@1371: + */ mgl@1371: + satu lr >> 0, 1 mgl@1371: +#else mgl@1371: + lsr lr, 31 mgl@1371: +#endif mgl@1371: + add r10, lr mgl@1371: + acr r11 mgl@1371: + mgl@1371: + /* Return result in [r11,r10] */ mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_add_opH_nan_or_inf: mgl@1371: + /* Check if opH is NaN, if so return NaN */ mgl@1371: + cbr r11, 20 mgl@1371: + or lr, r11, r10 mgl@1371: + brne __avr32_f64_add_return_nan mgl@1371: + mgl@1371: + /* opH is Inf. */ mgl@1371: + /* Check if opL is Inf. or NaN */ mgl@1371: + cp.w r6, 0x7ff mgl@1371: + breq __avr32_f64_add_opL_nan_or_inf mgl@1371: + ldm sp++, r5, r6, r7, pc/* opL not Inf or NaN, return opH */ mgl@1371: +__avr32_f64_add_opL_nan_or_inf: mgl@1371: + cbr r9, 20 mgl@1371: + or lr, r9, r8 mgl@1371: + brne __avr32_f64_add_return_nan mgl@1371: + mov r10, 0 /* Generate Inf in r11, r10 */ mgl@1371: + mov_imm r11, 0x7ff00000 mgl@1371: + ldm sp++, r5, r6, r7, pc/* opL Inf, return Inf */ mgl@1371: +__avr32_f64_add_return_nan: mgl@1371: + mov r10, -1 /* Generate NaN in r11, r10 */ mgl@1371: + mov r11, -1 mgl@1371: + ldm sp++, r5, r6, r7, pc/* opL Inf or NaN, return NaN */ mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_add_longshift: mgl@1371: + /* large (>=32) shift amount, only lsw will have bits left after shift. mgl@1371: + note that shift operations will use ((shift count=r6) mod 32) so mgl@1371: + we do not need to subtract 32 from shift count. */ mgl@1371: + /* Saturate the shift amount to 63. If the amount mgl@1371: + is any larger op2 is insignificant. */ mgl@1371: + satu r6 >> 0, 6 mgl@1371: + /* If shift amount is 32 there are no bits from the msw that are lost. */ mgl@1371: + moveq lr, r8 mgl@1371: + breq 0f mgl@1371: + /* first remember whether part that is lost contains any 1 bits ... */ mgl@1371: + lsl lr,r9,r5 /* save all lost bits from msw */ mgl@1371: +#if defined(L_avr32_f64_addsub) mgl@1371: + cp.w r8, 0 mgl@1371: + srne r8 mgl@1371: + or lr,r8 /* also save lost bits (all) from lsw mgl@1371: + now lr != 0 if we lose any bits */ mgl@1371: +#endif mgl@1371: +0: mgl@1371: + /* ... and now to the actual shift */ mgl@1371: + lsr r8,r9,r6 /* msw -> lsw and make rest of shift inside lsw*/ mgl@1371: + mov r9,0 /* clear msw */ mgl@1371: + rjmp __avr32_f64_add_shift_done mgl@1371: + mgl@1371: +__avr32_f64_add_res_of: mgl@1371: + /* We overflowed. Scale down mantissa by shifting right one position. */ mgl@1371: + or lr, lr, lr << 1 /* Remember stickybits*/ mgl@1371: + lsr r11, 1 mgl@1371: + ror r10 mgl@1371: + ror lr mgl@1371: + sub r7, -1 /* Increment exponent */ mgl@1371: + mgl@1371: + /* Clear mantissa to set result to Inf if the exponent is 255. */ mgl@1371: + cp.w r7, 0x7ff mgl@1371: + moveq r10, 0 mgl@1371: + moveq r11, 0 mgl@1371: + moveq lr, 0 mgl@1371: + rjmp __avr32_f64_add_res_of_done mgl@1371: + mgl@1371: +__avr32_f64_add_op2_subnormal: mgl@1371: + /* Set epxponent to 1 */ mgl@1371: + mov r6, 1 mgl@1371: + mgl@1371: + /* Check if op2 is also subnormal. */ mgl@1371: + cp.w r7, 0 mgl@1371: + brne 2b mgl@1371: + mgl@1371: + cbr r11, 20 mgl@1371: + /* Both operands are subnormal. Just addd the mantissas mgl@1371: + and the exponent will automatically be set to 1 if mgl@1371: + we overflow into a normal number. */ mgl@1371: + add r10, r8 mgl@1371: + adc r11, r11, r9 mgl@1371: + mgl@1371: + /* Add sign bit */ mgl@1371: + or r11, r12 mgl@1371: + mgl@1371: + /* Return result in [r11,r10] */ mgl@1371: + ldm sp++, r5, r6, r7,pc mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_to_u32 mgl@1371: + /* This goes into L_fixdfsi */ mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_to_s32 mgl@1371: + .global __avr32_f64_to_u32 mgl@1371: + .type __avr32_f64_to_u32,@function mgl@1371: +__avr32_f64_to_u32: mgl@1371: + cp.w r11, 0 mgl@1371: + retmi 0 /* Negative returns 0 */ mgl@1371: + mgl@1371: + /* Fallthrough to df to signed si conversion */ mgl@1371: + .global __avr32_f64_to_s32 mgl@1371: + .type __avr32_f64_to_s32,@function mgl@1371: +__avr32_f64_to_s32: mgl@1371: + lsl r12,r11,1 mgl@1371: + lsr r12,21 /* extract exponent*/ mgl@1371: + sub r12,1023 /* convert to unbiased exponent.*/ mgl@1371: + retlo 0 /* too small exponent implies zero. */ mgl@1371: + mgl@1371: +1: mgl@1371: + rsub r12,r12,31 /* shift count = 31 - exponent */ mgl@1371: + mov r9,r11 /* save sign for later...*/ mgl@1371: + lsl r11,11 /* remove exponent and sign*/ mgl@1371: + sbr r11,31 /* add implicit bit*/ mgl@1371: + or r11,r11,r10>>21 /* get rest of bits from lsw of double */ mgl@1371: + lsr r11,r11,r12 /* shift down mantissa to final place */ mgl@1371: + lsl r9,1 /* sign -> carry */ mgl@1371: + retcc r11 /* if positive, we are done */ mgl@1371: + neg r11 /* if negative float, negate result */ mgl@1371: + ret r11 mgl@1371: + mgl@1371: +#endif /* L_fixdfsi*/ mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_to_u64 mgl@1371: + /* Actual function is in L_fixdfdi */ mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_to_s64 mgl@1371: + .global __avr32_f64_to_u64 mgl@1371: + .type __avr32_f64_to_u64,@function mgl@1371: +__avr32_f64_to_u64: mgl@1371: + cp.w r11,0 mgl@1371: + /* Negative numbers return zero */ mgl@1371: + movmi r10, 0 mgl@1371: + movmi r11, 0 mgl@1371: + retmi r11 mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + /* Fallthrough */ mgl@1371: + .global __avr32_f64_to_s64 mgl@1371: + .type __avr32_f64_to_s64,@function mgl@1371: +__avr32_f64_to_s64: mgl@1371: + lsl r9,r11,1 mgl@1371: + lsr r9,21 /* get exponent*/ mgl@1371: + sub r9,1023 /* convert to correct range*/ mgl@1371: + /* Return zero if exponent to small */ mgl@1371: + movlo r10, 0 mgl@1371: + movlo r11, 0 mgl@1371: + retlo r11 mgl@1371: + mgl@1371: + mov r8,r11 /* save sign for later...*/ mgl@1371: +1: mgl@1371: + lsl r11,11 /* remove exponent */ mgl@1371: + sbr r11,31 /* add implicit bit*/ mgl@1371: + or r11,r11,r10>>21 /* get rest of bits from lsw of double*/ mgl@1371: + lsl r10,11 /* align lsw correctly as well */ mgl@1371: + rsub r9,r9,63 /* shift count = 63 - exponent */ mgl@1371: + breq 1f mgl@1371: + mgl@1371: + cp.w r9,32 /* is shift count more than one reg? */ mgl@1371: + brhs 0f mgl@1371: + mgl@1371: + mov r12,r11 /* save msw */ mgl@1371: + lsr r10,r10,r9 /* small shift count, shift down lsw */ mgl@1371: + lsr r11,r11,r9 /* small shift count, shift down msw */ mgl@1371: + rsub r9,r9,32 /* get 32-size of shifted out tail */ mgl@1371: + lsl r12,r12,r9 /* align part to move from msw to lsw */ mgl@1371: + or r10,r12 /* combine to get new lsw */ mgl@1371: + rjmp 1f mgl@1371: + mgl@1371: +0: mgl@1371: + lsr r10,r11,r9 /* large shift count,only lsw get bits mgl@1371: + note that shift count is modulo 32*/ mgl@1371: + mov r11,0 /* msw will be 0 */ mgl@1371: + mgl@1371: +1: mgl@1371: + lsl r8,1 /* sign -> carry */ mgl@1371: + retcc r11 /* if positive, we are done */ mgl@1371: + mgl@1371: + neg r11 /* if negative float, negate result */ mgl@1371: + neg r10 mgl@1371: + scr r11 mgl@1371: + ret r11 mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_u32_to_f64 mgl@1371: + /* Code located in L_floatsidf */ mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_s32_to_f64 mgl@1371: + .global __avr32_u32_to_f64 mgl@1371: + .type __avr32_u32_to_f64,@function mgl@1371: +__avr32_u32_to_f64: mgl@1371: + sub r11, r12, 0 /* Move to r11 and force Z flag to be updated */ mgl@1371: + mov r12, 0 /* always positive */ mgl@1371: + rjmp 0f /* Jump to common code for floatsidf */ mgl@1371: + mgl@1371: + .global __avr32_s32_to_f64 mgl@1371: + .type __avr32_s32_to_f64,@function mgl@1371: +__avr32_s32_to_f64: mgl@1371: + mov r11, r12 /* Keep original value in r12 for sign */ mgl@1371: + abs r11 /* Absolute value if r12 */ mgl@1371: +0: mgl@1371: + mov r10,0 /* let remaining bits be zero */ mgl@1371: + reteq r11 /* zero long will return zero float */ mgl@1371: + mgl@1371: + pushm lr mgl@1371: + mov r9,31+1023 /* set exponent */ mgl@1371: + mgl@1371: + normalize_df r9 /*exp*/, r10, r11 /* mantissa */, r8, lr /* scratch */ mgl@1371: + mgl@1371: + /* Check if a subnormal result was created */ mgl@1371: + cp.w r9, 0 mgl@1371: + brgt 0f mgl@1371: + mgl@1371: + adjust_subnormal_df r9 /* exp */, r10, r11 /* Mantissa */, r12 /*sign*/, r8, lr /* scratch */ mgl@1371: + popm pc mgl@1371: +0: mgl@1371: + mgl@1371: + /* Round result */ mgl@1371: + round_df r9 /*exp*/, r10, r11 /* Mantissa */, r8 /*scratch*/ mgl@1371: + cp.w r9,0x7ff mgl@1371: + brlt 0f mgl@1371: + /*Return infinity */ mgl@1371: + mov r10, 0 mgl@1371: + mov_imm r11, 0xffe00000 mgl@1371: + rjmp __floatsidf_return_op1 mgl@1371: + mgl@1371: +0: mgl@1371: + mgl@1371: + /* Pack */ mgl@1371: + pack_df r9 /*exp*/, r10, r11 /* mantissa */, r10, r11 /* Output df number*/ mgl@1371: +__floatsidf_return_op1: mgl@1371: + lsl r12,1 /* shift in sign bit */ mgl@1371: + ror r11 mgl@1371: + mgl@1371: + popm pc mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#ifdef L_avr32_f32_cmp_eq mgl@1371: + .global __avr32_f32_cmp_eq mgl@1371: + .type __avr32_f32_cmp_eq,@function mgl@1371: +__avr32_f32_cmp_eq: mgl@1371: + cp.w r12, r11 mgl@1371: + breq 0f mgl@1371: + /* If not equal check for +/-0 */ mgl@1371: + /* Or together the two values and shift out the sign bit. mgl@1371: + If the result is zero, then the two values are both zero. */ mgl@1371: + or r12, r11 mgl@1371: + lsl r12, 1 mgl@1371: + reteq 1 mgl@1371: + ret 0 mgl@1371: +0: mgl@1371: + /* Numbers were equal. Check for NaN or Inf */ mgl@1371: + mov_imm r11, 0xff000000 mgl@1371: + lsl r12, 1 mgl@1371: + cp.w r12, r11 mgl@1371: + retls 1 /* 0 if NaN, 1 otherwise */ mgl@1371: + ret 0 mgl@1371: +#endif mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_cmp_ge) || defined(L_avr32_f32_cmp_lt) mgl@1371: +#ifdef L_avr32_f32_cmp_ge mgl@1371: + .global __avr32_f32_cmp_ge mgl@1371: + .type __avr32_f32_cmp_ge,@function mgl@1371: +__avr32_f32_cmp_ge: mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f32_cmp_lt mgl@1371: + .global __avr32_f32_cmp_lt mgl@1371: + .type __avr32_f32_cmp_lt,@function mgl@1371: +__avr32_f32_cmp_lt: mgl@1371: +#endif mgl@1371: + lsl r10, r12, 1 /* Remove sign bits */ mgl@1371: + lsl r9, r11, 1 mgl@1371: + subfeq r10, 0 mgl@1371: +#ifdef L_avr32_f32_cmp_ge mgl@1371: + reteq 1 /* Both number are zero. Return true. */ mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f32_cmp_lt mgl@1371: + reteq 0 /* Both number are zero. Return false. */ mgl@1371: +#endif mgl@1371: + mov_imm r8, 0xff000000 mgl@1371: + cp.w r10, r8 mgl@1371: + rethi 0 /* Op0 is NaN */ mgl@1371: + cp.w r9, r8 mgl@1371: + rethi 0 /* Op1 is Nan */ mgl@1371: + mgl@1371: + eor r8, r11, r12 mgl@1371: + bld r12, 31 mgl@1371: +#ifdef L_avr32_f32_cmp_ge mgl@1371: + srcc r8 /* Set result to true if op0 is positive*/ mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f32_cmp_lt mgl@1371: + srcs r8 /* Set result to true if op0 is negative*/ mgl@1371: +#endif mgl@1371: + retmi r8 /* Return if signs are different */ mgl@1371: + brcs 0f /* Both signs negative? */ mgl@1371: + mgl@1371: + /* Both signs positive */ mgl@1371: + cp.w r12, r11 mgl@1371: +#ifdef L_avr32_f32_cmp_ge mgl@1371: + reths 1 mgl@1371: + retlo 0 mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f32_cmp_lt mgl@1371: + reths 0 mgl@1371: + retlo 1 mgl@1371: +#endif mgl@1371: +0: mgl@1371: + /* Both signs negative */ mgl@1371: + cp.w r11, r12 mgl@1371: +#ifdef L_avr32_f32_cmp_ge mgl@1371: + reths 1 mgl@1371: + retlo 0 mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f32_cmp_lt mgl@1371: + reths 0 mgl@1371: + retlo 1 mgl@1371: +#endif mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_cmp_eq mgl@1371: + .global __avr32_f64_cmp_eq mgl@1371: + .type __avr32_f64_cmp_eq,@function mgl@1371: +__avr32_f64_cmp_eq: mgl@1371: + cp.w r10,r8 mgl@1371: + cpc r11,r9 mgl@1371: + breq 0f mgl@1371: + mgl@1371: + /* Args were not equal*/ mgl@1371: + /* Both args could be zero with different sign bits */ mgl@1371: + lsl r11,1 /* get rid of sign bits */ mgl@1371: + lsl r9,1 mgl@1371: + or r11,r10 /* Check if all bits are zero */ mgl@1371: + or r11,r9 mgl@1371: + or r11,r8 mgl@1371: + reteq 1 /* If all zeros the arguments are equal mgl@1371: + so return 1 else return 0 */ mgl@1371: + ret 0 mgl@1371: +0: mgl@1371: + /* check for NaN */ mgl@1371: + lsl r11,1 mgl@1371: + mov_imm r12, 0xffe00000 mgl@1371: + cp.w r10,0 mgl@1371: + cpc r11,r12 /* check if nan or inf */ mgl@1371: + retls 1 /* If Arg is NaN return 0 else 1*/ mgl@1371: + ret 0 /* Return */ mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_cmp_ge) || defined(L_avr32_f64_cmp_lt) mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_cmp_ge mgl@1371: + .global __avr32_f64_cmp_ge mgl@1371: + .type __avr32_f64_cmp_ge,@function mgl@1371: +__avr32_f64_cmp_ge: mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f64_cmp_lt mgl@1371: + .global __avr32_f64_cmp_lt mgl@1371: + .type __avr32_f64_cmp_lt,@function mgl@1371: +__avr32_f64_cmp_lt: mgl@1371: +#endif mgl@1371: + mgl@1371: + /* compare magnitude of op1 and op2 */ mgl@1371: + lsl r11,1 /* Remove sign bit of op1 */ mgl@1371: + srcs r12 /* Sign op1 to lsb of r12*/ mgl@1371: + subfeq r10, 0 mgl@1371: + breq 3f /* op1 zero */ mgl@1371: + lsl r9,1 /* Remove sign bit of op2 */ mgl@1371: + rol r12 /* Sign op2 to lsb of lr, sign bit op1 bit 1 of r12*/ mgl@1371: + mgl@1371: + mgl@1371: + /* Check for Nan */ mgl@1371: + pushm lr mgl@1371: + mov_imm lr, 0xffe00000 mgl@1371: + cp.w r10,0 mgl@1371: + cpc r11,lr mgl@1371: + brhi 0f /* We have NaN */ mgl@1371: + cp.w r8,0 mgl@1371: + cpc r9,lr mgl@1371: + brhi 0f /* We have NaN */ mgl@1371: + popm lr mgl@1371: + mgl@1371: + cp.w r12,3 /* both operands negative ?*/ mgl@1371: + breq 1f mgl@1371: + mgl@1371: + cp.w r12,1 /* both operands positive? */ mgl@1371: + brlo 2f mgl@1371: + mgl@1371: + /* Different signs. If sign of op1 is negative the difference mgl@1371: + between op1 and op2 will always be negative, and if op1 is mgl@1371: + positive the difference will always be positive */ mgl@1371: +#ifdef L_avr32_f64_cmp_ge mgl@1371: + reteq 1 mgl@1371: + retne 0 mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f64_cmp_lt mgl@1371: + reteq 0 mgl@1371: + retne 1 mgl@1371: +#endif mgl@1371: + mgl@1371: +2: mgl@1371: + /* Both operands positive. Just compute the difference */ mgl@1371: + cp.w r10,r8 mgl@1371: + cpc r11,r9 mgl@1371: +#ifdef L_avr32_f64_cmp_ge mgl@1371: + reths 1 mgl@1371: + retlo 0 mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f64_cmp_lt mgl@1371: + reths 0 mgl@1371: + retlo 1 mgl@1371: +#endif mgl@1371: + mgl@1371: +1: mgl@1371: + /* Both operands negative. Compute the difference with operands switched */ mgl@1371: + cp r8,r10 mgl@1371: + cpc r9,r11 mgl@1371: +#ifdef L_avr32_f64_cmp_ge mgl@1371: + reths 1 mgl@1371: + retlo 0 mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f64_cmp_lt mgl@1371: + reths 0 mgl@1371: + retlo 1 mgl@1371: +#endif mgl@1371: + mgl@1371: +0: mgl@1371: + popm pc, r12=0 mgl@1371: +#endif mgl@1371: + mgl@1371: +3: mgl@1371: + lsl r9,1 /* Remove sign bit of op1 */ mgl@1371: +#ifdef L_avr32_f64_cmp_ge mgl@1371: + srcs r12 /* If op2 is negative then op1 >= op2. */ mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f64_cmp_lt mgl@1371: + srcc r12 /* If op2 is positve then op1 <= op2. */ mgl@1371: +#endif mgl@1371: + subfeq r8, 0 mgl@1371: +#ifdef L_avr32_f64_cmp_ge mgl@1371: + reteq 1 /* Both operands are zero. Return true. */ mgl@1371: +#endif mgl@1371: +#ifdef L_avr32_f64_cmp_lt mgl@1371: + reteq 0 /* Both operands are zero. Return false. */ mgl@1371: +#endif mgl@1371: + ret r12 mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_div) || defined(L_avr32_f64_div_fast) mgl@1371: + .align 2 mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_div_fast) mgl@1371: + .global __avr32_f64_div_fast mgl@1371: + .type __avr32_f64_div_fast,@function mgl@1371: +__avr32_f64_div_fast: mgl@1371: +#else mgl@1371: + .global __avr32_f64_div mgl@1371: + .type __avr32_f64_div,@function mgl@1371: +__avr32_f64_div: mgl@1371: +#endif mgl@1371: + stm --sp, r0, r1, r2, r3, r4, r5, r6, r7,lr mgl@1371: + /* op1 in {r11,r10}*/ mgl@1371: + /* op2 in {r9,r8}*/ mgl@1371: + eor lr, r11, r9 /* MSB(lr) = Sign(op1) ^ Sign(op2) */ mgl@1371: + mgl@1371: + mgl@1371: + /* Unpack op1 to 2.62 format*/ mgl@1371: + /* exp: r7 */ mgl@1371: + /* sf: r11, r10 */ mgl@1371: + lsr r7, r11, 20 /* Extract exponent */ mgl@1371: + mgl@1371: + lsl r11, 9 /* Extract mantissa, leave room for implicit bit */ mgl@1371: + or r11, r11, r10>>23 mgl@1371: + lsl r10, 9 mgl@1371: + sbr r11, 29 /* Insert implicit bit */ mgl@1371: + andh r11, 0x3fff /*Mask last part of exponent since we use 2.62 format*/ mgl@1371: + mgl@1371: + cbr r7, 11 /* Clear sign bit */ mgl@1371: + /* Check if normalization is needed */ mgl@1371: + breq 11f /*If number is subnormal, normalize it */ mgl@1371: +22: mgl@1371: + cp r7, 0x7ff mgl@1371: + brge 2f /* Check op1 for NaN or Inf */ mgl@1371: + mgl@1371: + /* Unpack op2 to 2.62 format*/ mgl@1371: + /* exp: r6 */ mgl@1371: + /* sf: r9, r8 */ mgl@1371: + lsr r6, r9, 20 /* Extract exponent */ mgl@1371: + mgl@1371: + lsl r9, 9 /* Extract mantissa, leave room for implicit bit */ mgl@1371: + or r9, r9, r8>>23 mgl@1371: + lsl r8, 9 mgl@1371: + sbr r9, 29 /* Insert implicit bit */ mgl@1371: + andh r9, 0x3fff /*Mask last part of exponent since we use 2.62 format*/ mgl@1371: + mgl@1371: + cbr r6, 11 /* Clear sign bit */ mgl@1371: + /* Check if normalization is needed */ mgl@1371: + breq 13f /*If number is subnormal, normalize it */ mgl@1371: +23: mgl@1371: + cp r6, 0x7ff mgl@1371: + brge 3f /* Check op2 for NaN or Inf */ mgl@1371: + mgl@1371: + /* Calculate new exponent */ mgl@1371: + sub r7, r6 mgl@1371: + sub r7,-1023 mgl@1371: + mgl@1371: + /* Divide */ mgl@1371: + /* Approximating 1/d with the following recurrence: */ mgl@1371: + /* R[j+1] = R[j]*(2-R[j]*d) */ mgl@1371: + /* Using 2.62 format */ mgl@1371: + /* TWO: r12 */ mgl@1371: + /* d = op2 = divisor (2.62 format): r9,r8 */ mgl@1371: + /* Multiply result : r5, r4 */ mgl@1371: + /* Initial guess : r3, r2 */ mgl@1371: + /* New approximations : r3, r2 */ mgl@1371: + /* op1 = Dividend (2.62 format) : r11, r10 */ mgl@1371: + mgl@1371: + mov_imm r12, 0x80000000 mgl@1371: + mgl@1371: + /* Load initial guess, using look-up table */ mgl@1371: + /* Initial guess is of format 01.XY, where XY is constructed as follows: */ mgl@1371: + /* Let d be of following format: 00.1xy....., then XY=~xy */ mgl@1371: + /* For d=00.100 = 0,5 -> initial guess=01.11 = 1,75 */ mgl@1371: + /* For d=00.101 = 0,625 -> initial guess=01.11 = 1,5 */ mgl@1371: + /* For d=00.110 = 0,75 -> initial guess=01.11 = 1,25 */ mgl@1371: + /* For d=00.111 = 0,875 -> initial guess=01.11 = 1,0 */ mgl@1371: + /* r2 is also part of the reg pair forming initial guess, but it*/ mgl@1371: + /* is kept uninitialized to save one cycle since it has so low significance*/ mgl@1371: + mgl@1371: + lsr r3, r12, 1 mgl@1371: + bfextu r4, r9, 27, 2 mgl@1371: + com r4 mgl@1371: + bfins r3, r4, 28, 2 mgl@1371: + mgl@1371: + /* First approximation */ mgl@1371: + /* Approximating to 32 bits */ mgl@1371: + /* r5 = R[j]*d */ mgl@1371: + mulu.d r4, r3, r9 mgl@1371: + /* r5 = 2-R[j]*d */ mgl@1371: + sub r5, r12, r5<<2 mgl@1371: + /* r3 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r4, r3, r5 mgl@1371: + lsl r3, r5, 2 mgl@1371: + mgl@1371: + /* Second approximation */ mgl@1371: + /* Approximating to 32 bits */ mgl@1371: + /* r5 = R[j]*d */ mgl@1371: + mulu.d r4, r3, r9 mgl@1371: + /* r5 = 2-R[j]*d */ mgl@1371: + sub r5, r12, r5<<2 mgl@1371: + /* r3 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r4, r3, r5 mgl@1371: + lsl r3, r5, 2 mgl@1371: + mgl@1371: + /* Third approximation */ mgl@1371: + /* Approximating to 32 bits */ mgl@1371: + /* r5 = R[j]*d */ mgl@1371: + mulu.d r4, r3, r9 mgl@1371: + /* r5 = 2-R[j]*d */ mgl@1371: + sub r5, r12, r5<<2 mgl@1371: + /* r3 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r4, r3, r5 mgl@1371: + lsl r3, r5, 2 mgl@1371: + mgl@1371: + /* Fourth approximation */ mgl@1371: + /* Approximating to 64 bits */ mgl@1371: + /* r5,r4 = R[j]*d */ mgl@1371: + mul_approx_df r3 /*ah*/, r2 /*al*/, r9 /*bh*/, r8 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/ mgl@1371: + lsl r5, 2 mgl@1371: + or r5, r5, r4>>30 mgl@1371: + lsl r4, 2 mgl@1371: + /* r5,r4 = 2-R[j]*d */ mgl@1371: + neg r4 mgl@1371: + sbc r5, r12, r5 mgl@1371: + /* r3,r2 = R[j]*(2-R[j]*d) */ mgl@1371: + mul_approx_df r3 /*ah*/, r2 /*al*/, r5 /*bh*/, r4 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/ mgl@1371: + lsl r3, r5, 2 mgl@1371: + or r3, r3, r4>>30 mgl@1371: + lsl r2, r4, 2 mgl@1371: + mgl@1371: + mgl@1371: + /* Fifth approximation */ mgl@1371: + /* Approximating to 64 bits */ mgl@1371: + /* r5,r4 = R[j]*d */ mgl@1371: + mul_approx_df r3 /*ah*/, r2 /*al*/, r9 /*bh*/, r8 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/ mgl@1371: + lsl r5, 2 mgl@1371: + or r5, r5, r4>>30 mgl@1371: + lsl r4, 2 mgl@1371: + /* r5,r4 = 2-R[j]*d */ mgl@1371: + neg r4 mgl@1371: + sbc r5, r12, r5 mgl@1371: + /* r3,r2 = R[j]*(2-R[j]*d) */ mgl@1371: + mul_approx_df r3 /*ah*/, r2 /*al*/, r5 /*bh*/, r4 /*bl*/, r5 /*rh*/, r4 /*rl*/, r1 /*sh*/, r0 /*sl*/ mgl@1371: + lsl r3, r5, 2 mgl@1371: + or r3, r3, r4>>30 mgl@1371: + lsl r2, r4, 2 mgl@1371: + mgl@1371: + mgl@1371: + /* Multiply with dividend to get quotient */ mgl@1371: + mul_approx_df r3 /*ah*/, r2 /*al*/, r11 /*bh*/, r10 /*bl*/, r3 /*rh*/, r2 /*rl*/, r1 /*sh*/, r0 /*sl*/ mgl@1371: + mgl@1371: + mgl@1371: + /* To increase speed, this result is not corrected before final rounding.*/ mgl@1371: + /* This may give a difference to IEEE compliant code of 1 ULP.*/ mgl@1371: + mgl@1371: + mgl@1371: + /* Adjust exponent and mantissa */ mgl@1371: + /* r7:exp, [r3, r2]:mant, [r5, r4]:scratch*/ mgl@1371: + /* Mantissa may be of the format 0.xxxx or 1.xxxx. */ mgl@1371: + /* In the first case, shift one pos to left.*/ mgl@1371: + bld r3, 31-3 mgl@1371: + breq 0f mgl@1371: + lsl r2, 1 mgl@1371: + rol r3 mgl@1371: + sub r7, 1 mgl@1371: +#if defined(L_avr32_f64_div) mgl@1371: + /* We must scale down the dividend to 5.59 format. */ mgl@1371: + lsr r10, 3 mgl@1371: + or r10, r10, r11 << 29 mgl@1371: + lsr r11, 3 mgl@1371: + rjmp 1f mgl@1371: +#endif mgl@1371: +0: mgl@1371: +#if defined(L_avr32_f64_div) mgl@1371: + /* We must scale down the dividend to 6.58 format. */ mgl@1371: + lsr r10, 4 mgl@1371: + or r10, r10, r11 << 28 mgl@1371: + lsr r11, 4 mgl@1371: +1: mgl@1371: +#endif mgl@1371: + cp r7, 0 mgl@1371: + brle __avr32_f64_div_res_subnormal /* Result was subnormal. */ mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f64_div) mgl@1371: + /* In order to round correctly we calculate the remainder: mgl@1371: + Remainder = dividend[11:r10] - divisor[r9:r8]*quotient[r3:r2] mgl@1371: + for the case when the quotient is halfway between the round-up mgl@1371: + value and the round down value. If the remainder then is negative mgl@1371: + it means that the quotient was to big and that it should not be mgl@1371: + rounded up, if the remainder is positive the quotient was to small mgl@1371: + and we need to round up. If the remainder is zero it means that the mgl@1371: + quotient is exact but since we need to remove the guard bit we should mgl@1371: + round to even. */ mgl@1371: + mgl@1371: + /* Truncate and add guard bit. */ mgl@1371: + andl r2, 0xff00 mgl@1371: + orl r2, 0x0080 mgl@1371: + mgl@1371: + mgl@1371: + /* Now do the multiplication. The quotient has the format 4.60 mgl@1371: + while the divisor has the format 2.62 which gives a result mgl@1371: + of 6.58 */ mgl@1371: + mulu.d r0, r3, r8 mgl@1371: + macu.d r0, r2, r9 mgl@1371: + mulu.d r4, r2, r8 mgl@1371: + mulu.d r8, r3, r9 mgl@1371: + add r5, r0 mgl@1371: + adc r8, r8, r1 mgl@1371: + acr r9 mgl@1371: + mgl@1371: + mgl@1371: + /* Check if remainder is positive, negative or equal. */ mgl@1371: + bfextu r12, r2, 8, 1 /* Get parity bit into bit 0 of r0 */ mgl@1371: + cp r4, 0 mgl@1371: + cpc r5 mgl@1371: +__avr32_f64_div_round_subnormal: mgl@1371: + cpc r8, r10 mgl@1371: + cpc r9, r11 mgl@1371: + srlo r6 /* Remainder positive: we need to round up.*/ mgl@1371: + moveq r6, r12 /* Remainder zero: round up if mantissa odd. */ mgl@1371: +#else mgl@1371: + bfextu r6, r2, 7, 1 /* Get guard bit */ mgl@1371: +#endif mgl@1371: + /* Final packing, scale down mantissa. */ mgl@1371: + lsr r10, r2, 8 mgl@1371: + or r10, r10, r3<<24 mgl@1371: + lsr r11, r3, 8 mgl@1371: + /* Insert exponent and sign bit*/ mgl@1371: + bfins r11, r7, 20, 11 mgl@1371: + bld lr, 31 mgl@1371: + bst r11, 31 mgl@1371: + mgl@1371: + /* Final rounding */ mgl@1371: + add r10, r6 mgl@1371: + acr r11 mgl@1371: + mgl@1371: + /* Return result in [r11,r10] */ mgl@1371: + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc mgl@1371: + mgl@1371: + mgl@1371: +2: mgl@1371: + /* Op1 is NaN or inf */ mgl@1371: + andh r11, 0x000f /* Extract mantissa */ mgl@1371: + or r11, r10 mgl@1371: + brne 16f /* Return NaN if op1 is NaN */ mgl@1371: + /* Op1 is inf check op2 */ mgl@1371: + lsr r6, r9, 20 /* Extract exponent */ mgl@1371: + cbr r6, 8 /* Clear sign bit */ mgl@1371: + cp r6, 0x7ff mgl@1371: + brne 17f /* Inf/number gives inf, return inf */ mgl@1371: + rjmp 16f /* The rest gives NaN*/ mgl@1371: + mgl@1371: +3: mgl@1371: + /* Op1 is a valid number. Op 2 is NaN or inf */ mgl@1371: + andh r9, 0x000f /* Extract mantissa */ mgl@1371: + or r9, r8 mgl@1371: + brne 16f /* Return NaN if op2 is NaN */ mgl@1371: + rjmp 15f /* Op2 was inf, return zero*/ mgl@1371: + mgl@1371: +11: /* Op1 was denormal. Fix it. */ mgl@1371: + lsl r11, 3 mgl@1371: + or r11, r11, r10 >> 29 mgl@1371: + lsl r10, 3 mgl@1371: + /* Check if op1 is zero. */ mgl@1371: + or r4, r10, r11 mgl@1371: + breq __avr32_f64_div_op1_zero mgl@1371: + normalize_df r7 /*exp*/, r10, r11 /*Mantissa*/, r4, r5 /*scratch*/ mgl@1371: + lsr r10, 2 mgl@1371: + or r10, r10, r11 << 30 mgl@1371: + lsr r11, 2 mgl@1371: + rjmp 22b mgl@1371: + mgl@1371: + mgl@1371: +13: /* Op2 was denormal. Fix it */ mgl@1371: + lsl r9, 3 mgl@1371: + or r9, r9, r8 >> 29 mgl@1371: + lsl r8, 3 mgl@1371: + /* Check if op2 is zero. */ mgl@1371: + or r4, r9, r8 mgl@1371: + breq 17f /* Divisor is zero -> return Inf */ mgl@1371: + normalize_df r6 /*exp*/, r8, r9 /*Mantissa*/, r4, r5 /*scratch*/ mgl@1371: + lsr r8, 2 mgl@1371: + or r8, r8, r9 << 30 mgl@1371: + lsr r9, 2 mgl@1371: + rjmp 23b mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f64_div_res_subnormal:/* Divide result was subnormal. */ mgl@1371: +#if defined(L_avr32_f64_div) mgl@1371: + /* Check how much we must scale down the mantissa. */ mgl@1371: + neg r7 mgl@1371: + sub r7, -1 /* We do no longer have an implicit bit. */ mgl@1371: + satu r7 >> 0, 6 /* Saturate shift amount to max 63. */ mgl@1371: + cp.w r7, 32 mgl@1371: + brge 0f mgl@1371: + /* Shift amount <32 */ mgl@1371: + /* Scale down quotient */ mgl@1371: + rsub r6, r7, 32 mgl@1371: + lsr r2, r2, r7 mgl@1371: + lsl r12, r3, r6 mgl@1371: + or r2, r12 mgl@1371: + lsr r3, r3, r7 mgl@1371: + /* Scale down the dividend to match the scaling of the quotient. */ mgl@1371: + lsl r1, r10, r6 mgl@1371: + lsr r10, r10, r7 mgl@1371: + lsl r12, r11, r6 mgl@1371: + or r10, r12 mgl@1371: + lsr r11, r11, r7 mgl@1371: + mov r0, 0 mgl@1371: + rjmp 1f mgl@1371: +0: mgl@1371: + /* Shift amount >=32 */ mgl@1371: + rsub r6, r7, 32 mgl@1371: + moveq r0, 0 mgl@1371: + moveq r12, 0 mgl@1371: + breq 0f mgl@1371: + lsl r0, r10, r6 mgl@1371: + lsl r12, r11, r6 mgl@1371: +0: mgl@1371: + lsr r2, r3, r7 mgl@1371: + mov r3, 0 mgl@1371: + /* Scale down the dividend to match the scaling of the quotient. */ mgl@1371: + lsr r1, r10, r7 mgl@1371: + or r1, r12 mgl@1371: + lsr r10, r11, r7 mgl@1371: + mov r11, 0 mgl@1371: +1: mgl@1371: + /* Start performing the same rounding as done for normal numbers mgl@1371: + but this time we have scaled the quotient and dividend and hence mgl@1371: + need a little different comparison. */ mgl@1371: + /* Truncate and add guard bit. */ mgl@1371: + andl r2, 0xff00 mgl@1371: + orl r2, 0x0080 mgl@1371: + mgl@1371: + /* Now do the multiplication. */ mgl@1371: + mulu.d r6, r3, r8 mgl@1371: + macu.d r6, r2, r9 mgl@1371: + mulu.d r4, r2, r8 mgl@1371: + mulu.d r8, r3, r9 mgl@1371: + add r5, r6 mgl@1371: + adc r8, r8, r7 mgl@1371: + acr r9 mgl@1371: + mgl@1371: + /* Set exponent to 0 */ mgl@1371: + mov r7, 0 mgl@1371: + mgl@1371: + /* Check if remainder is positive, negative or equal. */ mgl@1371: + bfextu r12, r2, 8, 1 /* Get parity bit into bit 0 of r0 */ mgl@1371: + cp r4, r0 mgl@1371: + cpc r5, r1 mgl@1371: + /* Now the rest of the rounding is the same as for normals. */ mgl@1371: + rjmp __avr32_f64_div_round_subnormal mgl@1371: + mgl@1371: +#endif mgl@1371: +15: mgl@1371: + /* Flush to zero for the fast version. */ mgl@1371: + mov r11, lr /*Get correct sign*/ mgl@1371: + andh r11, 0x8000, COH mgl@1371: + mov r10, 0 mgl@1371: + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc mgl@1371: + mgl@1371: +16: /* Return NaN. */ mgl@1371: + mov r11, -1 mgl@1371: + mov r10, -1 mgl@1371: + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc mgl@1371: + mgl@1371: +17: /* Return INF. */ mgl@1371: + mov r11, lr /*Get correct sign*/ mgl@1371: + andh r11, 0x8000, COH mgl@1371: + orh r11, 0x7ff0 mgl@1371: + mov r10, 0 mgl@1371: + ldm sp++, r0, r1, r2, r3, r4, r5, r6, r7,pc mgl@1371: + mgl@1371: +__avr32_f64_div_op1_zero: mgl@1371: + or r5, r8, r9 << 1 mgl@1371: + breq 16b /* 0.0/0.0 -> NaN */ mgl@1371: + bfextu r4, r9, 20, 11 mgl@1371: + cp r4, 0x7ff mgl@1371: + brne 15b /* Return zero */ mgl@1371: + /* Check if divisor is Inf or NaN */ mgl@1371: + or r5, r8, r9 << 12 mgl@1371: + breq 15b /* Divisor is inf -> return zero */ mgl@1371: + rjmp 16b /* Return NaN */ mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_addsub) || defined(L_avr32_f32_addsub_fast) mgl@1371: + mgl@1371: + .align 2 mgl@1371: +__avr32_f32_sub_from_add: mgl@1371: + /* Switch sign on op2 */ mgl@1371: + eorh r11, 0x8000 mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_addsub_fast) mgl@1371: + .global __avr32_f32_sub_fast mgl@1371: + .type __avr32_f32_sub_fast,@function mgl@1371: +__avr32_f32_sub_fast: mgl@1371: +#else mgl@1371: + .global __avr32_f32_sub mgl@1371: + .type __avr32_f32_sub,@function mgl@1371: +__avr32_f32_sub: mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Check signs */ mgl@1371: + eor r8, r11, r12 mgl@1371: + /* Different signs, use subtraction. */ mgl@1371: + brmi __avr32_f32_add_from_sub mgl@1371: + mgl@1371: + /* Get sign of op1 */ mgl@1371: + mov r8, r12 mgl@1371: + andh r12, 0x8000, COH mgl@1371: + mgl@1371: + /* Remove sign from operands */ mgl@1371: + cbr r11, 31 mgl@1371: +#if defined(L_avr32_f32_addsub_fast) mgl@1371: + reteq r8 /* If op2 is zero return op1 */ mgl@1371: +#endif mgl@1371: + cbr r8, 31 mgl@1371: + mgl@1371: + /* Put the number with the largest exponent in r10 mgl@1371: + and the number with the smallest exponent in r9 */ mgl@1371: + max r10, r8, r11 mgl@1371: + min r9, r8, r11 mgl@1371: + cp r10, r8 /*If largest operand (in R10) is not equal to op1*/ mgl@1371: + subne r12, 1 /* Subtract 1 from sign, which will invert MSB of r12*/ mgl@1371: + andh r12, 0x8000, COH /*Mask all but MSB*/ mgl@1371: + mgl@1371: + /* Unpack exponent and mantissa of op1 */ mgl@1371: + lsl r8, r10, 8 mgl@1371: + sbr r8, 31 /* Set implicit bit. */ mgl@1371: + lsr r10, 23 mgl@1371: + mgl@1371: + /* op1 is NaN or Inf. */ mgl@1371: + cp.w r10, 0xff mgl@1371: + breq __avr32_f32_sub_op1_nan_or_inf mgl@1371: + mgl@1371: + /* Unpack exponent and mantissa of op2 */ mgl@1371: + lsl r11, r9, 8 mgl@1371: + sbr r11, 31 /* Set implicit bit. */ mgl@1371: + lsr r9, 23 mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_addsub) mgl@1371: + /* Keep sticky bit for correct IEEE rounding */ mgl@1371: + st.w --sp, r12 mgl@1371: + mgl@1371: + /* op2 is either zero or subnormal. */ mgl@1371: + breq __avr32_f32_sub_op2_subnormal mgl@1371: +0: mgl@1371: + /* Get shift amount to scale mantissa of op2. */ mgl@1371: + sub r12, r10, r9 mgl@1371: + mgl@1371: + breq __avr32_f32_sub_shift_done mgl@1371: + mgl@1371: + /* Saturate the shift amount to 31. If the amount mgl@1371: + is any larger op2 is insignificant. */ mgl@1371: + satu r12 >> 0, 5 mgl@1371: + mgl@1371: + /* Put the remaining bits into r9.*/ mgl@1371: + rsub r9, r12, 32 mgl@1371: + lsl r9, r11, r9 mgl@1371: + mgl@1371: + /* If the remaining bits are non-zero then we must subtract one mgl@1371: + more from opL. */ mgl@1371: + subne r8, 1 mgl@1371: + srne r9 /* LSB of r9 represents sticky bits. */ mgl@1371: + mgl@1371: + /* Shift mantissa of op2 to same decimal point as the mantissa mgl@1371: + of op1. */ mgl@1371: + lsr r11, r11, r12 mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f32_sub_shift_done: mgl@1371: + /* Now subtract the mantissas. */ mgl@1371: + sub r8, r11 mgl@1371: + mgl@1371: + ld.w r12, sp++ mgl@1371: + mgl@1371: + /* Normalize resulting mantissa. */ mgl@1371: + clz r11, r8 mgl@1371: + mgl@1371: + retcs 0 mgl@1371: + lsl r8, r8, r11 mgl@1371: + sub r10, r11 mgl@1371: + brle __avr32_f32_sub_subnormal_result mgl@1371: + mgl@1371: + /* Insert the bits we will remove from the mantissa into r9[31:24] */ mgl@1371: + or r9, r9, r8 << 24 mgl@1371: +#else mgl@1371: + /* Ignore sticky bit to simplify and speed up rounding */ mgl@1371: + /* op2 is either zero or subnormal. */ mgl@1371: + breq __avr32_f32_sub_op2_subnormal mgl@1371: +0: mgl@1371: + /* Get shift amount to scale mantissa of op2. */ mgl@1371: + rsub r9, r10 mgl@1371: + mgl@1371: + /* Saturate the shift amount to 31. If the amount mgl@1371: + is any larger op2 is insignificant. */ mgl@1371: + satu r9 >> 0, 5 mgl@1371: + mgl@1371: + /* Shift mantissa of op2 to same decimal point as the mantissa mgl@1371: + of op1. */ mgl@1371: + lsr r11, r11, r9 mgl@1371: + mgl@1371: + /* Now subtract the mantissas. */ mgl@1371: + sub r8, r11 mgl@1371: + mgl@1371: + /* Normalize resulting mantissa. */ mgl@1371: + clz r9, r8 mgl@1371: + retcs 0 mgl@1371: + lsl r8, r8, r9 mgl@1371: + sub r10, r9 mgl@1371: + brle __avr32_f32_sub_subnormal_result mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Pack result. */ mgl@1371: + or r12, r12, r8 >> 8 mgl@1371: + bfins r12, r10, 23, 8 mgl@1371: + mgl@1371: + /* Round */ mgl@1371: +__avr32_f32_sub_round: mgl@1371: +#if defined(L_avr32_f32_addsub) mgl@1371: + mov_imm r10, 0x80000000 mgl@1371: + bld r12, 0 mgl@1371: + subne r10, -1 mgl@1371: + cp.w r9, r10 mgl@1371: + subhs r12, -1 mgl@1371: +#else mgl@1371: + bld r8, 7 mgl@1371: + acr r12 mgl@1371: +#endif mgl@1371: + mgl@1371: + ret r12 mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f32_sub_op2_subnormal: mgl@1371: + /* Fix implicit bit and adjust exponent of subnormals. */ mgl@1371: + cbr r11, 31 mgl@1371: + /* Set exponent to 1 if we do not have a zero. */ mgl@1371: + movne r9,1 mgl@1371: + mgl@1371: + /* Check if op1 is also subnormal. */ mgl@1371: + cp.w r10, 0 mgl@1371: + brne 0b mgl@1371: + mgl@1371: + cbr r8, 31 mgl@1371: + /* If op1 is not zero set exponent to 1. */ mgl@1371: + movne r10,1 mgl@1371: + mgl@1371: + rjmp 0b mgl@1371: + mgl@1371: +__avr32_f32_sub_op1_nan_or_inf: mgl@1371: + /* Check if op1 is NaN, if so return NaN */ mgl@1371: + lsl r11, r8, 1 mgl@1371: + retne -1 mgl@1371: + mgl@1371: + /* op1 is Inf. */ mgl@1371: + bfins r12, r10, 23, 8 /* Generate Inf in r12 */ mgl@1371: + mgl@1371: + /* Check if op2 is Inf. or NaN */ mgl@1371: + lsr r11, r9, 23 mgl@1371: + cp.w r11, 0xff mgl@1371: + retne r12 /* op2 not Inf or NaN, return op1 */ mgl@1371: + mgl@1371: + ret -1 /* op2 Inf or NaN, return NaN */ mgl@1371: + mgl@1371: +__avr32_f32_sub_subnormal_result: mgl@1371: + /* Check if the number is so small that mgl@1371: + it will be represented with zero. */ mgl@1371: + rsub r10, r10, 9 mgl@1371: + rsub r11, r10, 32 mgl@1371: + retcs 0 mgl@1371: + mgl@1371: + /* Shift the mantissa into the correct position.*/ mgl@1371: + lsr r10, r8, r10 mgl@1371: + /* Add sign bit. */ mgl@1371: + or r12, r10 mgl@1371: + mgl@1371: + /* Put the shifted out bits in the most significant part mgl@1371: + of r8. */ mgl@1371: + lsl r8, r8, r11 mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_addsub) mgl@1371: + /* Add all the remainder bits used for rounding into r9 */ mgl@1371: + or r9, r8 mgl@1371: +#else mgl@1371: + lsr r8, 24 mgl@1371: +#endif mgl@1371: + rjmp __avr32_f32_sub_round mgl@1371: + mgl@1371: + mgl@1371: + .align 2 mgl@1371: + mgl@1371: +__avr32_f32_add_from_sub: mgl@1371: + /* Switch sign on op2 */ mgl@1371: + eorh r11, 0x8000 mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_addsub_fast) mgl@1371: + .global __avr32_f32_add_fast mgl@1371: + .type __avr32_f32_add_fast,@function mgl@1371: +__avr32_f32_add_fast: mgl@1371: +#else mgl@1371: + .global __avr32_f32_add mgl@1371: + .type __avr32_f32_add,@function mgl@1371: +__avr32_f32_add: mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Check signs */ mgl@1371: + eor r8, r11, r12 mgl@1371: + /* Different signs, use subtraction. */ mgl@1371: + brmi __avr32_f32_sub_from_add mgl@1371: + mgl@1371: + /* Get sign of op1 */ mgl@1371: + mov r8, r12 mgl@1371: + andh r12, 0x8000, COH mgl@1371: + mgl@1371: + /* Remove sign from operands */ mgl@1371: + cbr r11, 31 mgl@1371: +#if defined(L_avr32_f32_addsub_fast) mgl@1371: + reteq r8 /* If op2 is zero return op1 */ mgl@1371: +#endif mgl@1371: + cbr r8, 31 mgl@1371: + mgl@1371: + /* Put the number with the largest exponent in r10 mgl@1371: + and the number with the smallest exponent in r9 */ mgl@1371: + max r10, r8, r11 mgl@1371: + min r9, r8, r11 mgl@1371: + mgl@1371: + /* Unpack exponent and mantissa of op1 */ mgl@1371: + lsl r8, r10, 8 mgl@1371: + sbr r8, 31 /* Set implicit bit. */ mgl@1371: + lsr r10, 23 mgl@1371: + mgl@1371: + /* op1 is NaN or Inf. */ mgl@1371: + cp.w r10, 0xff mgl@1371: + breq __avr32_f32_add_op1_nan_or_inf mgl@1371: + mgl@1371: + /* Unpack exponent and mantissa of op2 */ mgl@1371: + lsl r11, r9, 8 mgl@1371: + sbr r11, 31 /* Set implicit bit. */ mgl@1371: + lsr r9, 23 mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_addsub) mgl@1371: + /* op2 is either zero or subnormal. */ mgl@1371: + breq __avr32_f32_add_op2_subnormal mgl@1371: +0: mgl@1371: + /* Keep sticky bit for correct IEEE rounding */ mgl@1371: + st.w --sp, r12 mgl@1371: + mgl@1371: + /* Get shift amount to scale mantissa of op2. */ mgl@1371: + rsub r9, r10 mgl@1371: + mgl@1371: + /* Saturate the shift amount to 31. If the amount mgl@1371: + is any larger op2 is insignificant. */ mgl@1371: + satu r9 >> 0, 5 mgl@1371: + mgl@1371: + /* Shift mantissa of op2 to same decimal point as the mantissa mgl@1371: + of op1. */ mgl@1371: + lsr r12, r11, r9 mgl@1371: + mgl@1371: + /* Put the remainding bits into r11[23:..].*/ mgl@1371: + rsub r9, r9, (32-8) mgl@1371: + lsl r11, r11, r9 mgl@1371: + /* Insert the bits we will remove from the mantissa into r11[31:24] */ mgl@1371: + bfins r11, r12, 24, 8 mgl@1371: + mgl@1371: + /* Now add the mantissas. */ mgl@1371: + add r8, r12 mgl@1371: + mgl@1371: + ld.w r12, sp++ mgl@1371: +#else mgl@1371: + /* Ignore sticky bit to simplify and speed up rounding */ mgl@1371: + /* op2 is either zero or subnormal. */ mgl@1371: + breq __avr32_f32_add_op2_subnormal mgl@1371: +0: mgl@1371: + /* Get shift amount to scale mantissa of op2. */ mgl@1371: + rsub r9, r10 mgl@1371: + mgl@1371: + /* Saturate the shift amount to 31. If the amount mgl@1371: + is any larger op2 is insignificant. */ mgl@1371: + satu r9 >> 0, 5 mgl@1371: + mgl@1371: + /* Shift mantissa of op2 to same decimal point as the mantissa mgl@1371: + of op1. */ mgl@1371: + lsr r11, r11, r9 mgl@1371: + mgl@1371: + /* Now add the mantissas. */ mgl@1371: + add r8, r11 mgl@1371: + mgl@1371: +#endif mgl@1371: + /* Check if we overflowed. */ mgl@1371: + brcs __avr32_f32_add_res_of mgl@1371: +1: mgl@1371: + /* Pack result. */ mgl@1371: + or r12, r12, r8 >> 8 mgl@1371: + bfins r12, r10, 23, 8 mgl@1371: + mgl@1371: + /* Round */ mgl@1371: +#if defined(L_avr32_f32_addsub) mgl@1371: + mov_imm r10, 0x80000000 mgl@1371: + bld r12, 0 mgl@1371: + subne r10, -1 mgl@1371: + cp.w r11, r10 mgl@1371: + subhs r12, -1 mgl@1371: +#else mgl@1371: + bld r8, 7 mgl@1371: + acr r12 mgl@1371: +#endif mgl@1371: + mgl@1371: + ret r12 mgl@1371: + mgl@1371: +__avr32_f32_add_op2_subnormal: mgl@1371: + /* Fix implicit bit and adjust exponent of subnormals. */ mgl@1371: + cbr r11, 31 mgl@1371: + /* Set exponent to 1 if we do not have a zero. */ mgl@1371: + movne r9,1 mgl@1371: + mgl@1371: + /* Check if op1 is also subnormal. */ mgl@1371: + cp.w r10, 0 mgl@1371: + brne 0b mgl@1371: + /* Both operands subnormal, just add the mantissas and mgl@1371: + pack. If the addition of the subnormal numbers results mgl@1371: + in a normal number then the exponent will automatically mgl@1371: + be set to 1 by the addition. */ mgl@1371: + cbr r8, 31 mgl@1371: + add r11, r8 mgl@1371: + or r12, r12, r11 >> 8 mgl@1371: + ret r12 mgl@1371: + mgl@1371: +__avr32_f32_add_op1_nan_or_inf: mgl@1371: + /* Check if op1 is NaN, if so return NaN */ mgl@1371: + lsl r11, r8, 1 mgl@1371: + retne -1 mgl@1371: + mgl@1371: + /* op1 is Inf. */ mgl@1371: + bfins r12, r10, 23, 8 /* Generate Inf in r12 */ mgl@1371: + mgl@1371: + /* Check if op2 is Inf. or NaN */ mgl@1371: + lsr r11, r9, 23 mgl@1371: + cp.w r11, 0xff mgl@1371: + retne r12 /* op2 not Inf or NaN, return op1 */ mgl@1371: + mgl@1371: + lsl r9, 9 mgl@1371: + reteq r12 /* op2 Inf return op1 */ mgl@1371: + ret -1 /* op2 is NaN, return NaN */ mgl@1371: + mgl@1371: +__avr32_f32_add_res_of: mgl@1371: + /* We overflowed. Increase exponent and shift mantissa.*/ mgl@1371: + lsr r8, 1 mgl@1371: + sub r10, -1 mgl@1371: + mgl@1371: + /* Clear mantissa to set result to Inf if the exponent is 255. */ mgl@1371: + cp.w r10, 255 mgl@1371: + moveq r8, 0 mgl@1371: + moveq r11, 0 mgl@1371: + rjmp 1b mgl@1371: + mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_div) || defined(L_avr32_f32_div_fast) mgl@1371: + .align 2 mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_div_fast) mgl@1371: + .global __avr32_f32_div_fast mgl@1371: + .type __avr32_f32_div_fast,@function mgl@1371: +__avr32_f32_div_fast: mgl@1371: +#else mgl@1371: + .global __avr32_f32_div mgl@1371: + .type __avr32_f32_div,@function mgl@1371: +__avr32_f32_div: mgl@1371: +#endif mgl@1371: + mgl@1371: + eor r8, r11, r12 /* MSB(r8) = Sign(op1) ^ Sign(op2) */ mgl@1371: + mgl@1371: + /* Unpack */ mgl@1371: + lsl r12,1 mgl@1371: + reteq 0 /* Return zero if op1 is zero */ mgl@1371: + lsl r11,1 mgl@1371: + breq 4f /* Check op2 for zero */ mgl@1371: + mgl@1371: + /* Unpack op1*/ mgl@1371: + /* exp: r9 */ mgl@1371: + /* sf: r12 */ mgl@1371: + lsr r9, r12, 24 mgl@1371: + breq 11f /*If number is subnormal*/ mgl@1371: + cp r9, 0xff mgl@1371: + brhs 2f /* Check op1 for NaN or Inf */ mgl@1371: + lsl r12, 7 mgl@1371: + sbr r12, 31 /*Implicit bit*/ mgl@1371: +12: mgl@1371: + mgl@1371: + /* Unpack op2*/ mgl@1371: + /* exp: r10 */ mgl@1371: + /* sf: r11 */ mgl@1371: + lsr r10, r11, 24 mgl@1371: + breq 13f /*If number is subnormal*/ mgl@1371: + cp r10, 0xff mgl@1371: + brhs 3f /* Check op2 for NaN or Inf */ mgl@1371: + mgl@1371: + lsl r11,7 mgl@1371: + sbr r11, 31 /*Implicit bit*/ mgl@1371: +14: mgl@1371: + mgl@1371: + /* For UC3, store with predecrement is faster than stm */ mgl@1371: + st.w --sp, r5 mgl@1371: + st.d --sp, r6 mgl@1371: + mgl@1371: + /* Calculate new exponent */ mgl@1371: + sub r9, r10 mgl@1371: + sub r9,-127 mgl@1371: + mgl@1371: + /* Divide */ mgl@1371: + /* Approximating 1/d with the following recurrence: */ mgl@1371: + /* R[j+1] = R[j]*(2-R[j]*d) */ mgl@1371: + /* Using 2.30 format */ mgl@1371: + /* TWO: r10 */ mgl@1371: + /* d: r5 */ mgl@1371: + /* Multiply result : r6, r7 */ mgl@1371: + /* Initial guess : r11 */ mgl@1371: + /* New approximations : r11 */ mgl@1371: + /* Dividend : r12 */ mgl@1371: + mgl@1371: + /* Load TWO */ mgl@1371: + mov_imm r10, 0x80000000 mgl@1371: + mgl@1371: + lsr r12, 2 /* Get significand of Op1 in 2.30 format */ mgl@1371: + lsr r5, r11, 2 /* Get significand of Op2 (=d) in 2.30 format */ mgl@1371: + mgl@1371: + /* Load initial guess, using look-up table */ mgl@1371: + /* Initial guess is of format 01.XY, where XY is constructed as follows: */ mgl@1371: + /* Let d be of following format: 00.1xy....., then XY=~xy */ mgl@1371: + /* For d=00.100 = 0,5 -> initial guess=01.11 = 1,75 */ mgl@1371: + /* For d=00.101 = 0,625 -> initial guess=01.11 = 1,5 */ mgl@1371: + /* For d=00.110 = 0,75 -> initial guess=01.11 = 1,25 */ mgl@1371: + /* For d=00.111 = 0,875 -> initial guess=01.11 = 1,0 */ mgl@1371: + mgl@1371: + lsr r11, r10, 1 mgl@1371: + bfextu r6, r5, 27, 2 mgl@1371: + com r6 mgl@1371: + bfins r11, r6, 28, 2 mgl@1371: + mgl@1371: + /* First approximation */ mgl@1371: + /* r7 = R[j]*d */ mgl@1371: + mulu.d r6, r11, r5 mgl@1371: + /* r7 = 2-R[j]*d */ mgl@1371: + sub r7, r10, r7<<2 mgl@1371: + /* r11 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r6, r11, r7 mgl@1371: + lsl r11, r7, 2 mgl@1371: + mgl@1371: + /* Second approximation */ mgl@1371: + /* r7 = R[j]*d */ mgl@1371: + mulu.d r6, r11, r5 mgl@1371: + /* r7 = 2-R[j]*d */ mgl@1371: + sub r7, r10, r7<<2 mgl@1371: + /* r11 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r6, r11, r7 mgl@1371: + lsl r11, r7, 2 mgl@1371: + mgl@1371: + /* Third approximation */ mgl@1371: + /* r7 = R[j]*d */ mgl@1371: + mulu.d r6, r11, r5 mgl@1371: + /* r7 = 2-R[j]*d */ mgl@1371: + sub r7, r10, r7<<2 mgl@1371: + /* r11 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r6, r11, r7 mgl@1371: + lsl r11, r7, 2 mgl@1371: + mgl@1371: + /* Fourth approximation */ mgl@1371: + /* r7 = R[j]*d */ mgl@1371: + mulu.d r6, r11, r5 mgl@1371: + /* r7 = 2-R[j]*d */ mgl@1371: + sub r7, r10, r7<<2 mgl@1371: + /* r11 = R[j]*(2-R[j]*d) */ mgl@1371: + mulu.d r6, r11, r7 mgl@1371: + lsl r11, r7, 2 mgl@1371: + mgl@1371: + mgl@1371: + /* Multiply with dividend to get quotient, r7 = sf(op1)/sf(op2) */ mgl@1371: + mulu.d r6, r11, r12 mgl@1371: + mgl@1371: + /* Shift by 3 to get result in 1.31 format, as required by the exponent. */ mgl@1371: + /* Note that 1.31 format is already used by the exponent in r9, since */ mgl@1371: + /* a bias of 127 was added to the result exponent, even though the implicit */ mgl@1371: + /* bit was inserted. This gives the exponent an additional bias of 1, which */ mgl@1371: + /* supports 1.31 format. */ mgl@1371: + //lsl r10, r7, 3 mgl@1371: + mgl@1371: + /* Adjust exponent and mantissa in case the result is of format mgl@1371: + 0000.1xxx to 0001.xxx*/ mgl@1371: +#if defined(L_avr32_f32_div) mgl@1371: + lsr r12, 4 /* Scale dividend to 6.26 format to match the mgl@1371: + result of the multiplication of the divisor and mgl@1371: + quotient to get the remainder. */ mgl@1371: +#endif mgl@1371: + bld r7, 31-3 mgl@1371: + breq 0f mgl@1371: + lsl r7, 1 mgl@1371: + sub r9, 1 mgl@1371: +#if defined(L_avr32_f32_div) mgl@1371: + lsl r12, 1 /* Scale dividend to 5.27 format to match the mgl@1371: + result of the multiplication of the divisor and mgl@1371: + quotient to get the remainder. */ mgl@1371: +#endif mgl@1371: +0: mgl@1371: + cp r9, 0 mgl@1371: + brle __avr32_f32_div_res_subnormal /* Result was subnormal. */ mgl@1371: + mgl@1371: + mgl@1371: +#if defined(L_avr32_f32_div) mgl@1371: + /* In order to round correctly we calculate the remainder: mgl@1371: + Remainder = dividend[r12] - divisor[r5]*quotient[r7] mgl@1371: + for the case when the quotient is halfway between the round-up mgl@1371: + value and the round down value. If the remainder then is negative mgl@1371: + it means that the quotient was to big and that it should not be mgl@1371: + rounded up, if the remainder is positive the quotient was to small mgl@1371: + and we need to round up. If the remainder is zero it means that the mgl@1371: + quotient is exact but since we need to remove the guard bit we should mgl@1371: + round to even. */ mgl@1371: + andl r7, 0xffe0 mgl@1371: + orl r7, 0x0010 mgl@1371: + mgl@1371: + /* Now do the multiplication. The quotient has the format 4.28 mgl@1371: + while the divisor has the format 2.30 which gives a result mgl@1371: + of 6.26 */ mgl@1371: + mulu.d r10, r5, r7 mgl@1371: + mgl@1371: + /* Check if remainder is positive, negative or equal. */ mgl@1371: + bfextu r5, r7, 5, 1 /* Get parity bit into bit 0 of r5 */ mgl@1371: + cp r10, 0 mgl@1371: +__avr32_f32_div_round_subnormal: mgl@1371: + cpc r11, r12 mgl@1371: + srlo r11 /* Remainder positive: we need to round up.*/ mgl@1371: + moveq r11, r5 /* Remainder zero: round up if mantissa odd. */ mgl@1371: +#else mgl@1371: + bfextu r11, r7, 4, 1 /* Get guard bit */ mgl@1371: +#endif mgl@1371: + mgl@1371: + /* Pack final result*/ mgl@1371: + lsr r12, r7, 5 mgl@1371: + bfins r12, r9, 23, 8 mgl@1371: + /* For UC3, load with postincrement is faster than ldm */ mgl@1371: + ld.d r6, sp++ mgl@1371: + ld.w r5, sp++ mgl@1371: + bld r8, 31 mgl@1371: + bst r12, 31 mgl@1371: + /* Rounding add. */ mgl@1371: + add r12, r11 mgl@1371: + ret r12 mgl@1371: + mgl@1371: +__divsf_return_op1: mgl@1371: + lsl r8, 1 mgl@1371: + ror r12 mgl@1371: + ret r12 mgl@1371: + mgl@1371: + mgl@1371: +2: mgl@1371: + /* Op1 is NaN or inf */ mgl@1371: + retne -1 /* Return NaN if op1 is NaN */ mgl@1371: + /* Op1 is inf check op2 */ mgl@1371: + mov_imm r9, 0xff000000 mgl@1371: + cp r11, r9 mgl@1371: + brlo __divsf_return_op1 /* inf/number gives inf */ mgl@1371: + ret -1 /* The rest gives NaN*/ mgl@1371: +3: mgl@1371: + /* Op2 is NaN or inf */ mgl@1371: + reteq 0 /* Return zero if number/inf*/ mgl@1371: + ret -1 /* Return NaN*/ mgl@1371: +4: mgl@1371: + /* Op2 is zero ? */ mgl@1371: + tst r12,r12 mgl@1371: + reteq -1 /* 0.0/0.0 is NaN */ mgl@1371: + /* Nonzero/0.0 is Inf. Sign bit will be shifted in before returning*/ mgl@1371: + mov_imm r12, 0xff000000 mgl@1371: + rjmp __divsf_return_op1 mgl@1371: + mgl@1371: +11: /* Op1 was denormal. Fix it. */ mgl@1371: + lsl r12,7 mgl@1371: + clz r9,r12 mgl@1371: + lsl r12,r12,r9 mgl@1371: + rsub r9,r9,1 mgl@1371: + rjmp 12b mgl@1371: + mgl@1371: +13: /* Op2 was denormal. Fix it. */ mgl@1371: + lsl r11,7 mgl@1371: + clz r10,r11 mgl@1371: + lsl r11,r11,r10 mgl@1371: + rsub r10,r10,1 mgl@1371: + rjmp 14b mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f32_div_res_subnormal: /* Divide result was subnormal */ mgl@1371: +#if defined(L_avr32_f32_div) mgl@1371: + /* Check how much we must scale down the mantissa. */ mgl@1371: + neg r9 mgl@1371: + sub r9, -1 /* We do no longer have an implicit bit. */ mgl@1371: + satu r9 >> 0, 5 /* Saturate shift amount to max 32. */ mgl@1371: + /* Scale down quotient */ mgl@1371: + rsub r10, r9, 32 mgl@1371: + lsr r7, r7, r9 mgl@1371: + /* Scale down the dividend to match the scaling of the quotient. */ mgl@1371: + lsl r6, r12, r10 /* Make the divident 64-bit and put the lsw in r6 */ mgl@1371: + lsr r12, r12, r9 mgl@1371: + mgl@1371: + /* Start performing the same rounding as done for normal numbers mgl@1371: + but this time we have scaled the quotient and dividend and hence mgl@1371: + need a little different comparison. */ mgl@1371: + andl r7, 0xffe0 mgl@1371: + orl r7, 0x0010 mgl@1371: + mgl@1371: + /* Now do the multiplication. The quotient has the format 4.28 mgl@1371: + while the divisor has the format 2.30 which gives a result mgl@1371: + of 6.26 */ mgl@1371: + mulu.d r10, r5, r7 mgl@1371: + mgl@1371: + /* Set exponent to 0 */ mgl@1371: + mov r9, 0 mgl@1371: + mgl@1371: + /* Check if remainder is positive, negative or equal. */ mgl@1371: + bfextu r5, r7, 5, 1 /* Get parity bit into bit 0 of r5 */ mgl@1371: + cp r10, r6 mgl@1371: + rjmp __avr32_f32_div_round_subnormal mgl@1371: + mgl@1371: +#else mgl@1371: + ld.d r6, sp++ mgl@1371: + ld.w r5, sp++ mgl@1371: + /*Flush to zero*/ mgl@1371: + ret 0 mgl@1371: +#endif mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_f32_mul mgl@1371: + .global __avr32_f32_mul mgl@1371: + .type __avr32_f32_mul,@function mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f32_mul: mgl@1371: + mov r8, r12 mgl@1371: + eor r12, r11 /* MSB(r8) = Sign(op1) ^ Sign(op2) */ mgl@1371: + andh r12, 0x8000, COH mgl@1371: + mgl@1371: + /* arrange operands so that that op1 >= op2 */ mgl@1371: + cbr r8, 31 mgl@1371: + breq __avr32_f32_mul_op1_zero mgl@1371: + cbr r11, 31 mgl@1371: + mgl@1371: + /* Put the number with the largest exponent in r10 mgl@1371: + and the number with the smallest exponent in r9 */ mgl@1371: + max r10, r8, r11 mgl@1371: + min r9, r8, r11 mgl@1371: + mgl@1371: + /* Unpack exponent and mantissa of op1 */ mgl@1371: + lsl r8, r10, 8 mgl@1371: + sbr r8, 31 /* Set implicit bit. */ mgl@1371: + lsr r10, 23 mgl@1371: + mgl@1371: + /* op1 is NaN or Inf. */ mgl@1371: + cp.w r10, 0xff mgl@1371: + breq __avr32_f32_mul_op1_nan_or_inf mgl@1371: + mgl@1371: + /* Unpack exponent and mantissa of op2 */ mgl@1371: + lsl r11, r9, 8 mgl@1371: + sbr r11, 31 /* Set implicit bit. */ mgl@1371: + lsr r9, 23 mgl@1371: + mgl@1371: + /* op2 is either zero or subnormal. */ mgl@1371: + breq __avr32_f32_mul_op2_subnormal mgl@1371: +0: mgl@1371: + /* Calculate new exponent */ mgl@1371: + add r9,r10 mgl@1371: + mgl@1371: + /* Do the multiplication */ mgl@1371: + mulu.d r10,r8,r11 mgl@1371: + mgl@1371: + /* We might need to scale up by two if the MSB of the result is mgl@1371: + zero. */ mgl@1371: + lsl r8, r11, 1 mgl@1371: + movcc r11, r8 mgl@1371: + subcc r9, 1 mgl@1371: + mgl@1371: + /* Put the shifted out bits of the mantissa into r10 */ mgl@1371: + lsr r10, 8 mgl@1371: + bfins r10, r11, 24, 8 mgl@1371: + mgl@1371: + sub r9,(127-1) /* remove extra exponent bias */ mgl@1371: + brle __avr32_f32_mul_res_subnormal mgl@1371: + mgl@1371: + /* Check for Inf. */ mgl@1371: + cp.w r9, 0xff mgl@1371: + brge 1f mgl@1371: + mgl@1371: + /* Pack result. */ mgl@1371: + or r12, r12, r11 >> 8 mgl@1371: + bfins r12, r9, 23, 8 mgl@1371: + mgl@1371: + /* Round */ mgl@1371: +__avr32_f32_mul_round: mgl@1371: + mov_imm r8, 0x80000000 mgl@1371: + bld r12, 0 mgl@1371: + subne r8, -1 mgl@1371: + mgl@1371: + cp.w r10, r8 mgl@1371: + subhs r12, -1 mgl@1371: + mgl@1371: + ret r12 mgl@1371: + mgl@1371: +1: mgl@1371: + /* Return Inf */ mgl@1371: + orh r12, 0x7f80 mgl@1371: + ret r12 mgl@1371: + mgl@1371: +__avr32_f32_mul_op2_subnormal: mgl@1371: + cbr r11, 31 mgl@1371: + clz r9, r11 mgl@1371: + retcs 0 /* op2 is zero. Return 0 */ mgl@1371: + lsl r11, r11, r9 mgl@1371: + rsub r9, r9, 1 mgl@1371: + mgl@1371: + /* Check if op2 is subnormal. */ mgl@1371: + tst r10, r10 mgl@1371: + brne 0b mgl@1371: + mgl@1371: + /* op2 is subnormal */ mgl@1371: + cbr r8, 31 mgl@1371: + clz r10, r11 mgl@1371: + retcs 0 /* op1 is zero. Return 0 */ mgl@1371: + lsl r8, r8, r10 mgl@1371: + rsub r10, r10, 1 mgl@1371: + mgl@1371: + rjmp 0b mgl@1371: + mgl@1371: + mgl@1371: +__avr32_f32_mul_op1_nan_or_inf: mgl@1371: + /* Check if op1 is NaN, if so return NaN */ mgl@1371: + lsl r11, r8, 1 mgl@1371: + retne -1 mgl@1371: + mgl@1371: + /* op1 is Inf. */ mgl@1371: + tst r9, r9 mgl@1371: + reteq -1 /* Inf * 0 -> NaN */ mgl@1371: + mgl@1371: + bfins r12, r10, 23, 8 /* Generate Inf in r12 */ mgl@1371: + mgl@1371: + /* Check if op2 is Inf. or NaN */ mgl@1371: + lsr r11, r9, 23 mgl@1371: + cp.w r11, 0xff mgl@1371: + retne r12 /* op2 not Inf or NaN, return Info */ mgl@1371: + mgl@1371: + lsl r9, 9 mgl@1371: + reteq r12 /* op2 Inf return Inf */ mgl@1371: + ret -1 /* op2 is NaN, return NaN */ mgl@1371: + mgl@1371: +__avr32_f32_mul_res_subnormal: mgl@1371: + /* Check if the number is so small that mgl@1371: + it will be represented with zero. */ mgl@1371: + rsub r9, r9, 9 mgl@1371: + rsub r8, r9, 32 mgl@1371: + retcs 0 mgl@1371: + mgl@1371: + /* Shift the mantissa into the correct position.*/ mgl@1371: + lsr r9, r11, r9 mgl@1371: + /* Add sign bit. */ mgl@1371: + or r12, r9 mgl@1371: + /* Put the shifted out bits in the most significant part mgl@1371: + of r8. */ mgl@1371: + lsl r11, r11, r8 mgl@1371: + mgl@1371: + /* Add all the remainder bits used for rounding into r11 */ mgl@1371: + andh r10, 0x00FF mgl@1371: + or r10, r11 mgl@1371: + rjmp __avr32_f32_mul_round mgl@1371: + mgl@1371: +__avr32_f32_mul_op1_zero: mgl@1371: + bfextu r10, r11, 23, 8 mgl@1371: + cp.w r10, 0xff mgl@1371: + retne r12 mgl@1371: + reteq -1 mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#ifdef L_avr32_s32_to_f32 mgl@1371: + .global __avr32_s32_to_f32 mgl@1371: + .type __avr32_s32_to_f32,@function mgl@1371: +__avr32_s32_to_f32: mgl@1371: + cp r12, 0 mgl@1371: + reteq r12 /* If zero then return zero float */ mgl@1371: + mov r11, r12 /* Keep the sign */ mgl@1371: + abs r12 /* Compute the absolute value */ mgl@1371: + mov r10, 31 + 127 /* Set the correct exponent */ mgl@1371: + mgl@1371: + /* Normalize */ mgl@1371: + normalize_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/ mgl@1371: + mgl@1371: + /* Check for subnormal result */ mgl@1371: + cp.w r10, 0 mgl@1371: + brle __avr32_s32_to_f32_subnormal mgl@1371: + mgl@1371: + round_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/ mgl@1371: + pack_sf r12 /*sf*/, r10 /*exp*/, r12 /*mant*/ mgl@1371: + lsl r11, 1 mgl@1371: + ror r12 mgl@1371: + ret r12 mgl@1371: + mgl@1371: +__avr32_s32_to_f32_subnormal: mgl@1371: + /* Adjust a subnormal result */ mgl@1371: + adjust_subnormal_sf r12/*sf*/, r10 /*exp*/, r12 /*mant*/, r11/*sign*/, r9 /*scratch*/ mgl@1371: + ret r12 mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_u32_to_f32 mgl@1371: + .global __avr32_u32_to_f32 mgl@1371: + .type __avr32_u32_to_f32,@function mgl@1371: +__avr32_u32_to_f32: mgl@1371: + cp r12, 0 mgl@1371: + reteq r12 /* If zero then return zero float */ mgl@1371: + mov r10, 31 + 127 /* Set the correct exponent */ mgl@1371: + mgl@1371: + /* Normalize */ mgl@1371: + normalize_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/ mgl@1371: + mgl@1371: + /* Check for subnormal result */ mgl@1371: + cp.w r10, 0 mgl@1371: + brle __avr32_u32_to_f32_subnormal mgl@1371: + mgl@1371: + round_sf r10 /*exp*/, r12 /*mant*/, r9 /*scratch*/ mgl@1371: + pack_sf r12 /*sf*/, r10 /*exp*/, r12 /*mant*/ mgl@1371: + lsr r12,1 /* Sign bit is 0 for unsigned int */ mgl@1371: + ret r12 mgl@1371: + mgl@1371: +__avr32_u32_to_f32_subnormal: mgl@1371: + /* Adjust a subnormal result */ mgl@1371: + mov r8, 0 mgl@1371: + adjust_subnormal_sf r12/*sf*/,r10 /*exp*/, r12 /*mant*/,r8/*sign*/, r9 /*scratch*/ mgl@1371: + ret r12 mgl@1371: + mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#ifdef L_avr32_f32_to_s32 mgl@1371: + .global __avr32_f32_to_s32 mgl@1371: + .type __avr32_f32_to_s32,@function mgl@1371: +__avr32_f32_to_s32: mgl@1371: + bfextu r11, r12, 23, 8 mgl@1371: + sub r11,127 /* Fix bias */ mgl@1371: + retlo 0 /* Negative exponent yields zero integer */ mgl@1371: + mgl@1371: + /* Shift mantissa into correct position */ mgl@1371: + rsub r11,r11,31 /* Shift amount */ mgl@1371: + lsl r10,r12,8 /* Get mantissa */ mgl@1371: + sbr r10,31 /* Add implicit bit */ mgl@1371: + lsr r10,r10,r11 /* Perform shift */ mgl@1371: + lsl r12,1 /* Check sign */ mgl@1371: + retcc r10 /* if positive, we are done */ mgl@1371: + neg r10 /* if negative float, negate result */ mgl@1371: + ret r10 mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_f32_to_u32 mgl@1371: + .global __avr32_f32_to_u32 mgl@1371: + .type __avr32_f32_to_u32,@function mgl@1371: +__avr32_f32_to_u32: mgl@1371: + cp r12,0 mgl@1371: + retmi 0 /* Negative numbers gives 0 */ mgl@1371: + bfextu r11, r12, 23, 8 /* Extract exponent */ mgl@1371: + sub r11,127 /* Fix bias */ mgl@1371: + retlo 0 /* Negative exponent yields zero integer */ mgl@1371: + mgl@1371: + /* Shift mantissa into correct position */ mgl@1371: + rsub r11,r11,31 /* Shift amount */ mgl@1371: + lsl r12,8 /* Get mantissa */ mgl@1371: + sbr r12,31 /* Add implicit bit */ mgl@1371: + lsr r12,r12,r11 /* Perform shift */ mgl@1371: + ret r12 mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#ifdef L_avr32_f32_to_f64 mgl@1371: + .global __avr32_f32_to_f64 mgl@1371: + .type __avr32_f32_to_f64,@function mgl@1371: + mgl@1371: +__avr32_f32_to_f64: mgl@1371: + lsl r11,r12,1 /* Remove sign bit, keep original value in r12*/ mgl@1371: + moveq r10, 0 mgl@1371: + reteq r11 /* Return zero if input is zero */ mgl@1371: + mgl@1371: + bfextu r9,r11,24,8 /* Get exponent */ mgl@1371: + cp.w r9,0xff /* check for NaN or inf */ mgl@1371: + breq 0f mgl@1371: + mgl@1371: + lsl r11,7 /* Convert sf mantissa to df format */ mgl@1371: + mov r10,0 mgl@1371: + mgl@1371: + /* Check if implicit bit should be set */ mgl@1371: + cp.w r9, 0 mgl@1371: + subeq r9,-1 /* Adjust exponent if it was 0 */ mgl@1371: + srne r8 mgl@1371: + or r11, r11, r8 << 31 /* Set implicit bit if needed */ mgl@1371: + sub r9,(127-0x3ff) /* Convert exponent to df format exponent */ mgl@1371: + mgl@1371: + /*We know that low register of mantissa is 0, and will be unaffected by normalization.*/ mgl@1371: + /*We can therefore use the faster normalize_sf function instead of normalize_df.*/ mgl@1371: + normalize_sf r9 /*exp*/, r11 /*mantissa*/, r8 /*scratch*/ mgl@1371: + pack_df r9 /*exp*/, r10, r11 /*mantissa*/, r10, r11 /*df*/ mgl@1371: + mgl@1371: +__extendsfdf_return_op1: mgl@1371: + /* Rotate in sign bit */ mgl@1371: + lsl r12, 1 mgl@1371: + ror r11 mgl@1371: + ret r11 mgl@1371: + mgl@1371: +0: mgl@1371: + /* Inf or NaN*/ mgl@1371: + mov_imm r10, 0xffe00000 mgl@1371: + lsl r11,8 /* check mantissa */ mgl@1371: + movne r11, -1 /* Return NaN */ mgl@1371: + moveq r11, r10 /* Return inf */ mgl@1371: + rjmp __extendsfdf_return_op1 mgl@1371: +#endif mgl@1371: + mgl@1371: + mgl@1371: +#ifdef L_avr32_f64_to_f32 mgl@1371: + .global __avr32_f64_to_f32 mgl@1371: + .type __avr32_f64_to_f32,@function mgl@1371: + mgl@1371: +__avr32_f64_to_f32: mgl@1371: + /* Unpack */ mgl@1371: + lsl r9,r11,1 /* Unpack exponent */ mgl@1371: + lsr r9,21 mgl@1371: + mgl@1371: + reteq 0 /* If exponent is 0 the number is so small mgl@1371: + that the conversion to single float gives mgl@1371: + zero */ mgl@1371: + mgl@1371: + lsl r8,r11,10 /* Adjust mantissa */ mgl@1371: + or r12,r8,r10>>22 mgl@1371: + mgl@1371: + lsl r10,10 /* Check if there are any remaining bits mgl@1371: + in the low part of the mantissa.*/ mgl@1371: + neg r10 mgl@1371: + rol r12 /* If there were remaining bits then set lsb mgl@1371: + of mantissa to 1 */ mgl@1371: + mgl@1371: + cp r9,0x7ff mgl@1371: + breq 2f /* Check for NaN or inf */ mgl@1371: + mgl@1371: + sub r9,(0x3ff-127) /* Adjust bias of exponent */ mgl@1371: + sbr r12,31 /* set the implicit bit.*/ mgl@1371: + mgl@1371: + cp.w r9, 0 /* Check for subnormal number */ mgl@1371: + brle 3f mgl@1371: + mgl@1371: + round_sf r9 /*exp*/, r12 /*mant*/, r10 /*scratch*/ mgl@1371: + pack_sf r12 /*sf*/, r9 /*exp*/, r12 /*mant*/ mgl@1371: +__truncdfsf_return_op1: mgl@1371: + /* Rotate in sign bit */ mgl@1371: + lsl r11, 1 mgl@1371: + ror r12 mgl@1371: + ret r12 mgl@1371: + mgl@1371: +2: mgl@1371: + /* NaN or inf */ mgl@1371: + cbr r12,31 /* clear implicit bit */ mgl@1371: + retne -1 /* Return NaN if mantissa not zero */ mgl@1371: + mov_imm r12, 0xff000000 mgl@1371: + ret r12 /* Return inf */ mgl@1371: + mgl@1371: +3: /* Result is subnormal. Adjust it.*/ mgl@1371: + adjust_subnormal_sf r12/*sf*/,r9 /*exp*/, r12 /*mant*/, r11/*sign*/, r10 /*scratch*/ mgl@1371: + ret r12 mgl@1371: + mgl@1371: + mgl@1371: +#endif mgl@1371: + mgl@1371: +#if defined(L_mulsi3) && (__AVR32_UC__ == 3) mgl@1371: + .global __mulsi3 mgl@1371: + .type __mulsi3,@function mgl@1371: + mgl@1371: +__mulsi3: mgl@1371: + mov r9, 0 mgl@1371: +0: mgl@1371: + lsr r11, 1 mgl@1371: + addcs r9, r9, r12 mgl@1371: + breq 1f mgl@1371: + lsl r12, 1 mgl@1371: + rjmp 0b mgl@1371: +1: mgl@1371: + ret r9 mgl@1371: +#endif mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/lib2funcs.S mgl@1371: @@ -0,0 +1,21 @@ mgl@1371: + .align 4 mgl@1371: + .global __nonlocal_goto mgl@1371: + .type __nonlocal_goto,@function mgl@1371: + mgl@1371: +/* __nonlocal_goto: This function handles nonlocal_goto's in gcc. mgl@1371: + mgl@1371: + parameter 0 (r12) = New Frame Pointer mgl@1371: + parameter 1 (r11) = Address to goto mgl@1371: + parameter 2 (r10) = New Stack Pointer mgl@1371: + mgl@1371: + This function invalidates the return stack, since it returns from a mgl@1371: + function without using a return instruction. mgl@1371: +*/ mgl@1371: +__nonlocal_goto: mgl@1371: + mov r7, r12 mgl@1371: + mov sp, r10 mgl@1371: + frs # Flush return stack mgl@1371: + mov pc, r11 mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/linux-elf.h mgl@1371: @@ -0,0 +1,151 @@ mgl@1371: +/* mgl@1371: + Linux/Elf specific definitions. mgl@1371: + Copyright 2003-2006 Atmel Corporation. mgl@1371: + mgl@1371: + Written by Ronny Pedersen, Atmel Norway, mgl@1371: + and H�vard Skinnemoen, Atmel Norway, mgl@1371: + mgl@1371: + This file is part of GCC. mgl@1371: + mgl@1371: + This program is free software; you can redistribute it and/or modify mgl@1371: + it under the terms of the GNU General Public License as published by mgl@1371: + the Free Software Foundation; either version 2 of the License, or mgl@1371: + (at your option) any later version. mgl@1371: + mgl@1371: + This program is distributed in the hope that it will be useful, mgl@1371: + but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: + GNU General Public License for more details. mgl@1371: + mgl@1371: + You should have received a copy of the GNU General Public License mgl@1371: + along with this program; if not, write to the Free Software mgl@1371: + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* elfos.h should have already been included. Now just override mgl@1371: + any conflicting definitions and add any extras. */ mgl@1371: + mgl@1371: +/* Run-time Target Specification. */ mgl@1371: +#undef TARGET_VERSION mgl@1371: +#define TARGET_VERSION fputs (" (AVR32 GNU/Linux with ELF)", stderr); mgl@1371: + mgl@1371: +/* Do not assume anything about header files. */ mgl@1371: +#define NO_IMPLICIT_EXTERN_C mgl@1371: + mgl@1371: +/* The GNU C++ standard library requires that these macros be defined. */ mgl@1371: +#undef CPLUSPLUS_CPP_SPEC mgl@1371: +#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" mgl@1371: + mgl@1371: +/* Now we define the strings used to build the spec file. */ mgl@1371: +#undef LIB_SPEC mgl@1371: +#define LIB_SPEC \ mgl@1371: + "%{pthread:-lpthread} \ mgl@1371: + %{shared:-lc} \ mgl@1371: + %{!shared:%{profile:-lc_p}%{!profile:-lc}}" mgl@1371: + mgl@1371: +/* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add mgl@1371: + the GNU/Linux magical crtbegin.o file (see crtstuff.c) which mgl@1371: + provides part of the support for getting C++ file-scope static mgl@1371: + object constructed before entering `main'. */ mgl@1371: + mgl@1371: +#undef STARTFILE_SPEC mgl@1371: +#define STARTFILE_SPEC \ mgl@1371: + "%{!shared: \ mgl@1371: + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} \ mgl@1371: + %{!p:%{profile:gcrt1.o%s} \ mgl@1371: + %{!profile:crt1.o%s}}}} \ mgl@1371: + crti.o%s %{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" mgl@1371: + mgl@1371: +/* Provide a ENDFILE_SPEC appropriate for GNU/Linux. Here we tack on mgl@1371: + the GNU/Linux magical crtend.o file (see crtstuff.c) which mgl@1371: + provides part of the support for getting C++ file-scope static mgl@1371: + object constructed before entering `main', followed by a normal mgl@1371: + GNU/Linux "finalizer" file, `crtn.o'. */ mgl@1371: + mgl@1371: +#undef ENDFILE_SPEC mgl@1371: +#define ENDFILE_SPEC \ mgl@1371: + "%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" mgl@1371: + mgl@1371: +#undef ASM_SPEC mgl@1371: +#define ASM_SPEC "%{!mno-pic:%{!fno-pic:--pic}} %{mrelax|O*:%{mno-relax|O0|O1: ;:--linkrelax}} %{mcpu=*:-mcpu=%*}" mgl@1371: + mgl@1371: +#undef LINK_SPEC mgl@1371: +#define LINK_SPEC "%{version:-v} \ mgl@1371: + %{static:-Bstatic} \ mgl@1371: + %{shared:-shared} \ mgl@1371: + %{symbolic:-Bsymbolic} \ mgl@1371: + %{rdynamic:-export-dynamic} \ mgl@1371: + %{!dynamic-linker:-dynamic-linker /lib/ld-uClibc.so.0} \ mgl@1371: + %{mrelax|O*:%{mno-relax|O0|O1: ;:--relax}}" mgl@1371: + mgl@1371: +#define TARGET_OS_CPP_BUILTINS() LINUX_TARGET_OS_CPP_BUILTINS() mgl@1371: + mgl@1371: +/* This is how we tell the assembler that two symbols have the same value. */ mgl@1371: +#define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + assemble_name (FILE, NAME1); \ mgl@1371: + fputs (" = ", FILE); \ mgl@1371: + assemble_name (FILE, NAME2); \ mgl@1371: + fputc ('\n', FILE); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +#undef CC1_SPEC mgl@1371: +#define CC1_SPEC "%{profile:-p}" mgl@1371: + mgl@1371: +/* Target CPU builtins. */ mgl@1371: +#define TARGET_CPU_CPP_BUILTINS() \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + builtin_define ("__avr32__"); \ mgl@1371: + builtin_define ("__AVR32__"); \ mgl@1371: + builtin_define ("__AVR32_LINUX__"); \ mgl@1371: + builtin_define (avr32_part->macro); \ mgl@1371: + builtin_define (avr32_arch->macro); \ mgl@1371: + if (avr32_arch->uarch_type == UARCH_TYPE_AVR32A) \ mgl@1371: + builtin_define ("__AVR32_AVR32A__"); \ mgl@1371: + else \ mgl@1371: + builtin_define ("__AVR32_AVR32B__"); \ mgl@1371: + if (TARGET_UNALIGNED_WORD) \ mgl@1371: + builtin_define ("__AVR32_HAS_UNALIGNED_WORD__"); \ mgl@1371: + if (TARGET_SIMD) \ mgl@1371: + builtin_define ("__AVR32_HAS_SIMD__"); \ mgl@1371: + if (TARGET_DSP) \ mgl@1371: + builtin_define ("__AVR32_HAS_DSP__"); \ mgl@1371: + if (TARGET_RMW) \ mgl@1371: + builtin_define ("__AVR32_HAS_RMW__"); \ mgl@1371: + if (TARGET_BRANCH_PRED) \ mgl@1371: + builtin_define ("__AVR32_HAS_BRANCH_PRED__"); \ mgl@1371: + if (TARGET_FAST_FLOAT) \ mgl@1371: + builtin_define ("__AVR32_FAST_FLOAT__"); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +/* Call the function profiler with a given profile label. */ mgl@1371: +#undef FUNCTION_PROFILER mgl@1371: +#define FUNCTION_PROFILER(STREAM, LABELNO) \ mgl@1371: + do \ mgl@1371: + { \ mgl@1371: + fprintf (STREAM, "\tmov\tlr, lo(mcount)\n\torh\tlr, hi(mcount)\n"); \ mgl@1371: + fprintf (STREAM, "\ticall lr\n"); \ mgl@1371: + } \ mgl@1371: + while (0) mgl@1371: + mgl@1371: +#define NO_PROFILE_COUNTERS 1 mgl@1371: + mgl@1371: +/* For dynamic libraries to work */ mgl@1371: +/* #define PLT_REG_CALL_CLOBBERED 1 */ mgl@1371: +#define AVR32_ALWAYS_PIC 1 mgl@1371: + mgl@1371: +/* uclibc does not implement sinf, cosf etc. */ mgl@1371: +#undef TARGET_C99_FUNCTIONS mgl@1371: +#define TARGET_C99_FUNCTIONS 0 mgl@1371: + mgl@1371: +#define LINK_GCC_C_SEQUENCE_SPEC \ mgl@1371: + "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}" mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/predicates.md mgl@1371: @@ -0,0 +1,419 @@ mgl@1371: +;; AVR32 predicates file. mgl@1371: +;; Copyright 2003-2006 Atmel Corporation. mgl@1371: +;; mgl@1371: +;; Written by Ronny Pedersen, Atmel Norway, mgl@1371: +;; mgl@1371: +;; This file is part of GCC. mgl@1371: +;; mgl@1371: +;; This program is free software; you can redistribute it and/or modify mgl@1371: +;; it under the terms of the GNU General Public License as published by mgl@1371: +;; the Free Software Foundation; either version 2 of the License, or mgl@1371: +;; (at your option) any later version. mgl@1371: +;; mgl@1371: +;; This program is distributed in the hope that it will be useful, mgl@1371: +;; but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: +;; GNU General Public License for more details. mgl@1371: +;; mgl@1371: +;; You should have received a copy of the GNU General Public License mgl@1371: +;; along with this program; if not, write to the Free Software mgl@1371: +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. mgl@1371: + mgl@1371: + mgl@1371: +;; True if the operand is a memory reference which contains an mgl@1371: +;; Address consisting of a single pointer register mgl@1371: +(define_predicate "avr32_indirect_register_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "register_operand(XEXP(op, 0), SImode)"))) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +;; Address expression with a base pointer offset with mgl@1371: +;; a register displacement mgl@1371: +(define_predicate "avr32_indexed_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "GET_CODE(XEXP(op, 0)) == PLUS")) mgl@1371: + { mgl@1371: + mgl@1371: + rtx op0 = XEXP(XEXP(op, 0), 0); mgl@1371: + rtx op1 = XEXP(XEXP(op, 0), 1); mgl@1371: + mgl@1371: + return ((avr32_address_register_rtx_p (op0, 0) mgl@1371: + && avr32_legitimate_index_p (GET_MODE(op), op1, 0)) mgl@1371: + || (avr32_address_register_rtx_p (op1, 0) mgl@1371: + && avr32_legitimate_index_p (GET_MODE(op), op0, 0))); mgl@1371: + mgl@1371: + }) mgl@1371: + mgl@1371: +;; Operand suitable for the ld.sb instruction mgl@1371: +(define_predicate "load_sb_memory_operand" mgl@1371: + (ior (match_operand 0 "avr32_indirect_register_operand") mgl@1371: + (match_operand 0 "avr32_indexed_memory_operand"))) mgl@1371: + mgl@1371: + mgl@1371: +;; Operand suitable as operand to insns sign extending QI values mgl@1371: +(define_predicate "extendqi_operand" mgl@1371: + (ior (match_operand 0 "load_sb_memory_operand") mgl@1371: + (match_operand 0 "register_operand"))) mgl@1371: + mgl@1371: +(define_predicate "post_inc_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "(GET_CODE(XEXP(op, 0)) == POST_INC) mgl@1371: + && REG_P(XEXP(XEXP(op, 0), 0))"))) mgl@1371: + mgl@1371: +(define_predicate "pre_dec_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "(GET_CODE(XEXP(op, 0)) == PRE_DEC) mgl@1371: + && REG_P(XEXP(XEXP(op, 0), 0))"))) mgl@1371: + mgl@1371: +;; Operand suitable for add instructions mgl@1371: +(define_predicate "avr32_add_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'I', \"Is21\")")))) mgl@1371: + mgl@1371: +;; Operand is a power of two immediate mgl@1371: +(define_predicate "power_of_two_operand" mgl@1371: + (match_code "const_int") mgl@1371: +{ mgl@1371: + HOST_WIDE_INT value = INTVAL (op); mgl@1371: + mgl@1371: + return value != 0 && (value & (value - 1)) == 0; mgl@1371: +}) mgl@1371: + mgl@1371: +;; Operand is a multiple of 8 immediate mgl@1371: +(define_predicate "multiple_of_8_operand" mgl@1371: + (match_code "const_int") mgl@1371: +{ mgl@1371: + HOST_WIDE_INT value = INTVAL (op); mgl@1371: + mgl@1371: + return (value & 0x7) == 0 ; mgl@1371: +}) mgl@1371: + mgl@1371: +;; Operand is a multiple of 16 immediate mgl@1371: +(define_predicate "multiple_of_16_operand" mgl@1371: + (match_code "const_int") mgl@1371: +{ mgl@1371: + HOST_WIDE_INT value = INTVAL (op); mgl@1371: + mgl@1371: + return (value & 0xf) == 0 ; mgl@1371: +}) mgl@1371: + mgl@1371: +;; Operand is a mask used for masking away upper bits of a reg mgl@1371: +(define_predicate "avr32_mask_upper_bits_operand" mgl@1371: + (match_code "const_int") mgl@1371: +{ mgl@1371: + HOST_WIDE_INT value = INTVAL (op) + 1; mgl@1371: + mgl@1371: + return value != 1 && value != 0 && (value & (value - 1)) == 0; mgl@1371: +}) mgl@1371: + mgl@1371: + mgl@1371: +;; Operand suitable for mul instructions mgl@1371: +(define_predicate "avr32_mul_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")")))) mgl@1371: + mgl@1371: +;; True for logical binary operators. mgl@1371: +(define_predicate "logical_binary_operator" mgl@1371: + (match_code "ior,xor,and")) mgl@1371: + mgl@1371: +;; True for logical shift operators mgl@1371: +(define_predicate "logical_shift_operator" mgl@1371: + (match_code "ashift,lshiftrt")) mgl@1371: + mgl@1371: +;; True for shift operand for logical and, or and eor insns mgl@1371: +(define_predicate "avr32_logical_shift_operand" mgl@1371: + (and (match_code "ashift,lshiftrt") mgl@1371: + (ior (and (match_test "GET_CODE(XEXP(op, 1)) == CONST_INT") mgl@1371: + (match_test "register_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))")) mgl@1371: + (and (match_test "GET_CODE(XEXP(op, 0)) == CONST_INT") mgl@1371: + (match_test "register_operand(XEXP(op, 1), GET_MODE(XEXP(op, 1)))")))) mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;; Predicate for second operand to and, ior and xor insn patterns mgl@1371: +(define_predicate "avr32_logical_insn_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (match_operand 0 "avr32_logical_shift_operand")) mgl@1371: +) mgl@1371: + mgl@1371: + mgl@1371: +;; True for avr32 comparison operators mgl@1371: +(define_predicate "avr32_comparison_operator" mgl@1371: + (ior (match_code "eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu") mgl@1371: + (and (match_code "unspec") mgl@1371: + (match_test "(XINT(op, 1) == UNSPEC_COND_MI) mgl@1371: + || (XINT(op, 1) == UNSPEC_COND_PL)")))) mgl@1371: + mgl@1371: +(define_predicate "avr32_cond3_comparison_operator" mgl@1371: + (ior (match_code "eq, ne, ge, lt, geu, ltu") mgl@1371: + (and (match_code "unspec") mgl@1371: + (match_test "(XINT(op, 1) == UNSPEC_COND_MI) mgl@1371: + || (XINT(op, 1) == UNSPEC_COND_PL)")))) mgl@1371: + mgl@1371: +;; True for avr32 comparison operand mgl@1371: +(define_predicate "avr32_comparison_operand" mgl@1371: + (ior (and (match_code "eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu") mgl@1371: + (match_test "(CC0_P (XEXP(op,0)) && rtx_equal_p (XEXP(op,1), const0_rtx))")) mgl@1371: + (and (match_code "unspec") mgl@1371: + (match_test "(XINT(op, 1) == UNSPEC_COND_MI) mgl@1371: + || (XINT(op, 1) == UNSPEC_COND_PL)")))) mgl@1371: + mgl@1371: +;; True if this is a const_int with one bit set mgl@1371: +(define_predicate "one_bit_set_operand" mgl@1371: + (match_code "const_int") mgl@1371: + { mgl@1371: + int i; mgl@1371: + int value; mgl@1371: + int ones = 0; mgl@1371: + mgl@1371: + value = INTVAL(op); mgl@1371: + for ( i = 0 ; i < 32; i++ ){ mgl@1371: + if ( value & ( 1 << i ) ){ mgl@1371: + ones++; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + return ( ones == 1 ); mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +;; True if this is a const_int with one bit cleared mgl@1371: +(define_predicate "one_bit_cleared_operand" mgl@1371: + (match_code "const_int") mgl@1371: + { mgl@1371: + int i; mgl@1371: + int value; mgl@1371: + int zeroes = 0; mgl@1371: + mgl@1371: + value = INTVAL(op); mgl@1371: + for ( i = 0 ; i < 32; i++ ){ mgl@1371: + if ( !(value & ( 1 << i )) ){ mgl@1371: + zeroes++; mgl@1371: + } mgl@1371: + } mgl@1371: + mgl@1371: + return ( zeroes == 1 ); mgl@1371: + }) mgl@1371: + mgl@1371: + mgl@1371: +;; Immediate all the low 16-bits cleared mgl@1371: +(define_predicate "avr32_hi16_immediate_operand" mgl@1371: + (match_code "const_int") mgl@1371: + { mgl@1371: + /* If the low 16-bits are zero then this mgl@1371: + is a hi16 immediate. */ mgl@1371: + return ((INTVAL(op) & 0xffff) == 0); mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +;; True if this is a register or immediate operand mgl@1371: +(define_predicate "register_immediate_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (match_operand 0 "immediate_operand"))) mgl@1371: + mgl@1371: +;; True if this is a register or const_int operand mgl@1371: +(define_predicate "register_const_int_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (and (match_operand 0 "const_int_operand") mgl@1371: + (match_operand 0 "immediate_operand")))) mgl@1371: + mgl@1371: +;; True if this is a register or const_double operand mgl@1371: +(define_predicate "register_const_double_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (match_operand 0 "const_double_operand"))) mgl@1371: + mgl@1371: +;; True is this is an operand containing a label_ref mgl@1371: +(define_predicate "avr32_label_ref_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "avr32_find_symbol(op) mgl@1371: + && (GET_CODE(avr32_find_symbol(op)) == LABEL_REF)"))) mgl@1371: + mgl@1371: +;; True is this is a valid symbol pointing to the constant pool mgl@1371: +(define_predicate "avr32_const_pool_operand" mgl@1371: + (and (match_code "symbol_ref") mgl@1371: + (match_test "CONSTANT_POOL_ADDRESS_P(op)")) mgl@1371: + { mgl@1371: + return (flag_pic ? (!(symbol_mentioned_p (get_pool_constant (op)) mgl@1371: + || label_mentioned_p (get_pool_constant (op))) mgl@1371: + || avr32_got_mentioned_p(get_pool_constant (op))) mgl@1371: + : true); mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +;; True is this is a memory reference to the constant or mini pool mgl@1371: +(define_predicate "avr32_const_pool_ref_operand" mgl@1371: + (ior (match_operand 0 "avr32_label_ref_operand") mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "avr32_const_pool_operand(XEXP(op,0), GET_MODE(XEXP(op,0)))")))) mgl@1371: + mgl@1371: + mgl@1371: +;; Legal source operand for movti insns mgl@1371: +(define_predicate "avr32_movti_src_operand" mgl@1371: + (ior (match_operand 0 "avr32_const_pool_ref_operand") mgl@1371: + (ior (ior (match_operand 0 "register_immediate_operand") mgl@1371: + (match_operand 0 "avr32_indirect_register_operand")) mgl@1371: + (match_operand 0 "post_inc_memory_operand")))) mgl@1371: + mgl@1371: +;; Legal destination operand for movti insns mgl@1371: +(define_predicate "avr32_movti_dst_operand" mgl@1371: + (ior (ior (match_operand 0 "register_operand") mgl@1371: + (match_operand 0 "avr32_indirect_register_operand")) mgl@1371: + (match_operand 0 "pre_dec_memory_operand"))) mgl@1371: + mgl@1371: + mgl@1371: +;; True is this is a k12 offseted memory operand mgl@1371: +(define_predicate "avr32_k12_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (ior (match_test "REG_P(XEXP(op, 0))") mgl@1371: + (match_test "GET_CODE(XEXP(op, 0)) == PLUS mgl@1371: + && REG_P(XEXP(XEXP(op, 0), 0)) mgl@1371: + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT) mgl@1371: + && (CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(XEXP(op, 0), 0)), mgl@1371: + 'K', (mode == SImode) ? \"Ks14\" : ((mode == HImode) ? \"Ks13\" : \"Ks12\")))")))) mgl@1371: + mgl@1371: +;; True is this is a memory operand with an immediate displacement mgl@1371: +(define_predicate "avr32_imm_disp_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "GET_CODE(XEXP(op, 0)) == PLUS mgl@1371: + && REG_P(XEXP(XEXP(op, 0), 0)) mgl@1371: + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT)"))) mgl@1371: + mgl@1371: +;; True is this is a bswap operand mgl@1371: +(define_predicate "avr32_bswap_operand" mgl@1371: + (ior (match_operand 0 "avr32_k12_memory_operand") mgl@1371: + (match_operand 0 "register_operand"))) mgl@1371: + mgl@1371: +;; True is this is a valid coprocessor insn memory operand mgl@1371: +(define_predicate "avr32_cop_memory_operand" mgl@1371: + (and (match_operand 0 "memory_operand") mgl@1371: + (not (match_test "GET_CODE(XEXP(op, 0)) == PLUS mgl@1371: + && REG_P(XEXP(XEXP(op, 0), 0)) mgl@1371: + && (GET_CODE(XEXP(XEXP(op, 0), 1)) == CONST_INT) mgl@1371: + && !(CONST_OK_FOR_CONSTRAINT_P(INTVAL(XEXP(XEXP(op, 0), 0)), 'K', \"Ku10\"))")))) mgl@1371: + mgl@1371: +;; True is this is a valid source/destination operand mgl@1371: +;; for moving values to/from a coprocessor mgl@1371: +(define_predicate "avr32_cop_move_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (match_operand 0 "avr32_cop_memory_operand"))) mgl@1371: + mgl@1371: + mgl@1371: +;; True is this is a valid extract byte offset for use in mgl@1371: +;; load extracted index insns mgl@1371: +(define_predicate "avr32_extract_shift_operand" mgl@1371: + (and (match_operand 0 "const_int_operand") mgl@1371: + (match_test "(INTVAL(op) == 0) || (INTVAL(op) == 8) mgl@1371: + || (INTVAL(op) == 16) || (INTVAL(op) == 24)"))) mgl@1371: + mgl@1371: +;; True is this is a floating-point register mgl@1371: +(define_predicate "avr32_fp_register_operand" mgl@1371: + (and (match_operand 0 "register_operand") mgl@1371: + (match_test "REGNO_REG_CLASS(REGNO(op)) == FP_REGS"))) mgl@1371: + mgl@1371: +;; True is this is valid avr32 symbol operand mgl@1371: +(define_predicate "avr32_symbol_operand" mgl@1371: + (and (match_code "label_ref, symbol_ref, const") mgl@1371: + (match_test "avr32_find_symbol(op)"))) mgl@1371: + mgl@1371: +;; True is this is valid operand for the lda.w and call pseudo insns mgl@1371: +(define_predicate "avr32_address_operand" mgl@1371: + (and (and (match_code "label_ref, symbol_ref") mgl@1371: + (match_test "avr32_find_symbol(op)")) mgl@1371: + (ior (match_test "TARGET_HAS_ASM_ADDR_PSEUDOS") mgl@1371: + (match_test "flag_pic")) )) mgl@1371: + mgl@1371: +;; An immediate k16 address operand mgl@1371: +(define_predicate "avr32_ks16_address_operand" mgl@1371: + (and (match_operand 0 "address_operand") mgl@1371: + (ior (match_test "REG_P(op)") mgl@1371: + (match_test "GET_CODE(op) == PLUS mgl@1371: + && ((GET_CODE(XEXP(op,0)) == CONST_INT) mgl@1371: + || (GET_CODE(XEXP(op,1)) == CONST_INT))")) )) mgl@1371: + mgl@1371: +;; An offset k16 memory operand mgl@1371: +(define_predicate "avr32_ks16_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "avr32_ks16_address_operand (XEXP (op, 0), GET_MODE (XEXP (op, 0)))"))) mgl@1371: + mgl@1371: +;; An immediate k11 address operand mgl@1371: +(define_predicate "avr32_ks11_address_operand" mgl@1371: + (and (match_operand 0 "address_operand") mgl@1371: + (ior (match_test "REG_P(op)") mgl@1371: + (match_test "GET_CODE(op) == PLUS mgl@1371: + && (((GET_CODE(XEXP(op,0)) == CONST_INT) mgl@1371: + && avr32_const_ok_for_constraint_p(INTVAL(XEXP(op,0)), 'K', \"Ks11\")) mgl@1371: + || ((GET_CODE(XEXP(op,1)) == CONST_INT) mgl@1371: + && avr32_const_ok_for_constraint_p(INTVAL(XEXP(op,1)), 'K', \"Ks11\")))")) )) mgl@1371: + mgl@1371: +;; True if this is a avr32 call operand mgl@1371: +(define_predicate "avr32_call_operand" mgl@1371: + (ior (ior (match_operand 0 "register_operand") mgl@1371: + (ior (match_operand 0 "avr32_const_pool_ref_operand") mgl@1371: + (match_operand 0 "avr32_address_operand"))) mgl@1371: + (match_test "SYMBOL_REF_RCALL_FUNCTION_P(op)"))) mgl@1371: + mgl@1371: +;; Return true for operators performing ALU operations mgl@1371: + mgl@1371: +(define_predicate "alu_operator" mgl@1371: + (match_code "ior, xor, and, plus, minus, ashift, lshiftrt, ashiftrt")) mgl@1371: + mgl@1371: +(define_predicate "avr32_add_shift_immediate_operand" mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ku02\")"))) mgl@1371: + mgl@1371: +(define_predicate "avr32_cond_register_immediate_operand" mgl@1371: + (ior (match_operand 0 "register_operand") mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")")))) mgl@1371: + mgl@1371: +(define_predicate "avr32_cond_immediate_operand" mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'I', \"Is08\")"))) mgl@1371: + mgl@1371: + mgl@1371: +(define_predicate "avr32_cond_move_operand" mgl@1371: + (ior (ior (match_operand 0 "register_operand") mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks08\")"))) mgl@1371: + (and (match_test "TARGET_V2_INSNS") mgl@1371: + (match_operand 0 "memory_operand")))) mgl@1371: + mgl@1371: +(define_predicate "avr32_mov_immediate_operand" mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "avr32_const_ok_for_move(INTVAL(op))"))) mgl@1371: + mgl@1371: + mgl@1371: +(define_predicate "avr32_rmw_address_operand" mgl@1371: + (ior (and (match_code "symbol_ref") mgl@1371: + (match_test "({rtx symbol = avr32_find_symbol(op); \ mgl@1371: + symbol && (GET_CODE (symbol) == SYMBOL_REF) && SYMBOL_REF_RMW_ADDR(symbol);})")) mgl@1371: + (and (match_operand 0 "immediate_operand") mgl@1371: + (match_test "CONST_OK_FOR_CONSTRAINT_P(INTVAL(op), 'K', \"Ks17\")"))) mgl@1371: + { mgl@1371: + return TARGET_RMW && !flag_pic; mgl@1371: + } mgl@1371: +) mgl@1371: + mgl@1371: +(define_predicate "avr32_rmw_memory_operand" mgl@1371: + (and (match_code "mem") mgl@1371: + (match_test "(GET_MODE(op) == SImode) && mgl@1371: + avr32_rmw_address_operand(XEXP(op, 0), GET_MODE(XEXP(op, 0)))"))) mgl@1371: + mgl@1371: +(define_predicate "avr32_rmw_memory_or_register_operand" mgl@1371: + (ior (match_operand 0 "avr32_rmw_memory_operand") mgl@1371: + (match_operand 0 "register_operand"))) mgl@1371: + mgl@1371: +(define_predicate "avr32_non_rmw_memory_operand" mgl@1371: + (and (not (match_operand 0 "avr32_rmw_memory_operand")) mgl@1371: + (match_operand 0 "memory_operand"))) mgl@1371: + mgl@1371: +(define_predicate "avr32_non_rmw_general_operand" mgl@1371: + (and (not (match_operand 0 "avr32_rmw_memory_operand")) mgl@1371: + (match_operand 0 "general_operand"))) mgl@1371: + mgl@1371: +(define_predicate "avr32_non_rmw_nonimmediate_operand" mgl@1371: + (and (not (match_operand 0 "avr32_rmw_memory_operand")) mgl@1371: + (match_operand 0 "nonimmediate_operand"))) mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/simd.md mgl@1371: @@ -0,0 +1,145 @@ mgl@1371: +;; AVR32 machine description file for SIMD instructions. mgl@1371: +;; Copyright 2003-2006 Atmel Corporation. mgl@1371: +;; mgl@1371: +;; Written by Ronny Pedersen, Atmel Norway, mgl@1371: +;; mgl@1371: +;; This file is part of GCC. mgl@1371: +;; mgl@1371: +;; This program is free software; you can redistribute it and/or modify mgl@1371: +;; it under the terms of the GNU General Public License as published by mgl@1371: +;; the Free Software Foundation; either version 2 of the License, or mgl@1371: +;; (at your option) any later version. mgl@1371: +;; mgl@1371: +;; This program is distributed in the hope that it will be useful, mgl@1371: +;; but WITHOUT ANY WARRANTY; without even the implied warranty of mgl@1371: +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the mgl@1371: +;; GNU General Public License for more details. mgl@1371: +;; mgl@1371: +;; You should have received a copy of the GNU General Public License mgl@1371: +;; along with this program; if not, write to the Free Software mgl@1371: +;; Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. mgl@1371: + mgl@1371: +;; -*- Mode: Scheme -*- mgl@1371: + mgl@1371: + mgl@1371: +;; Vector modes mgl@1371: +(define_mode_macro VECM [V2HI V4QI]) mgl@1371: +(define_mode_attr size [(V2HI "h") (V4QI "b")]) mgl@1371: + mgl@1371: +(define_insn "add3" mgl@1371: + [(set (match_operand:VECM 0 "register_operand" "=r") mgl@1371: + (plus:VECM (match_operand:VECM 1 "register_operand" "r") mgl@1371: + (match_operand:VECM 2 "register_operand" "r")))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "padd.\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "sub3" mgl@1371: + [(set (match_operand:VECM 0 "register_operand" "=r") mgl@1371: + (minus:VECM (match_operand:VECM 1 "register_operand" "r") mgl@1371: + (match_operand:VECM 2 "register_operand" "r")))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "psub.\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "abs2" mgl@1371: + [(set (match_operand:VECM 0 "register_operand" "=r") mgl@1371: + (abs:VECM (match_operand:VECM 1 "register_operand" "r")))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "pabs.s\t%0, %1" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "ashl3" mgl@1371: + [(set (match_operand:VECM 0 "register_operand" "=r") mgl@1371: + (ashift:VECM (match_operand:VECM 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku04")))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "plsl.\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "ashr3" mgl@1371: + [(set (match_operand:VECM 0 "register_operand" "=r") mgl@1371: + (ashiftrt:VECM (match_operand:VECM 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku04")))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "pasr.\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "lshr3" mgl@1371: + [(set (match_operand:VECM 0 "register_operand" "=r") mgl@1371: + (lshiftrt:VECM (match_operand:VECM 1 "register_operand" "r") mgl@1371: + (match_operand:SI 2 "immediate_operand" "Ku04")))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "plsr.\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "smaxv2hi3" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "=r") mgl@1371: + (smax:V2HI (match_operand:V2HI 1 "register_operand" "r") mgl@1371: + (match_operand:V2HI 2 "register_operand" "r")))] mgl@1371: + mgl@1371: + "TARGET_SIMD" mgl@1371: + "pmax.sh\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "sminv2hi3" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "=r") mgl@1371: + (smin:V2HI (match_operand:V2HI 1 "register_operand" "r") mgl@1371: + (match_operand:V2HI 2 "register_operand" "r")))] mgl@1371: + mgl@1371: + "TARGET_SIMD" mgl@1371: + "pmin.sh\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "umaxv4qi3" mgl@1371: + [(set (match_operand:V4QI 0 "register_operand" "=r") mgl@1371: + (umax:V4QI (match_operand:V4QI 1 "register_operand" "r") mgl@1371: + (match_operand:V4QI 2 "register_operand" "r")))] mgl@1371: + mgl@1371: + "TARGET_SIMD" mgl@1371: + "pmax.ub\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "uminv4qi3" mgl@1371: + [(set (match_operand:V4QI 0 "register_operand" "=r") mgl@1371: + (umin:V4QI (match_operand:V4QI 1 "register_operand" "r") mgl@1371: + (match_operand:V4QI 2 "register_operand" "r")))] mgl@1371: + mgl@1371: + "TARGET_SIMD" mgl@1371: + "pmin.ub\t%0, %1, %2" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "addsubv2hi" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "=r") mgl@1371: + (vec_concat:V2HI mgl@1371: + (plus:HI (match_operand:HI 1 "register_operand" "r") mgl@1371: + (match_operand:HI 2 "register_operand" "r")) mgl@1371: + (minus:HI (match_dup 1) (match_dup 2))))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "paddsub.h\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: + mgl@1371: +(define_insn "subaddv2hi" mgl@1371: + [(set (match_operand:V2HI 0 "register_operand" "=r") mgl@1371: + (vec_concat:V2HI mgl@1371: + (minus:HI (match_operand:HI 1 "register_operand" "r") mgl@1371: + (match_operand:HI 2 "register_operand" "r")) mgl@1371: + (plus:HI (match_dup 1) (match_dup 2))))] mgl@1371: + "TARGET_SIMD" mgl@1371: + "psubadd.h\t%0, %1:b, %2:b" mgl@1371: + [(set_attr "length" "4") mgl@1371: + (set_attr "type" "alu")]) mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/sync.md mgl@1371: @@ -0,0 +1,244 @@ mgl@1371: +;;================================================================= mgl@1371: +;; Atomic operations mgl@1371: +;;================================================================= mgl@1371: + mgl@1371: + mgl@1371: +(define_insn "sync_compare_and_swapsi" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=&r,&r") mgl@1371: + (match_operand:SI 1 "memory_operand" "+RKs16,+RKs16")) mgl@1371: + (set (match_dup 1) mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_dup 1) mgl@1371: + (match_operand:SI 2 "register_immediate_operand" "r,Ks21") mgl@1371: + (match_operand:SI 3 "register_operand" "r,r")] mgl@1371: + VUNSPEC_SYNC_CMPXCHG)) ] mgl@1371: + "" mgl@1371: + "0: mgl@1371: + ssrf\t5 mgl@1371: + ld.w\t%0,%1 mgl@1371: + cp.w\t%0,%2 mgl@1371: + brne\t0f mgl@1371: + stcond\t%1, %3 mgl@1371: + brne\t0b mgl@1371: + 0: mgl@1371: + " mgl@1371: + [(set_attr "length" "16,18") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_code_macro atomic_op [plus minus and ior xor]) mgl@1371: +(define_code_attr atomic_asm_insn [(plus "add") (minus "sub") (and "and") (ior "or") (xor "eor")]) mgl@1371: +(define_code_attr atomic_insn [(plus "add") (minus "sub") (and "and") (ior "ior") (xor "xor")]) mgl@1371: + mgl@1371: +(define_insn "sync_loadsi" mgl@1371: + ; NB! Put an early clobber on the destination operand to mgl@1371: + ; avoid gcc using the same register in the source and mgl@1371: + ; destination. This is done in order to avoid gcc to mgl@1371: + ; clobber the source operand since these instructions mgl@1371: + ; are actually inside a "loop". mgl@1371: + [(set (match_operand:SI 0 "register_operand" "=&r") mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_operand:SI 1 "avr32_ks16_memory_operand" "RKs16") mgl@1371: + (label_ref (match_operand 2 "" ""))] mgl@1371: + VUNSPEC_SYNC_SET_LOCK_AND_LOAD) )] mgl@1371: + "" mgl@1371: + "%2: mgl@1371: + ssrf\t5 mgl@1371: + ld.w\t%0,%1" mgl@1371: + [(set_attr "length" "6") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: +(define_insn "sync_store_if_lock" mgl@1371: + [(set (match_operand:SI 0 "avr32_ks16_memory_operand" "=RKs16") mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_operand:SI 1 "register_operand" "r") mgl@1371: + (label_ref (match_operand 2 "" ""))] mgl@1371: + VUNSPEC_SYNC_STORE_IF_LOCK) )] mgl@1371: + "" mgl@1371: + "stcond\t%0, %1 mgl@1371: + brne\t%2" mgl@1371: + [(set_attr "length" "6") mgl@1371: + (set_attr "cc" "clobber")] mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "sync_si" mgl@1371: + [(set (match_dup 2) mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_operand:SI 0 "avr32_ks16_memory_operand" "") mgl@1371: + (match_dup 3)] mgl@1371: + VUNSPEC_SYNC_SET_LOCK_AND_LOAD)) mgl@1371: + (set (match_dup 2) mgl@1371: + (atomic_op:SI (match_dup 2) mgl@1371: + (match_operand:SI 1 "register_immediate_operand" ""))) mgl@1371: + (set (match_dup 0) mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_dup 2) mgl@1371: + (match_dup 3)] mgl@1371: + VUNSPEC_SYNC_STORE_IF_LOCK) ) mgl@1371: + (use (match_dup 1)) mgl@1371: + (use (match_dup 4))] mgl@1371: + "" mgl@1371: + { mgl@1371: + rtx *mem_expr = &operands[0]; mgl@1371: + rtx ptr_reg; mgl@1371: + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) ) mgl@1371: + { mgl@1371: + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0)); mgl@1371: + XEXP (*mem_expr, 0) = ptr_reg; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + rtx address = XEXP (*mem_expr, 0); mgl@1371: + if ( REG_P (address) ) mgl@1371: + ptr_reg = address; mgl@1371: + else if ( REG_P (XEXP (address, 0)) ) mgl@1371: + ptr_reg = XEXP (address, 0); mgl@1371: + else mgl@1371: + ptr_reg = XEXP (address, 1); mgl@1371: + } mgl@1371: + mgl@1371: + operands[2] = gen_reg_rtx (SImode); mgl@1371: + operands[3] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ()); mgl@1371: + operands[4] = ptr_reg; mgl@1371: + mgl@1371: + } mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +(define_expand "sync_old_si" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_operand:SI 1 "avr32_ks16_memory_operand" "") mgl@1371: + (match_dup 4)] mgl@1371: + VUNSPEC_SYNC_SET_LOCK_AND_LOAD)) mgl@1371: + (set (match_dup 3) mgl@1371: + (atomic_op:SI (match_dup 0) mgl@1371: + (match_operand:SI 2 "register_immediate_operand" ""))) mgl@1371: + (set (match_dup 1) mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_dup 3) mgl@1371: + (match_dup 4)] mgl@1371: + VUNSPEC_SYNC_STORE_IF_LOCK) ) mgl@1371: + (use (match_dup 2)) mgl@1371: + (use (match_dup 5))] mgl@1371: + "" mgl@1371: + { mgl@1371: + rtx *mem_expr = &operands[1]; mgl@1371: + rtx ptr_reg; mgl@1371: + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) ) mgl@1371: + { mgl@1371: + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0)); mgl@1371: + XEXP (*mem_expr, 0) = ptr_reg; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + rtx address = XEXP (*mem_expr, 0); mgl@1371: + if ( REG_P (address) ) mgl@1371: + ptr_reg = address; mgl@1371: + else if ( REG_P (XEXP (address, 0)) ) mgl@1371: + ptr_reg = XEXP (address, 0); mgl@1371: + else mgl@1371: + ptr_reg = XEXP (address, 1); mgl@1371: + } mgl@1371: + mgl@1371: + operands[3] = gen_reg_rtx (SImode); mgl@1371: + operands[4] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ()); mgl@1371: + operands[5] = ptr_reg; mgl@1371: + } mgl@1371: + ) mgl@1371: + mgl@1371: +(define_expand "sync_new_si" mgl@1371: + [(set (match_operand:SI 0 "register_operand" "") mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_operand:SI 1 "avr32_ks16_memory_operand" "") mgl@1371: + (match_dup 3)] mgl@1371: + VUNSPEC_SYNC_SET_LOCK_AND_LOAD)) mgl@1371: + (set (match_dup 0) mgl@1371: + (atomic_op:SI (match_dup 0) mgl@1371: + (match_operand:SI 2 "register_immediate_operand" ""))) mgl@1371: + (set (match_dup 1) mgl@1371: + (unspec_volatile:SI mgl@1371: + [(match_dup 0) mgl@1371: + (match_dup 3)] mgl@1371: + VUNSPEC_SYNC_STORE_IF_LOCK) ) mgl@1371: + (use (match_dup 2)) mgl@1371: + (use (match_dup 4))] mgl@1371: + "" mgl@1371: + { mgl@1371: + rtx *mem_expr = &operands[1]; mgl@1371: + rtx ptr_reg; mgl@1371: + if ( !avr32_ks16_memory_operand (*mem_expr, GET_MODE (*mem_expr)) ) mgl@1371: + { mgl@1371: + ptr_reg = force_reg (Pmode, XEXP (*mem_expr, 0)); mgl@1371: + XEXP (*mem_expr, 0) = ptr_reg; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + rtx address = XEXP (*mem_expr, 0); mgl@1371: + if ( REG_P (address) ) mgl@1371: + ptr_reg = address; mgl@1371: + else if ( REG_P (XEXP (address, 0)) ) mgl@1371: + ptr_reg = XEXP (address, 0); mgl@1371: + else mgl@1371: + ptr_reg = XEXP (address, 1); mgl@1371: + } mgl@1371: + mgl@1371: + operands[3] = gen_rtx_LABEL_REF(Pmode, gen_label_rtx ()); mgl@1371: + operands[4] = ptr_reg; mgl@1371: + } mgl@1371: + ) mgl@1371: + mgl@1371: + mgl@1371: +;(define_insn "sync_si" mgl@1371: +; [(set (match_operand:SI 0 "memory_operand" "+RKs16") mgl@1371: +; (unspec_volatile:SI mgl@1371: +; [(atomic_op:SI (match_dup 0) mgl@1371: +; (match_operand:SI 1 "register_operand" "r"))] mgl@1371: +; VUNSPEC_SYNC_CMPXCHG)) mgl@1371: +; (clobber (match_scratch:SI 2 "=&r"))] mgl@1371: +; "" mgl@1371: +; "0: mgl@1371: +; ssrf\t5 mgl@1371: +; ld.w\t%2,%0 mgl@1371: +; \t%2,%1 mgl@1371: +; stcond\t%0, %2 mgl@1371: +; brne\t0b mgl@1371: +; " mgl@1371: +; [(set_attr "length" "14") mgl@1371: +; (set_attr "cc" "clobber")] mgl@1371: +; ) mgl@1371: +; mgl@1371: +;(define_insn "sync_new_si" mgl@1371: +; [(set (match_operand:SI 1 "memory_operand" "+RKs16") mgl@1371: +; (unspec_volatile:SI mgl@1371: +; [(atomic_op:SI (match_dup 1) mgl@1371: +; (match_operand:SI 2 "register_operand" "r"))] mgl@1371: +; VUNSPEC_SYNC_CMPXCHG)) mgl@1371: +; (set (match_operand:SI 0 "register_operand" "=&r") mgl@1371: +; (atomic_op:SI (match_dup 1) mgl@1371: +; (match_dup 2)))] mgl@1371: +; "" mgl@1371: +; "0: mgl@1371: +; ssrf\t5 mgl@1371: +; ld.w\t%0,%1 mgl@1371: +; \t%0,%2 mgl@1371: +; stcond\t%1, %0 mgl@1371: +; brne\t0b mgl@1371: +; " mgl@1371: +; [(set_attr "length" "14") mgl@1371: +; (set_attr "cc" "clobber")] mgl@1371: +; ) mgl@1371: + mgl@1371: +(define_insn "sync_lock_test_and_setsi" mgl@1371: + [ (set (match_operand:SI 0 "register_operand" "=&r") mgl@1371: + (match_operand:SI 1 "memory_operand" "+RKu00")) mgl@1371: + (set (match_dup 1) mgl@1371: + (match_operand:SI 2 "register_operand" "r")) ] mgl@1371: + "" mgl@1371: + "xchg\t%0, %p1, %2" mgl@1371: + [(set_attr "length" "4")] mgl@1371: + ) mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/t-avr32 mgl@1371: @@ -0,0 +1,77 @@ mgl@1371: + mgl@1371: +MD_INCLUDES= $(srcdir)/config/avr32/avr32.md \ mgl@1371: + $(srcdir)/config/avr32/sync.md \ mgl@1371: + $(srcdir)/config/avr32/fpcp.md \ mgl@1371: + $(srcdir)/config/avr32/simd.md \ mgl@1371: + $(srcdir)/config/avr32/predicates.md mgl@1371: + mgl@1371: +s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \ mgl@1371: + s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES) mgl@1371: + mgl@1371: +# We want fine grained libraries, so use the new code mgl@1371: +# to build the floating point emulation libraries. mgl@1371: +FPBIT = fp-bit.c mgl@1371: +DPBIT = dp-bit.c mgl@1371: + mgl@1371: +LIB1ASMSRC = avr32/lib1funcs.S mgl@1371: +LIB1ASMFUNCS = _avr32_f64_mul _avr32_f64_mul_fast _avr32_f64_addsub _avr32_f64_addsub_fast _avr32_f64_to_u32 \ mgl@1371: + _avr32_f64_to_s32 _avr32_f64_to_u64 _avr32_f64_to_s64 _avr32_u32_to_f64 \ mgl@1371: + _avr32_s32_to_f64 _avr32_f64_cmp_eq _avr32_f64_cmp_ge _avr32_f64_cmp_lt \ mgl@1371: + _avr32_f32_cmp_eq _avr32_f32_cmp_ge _avr32_f32_cmp_lt _avr32_f64_div _avr32_f64_div_fast \ mgl@1371: + _avr32_f32_div _avr32_f32_div_fast _avr32_f32_addsub _avr32_f32_addsub_fast \ mgl@1371: + _avr32_f32_mul _avr32_s32_to_f32 _avr32_u32_to_f32 _avr32_f32_to_s32 \ mgl@1371: + _avr32_f32_to_u32 _avr32_f32_to_f64 _avr32_f64_to_f32 _mulsi3 mgl@1371: + mgl@1371: +#LIB2FUNCS_EXTRA += $(srcdir)/config/avr32/lib2funcs.S mgl@1371: + mgl@1371: +MULTILIB_OPTIONS = march=ap/march=ucr1/march=ucr2/march=ucr2nomul mgl@1371: +MULTILIB_DIRNAMES = ap ucr1 ucr2 ucr2nomul mgl@1371: +MULTILIB_EXCEPTIONS = mgl@1371: +MULTILIB_MATCHES += march?ap=mpart?ap7000 mgl@1371: +MULTILIB_MATCHES += march?ap=mpart?ap7001 mgl@1371: +MULTILIB_MATCHES += march?ap=mpart?ap7002 mgl@1371: +MULTILIB_MATCHES += march?ap=mpart?ap7200 mgl@1371: +MULTILIB_MATCHES += march?ucr1=march?uc mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3a0512es mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0128 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0256 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a0512 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1128 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1256 mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3a1512es mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a1512 mgl@1371: +MULTILIB_MATCHES += march?ucr2nomul=mpart?uc3a3revd mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a364s mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3128s mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256 mgl@1371: +MULTILIB_MATCHES += march?ucr2=mpart?uc3a3256s mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b064 mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0128 mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256es mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b0256 mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b164 mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1128 mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256es mgl@1371: +MULTILIB_MATCHES += march?ucr1=mpart?uc3b1256 mgl@1371: + mgl@1371: + mgl@1371: +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o crti.o crtn.o mgl@1371: + mgl@1371: +CRTSTUFF_T_CFLAGS = -mrelax mgl@1371: +CRTSTUFF_T_CFLAGS_S = -mrelax -fPIC mgl@1371: +TARGET_LIBGCC2_CFLAGS += -mrelax mgl@1371: + mgl@1371: +LIBGCC = stmp-multilib mgl@1371: +INSTALL_LIBGCC = install-multilib mgl@1371: + mgl@1371: +fp-bit.c: $(srcdir)/config/fp-bit.c mgl@1371: + echo '#define FLOAT' > fp-bit.c mgl@1371: + cat $(srcdir)/config/fp-bit.c >> fp-bit.c mgl@1371: + mgl@1371: +dp-bit.c: $(srcdir)/config/fp-bit.c mgl@1371: + cat $(srcdir)/config/fp-bit.c > dp-bit.c mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/t-elf mgl@1371: @@ -0,0 +1,16 @@ mgl@1371: + mgl@1371: +# Assemble startup files. mgl@1371: +$(T)crti.o: $(srcdir)/config/avr32/crti.asm $(GCC_PASSES) mgl@1371: + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) $(INCLUDES) \ mgl@1371: + -c -o $(T)crti.o -x assembler-with-cpp $(srcdir)/config/avr32/crti.asm mgl@1371: + mgl@1371: +$(T)crtn.o: $(srcdir)/config/avr32/crtn.asm $(GCC_PASSES) mgl@1371: + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) $(INCLUDES) \ mgl@1371: + -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/avr32/crtn.asm mgl@1371: + mgl@1371: + mgl@1371: +# Build the libraries for both hard and soft floating point mgl@1371: +EXTRA_MULTILIB_PARTS = crtbegin.o crtbeginS.o crtend.o crtendS.o crti.o crtn.o mgl@1371: + mgl@1371: +LIBGCC = stmp-multilib mgl@1371: +INSTALL_LIBGCC = install-multilib mgl@1371: --- /dev/null mgl@1371: +++ b/gcc/config/avr32/uclinux-elf.h mgl@1371: @@ -0,0 +1,20 @@ mgl@1371: + mgl@1371: +/* Run-time Target Specification. */ mgl@1371: +#undef TARGET_VERSION mgl@1371: +#define TARGET_VERSION fputs (" (AVR32 uClinux with ELF)", stderr) mgl@1371: + mgl@1371: +/* We don't want a .jcr section on uClinux. As if this makes a difference... */ mgl@1371: +#define TARGET_USE_JCR_SECTION 0 mgl@1371: + mgl@1371: +/* Here we go. Drop the crtbegin/crtend stuff completely. */ mgl@1371: +#undef STARTFILE_SPEC mgl@1371: +#define STARTFILE_SPEC \ mgl@1371: + "%{!shared: %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s}" \ mgl@1371: + " %{!p:%{profile:gcrt1.o%s}" \ mgl@1371: + " %{!profile:crt1.o%s}}}} crti.o%s" mgl@1371: + mgl@1371: +#undef ENDFILE_SPEC mgl@1371: +#define ENDFILE_SPEC "crtn.o%s" mgl@1371: + mgl@1371: +#undef TARGET_DEFAULT mgl@1371: +#define TARGET_DEFAULT (AVR32_FLAG_NO_INIT_GOT) mgl@1371: --- a/gcc/config/host-linux.c mgl@1371: +++ b/gcc/config/host-linux.c mgl@1371: @@ -25,6 +25,9 @@ mgl@1371: #include "hosthooks.h" mgl@1371: #include "hosthooks-def.h" mgl@1371: mgl@1371: +#ifndef SSIZE_MAX mgl@1371: +#define SSIZE_MAX LONG_MAX mgl@1371: +#endif mgl@1371: mgl@1371: /* Linux has a feature called exec-shield-randomize that perturbs the mgl@1371: address of non-fixed mapped segments by a (relatively) small amount. mgl@1371: --- a/gcc/config.gcc mgl@1371: +++ b/gcc/config.gcc mgl@1371: @@ -781,6 +781,24 @@ avr-*-*) mgl@1371: tm_file="avr/avr.h dbxelf.h" mgl@1371: use_fixproto=yes mgl@1371: ;; mgl@1371: +avr32*-*-linux*) mgl@1371: + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/avr32.h " mgl@1371: + tmake_file="t-linux avr32/t-avr32 avr32/t-elf" mgl@1371: + extra_parts="crtbegin.o crtbeginS.o crtend.o crtendS.o" mgl@1371: + extra_modes=avr32/avr32-modes.def mgl@1371: + gnu_ld=yes mgl@1371: + ;; mgl@1371: +avr32*-*-uclinux*) mgl@1371: + tm_file="dbxelf.h elfos.h linux.h avr32/linux-elf.h avr32/uclinux-elf.h avr32/avr32.h" mgl@1371: + tmake_file="t-linux avr32/t-avr32 avr32/t-elf" mgl@1371: + extra_modes=avr32/avr32-modes.def mgl@1371: + gnu_ld=yes mgl@1371: + ;; mgl@1371: +avr32-*-*) mgl@1371: + tm_file="dbxelf.h elfos.h avr32/avr32.h avr32/avr32-elf.h" mgl@1371: + tmake_file="avr32/t-avr32 avr32/t-elf" mgl@1371: + extra_modes=avr32/avr32-modes.def mgl@1371: + ;; mgl@1371: bfin*-elf*) mgl@1371: tm_file="${tm_file} dbxelf.h elfos.h bfin/elf.h" mgl@1371: tmake_file=bfin/t-bfin-elf mgl@1371: @@ -1681,6 +1699,9 @@ pdp11-*-bsd) mgl@1371: pdp11-*-*) mgl@1371: use_fixproto=yes mgl@1371: ;; mgl@1371: +avr-*-*) mgl@1371: + use_fixproto=yes mgl@1371: + ;; mgl@1371: # port not yet contributed mgl@1371: #powerpc-*-openbsd*) mgl@1371: # tmake_file="${tmake_file} rs6000/t-fprules rs6000/t-fprules-fpbit " mgl@1371: @@ -2717,6 +2738,32 @@ case "${target}" in mgl@1371: fi mgl@1371: ;; mgl@1371: mgl@1371: + avr32*-*-*) mgl@1371: + supported_defaults="part arch" mgl@1371: + mgl@1371: + case "$with_part" in mgl@1371: + "" \ mgl@1371: + | "ap7000" | "ap7010" | "ap7020" | "uc3a0256" | "uc3a0512" | "uc3a1128" | "uc3a1256" | "uc3a1512" ) mgl@1371: + # OK mgl@1371: + ;; mgl@1371: + *) mgl@1371: + echo "Unknown part used in --with-part=$with_part" 1>&2 mgl@1371: + exit 1 mgl@1371: + ;; mgl@1371: + esac mgl@1371: + mgl@1371: + case "$with_arch" in mgl@1371: + "" \ mgl@1371: + | "ap" | "uc") mgl@1371: + # OK mgl@1371: + ;; mgl@1371: + *) mgl@1371: + echo "Unknown arch used in --with-arch=$with_arch" 1>&2 mgl@1371: + exit 1 mgl@1371: + ;; mgl@1371: + esac mgl@1371: + ;; mgl@1371: + mgl@1371: fr*-*-*linux*) mgl@1371: supported_defaults=cpu mgl@1371: case "$with_cpu" in mgl@1371: --- a/gcc/doc/extend.texi mgl@1371: +++ b/gcc/doc/extend.texi mgl@1371: @@ -1981,7 +1981,7 @@ this attribute to work correctly. mgl@1371: mgl@1371: @item interrupt mgl@1371: @cindex interrupt handler functions mgl@1371: -Use this attribute on the ARM, AVR, C4x, CRX, M32C, M32R/D, MS1, and Xstormy16 mgl@1371: +Use this attribute on the ARM, AVR, AVR32, C4x, CRX, M32C, M32R/D, MS1, and Xstormy16 mgl@1371: ports to indicate that the specified function is an interrupt handler. mgl@1371: The compiler will generate function entry and exit sequences suitable mgl@1371: for use in an interrupt handler when this attribute is present. mgl@1371: @@ -2000,6 +2000,15 @@ void f () __attribute__ ((interrupt ("IR mgl@1371: mgl@1371: Permissible values for this parameter are: IRQ, FIQ, SWI, ABORT and UNDEF@. mgl@1371: mgl@1371: +Note, for the AVR32, you can specify which banking scheme is used for mgl@1371: +the interrupt mode this interrupt handler is used in like this: mgl@1371: + mgl@1371: +@smallexample mgl@1371: +void f () __attribute__ ((interrupt ("FULL"))); mgl@1371: +@end smallexample mgl@1371: + mgl@1371: +Permissible values for this parameter are: FULL, HALF, NONE and UNDEF. mgl@1371: + mgl@1371: @item interrupt_handler mgl@1371: @cindex interrupt handler functions on the Blackfin, m68k, H8/300 and SH processors mgl@1371: Use this attribute on the Blackfin, m68k, H8/300, H8/300H, H8S, and SH to mgl@1371: @@ -3460,6 +3469,23 @@ placed in either the @code{.bss_below100 mgl@1371: mgl@1371: @end table mgl@1371: mgl@1371: +@subsection AVR32 Variable Attributes mgl@1371: + mgl@1371: +One attribute is currently defined for AVR32 configurations: mgl@1371: +@code{rmw_addressable} mgl@1371: + mgl@1371: +@table @code mgl@1371: +@item rmw_addressable mgl@1371: +@cindex @code{rmw_addressable} attribute mgl@1371: + mgl@1371: +This attribute can be used to signal that a variable can be accessed mgl@1371: +with the addressing mode of the AVR32 Atomic Read-Modify-Write memory mgl@1371: +instructions and hence make it possible for gcc to generate these mgl@1371: +instructions without using built-in functions or inline assembly statements. mgl@1371: +Variables used within the AVR32 Atomic Read-Modify-Write built-in mgl@1371: +functions will automatically get the @code{rmw_addressable} attribute. mgl@1371: +@end table mgl@1371: + mgl@1371: @node Type Attributes mgl@1371: @section Specifying Attributes of Types mgl@1371: @cindex attribute of types mgl@1371: @@ -6167,6 +6193,7 @@ instructions, but allow the compiler to mgl@1371: @menu mgl@1371: * Alpha Built-in Functions:: mgl@1371: * ARM Built-in Functions:: mgl@1371: +* AVR32 Built-in Functions:: mgl@1371: * Blackfin Built-in Functions:: mgl@1371: * FR-V Built-in Functions:: mgl@1371: * X86 Built-in Functions:: mgl@1371: @@ -6405,6 +6432,76 @@ long long __builtin_arm_wxor (long long, mgl@1371: long long __builtin_arm_wzero () mgl@1371: @end smallexample mgl@1371: mgl@1371: +@node AVR32 Built-in Functions mgl@1371: +@subsection AVR32 Built-in Functions mgl@1371: + mgl@1371: + mgl@1371: + mgl@1371: +Built-in functions for atomic memory (RMW) instructions. Note that these mgl@1371: +built-ins will fail for targets where the RMW instructions are not mgl@1371: +implemented. Also note that these instructions only that a Ks15 << 2 mgl@1371: +memory address and will therefor not work with any runtime computed mgl@1371: +memory addresses. The user is responsible for making sure that any mgl@1371: +pointers used within these functions points to a valid memory address. mgl@1371: + mgl@1371: +@smallexample mgl@1371: +void __builtin_mems(int */*ptr*/, int /*bit*/) mgl@1371: +void __builtin_memc(int */*ptr*/, int /*bit*/) mgl@1371: +void __builtin_memt(int */*ptr*/, int /*bit*/) mgl@1371: +@end smallexample mgl@1371: + mgl@1371: +Built-in functions for DSP instructions. Note that these built-ins will mgl@1371: +fail for targets where the DSP instructions are not implemented. mgl@1371: + mgl@1371: +@smallexample mgl@1371: +int __builtin_sats (int /*Rd*/,int /*sa*/, int /*bn*/) mgl@1371: +int __builtin_satu (int /*Rd*/,int /*sa*/, int /*bn*/) mgl@1371: +int __builtin_satrnds (int /*Rd*/,int /*sa*/, int /*bn*/) mgl@1371: +int __builtin_satrndu (int /*Rd*/,int /*sa*/, int /*bn*/) mgl@1371: +short __builtin_mulsathh_h (short, short) mgl@1371: +int __builtin_mulsathh_w (short, short) mgl@1371: +short __builtin_mulsatrndhh_h (short, short) mgl@1371: +int __builtin_mulsatrndwh_w (int, short) mgl@1371: +int __builtin_mulsatwh_w (int, short) mgl@1371: +int __builtin_macsathh_w (int, short, short) mgl@1371: +short __builtin_satadd_h (short, short) mgl@1371: +short __builtin_satsub_h (short, short) mgl@1371: +int __builtin_satadd_w (int, int) mgl@1371: +int __builtin_satsub_w (int, int) mgl@1371: +long long __builtin_mulwh_d(int, short) mgl@1371: +long long __builtin_mulnwh_d(int, short) mgl@1371: +long long __builtin_macwh_d(long long, int, short) mgl@1371: +long long __builtin_machh_d(long long, short, short) mgl@1371: +@end smallexample mgl@1371: + mgl@1371: +Other built-in functions for instructions that cannot easily be mgl@1371: +generated by the compiler. mgl@1371: + mgl@1371: +@smallexample mgl@1371: +void __builtin_ssrf(int); mgl@1371: +void __builtin_csrf(int); mgl@1371: +void __builtin_musfr(int); mgl@1371: +int __builtin_mustr(void); mgl@1371: +int __builtin_mfsr(int /*Status Register Address*/) mgl@1371: +void __builtin_mtsr(int /*Status Register Address*/, int /*Value*/) mgl@1371: +int __builtin_mfdr(int /*Debug Register Address*/) mgl@1371: +void __builtin_mtdr(int /*Debug Register Address*/, int /*Value*/) mgl@1371: +void __builtin_cache(void * /*Address*/, int /*Cache Operation*/) mgl@1371: +void __builtin_sync(int /*Sync Operation*/) mgl@1371: +void __builtin_tlbr(void) mgl@1371: +void __builtin_tlbs(void) mgl@1371: +void __builtin_tlbw(void) mgl@1371: +void __builtin_breakpoint(void) mgl@1371: +int __builtin_xchg(void * /*Address*/, int /*Value*/ ) mgl@1371: +short __builtin_bswap_16(short) mgl@1371: +int __builtin_bswap_32(int) mgl@1371: +void __builtin_cop(int/*cpnr*/, int/*crd*/, int/*crx*/, int/*cry*/, int/*op*/) mgl@1371: +int __builtin_mvcr_w(int/*cpnr*/, int/*crs*/) mgl@1371: +void __builtin_mvrc_w(int/*cpnr*/, int/*crd*/, int/*value*/) mgl@1371: +long long __builtin_mvcr_d(int/*cpnr*/, int/*crs*/) mgl@1371: +void __builtin_mvrc_d(int/*cpnr*/, int/*crd*/, long long/*value*/) mgl@1371: +@end smallexample mgl@1371: + mgl@1371: @node Blackfin Built-in Functions mgl@1371: @subsection Blackfin Built-in Functions mgl@1371: mgl@1371: --- a/gcc/doc/invoke.texi mgl@1371: +++ b/gcc/doc/invoke.texi mgl@1371: @@ -190,7 +190,7 @@ in the following sections. mgl@1371: -fno-default-inline -fvisibility-inlines-hidden @gol mgl@1371: -Wabi -Wctor-dtor-privacy @gol mgl@1371: -Wnon-virtual-dtor -Wreorder @gol mgl@1371: --Weffc++ -Wno-deprecated -Wstrict-null-sentinel @gol mgl@1371: +-Weffc++ -Wno-deprecated @gol mgl@1371: -Wno-non-template-friend -Wold-style-cast @gol mgl@1371: -Woverloaded-virtual -Wno-pmf-conversions @gol mgl@1371: -Wsign-promo} mgl@1371: @@ -588,6 +588,12 @@ Objective-C and Objective-C++ Dialects}. mgl@1371: -mauto-incdec -minmax -mlong-calls -mshort @gol mgl@1371: -msoft-reg-count=@var{count}} mgl@1371: mgl@1371: +@emph{AVR32 Options} mgl@1371: +@gccoptlist{-muse-rodata-section -mhard-float -msoft-float -mrelax @gol mgl@1371: +-mforce-double-align -mno-init-got -mrelax -mmd-reorg-opt -masm-addr-pseudos @gol mgl@1371: +-mpart=@var{part} -mcpu=@var{cpu} -march=@var{arch} @gol mgl@1371: +-mfast-float -mimm-in-const-pool} mgl@1371: + mgl@1371: @emph{MCore Options} mgl@1371: @gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol mgl@1371: -mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol mgl@1371: @@ -1868,14 +1874,6 @@ to filter out those warnings. mgl@1371: @opindex Wno-deprecated mgl@1371: Do not warn about usage of deprecated features. @xref{Deprecated Features}. mgl@1371: mgl@1371: -@item -Wstrict-null-sentinel @r{(C++ only)} mgl@1371: -@opindex Wstrict-null-sentinel mgl@1371: -Warn also about the use of an uncasted @code{NULL} as sentinel. When mgl@1371: -compiling only with GCC this is a valid sentinel, as @code{NULL} is defined mgl@1371: -to @code{__null}. Although it is a null pointer constant not a null pointer, mgl@1371: -it is guaranteed to of the same size as a pointer. But this use is mgl@1371: -not portable across different compilers. mgl@1371: - mgl@1371: @item -Wno-non-template-friend @r{(C++ only)} mgl@1371: @opindex Wno-non-template-friend mgl@1371: Disable warnings when non-templatized friend functions are declared mgl@1371: @@ -2732,13 +2730,11 @@ requiring @option{-O}. mgl@1371: If you want to warn about code which uses the uninitialized value of the mgl@1371: variable in its own initializer, use the @option{-Winit-self} option. mgl@1371: mgl@1371: -These warnings occur for individual uninitialized or clobbered mgl@1371: -elements of structure, union or array variables as well as for mgl@1371: -variables which are uninitialized or clobbered as a whole. They do mgl@1371: -not occur for variables or elements declared @code{volatile}. Because mgl@1371: -these warnings depend on optimization, the exact variables or elements mgl@1371: -for which there are warnings will depend on the precise optimization mgl@1371: -options and version of GCC used. mgl@1371: +These warnings occur only for variables that are candidates for mgl@1371: +register allocation. Therefore, they do not occur for a variable that mgl@1371: +is declared @code{volatile}, or whose address is taken, or whose size mgl@1371: +is other than 1, 2, 4 or 8 bytes. Also, they do not occur for mgl@1371: +structures, unions or arrays, even when they are in registers. mgl@1371: mgl@1371: Note that there may be no warning about a variable that is used only mgl@1371: to compute a value that itself is never used, because such mgl@1371: @@ -6201,10 +6197,6 @@ If number of candidates in the set is sm mgl@1371: we always try to remove unnecessary ivs from the set during its mgl@1371: optimization when a new iv is added to the set. mgl@1371: mgl@1371: -@item scev-max-expr-size mgl@1371: -Bound on size of expressions used in the scalar evolutions analyzer. mgl@1371: -Large expressions slow the analyzer. mgl@1371: - mgl@1371: @item vect-max-version-checks mgl@1371: The maximum number of runtime checks that can be performed when doing mgl@1371: loop versioning in the vectorizer. See option ftree-vect-loop-version mgl@1371: @@ -7402,7 +7394,7 @@ platform. mgl@1371: * ARC Options:: mgl@1371: * ARM Options:: mgl@1371: * AVR Options:: mgl@1371: -* Blackfin Options:: mgl@1371: +* AVR32 Options:: mgl@1371: * CRIS Options:: mgl@1371: * CRX Options:: mgl@1371: * Darwin Options:: mgl@1371: @@ -7867,81 +7859,80 @@ comply to the C standards, but it will p mgl@1371: size. mgl@1371: @end table mgl@1371: mgl@1371: -@node Blackfin Options mgl@1371: -@subsection Blackfin Options mgl@1371: -@cindex Blackfin Options mgl@1371: +@node AVR32 Options mgl@1371: +@subsection AVR32 Options mgl@1371: +@cindex AVR32 Options mgl@1371: + mgl@1371: +These options are defined for AVR32 implementations: mgl@1371: mgl@1371: @table @gcctabopt mgl@1371: -@item -momit-leaf-frame-pointer mgl@1371: -@opindex momit-leaf-frame-pointer mgl@1371: -Don't keep the frame pointer in a register for leaf functions. This mgl@1371: -avoids the instructions to save, set up and restore frame pointers and mgl@1371: -makes an extra register available in leaf functions. The option mgl@1371: -@option{-fomit-frame-pointer} removes the frame pointer for all functions mgl@1371: -which might make debugging harder. mgl@1371: +@item -muse-rodata-section mgl@1371: +@opindex muse-rodata-section mgl@1371: +Use section @samp{.rodata} for read-only data instead of @samp{.text}. mgl@1371: mgl@1371: -@item -mspecld-anomaly mgl@1371: -@opindex mspecld-anomaly mgl@1371: -When enabled, the compiler will ensure that the generated code does not mgl@1371: -contain speculative loads after jump instructions. This option is enabled mgl@1371: -by default. mgl@1371: - mgl@1371: -@item -mno-specld-anomaly mgl@1371: -@opindex mno-specld-anomaly mgl@1371: -Don't generate extra code to prevent speculative loads from occurring. mgl@1371: - mgl@1371: -@item -mcsync-anomaly mgl@1371: -@opindex mcsync-anomaly mgl@1371: -When enabled, the compiler will ensure that the generated code does not mgl@1371: -contain CSYNC or SSYNC instructions too soon after conditional branches. mgl@1371: -This option is enabled by default. mgl@1371: - mgl@1371: -@item -mno-csync-anomaly mgl@1371: -@opindex mno-csync-anomaly mgl@1371: -Don't generate extra code to prevent CSYNC or SSYNC instructions from mgl@1371: -occurring too soon after a conditional branch. mgl@1371: - mgl@1371: -@item -mlow-64k mgl@1371: -@opindex mlow-64k mgl@1371: -When enabled, the compiler is free to take advantage of the knowledge that mgl@1371: -the entire program fits into the low 64k of memory. mgl@1371: - mgl@1371: -@item -mno-low-64k mgl@1371: -@opindex mno-low-64k mgl@1371: -Assume that the program is arbitrarily large. This is the default. mgl@1371: +@item -mhard-float mgl@1371: +@opindex mhard-float mgl@1371: +Use floating point coprocessor instructions. mgl@1371: mgl@1371: -@item -mid-shared-library mgl@1371: -@opindex mid-shared-library mgl@1371: -Generate code that supports shared libraries via the library ID method. mgl@1371: -This allows for execute in place and shared libraries in an environment mgl@1371: -without virtual memory management. This option implies @option{-fPIC}. mgl@1371: +@item -msoft-float mgl@1371: +@opindex msoft-float mgl@1371: +Use software floating-point library for floating-point operations. mgl@1371: mgl@1371: -@item -mno-id-shared-library mgl@1371: -@opindex mno-id-shared-library mgl@1371: -Generate code that doesn't assume ID based shared libraries are being used. mgl@1371: -This is the default. mgl@1371: +@item -mforce-double-align mgl@1371: +@opindex mforce-double-align mgl@1371: +Force double-word alignment for double-word memory accesses. mgl@1371: + mgl@1371: +@item -mno-init-got mgl@1371: +@opindex mno-init-got mgl@1371: +Do not initialize the GOT register before using it when compiling PIC mgl@1371: +code. mgl@1371: mgl@1371: -@item -mshared-library-id=n mgl@1371: -@opindex mshared-library-id mgl@1371: -Specified the identification number of the ID based shared library being mgl@1371: -compiled. Specifying a value of 0 will generate more compact code, specifying mgl@1371: -other values will force the allocation of that number to the current mgl@1371: -library but is no more space or time efficient than omitting this option. mgl@1371: +@item -mrelax mgl@1371: +@opindex mrelax mgl@1371: +Let invoked assembler and linker do relaxing mgl@1371: +(Enabled by default when optimization level is >1). mgl@1371: +This means that when the address of symbols are known at link time, mgl@1371: +the linker can optimize @samp{icall} and @samp{mcall} mgl@1371: +instructions into a @samp{rcall} instruction if possible. mgl@1371: +Loading the address of a symbol can also be optimized. mgl@1371: + mgl@1371: +@item -mmd-reorg-opt mgl@1371: +@opindex mmd-reorg-opt mgl@1371: +Perform machine dependent optimizations in reorg stage. mgl@1371: + mgl@1371: +@item -masm-addr-pseudos mgl@1371: +@opindex masm-addr-pseudos mgl@1371: +Use assembler pseudo-instructions lda.w and call for handling direct mgl@1371: +addresses. (Enabled by default) mgl@1371: + mgl@1371: +@item -mpart=@var{part} mgl@1371: +@opindex mpart mgl@1371: +Generate code for the specified part. Permissible parts are: mgl@1371: +@samp{ap7000}, @samp{ap7010},@samp{ap7020}, mgl@1371: +@samp{uc3a0128}, @samp{uc3a0256}, @samp{uc3a0512}, mgl@1371: +@samp{uc3a1128}, @samp{uc3a1256}, @samp{uc3a1512}, mgl@1371: +@samp{uc3b064}, @samp{uc3b0128}, @samp{uc3b0256}, mgl@1371: +@samp{uc3b164}, @samp{uc3b1128}, @samp{uc3b1256}. mgl@1371: mgl@1371: -@item -mlong-calls mgl@1371: -@itemx -mno-long-calls mgl@1371: -@opindex mlong-calls mgl@1371: -@opindex mno-long-calls mgl@1371: -Tells the compiler to perform function calls by first loading the mgl@1371: -address of the function into a register and then performing a subroutine mgl@1371: -call on this register. This switch is needed if the target function mgl@1371: -will lie outside of the 24 bit addressing range of the offset based mgl@1371: -version of subroutine call instruction. mgl@1371: +@item -mcpu=@var{cpu-type} mgl@1371: +@opindex mcpu mgl@1371: +Same as -mpart. Obsolete. mgl@1371: + mgl@1371: +@item -march=@var{arch} mgl@1371: +@opindex march mgl@1371: +Generate code for the specified architecture. Permissible architectures are: mgl@1371: +@samp{ap} and @samp{uc}. mgl@1371: + mgl@1371: +@item -mfast-float mgl@1371: +@opindex mfast-float mgl@1371: +Enable fast floating-point library that does not conform to ieee but is still good enough mgl@1371: +for most applications. The fast floating-point library does not round to the nearest even mgl@1371: +but away from zero. Enabled by default if the -funsafe-math-optimizations switch is specified. mgl@1371: + mgl@1371: +@item -mimm-in-const-pool mgl@1371: +@opindex mimm-in-const-pool mgl@1371: +Put large immediates in constant pool. This is enabled by default for archs with insn-cache. mgl@1371: mgl@1371: -This feature is not enabled by default. Specifying mgl@1371: -@option{-mno-long-calls} will restore the default behavior. Note these mgl@1371: -switches have no effect on how the compiler generates code to handle mgl@1371: -function calls via function pointers. mgl@1371: @end table mgl@1371: mgl@1371: @node CRIS Options mgl@1371: --- a/gcc/doc/md.texi mgl@1371: +++ b/gcc/doc/md.texi mgl@1371: @@ -1681,6 +1681,80 @@ A memory reference suitable for iWMMXt l mgl@1371: A memory reference suitable for the ARMv4 ldrsb instruction. mgl@1371: @end table mgl@1371: mgl@1371: +@item AVR32 family---@file{avr32.h} mgl@1371: +@table @code mgl@1371: +@item f mgl@1371: +Floating-point registers (f0 to f15) (Reserved for future use) mgl@1371: + mgl@1371: +@item Ku@var{bits} mgl@1371: +Unsigned constant representable with @var{bits} number of bits (Must be mgl@1371: +two digits). I.e: An unsigned 8-bit constant is written as @samp{Ku08} mgl@1371: + mgl@1371: +@item Ks@var{bits} mgl@1371: +Signed constant representable with @var{bits} number of bits (Must be mgl@1371: +two digits). I.e: A signed 12-bit constant is written as @samp{Ks12} mgl@1371: + mgl@1371: +@item Is@var{bits} mgl@1371: +The negated range of a signed constant representable with @var{bits} mgl@1371: +number of bits. The same as @samp{Ks@var{bits}} with a negated range. mgl@1371: +This means that the constant must be in the range @math{-2^{bits-1}-1} to @math{2^{bits-1}} mgl@1371: + mgl@1371: +@item G mgl@1371: +A single/double precision floating-point immediate or 64-bit integer mgl@1371: +immediate where the least and most significant words both can be mgl@1371: +loaded with a move instruction. That is the the integer form of the mgl@1371: +values in the least and most significant words both are in the range mgl@1371: +@math{-2^{20}} to @math{2^{20}-1}. mgl@1371: + mgl@1371: +@item M mgl@1371: +Any 32-bit immediate with the most significant bits set to zero and the mgl@1371: +remaining least significant bits set to one. mgl@1371: + mgl@1371: +@item J mgl@1371: +A 32-bit immediate where all the lower 16-bits are zero. mgl@1371: + mgl@1371: +@item O mgl@1371: +A 32-bit immediate with one bit set and the rest of the bits cleared. mgl@1371: + mgl@1371: +@item N mgl@1371: +A 32-bit immediate with one bit cleared and the rest of the bits set. mgl@1371: + mgl@1371: +@item L mgl@1371: +A 32-bit immediate where all the lower 16-bits are set. mgl@1371: + mgl@1371: +@item Q mgl@1371: +Any AVR32 memory reference except for reference used for the atomic memory (RMW) instructions. mgl@1371: + mgl@1371: +@item RKs@var{bits} mgl@1371: +A memory reference where the address consists of a base register mgl@1371: +plus a signed immediate displacement with range given by @samp{Ks@var{bits}} mgl@1371: +which has the same format as for the signed immediate integer constraint mgl@1371: +given above. mgl@1371: + mgl@1371: +@item RKu@var{bits} mgl@1371: +A memory reference where the address consists of a base register mgl@1371: +plus an unsigned immediate displacement with range given by @samp{Ku@var{bits}} mgl@1371: +which has the same format as for the unsigned immediate integer constraint mgl@1371: +given above. mgl@1371: + mgl@1371: +@item S mgl@1371: +A memory reference with an immediate or register offset mgl@1371: + mgl@1371: +@item T mgl@1371: +A memory reference to a constant pool entry mgl@1371: + mgl@1371: +@item W mgl@1371: +A valid operand for use in the @samp{lda.w} instruction macro when mgl@1371: +relaxing is enabled mgl@1371: + mgl@1371: +@item Y mgl@1371: +A memory reference suitable for the atomic memory (RMW) instructions. mgl@1371: + mgl@1371: +@item Z mgl@1371: +A memory reference valid for coprocessor memory instructions mgl@1371: + mgl@1371: +@end table mgl@1371: + mgl@1371: @item AVR family---@file{config/avr/constraints.md} mgl@1371: @table @code mgl@1371: @item l mgl@1371: --- a/gcc/expmed.c mgl@1371: +++ b/gcc/expmed.c mgl@1371: @@ -36,6 +36,7 @@ along with GCC; see the file COPYING3. mgl@1371: #include "real.h" mgl@1371: #include "recog.h" mgl@1371: #include "langhooks.h" mgl@1371: +#include "target.h" mgl@1371: mgl@1371: static void store_fixed_bit_field (rtx, unsigned HOST_WIDE_INT, mgl@1371: unsigned HOST_WIDE_INT, mgl@1371: @@ -454,9 +455,19 @@ store_bit_field (rtx str_rtx, unsigned H mgl@1371: ? ((GET_MODE_SIZE (fieldmode) >= UNITS_PER_WORD mgl@1371: || GET_MODE_SIZE (GET_MODE (op0)) == GET_MODE_SIZE (fieldmode)) mgl@1371: && byte_offset % GET_MODE_SIZE (fieldmode) == 0) mgl@1371: - : (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0)) mgl@1371: - || (offset * BITS_PER_UNIT % bitsize == 0 mgl@1371: - && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0)))) mgl@1371: + : ( mgl@1371: + mgl@1371: + /* NB! Added for AVR32, and I think this should be true for mgl@1371: + all targets not using narrow volatile bitfields. If the mgl@1371: + bitfield is volatile then we need to perform an access mgl@1371: + consistent with the container type. */ mgl@1371: + !(MEM_VOLATILE_P (op0) mgl@1371: + && GET_MODE_BITSIZE (GET_MODE (op0)) != bitsize mgl@1371: + && bitsize < BITS_PER_WORD mgl@1371: + && !targetm.narrow_volatile_bitfield ()) mgl@1371: + && (! SLOW_UNALIGNED_ACCESS (fieldmode, MEM_ALIGN (op0)) mgl@1371: + || (offset * BITS_PER_UNIT % bitsize == 0 mgl@1371: + && MEM_ALIGN (op0) % GET_MODE_BITSIZE (fieldmode) == 0))))) mgl@1371: { mgl@1371: if (MEM_P (op0)) mgl@1371: op0 = adjust_address (op0, fieldmode, offset); mgl@1371: @@ -1256,6 +1267,13 @@ extract_bit_field (rtx str_rtx, unsigned mgl@1371: && GET_MODE_SIZE (mode1) != 0 mgl@1371: && byte_offset % GET_MODE_SIZE (mode1) == 0) mgl@1371: || (MEM_P (op0) mgl@1371: + /* NB! Added for AVR32, and I think this should be true for mgl@1371: + all targets not using narrow volatile bitfields. If the mgl@1371: + bitfield is volatile then we need to perform an access mgl@1371: + consistent with the container type. */ mgl@1371: + && !(MEM_VOLATILE_P (op0) mgl@1371: + && GET_MODE_BITSIZE (GET_MODE (op0)) != bitsize mgl@1371: + && !targetm.narrow_volatile_bitfield ()) mgl@1371: && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (op0)) mgl@1371: || (offset * BITS_PER_UNIT % bitsize == 0 mgl@1371: && MEM_ALIGN (op0) % bitsize == 0))))) mgl@1371: --- a/gcc/expr.c mgl@1371: +++ b/gcc/expr.c mgl@1371: @@ -3519,18 +3519,19 @@ emit_single_push_insn (enum machine_mode mgl@1371: } mgl@1371: else mgl@1371: { mgl@1371: + emit_move_insn (stack_pointer_rtx, mgl@1371: + expand_binop (Pmode, mgl@1371: #ifdef STACK_GROWS_DOWNWARD mgl@1371: - /* ??? This seems wrong if STACK_PUSH_CODE == POST_DEC. */ mgl@1371: - dest_addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, mgl@1371: - GEN_INT (-(HOST_WIDE_INT) rounded_size)); mgl@1371: + sub_optab, mgl@1371: #else mgl@1371: - /* ??? This seems wrong if STACK_PUSH_CODE == POST_INC. */ mgl@1371: - dest_addr = gen_rtx_PLUS (Pmode, stack_pointer_rtx, mgl@1371: - GEN_INT (rounded_size)); mgl@1371: + add_optab, mgl@1371: #endif mgl@1371: - dest_addr = gen_rtx_PRE_MODIFY (Pmode, stack_pointer_rtx, dest_addr); mgl@1371: + stack_pointer_rtx, mgl@1371: + GEN_INT (rounded_size), mgl@1371: + NULL_RTX, 0, OPTAB_LIB_WIDEN)); mgl@1371: + dest_addr = stack_pointer_rtx; mgl@1371: } mgl@1371: - mgl@1371: + mgl@1371: dest = gen_rtx_MEM (mode, dest_addr); mgl@1371: mgl@1371: if (type != 0) mgl@1371: @@ -5509,7 +5510,21 @@ store_field (rtx target, HOST_WIDE_INT b mgl@1371: is a bit field, we cannot use addressing to access it. mgl@1371: Use bit-field techniques or SUBREG to store in it. */ mgl@1371: mgl@1371: - if (mode == VOIDmode mgl@1371: + if ( mgl@1371: + /* NB! Added for AVR32, and I think this should be true for mgl@1371: + all targets not using narrow volatile bitfields. If the mgl@1371: + bitfield is volatile then we need to perform an access mgl@1371: + consistent with the container type. */ mgl@1371: + (MEM_P (target) mgl@1371: + && MEM_VOLATILE_P (target) mgl@1371: + && ((GET_MODE (target) != BLKmode mgl@1371: + && GET_MODE_BITSIZE (GET_MODE (target)) > bitsize ) mgl@1371: + /* If BLKmode, check if this is a record. Do not know mgl@1371: + if this is really necesarry though...*/ mgl@1371: + || (GET_MODE (target) == BLKmode mgl@1371: + && TREE_CODE (type) == RECORD_TYPE)) mgl@1371: + && !targetm.narrow_volatile_bitfield ()) mgl@1371: + || mode == VOIDmode mgl@1371: || (mode != BLKmode && ! direct_store[(int) mode] mgl@1371: && GET_MODE_CLASS (mode) != MODE_COMPLEX_INT mgl@1371: && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) mgl@1371: @@ -7560,7 +7575,21 @@ expand_expr_real_1 (tree exp, rtx target mgl@1371: by doing the extract into an object as wide as the field mgl@1371: (which we know to be the width of a basic mode), then mgl@1371: storing into memory, and changing the mode to BLKmode. */ mgl@1371: - if (mode1 == VOIDmode mgl@1371: + if ( mgl@1371: + /* NB! Added for AVR32, and I think this should be true for mgl@1371: + all targets not using narrow volatile bitfields. If the mgl@1371: + bitfield is volatile then we need to perform an access mgl@1371: + consistent with the container type. */ mgl@1371: + (MEM_P (op0) mgl@1371: + && MEM_VOLATILE_P (op0) mgl@1371: + && ((GET_MODE (op0) != BLKmode mgl@1371: + && GET_MODE_BITSIZE (GET_MODE (op0)) > bitsize ) mgl@1371: + /* If BLKmode, check if this is a record. Do not know mgl@1371: + if this is really necesarry though...*/ mgl@1371: + || (GET_MODE (op0) == BLKmode mgl@1371: + && TREE_CODE (type) == RECORD_TYPE)) mgl@1371: + && !targetm.narrow_volatile_bitfield ()) mgl@1371: + || mode1 == VOIDmode mgl@1371: || REG_P (op0) || GET_CODE (op0) == SUBREG mgl@1371: || (mode1 != BLKmode && ! direct_load[(int) mode1] mgl@1371: && GET_MODE_CLASS (mode) != MODE_COMPLEX_INT mgl@1371: --- a/gcc/flow.c mgl@1371: +++ b/gcc/flow.c mgl@1371: @@ -3327,12 +3327,12 @@ not_reg_cond (rtx x) mgl@1371: if (GET_CODE (x) == NOT) mgl@1371: return XEXP (x, 0); mgl@1371: if (COMPARISON_P (x) mgl@1371: - && REG_P (XEXP (x, 0))) mgl@1371: + /* && REG_P (XEXP (x, 0))*/) mgl@1371: { mgl@1371: - gcc_assert (XEXP (x, 1) == const0_rtx); mgl@1371: + /*gcc_assert (XEXP (x, 1) == const0_rtx);*/ mgl@1371: mgl@1371: return gen_rtx_fmt_ee (reversed_comparison_code (x, NULL), mgl@1371: - VOIDmode, XEXP (x, 0), const0_rtx); mgl@1371: + VOIDmode, XEXP (x, 0), XEXP (x, 0) /*const0_rtx*/); mgl@1371: } mgl@1371: return gen_rtx_NOT (0, x); mgl@1371: } mgl@1371: --- a/gcc/function.c mgl@1371: +++ b/gcc/function.c mgl@1371: @@ -2676,8 +2676,12 @@ assign_parm_setup_reg (struct assign_par mgl@1371: SET_DECL_RTL (parm, parmreg); mgl@1371: mgl@1371: /* Copy the value into the register. */ mgl@1371: - if (data->nominal_mode != data->passed_mode mgl@1371: - || promoted_nominal_mode != data->promoted_mode) mgl@1371: + if ( (data->nominal_mode != data->passed_mode mgl@1371: + /* Added for AVR32: If passed_mode is equal mgl@1371: + to promoted nominal mode why should be convert? mgl@1371: + The conversion should make no difference. */ mgl@1371: + && data->passed_mode != promoted_nominal_mode) mgl@1371: + || promoted_nominal_mode != data->promoted_mode) mgl@1371: { mgl@1371: int save_tree_used; mgl@1371: mgl@1371: --- a/gcc/genemit.c mgl@1371: +++ b/gcc/genemit.c mgl@1371: @@ -121,6 +121,24 @@ max_operand_vec (rtx insn, int arg) mgl@1371: } mgl@1371: mgl@1371: static void mgl@1371: +gen_vararg_prologue(int operands) mgl@1371: +{ mgl@1371: + int i; mgl@1371: + mgl@1371: + if (operands > 1) mgl@1371: + { mgl@1371: + for (i = 1; i < operands; i++) mgl@1371: + printf(" rtx operand%d ATTRIBUTE_UNUSED;\n", i); mgl@1371: + mgl@1371: + printf(" va_list args;\n\n"); mgl@1371: + printf(" va_start(args, operand0);\n"); mgl@1371: + for (i = 1; i < operands; i++) mgl@1371: + printf(" operand%d = va_arg(args, rtx);\n", i); mgl@1371: + printf(" va_end(args);\n\n"); mgl@1371: + } mgl@1371: +} mgl@1371: + mgl@1371: +static void mgl@1371: print_code (RTX_CODE code) mgl@1371: { mgl@1371: const char *p1; mgl@1371: @@ -405,18 +423,16 @@ gen_insn (rtx insn, int lineno) mgl@1371: fatal ("match_dup operand number has no match_operand"); mgl@1371: mgl@1371: /* Output the function name and argument declarations. */ mgl@1371: - printf ("rtx\ngen_%s (", XSTR (insn, 0)); mgl@1371: + printf ("rtx\ngen_%s ", XSTR (insn, 0)); mgl@1371: + mgl@1371: if (operands) mgl@1371: - for (i = 0; i < operands; i++) mgl@1371: - if (i) mgl@1371: - printf (",\n\trtx operand%d ATTRIBUTE_UNUSED", i); mgl@1371: - else mgl@1371: - printf ("rtx operand%d ATTRIBUTE_UNUSED", i); mgl@1371: + printf("(rtx operand0 ATTRIBUTE_UNUSED, ...)\n"); mgl@1371: else mgl@1371: - printf ("void"); mgl@1371: - printf (")\n"); mgl@1371: + printf("(void)\n"); mgl@1371: printf ("{\n"); mgl@1371: mgl@1371: + gen_vararg_prologue(operands); mgl@1371: + mgl@1371: /* Output code to construct and return the rtl for the instruction body. */ mgl@1371: mgl@1371: if (XVECLEN (insn, 1) == 1) mgl@1371: @@ -456,16 +472,12 @@ gen_expand (rtx expand) mgl@1371: operands = max_operand_vec (expand, 1); mgl@1371: mgl@1371: /* Output the function name and argument declarations. */ mgl@1371: - printf ("rtx\ngen_%s (", XSTR (expand, 0)); mgl@1371: + printf ("rtx\ngen_%s ", XSTR (expand, 0)); mgl@1371: if (operands) mgl@1371: - for (i = 0; i < operands; i++) mgl@1371: - if (i) mgl@1371: - printf (",\n\trtx operand%d", i); mgl@1371: - else mgl@1371: - printf ("rtx operand%d", i); mgl@1371: + printf("(rtx operand0 ATTRIBUTE_UNUSED, ...)\n"); mgl@1371: else mgl@1371: - printf ("void"); mgl@1371: - printf (")\n"); mgl@1371: + printf("(void)\n"); mgl@1371: + mgl@1371: printf ("{\n"); mgl@1371: mgl@1371: /* If we don't have any C code to write, only one insn is being written, mgl@1371: @@ -475,6 +487,8 @@ gen_expand (rtx expand) mgl@1371: && operands > max_dup_opno mgl@1371: && XVECLEN (expand, 1) == 1) mgl@1371: { mgl@1371: + gen_vararg_prologue(operands); mgl@1371: + mgl@1371: printf (" return "); mgl@1371: gen_exp (XVECEXP (expand, 1, 0), DEFINE_EXPAND, NULL); mgl@1371: printf (";\n}\n\n"); mgl@1371: @@ -488,6 +502,7 @@ gen_expand (rtx expand) mgl@1371: for (; i <= max_scratch_opno; i++) mgl@1371: printf (" rtx operand%d ATTRIBUTE_UNUSED;\n", i); mgl@1371: printf (" rtx _val = 0;\n"); mgl@1371: + gen_vararg_prologue(operands); mgl@1371: printf (" start_sequence ();\n"); mgl@1371: mgl@1371: /* The fourth operand of DEFINE_EXPAND is some code to be executed mgl@1371: --- a/gcc/genflags.c mgl@1371: +++ b/gcc/genflags.c mgl@1371: @@ -127,7 +127,6 @@ static void mgl@1371: gen_proto (rtx insn) mgl@1371: { mgl@1371: int num = num_operands (insn); mgl@1371: - int i; mgl@1371: const char *name = XSTR (insn, 0); mgl@1371: int truth = maybe_eval_c_test (XSTR (insn, 2)); mgl@1371: mgl@1371: @@ -158,12 +157,7 @@ gen_proto (rtx insn) mgl@1371: if (num == 0) mgl@1371: fputs ("void", stdout); mgl@1371: else mgl@1371: - { mgl@1371: - for (i = 1; i < num; i++) mgl@1371: - fputs ("rtx, ", stdout); mgl@1371: - mgl@1371: - fputs ("rtx", stdout); mgl@1371: - } mgl@1371: + fputs("rtx, ...", stdout); mgl@1371: mgl@1371: puts (");"); mgl@1371: mgl@1371: @@ -173,12 +167,7 @@ gen_proto (rtx insn) mgl@1371: { mgl@1371: printf ("static inline rtx\ngen_%s", name); mgl@1371: if (num > 0) mgl@1371: - { mgl@1371: - putchar ('('); mgl@1371: - for (i = 0; i < num-1; i++) mgl@1371: - printf ("rtx ARG_UNUSED (%c), ", 'a' + i); mgl@1371: - printf ("rtx ARG_UNUSED (%c))\n", 'a' + i); mgl@1371: - } mgl@1371: + puts("(rtx ARG_UNUSED(a), ...)"); mgl@1371: else mgl@1371: puts ("(void)"); mgl@1371: puts ("{\n return 0;\n}"); mgl@1371: --- a/gcc/genoutput.c mgl@1371: +++ b/gcc/genoutput.c mgl@1371: @@ -386,7 +386,7 @@ output_insn_data (void) mgl@1371: } mgl@1371: mgl@1371: if (d->name && d->name[0] != '*') mgl@1371: - printf (" (insn_gen_fn) gen_%s,\n", d->name); mgl@1371: + printf (" gen_%s,\n", d->name); mgl@1371: else mgl@1371: printf (" 0,\n"); mgl@1371: mgl@1371: --- a/gcc/ifcvt.c mgl@1371: +++ b/gcc/ifcvt.c mgl@1371: @@ -77,7 +77,7 @@ static int num_possible_if_blocks; mgl@1371: static int num_updated_if_blocks; mgl@1371: mgl@1371: /* # of changes made which require life information to be updated. */ mgl@1371: -static int num_true_changes; mgl@1371: +int num_true_changes; mgl@1371: mgl@1371: /* Whether conditional execution changes were made. */ mgl@1371: static int cond_exec_changed_p; mgl@1371: @@ -287,12 +287,15 @@ cond_exec_process_insns (ce_if_block_t * mgl@1371: if (must_be_last) mgl@1371: return FALSE; mgl@1371: mgl@1371: - if (modified_in_p (test, insn)) mgl@1371: - { mgl@1371: - if (!mod_ok) mgl@1371: - return FALSE; mgl@1371: - must_be_last = TRUE; mgl@1371: - } mgl@1371: +#ifdef IFCVT_ALLOW_MODIFY_TEST_IN_INSN mgl@1371: + if ( !IFCVT_ALLOW_MODIFY_TEST_IN_INSN ) mgl@1371: +#endif mgl@1371: + if (modified_in_p (test, insn)) mgl@1371: + { mgl@1371: + if (!mod_ok) mgl@1371: + return FALSE; mgl@1371: + must_be_last = TRUE; mgl@1371: + } mgl@1371: mgl@1371: /* Now build the conditional form of the instruction. */ mgl@1371: pattern = PATTERN (insn); mgl@1371: @@ -566,16 +569,19 @@ cond_exec_process_if_block (ce_if_block_ mgl@1371: /* Do any machine dependent final modifications. */ mgl@1371: IFCVT_MODIFY_FINAL (ce_info); mgl@1371: #endif mgl@1371: - mgl@1371: - /* Conversion succeeded. */ mgl@1371: - if (dump_file) mgl@1371: - fprintf (dump_file, "%d insn%s converted to conditional execution.\n", mgl@1371: - n_insns, (n_insns == 1) ? " was" : "s were"); mgl@1371: - mgl@1371: + mgl@1371: /* Merge the blocks! */ mgl@1371: - merge_if_block (ce_info); mgl@1371: - cond_exec_changed_p = TRUE; mgl@1371: - return TRUE; mgl@1371: + if ( reload_completed ){ mgl@1371: + /* Conversion succeeded. */ mgl@1371: + if (dump_file) mgl@1371: + fprintf (dump_file, "%d insn%s converted to conditional execution.\n", mgl@1371: + n_insns, (n_insns == 1) ? " was" : "s were"); mgl@1371: + mgl@1371: + merge_if_block (ce_info); mgl@1371: + cond_exec_changed_p = TRUE; mgl@1371: + return TRUE; mgl@1371: + } mgl@1371: + return FALSE; mgl@1371: mgl@1371: fail: mgl@1371: #ifdef IFCVT_MODIFY_CANCEL mgl@1371: @@ -1050,7 +1056,11 @@ noce_try_addcc (struct noce_if_info *if_ mgl@1371: != UNKNOWN)) mgl@1371: { mgl@1371: rtx cond = if_info->cond; mgl@1371: - enum rtx_code code = reversed_comparison_code (cond, if_info->jump); mgl@1371: + /* This generates wrong code for AVR32. The cond code need not be reversed mgl@1371: + since the addmodecc patterns add if the condition is NOT met. */ mgl@1371: + /* enum rtx_code code = reversed_comparison_code (cond, if_info->jump);*/ mgl@1371: + enum rtx_code code = GET_CODE(cond); mgl@1371: + mgl@1371: mgl@1371: /* First try to use addcc pattern. */ mgl@1371: if (general_operand (XEXP (cond, 0), VOIDmode) mgl@1371: @@ -2651,7 +2661,12 @@ process_if_block (struct ce_if_block * c mgl@1371: && cond_move_process_if_block (ce_info)) mgl@1371: return TRUE; mgl@1371: mgl@1371: - if (HAVE_conditional_execution && reload_completed) mgl@1371: + if (HAVE_conditional_execution && mgl@1371: +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD mgl@1371: + (reload_completed || IFCVT_COND_EXEC_BEFORE_RELOAD)) mgl@1371: +#else mgl@1371: + reload_completed) mgl@1371: +#endif mgl@1371: { mgl@1371: /* If we have && and || tests, try to first handle combining the && and mgl@1371: || tests into the conditional code, and if that fails, go back and mgl@1371: @@ -4036,6 +4051,15 @@ rest_of_handle_if_after_reload (void) mgl@1371: cleanup_cfg (CLEANUP_EXPENSIVE mgl@1371: | CLEANUP_UPDATE_LIFE mgl@1371: | (flag_crossjumping ? CLEANUP_CROSSJUMP : 0)); mgl@1371: + mgl@1371: + /* Hack for the AVR32 experimental ifcvt processing before reload. mgl@1371: + The AVR32 specific ifcvt code needs to know when ifcvt after reload mgl@1371: + has begun. */ mgl@1371: +#ifdef IFCVT_COND_EXEC_BEFORE_RELOAD mgl@1371: + if ( IFCVT_COND_EXEC_BEFORE_RELOAD ) mgl@1371: + cfun->machine->ifcvt_after_reload = 1; mgl@1371: +#endif mgl@1371: + mgl@1371: if (flag_if_conversion2) mgl@1371: if_convert (1); mgl@1371: return 0; mgl@1371: --- a/gcc/longlong.h mgl@1371: +++ b/gcc/longlong.h mgl@1371: @@ -226,6 +226,41 @@ UDItype __umulsidi3 (USItype, USItype); mgl@1371: #define UDIV_TIME 100 mgl@1371: #endif /* __arm__ */ mgl@1371: mgl@1371: +#if defined (__avr32__) && W_TYPE_SIZE == 32 mgl@1371: +#define add_ssaaaa(sh, sl, ah, al, bh, bl) \ mgl@1371: + __asm__ ("add\t%1, %4, %5\n\tadc\t%0, %2, %3" \ mgl@1371: + : "=r" ((USItype) (sh)), \ mgl@1371: + "=&r" ((USItype) (sl)) \ mgl@1371: + : "r" ((USItype) (ah)), \ mgl@1371: + "r" ((USItype) (bh)), \ mgl@1371: + "r" ((USItype) (al)), \ mgl@1371: + "r" ((USItype) (bl)) __CLOBBER_CC) mgl@1371: +#define sub_ddmmss(sh, sl, ah, al, bh, bl) \ mgl@1371: + __asm__ ("sub\t%1, %4, %5\n\tsbc\t%0, %2, %3" \ mgl@1371: + : "=r" ((USItype) (sh)), \ mgl@1371: + "=&r" ((USItype) (sl)) \ mgl@1371: + : "r" ((USItype) (ah)), \ mgl@1371: + "r" ((USItype) (bh)), \ mgl@1371: + "r" ((USItype) (al)), \ mgl@1371: + "r" ((USItype) (bl)) __CLOBBER_CC) mgl@1371: + mgl@1371: +#if !defined (__AVR32_UC__) || __AVR32_UC__ != 3 mgl@1371: +#define __umulsidi3(a,b) ((UDItype)(a) * (UDItype)(b)) mgl@1371: + mgl@1371: +#define umul_ppmm(w1, w0, u, v) \ mgl@1371: +{ \ mgl@1371: + DWunion __w; \ mgl@1371: + __w.ll = __umulsidi3 (u, v); \ mgl@1371: + w1 = __w.s.high; \ mgl@1371: + w0 = __w.s.low; \ mgl@1371: +} mgl@1371: +#endif mgl@1371: + mgl@1371: +#define count_leading_zeros(COUNT,X) ((COUNT) = __builtin_clz (X)) mgl@1371: +#define count_trailing_zeros(COUNT,X) ((COUNT) = __builtin_ctz (X)) mgl@1371: +#define COUNT_LEADING_ZEROS_0 32 mgl@1371: +#endif mgl@1371: + mgl@1371: #if defined (__hppa) && W_TYPE_SIZE == 32 mgl@1371: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ mgl@1371: __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0" \ mgl@1371: --- a/gcc/optabs.h mgl@1371: +++ b/gcc/optabs.h mgl@1371: @@ -431,7 +431,7 @@ extern enum insn_code reload_out_optab[N mgl@1371: extern GTY(()) optab code_to_optab[NUM_RTX_CODE + 1]; mgl@1371: mgl@1371: mgl@1371: -typedef rtx (*rtxfun) (rtx); mgl@1371: +typedef rtx (*rtxfun) (rtx, ...); mgl@1371: mgl@1371: /* Indexed by the rtx-code for a conditional (e.g. EQ, LT,...) mgl@1371: gives the gen_function to make a branch to test that condition. */ mgl@1371: --- a/gcc/regrename.c mgl@1371: +++ b/gcc/regrename.c mgl@1371: @@ -1592,6 +1592,9 @@ copyprop_hardreg_forward_1 (basic_block mgl@1371: bool changed = false; mgl@1371: rtx insn; mgl@1371: mgl@1371: + rtx prev_pred_test; mgl@1371: + int prev_pred_insn_skipped = 0; mgl@1371: + mgl@1371: for (insn = BB_HEAD (bb); ; insn = NEXT_INSN (insn)) mgl@1371: { mgl@1371: int n_ops, i, alt, predicated; mgl@1371: @@ -1630,7 +1633,60 @@ copyprop_hardreg_forward_1 (basic_block mgl@1371: || (predicated && recog_data.operand_type[i] == OP_OUT)) mgl@1371: recog_data.operand_type[i] = OP_INOUT; mgl@1371: } mgl@1371: + mgl@1371: mgl@1371: + /* Added for targets (AVR32) which supports test operands to be modified mgl@1371: + in cond_exec instruction. For these targets we cannot make a change to mgl@1371: + the test operands if one of the test operands is an output operand This beacuse mgl@1371: + changing the test operands might cause the need for inserting a new test mgl@1371: + insns in the middle of a sequence of cond_exec insns and if the test operands mgl@1371: + are modified these tests will fail. mgl@1371: + */ mgl@1371: + mgl@1371: + if ( IFCVT_ALLOW_MODIFY_TEST_IN_INSN mgl@1371: + && predicated ) mgl@1371: + { mgl@1371: + int insn_skipped = 0; mgl@1371: + rtx test = COND_EXEC_TEST (PATTERN (insn)); mgl@1371: + mgl@1371: + /* Check if the previous insn was a skipped predicated insn with the same mgl@1371: + test as this predicated insns. If so we cannot do any modification to mgl@1371: + this insn either since we cannot emit the test insn because the operands mgl@1371: + are clobbered. */ mgl@1371: + if ( prev_pred_insn_skipped mgl@1371: + && (rtx_equal_p (test, prev_pred_test) mgl@1371: + || rtx_equal_p (test, reversed_condition (prev_pred_test))) ) mgl@1371: + { mgl@1371: + insn_skipped = 1; mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + /* Check if the output operand is used in the test expression. */ mgl@1371: + for (i = 0; i < n_ops; ++i) mgl@1371: + if ( recog_data.operand_type[i] == OP_INOUT mgl@1371: + && reg_mentioned_p (recog_data.operand[i], test) ) mgl@1371: + { mgl@1371: + insn_skipped = 1; mgl@1371: + break; mgl@1371: + } mgl@1371: + mgl@1371: + } mgl@1371: + mgl@1371: + prev_pred_test = test; mgl@1371: + prev_pred_insn_skipped = insn_skipped; mgl@1371: + if ( insn_skipped ) mgl@1371: + { mgl@1371: + if (insn == BB_END (bb)) mgl@1371: + break; mgl@1371: + else mgl@1371: + continue; mgl@1371: + } mgl@1371: + } mgl@1371: + else mgl@1371: + { mgl@1371: + prev_pred_insn_skipped = 0; mgl@1371: + } mgl@1371: + mgl@1371: /* For each earlyclobber operand, zap the value data. */ mgl@1371: for (i = 0; i < n_ops; i++) mgl@1371: if (recog_op_alt[i][alt].earlyclobber) mgl@1371: --- a/gcc/reload.c mgl@1371: +++ b/gcc/reload.c mgl@1371: @@ -4574,7 +4574,7 @@ find_reloads_toplev (rtx x, int opnum, e mgl@1371: x = mem; mgl@1371: i = find_reloads_address (GET_MODE (x), &x, XEXP (x, 0), &XEXP (x, 0), mgl@1371: opnum, type, ind_levels, insn); mgl@1371: - if (x != mem) mgl@1371: + if (!rtx_equal_p (x, mem)) mgl@1371: push_reg_equiv_alt_mem (regno, x); mgl@1371: if (address_reloaded) mgl@1371: *address_reloaded = i; mgl@1371: --- a/gcc/sched-deps.c mgl@1371: +++ b/gcc/sched-deps.c mgl@1371: @@ -649,7 +649,14 @@ fixup_sched_groups (rtx insn) mgl@1371: mgl@1371: prev_nonnote = prev_nonnote_insn (insn); mgl@1371: if (BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (prev_nonnote) mgl@1371: - && ! sched_insns_conditions_mutex_p (insn, prev_nonnote)) mgl@1371: + /* Modification for AVR32 by RP: Why is this here, this will mgl@1371: + cause instruction to be without any dependencies which might mgl@1371: + cause it to be moved anywhere. For the AVR32 we try to keep mgl@1371: + a group of conditionals together even if they are mutual exclusive. mgl@1371: + */ mgl@1371: + && (! sched_insns_conditions_mutex_p (insn, prev_nonnote) mgl@1371: + || GET_CODE (PATTERN (insn)) == COND_EXEC ) mgl@1371: + ) mgl@1371: add_dependence (insn, prev_nonnote, REG_DEP_ANTI); mgl@1371: } mgl@1371: mgl@1371: @@ -1123,8 +1130,29 @@ sched_analyze_insn (struct deps *deps, r mgl@1371: mgl@1371: if (code == COND_EXEC) mgl@1371: { mgl@1371: +#ifdef IFCVT_ALLOW_MODIFY_TEST_IN_INSN mgl@1371: + if (IFCVT_ALLOW_MODIFY_TEST_IN_INSN) mgl@1371: + { mgl@1371: + /* Check if we have a group og conditional instructions with the same test. mgl@1371: + If so we must make sure that they are not scheduled apart in order to mgl@1371: + avoid unnecesarry tests and if one of the registers in the test is modified mgl@1371: + in the instruction this is needed to ensure correct code. */ mgl@1371: + if ( prev_nonnote_insn (insn) mgl@1371: + && INSN_P (prev_nonnote_insn (insn)) mgl@1371: + && GET_CODE (PATTERN (prev_nonnote_insn (insn))) == COND_EXEC mgl@1371: + && rtx_equal_p (XEXP(COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn))), 0), XEXP (COND_EXEC_TEST (x), 0)) mgl@1371: + && rtx_equal_p (XEXP(COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn))), 1), XEXP (COND_EXEC_TEST (x), 1)) mgl@1371: + && ( GET_CODE (COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn)))) == GET_CODE (COND_EXEC_TEST (x)) mgl@1371: + || GET_CODE (COND_EXEC_TEST (PATTERN (prev_nonnote_insn (insn)))) == reversed_comparison_code (COND_EXEC_TEST (x), insn))) mgl@1371: + { mgl@1371: + SCHED_GROUP_P (insn) = 1; mgl@1371: + //CANT_MOVE (prev_nonnote_insn (insn)) = 1; mgl@1371: + } mgl@1371: + } mgl@1371: +#endif mgl@1371: sched_analyze_2 (deps, COND_EXEC_TEST (x), insn); mgl@1371: mgl@1371: + mgl@1371: /* ??? Should be recording conditions so we reduce the number of mgl@1371: false dependencies. */ mgl@1371: x = COND_EXEC_CODE (x); mgl@1371: --- a/gcc/testsuite/gcc.dg/sibcall-3.c mgl@1371: +++ b/gcc/testsuite/gcc.dg/sibcall-3.c mgl@1371: @@ -5,7 +5,7 @@ mgl@1371: Copyright (C) 2002 Free Software Foundation Inc. mgl@1371: Contributed by Hans-Peter Nilsson */ mgl@1371: mgl@1371: -/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */ mgl@1371: +/* { dg-do run { xfail arc-*-* avr-*-* avr32-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */ mgl@1371: /* { dg-options "-O2 -foptimize-sibling-calls" } */ mgl@1371: mgl@1371: /* The option -foptimize-sibling-calls is the default, but serves as mgl@1371: --- a/gcc/testsuite/gcc.dg/sibcall-4.c mgl@1371: +++ b/gcc/testsuite/gcc.dg/sibcall-4.c mgl@1371: @@ -5,7 +5,7 @@ mgl@1371: Copyright (C) 2002 Free Software Foundation Inc. mgl@1371: Contributed by Hans-Peter Nilsson */ mgl@1371: mgl@1371: -/* { dg-do run { xfail arc-*-* avr-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */ mgl@1371: +/* { dg-do run { xfail arc-*-* avr-*-* avr32-*-* c4x-*-* cris-*-* h8300-*-* hppa*64*-*-* m32r-*-* m68hc1?-*-* m681?-*-* m680*-*-* m68k-*-* mcore-*-* mn10300-*-* xstormy16-*-* v850*-*-* vax-*-* xtensa-*-* } } */ mgl@1371: /* { dg-options "-O2 -foptimize-sibling-calls" } */ mgl@1371: mgl@1371: /* The option -foptimize-sibling-calls is the default, but serves as mgl@1371: --- a/gcc/testsuite/gcc.dg/trampoline-1.c mgl@1371: +++ b/gcc/testsuite/gcc.dg/trampoline-1.c mgl@1371: @@ -46,6 +46,8 @@ void foo (void) mgl@1371: mgl@1371: int main (void) mgl@1371: { mgl@1371: +#ifndef NO_TRAMPOLINES mgl@1371: foo (); mgl@1371: +#endif mgl@1371: return 0; mgl@1371: } mgl@1371: --- a/gcc/testsuite/g++.old-deja/g++.pt/static11.C mgl@1371: +++ b/gcc/testsuite/g++.old-deja/g++.pt/static11.C mgl@1371: @@ -2,7 +2,7 @@ mgl@1371: // in their dejagnu baseboard description) require that the status is mgl@1371: // final when exit is entered (or main returns), and not "overruled" by a mgl@1371: // destructor calling _exit. It's not really worth it to handle that. mgl@1371: -// { dg-do run { xfail mmix-knuth-mmixware xtensa-*-elf* arm*-*-elf arm*-*-eabi m68k-*-elf } } mgl@1371: +// { dg-do run { xfail mmix-knuth-mmixware xtensa-*-elf* avr32-*-elf arm*-*-elf arm*-*-eabi m68k-*-elf } } mgl@1371: mgl@1371: // Bug: g++ was failing to destroy C::a because it was using two mgl@1371: // different sentry variables for construction and destruction. mgl@1371: --- a/gcc/version.c mgl@1371: +++ b/gcc/version.c mgl@1371: @@ -8,7 +8,7 @@ mgl@1371: in parentheses. You may also wish to include a number indicating mgl@1371: the revision of your modified compiler. */ mgl@1371: mgl@1371: -#define VERSUFFIX "" mgl@1371: +#define VERSUFFIX "-atmel.1.1.3.avr32linux.1" mgl@1371: mgl@1371: /* This is the location of the online document giving instructions for mgl@1371: reporting bugs. If you distribute a modified version of GCC, mgl@1371: @@ -17,9 +17,9 @@ mgl@1371: forward us bugs reported to you, if you determine that they are mgl@1371: not bugs in your modifications.) */ mgl@1371: mgl@1371: -const char bug_report_url[] = ""; mgl@1371: +const char bug_report_url[] = ""; mgl@1371: mgl@1371: /* The complete version string, assembled from several pieces. mgl@1371: BASEVER, DATESTAMP, and DEVPHASE are defined by the Makefile. */ mgl@1371: mgl@1371: -const char version_string[] = BASEVER DATESTAMP DEVPHASE VERSUFFIX; mgl@1371: +const char version_string[] = BASEVER VERSUFFIX DATESTAMP DEVPHASE; mgl@1371: --- a/libstdc++-v3/acinclude.m4 mgl@1371: +++ b/libstdc++-v3/acinclude.m4 mgl@1371: @@ -125,15 +125,6 @@ AC_DEFUN([GLIBCXX_CONFIGURE], [ mgl@1371: ## other macros from doing the same. This should be automated.) -pme mgl@1371: need_libmath=no mgl@1371: mgl@1371: - # Check for uClibc since Linux platforms use different configuration mgl@1371: - # directories depending on the C library in use. mgl@1371: - AC_EGREP_CPP([_using_uclibc], [ mgl@1371: - #include mgl@1371: - #if __UCLIBC__ mgl@1371: - _using_uclibc mgl@1371: - #endif mgl@1371: - ], uclibc=yes, uclibc=no) mgl@1371: - mgl@1371: # Find platform-specific directories containing configuration info. mgl@1371: # Also possibly modify flags used elsewhere, as needed by the platform. mgl@1371: GLIBCXX_CHECK_HOST mgl@1371: @@ -1389,8 +1380,8 @@ AC_DEFUN([GLIBCXX_ENABLE_CLOCALE], [ mgl@1371: #endif mgl@1371: int main() mgl@1371: { mgl@1371: - const char __one[] = "Äuglein Augmen"; mgl@1371: - const char __two[] = "Äuglein"; mgl@1371: + const char __one[] = "Äuglein Augmen"; mgl@1371: + const char __two[] = "Äuglein"; mgl@1371: int i; mgl@1371: int j; mgl@1371: __locale_t loc; mgl@1371: --- a/libstdc++-v3/config/os/gnu-linux/ctype_base.h mgl@1371: +++ b/libstdc++-v3/config/os/gnu-linux/ctype_base.h mgl@1371: @@ -31,6 +31,8 @@ mgl@1371: // mgl@1371: // ISO C++ 14882: 22.1 Locales mgl@1371: // mgl@1371: +#include mgl@1371: +#include mgl@1371: mgl@1371: /** @file ctype_base.h mgl@1371: * This is an internal header file, included by other library headers. mgl@1371: @@ -45,8 +47,12 @@ _GLIBCXX_BEGIN_NAMESPACE(std) mgl@1371: struct ctype_base mgl@1371: { mgl@1371: // Non-standard typedefs. mgl@1371: - typedef const int* __to_type; mgl@1371: - mgl@1371: +#ifdef __UCLIBC__ mgl@1371: + typedef const __ctype_touplow_t* __to_type; mgl@1371: +#else mgl@1371: + typedef const int* __to_type; mgl@1371: +#endif mgl@1371: + mgl@1371: // NB: Offsets into ctype::_M_table force a particular size mgl@1371: // on the mask type. Because of this, we don't use an enum. mgl@1371: typedef unsigned short mask; mgl@1371: --- a/libstdc++-v3/include/Makefile.in mgl@1371: +++ b/libstdc++-v3/include/Makefile.in mgl@1371: @@ -36,6 +36,7 @@ POST_UNINSTALL = : mgl@1371: build_triplet = @build@ mgl@1371: host_triplet = @host@ mgl@1371: target_triplet = @target@ mgl@1371: +LIBOBJDIR = mgl@1371: DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ mgl@1371: $(top_srcdir)/fragment.am mgl@1371: subdir = include mgl@1371: --- a/libstdc++-v3/libmath/Makefile.in mgl@1371: +++ b/libstdc++-v3/libmath/Makefile.in mgl@1371: @@ -37,6 +37,7 @@ POST_UNINSTALL = : mgl@1371: build_triplet = @build@ mgl@1371: host_triplet = @host@ mgl@1371: target_triplet = @target@ mgl@1371: +LIBOBJDIR = mgl@1371: subdir = libmath mgl@1371: DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in mgl@1371: ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 mgl@1371: --- a/libstdc++-v3/libsupc++/Makefile.in mgl@1371: +++ b/libstdc++-v3/libsupc++/Makefile.in mgl@1371: @@ -38,6 +38,7 @@ POST_UNINSTALL = : mgl@1371: build_triplet = @build@ mgl@1371: host_triplet = @host@ mgl@1371: target_triplet = @target@ mgl@1371: +LIBOBJDIR = mgl@1371: DIST_COMMON = $(glibcxxinstall_HEADERS) $(srcdir)/Makefile.am \ mgl@1371: $(srcdir)/Makefile.in $(top_srcdir)/fragment.am mgl@1371: subdir = libsupc++ mgl@1371: --- a/libstdc++-v3/Makefile.in mgl@1371: +++ b/libstdc++-v3/Makefile.in mgl@1371: @@ -36,6 +36,7 @@ POST_UNINSTALL = : mgl@1371: build_triplet = @build@ mgl@1371: host_triplet = @host@ mgl@1371: target_triplet = @target@ mgl@1371: +LIBOBJDIR = mgl@1371: DIST_COMMON = README $(am__configure_deps) $(srcdir)/../config.guess \ mgl@1371: $(srcdir)/../config.sub $(srcdir)/../install-sh \ mgl@1371: $(srcdir)/../ltmain.sh $(srcdir)/../missing \ mgl@1371: --- a/libstdc++-v3/po/Makefile.in mgl@1371: +++ b/libstdc++-v3/po/Makefile.in mgl@1371: @@ -36,6 +36,7 @@ POST_UNINSTALL = : mgl@1371: build_triplet = @build@ mgl@1371: host_triplet = @host@ mgl@1371: target_triplet = @target@ mgl@1371: +LIBOBJDIR = mgl@1371: DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ mgl@1371: $(top_srcdir)/fragment.am mgl@1371: subdir = po mgl@1371: --- a/libstdc++-v3/src/Makefile.in mgl@1371: +++ b/libstdc++-v3/src/Makefile.in mgl@1371: @@ -36,6 +36,7 @@ POST_UNINSTALL = : mgl@1371: build_triplet = @build@ mgl@1371: host_triplet = @host@ mgl@1371: target_triplet = @target@ mgl@1371: +LIBOBJDIR = mgl@1371: DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in \ mgl@1371: $(top_srcdir)/fragment.am mgl@1371: subdir = src mgl@1371: --- a/Makefile.def mgl@1371: +++ b/Makefile.def mgl@1371: @@ -481,7 +481,7 @@ lang_env_dependencies = { module=rda; }; mgl@1371: lang_env_dependencies = { module=winsup; }; mgl@1371: lang_env_dependencies = { module=qthreads; }; mgl@1371: mgl@1371: -dependencies = { module=all-target-libgloss; on=configure-target-newlib; }; mgl@1371: +dependencies = { module=all-target-libgloss; on=all-target-newlib; }; mgl@1371: dependencies = { module=all-target-winsup; on=all-target-libiberty; }; mgl@1371: dependencies = { module=all-target-winsup; on=all-target-libtermcap; }; mgl@1371: mgl@1371: --- a/Makefile.in mgl@1371: +++ b/Makefile.in mgl@1371: @@ -43791,7 +43791,7 @@ all-target-libobjc: maybe-all-target-boe mgl@1371: all-target-libstdc++-v3: maybe-all-target-libiberty mgl@1371: install-target-libssp: maybe-install-gcc mgl@1371: install-target-libgomp: maybe-install-gcc mgl@1371: -all-target-libgloss: maybe-configure-target-newlib mgl@1371: +all-target-libgloss: maybe-all-target-newlib mgl@1371: all-target-winsup: maybe-all-target-libiberty mgl@1371: all-target-winsup: maybe-all-target-libtermcap mgl@1371: mgl@1371: --- a/gcc/configure.ac mgl@1371: +++ b/gcc/configure.ac mgl@1371: @@ -2158,7 +2158,7 @@ L2:], mgl@1371: as_ver=`$gcc_cv_as --version 2>/dev/null | sed 1q` mgl@1371: if echo "$as_ver" | grep GNU > /dev/null; then mgl@1371: changequote(,)dnl mgl@1371: - as_ver=`echo $as_ver | sed -e 's/GNU assembler \([0-9.][0-9.]*\).*/\1/'` mgl@1371: + as_ver=`echo $as_ver | sed -e 's/GNU assembler\( (GNU Binutils)\)\? \([0-9.][0-9.]*\).*/\2/'` mgl@1371: as_major=`echo $as_ver | sed 's/\..*//'` mgl@1371: as_minor=`echo $as_ver | sed 's/[^.]*\.\([0-9]*\).*/\1/'` mgl@1371: changequote([,])dnl mgl@1371: @@ -2971,7 +2971,7 @@ esac mgl@1371: case "$target" in mgl@1371: i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \ mgl@1371: | x86_64*-*-* | hppa*-*-* | arm*-*-* | strongarm*-*-* | xscale*-*-* \ mgl@1371: - | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-*) mgl@1371: + | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-* | avr32-*-*) mgl@1371: insn="nop" mgl@1371: ;; mgl@1371: ia64*-*-* | s390*-*-*) mgl@1371: --- a/gcc/configure mgl@1371: +++ b/gcc/configure mgl@1371: @@ -14023,7 +14023,7 @@ L2:' > conftest.s mgl@1371: # arbitrary sections are supported and try the test. mgl@1371: as_ver=`$gcc_cv_as --version 2>/dev/null | sed 1q` mgl@1371: if echo "$as_ver" | grep GNU > /dev/null; then mgl@1371: - as_ver=`echo $as_ver | sed -e 's/GNU assembler \([0-9.][0-9.]*\).*/\1/'` mgl@1371: + as_ver=`echo $as_ver | sed -e 's/GNU assembler\( (GNU Binutils)\)\? \([0-9.][0-9.]*\).*/\2/'` mgl@1371: as_major=`echo $as_ver | sed 's/\..*//'` mgl@1371: as_minor=`echo $as_ver | sed 's/[^.]*\.\([0-9]*\).*/\1/'` mgl@1371: if test $as_major -eq 2 && test $as_minor -lt 11 mgl@1371: @@ -15610,7 +15610,7 @@ esac mgl@1371: case "$target" in mgl@1371: i?86*-*-* | mips*-*-* | alpha*-*-* | powerpc*-*-* | sparc*-*-* | m68*-*-* \ mgl@1371: | x86_64*-*-* | hppa*-*-* | arm*-*-* | strongarm*-*-* | xscale*-*-* \ mgl@1371: - | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-*) mgl@1371: + | xstormy16*-*-* | cris-*-* | xtensa-*-* | bfin-*-* | score*-*-* | avr32-*-*) mgl@1371: insn="nop" mgl@1371: ;; mgl@1371: ia64*-*-* | s390*-*-*)