yann@1: Fixes error yann@1: ./longlong.h:423: error: parse error before '%' token yann@1: ./longlong.h:423: error: missing terminating " character yann@1: ./longlong.h:432: error: missing terminating " character yann@1: See also patches/glibc-2.1.3/glibc-2.1.3-allow-gcc3-longlong.patch yann@1: yann@1: =================================================================== yann@1: --- glibc-2.2.2/stdlib/longlong.h.old 2000-02-11 15:48:58.000000000 -0800 yann@1: +++ glibc-2.2.2/stdlib/longlong.h 2005-04-11 15:36:10.000000000 -0700 yann@1: @@ -108,8 +108,8 @@ yann@1: yann@1: #if (defined (__a29k__) || defined (_AM29K)) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("add %1,%4,%5 yann@1: - addc %0,%2,%3" \ yann@1: + __asm__ ("add %1,%4,%5\n" \ yann@1: + "addc %0,%2,%3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%r" ((USItype) (ah)), \ yann@1: @@ -117,8 +117,8 @@ yann@1: "%r" ((USItype) (al)), \ yann@1: "rI" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("sub %1,%4,%5 yann@1: - subc %0,%2,%3" \ yann@1: + __asm__ ("sub %1,%4,%5\n" \ yann@1: + "subc %0,%2,%3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "r" ((USItype) (ah)), \ yann@1: @@ -175,8 +175,8 @@ yann@1: yann@1: #if defined (__arc__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("add.f %1, %4, %5 yann@1: - adc %0, %2, %3" \ yann@1: + __asm__ ("add.f %1, %4, %5\n" \ yann@1: + "adc %0, %2, %3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%r" ((USItype) (ah)), \ yann@1: @@ -184,8 +184,8 @@ yann@1: "%r" ((USItype) (al)), \ yann@1: "rIJ" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("sub.f %1, %4, %5 yann@1: - sbc %0, %2, %3" \ yann@1: + __asm__ ("sub.f %1, %4, %5\n" \ yann@1: + "sbc %0, %2, %3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "r" ((USItype) (ah)), \ yann@1: @@ -206,8 +206,8 @@ yann@1: yann@1: #if defined (__arm__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("adds %1, %4, %5 yann@1: - adc %0, %2, %3" \ yann@1: + __asm__ ("adds %1, %4, %5\n" \ yann@1: + "adc %0, %2, %3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%r" ((USItype) (ah)), \ yann@1: @@ -215,8 +215,8 @@ yann@1: "%r" ((USItype) (al)), \ yann@1: "rI" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subs %1, %4, %5 yann@1: - sbc %0, %2, %3" \ yann@1: + __asm__ ("subs %1, %4, %5\n" \ yann@1: + "sbc %0, %2, %3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "r" ((USItype) (ah)), \ yann@1: @@ -225,19 +225,19 @@ yann@1: "rI" ((USItype) (bl))) yann@1: #define umul_ppmm(xh, xl, a, b) \ yann@1: {register USItype __t0, __t1, __t2; \ yann@1: - __asm__ ("%@ Inlined umul_ppmm yann@1: - mov %2, %5, lsr #16 yann@1: - mov %0, %6, lsr #16 yann@1: - bic %3, %5, %2, lsl #16 yann@1: - bic %4, %6, %0, lsl #16 yann@1: - mul %1, %3, %4 yann@1: - mul %4, %2, %4 yann@1: - mul %3, %0, %3 yann@1: - mul %0, %2, %0 yann@1: - adds %3, %4, %3 yann@1: - addcs %0, %0, #65536 yann@1: - adds %1, %1, %3, lsl #16 yann@1: - adc %0, %0, %3, lsr #16" \ yann@1: + __asm__ ("%@ Inlined umul_ppmm\n" \ yann@1: + "mov %2, %5, lsr #16\n" \ yann@1: + "mov %0, %6, lsr #16\n" \ yann@1: + "bic %3, %5, %2, lsl #16\n" \ yann@1: + "bic %4, %6, %0, lsl #16\n" \ yann@1: + "mul %1, %3, %4\n" \ yann@1: + "mul %4, %2, %4\n" \ yann@1: + "mul %3, %0, %3\n" \ yann@1: + "mul %0, %2, %0\n" \ yann@1: + "adds %3, %4, %3\n" \ yann@1: + "addcs %0, %0, #65536\n" \ yann@1: + "adds %1, %1, %3, lsl #16\n" \ yann@1: + "adc %0, %0, %3, lsr #16" \ yann@1: : "=&r" ((USItype) (xh)), \ yann@1: "=r" ((USItype) (xl)), \ yann@1: "=&r" (__t0), "=&r" (__t1), "=r" (__t2) \ yann@1: @@ -277,8 +277,8 @@ yann@1: yann@1: #if defined (__gmicro__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("add.w %5,%1 yann@1: - addx %3,%0" \ yann@1: + __asm__ ("add.w %5,%1\n" \ yann@1: + "addx %3,%0" \ yann@1: : "=g" ((USItype) (sh)), \ yann@1: "=&g" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -286,8 +286,8 @@ yann@1: "%1" ((USItype) (al)), \ yann@1: "g" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("sub.w %5,%1 yann@1: - subx %3,%0" \ yann@1: + __asm__ ("sub.w %5,%1\n" \ yann@1: + "subx %3,%0" \ yann@1: : "=g" ((USItype) (sh)), \ yann@1: "=&g" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \ yann@1: @@ -316,8 +316,8 @@ yann@1: yann@1: #if defined (__hppa) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("add %4,%5,%1 yann@1: - addc %2,%3,%0" \ yann@1: + __asm__ ("add %4,%5,%1\n" \ yann@1: + "addc %2,%3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%rM" ((USItype) (ah)), \ yann@1: @@ -325,8 +325,8 @@ yann@1: "%rM" ((USItype) (al)), \ yann@1: "rM" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("sub %4,%5,%1 yann@1: - subb %2,%3,%0" \ yann@1: + __asm__ ("sub %4,%5,%1\n" \ yann@1: + "subb %2,%3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "rM" ((USItype) (ah)), \ yann@1: @@ -357,22 +357,22 @@ yann@1: do { \ yann@1: USItype __tmp; \ yann@1: __asm__ ( \ yann@1: - "ldi 1,%0 yann@1: - extru,= %1,15,16,%%r0 ; Bits 31..16 zero? yann@1: - extru,tr %1,15,16,%1 ; No. Shift down, skip add. yann@1: - ldo 16(%0),%0 ; Yes. Perform add. yann@1: - extru,= %1,23,8,%%r0 ; Bits 15..8 zero? yann@1: - extru,tr %1,23,8,%1 ; No. Shift down, skip add. yann@1: - ldo 8(%0),%0 ; Yes. Perform add. yann@1: - extru,= %1,27,4,%%r0 ; Bits 7..4 zero? yann@1: - extru,tr %1,27,4,%1 ; No. Shift down, skip add. yann@1: - ldo 4(%0),%0 ; Yes. Perform add. yann@1: - extru,= %1,29,2,%%r0 ; Bits 3..2 zero? yann@1: - extru,tr %1,29,2,%1 ; No. Shift down, skip add. yann@1: - ldo 2(%0),%0 ; Yes. Perform add. yann@1: - extru %1,30,1,%1 ; Extract bit 1. yann@1: - sub %0,%1,%0 ; Subtract it. yann@1: - " : "=r" (count), "=r" (__tmp) : "1" (x)); \ yann@1: + "ldi 1,%0\n" \ yann@1: + "extru,= %1,15,16,%%r0 ; Bits 31..16 zero?\n" \ yann@1: + "extru,tr %1,15,16,%1 ; No. Shift down, skip add.\n" \ yann@1: + "ldo 16(%0),%0 ; Yes. Perform add.\n" \ yann@1: + "extru,= %1,23,8,%%r0 ; Bits 15..8 zero?\n" \ yann@1: + "extru,tr %1,23,8,%1 ; No. Shift down, skip add.\n" \ yann@1: + "ldo 8(%0),%0 ; Yes. Perform add.\n" \ yann@1: + "extru,= %1,27,4,%%r0 ; Bits 7..4 zero?\n" \ yann@1: + "extru,tr %1,27,4,%1 ; No. Shift down, skip add.\n" \ yann@1: + "ldo 4(%0),%0 ; Yes. Perform add.\n" \ yann@1: + "extru,= %1,29,2,%%r0 ; Bits 3..2 zero?\n" \ yann@1: + "extru,tr %1,29,2,%1 ; No. Shift down, skip add.\n" \ yann@1: + "ldo 2(%0),%0 ; Yes. Perform add.\n" \ yann@1: + "extru %1,30,1,%1 ; Extract bit 1.\n" \ yann@1: + "sub %0,%1,%0 ; Subtract it.\n" \ yann@1: + : "=r" (count), "=r" (__tmp) : "1" (x)); \ yann@1: } while (0) yann@1: #endif yann@1: yann@1: @@ -419,8 +419,8 @@ yann@1: yann@1: #if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("addl %5,%1 yann@1: - adcl %3,%0" \ yann@1: + __asm__ ("addl %5,%1\n" \ yann@1: + "adcl %3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -428,8 +428,8 @@ yann@1: "%1" ((USItype) (al)), \ yann@1: "g" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subl %5,%1 yann@1: - sbbl %3,%0" \ yann@1: + __asm__ ("subl %5,%1\n" \ yann@1: + "sbbl %3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \ yann@1: @@ -525,9 +525,9 @@ yann@1: #if defined (__M32R__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: /* The cmp clears the condition bit. */ \ yann@1: - __asm__ ("cmp %0,%0 yann@1: - addx %%5,%1 yann@1: - addx %%3,%0" \ yann@1: + __asm__ ("cmp %0,%0\n" \ yann@1: + "addx %%5,%1\n" \ yann@1: + "addx %%3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -537,9 +537,9 @@ yann@1: : "cbit") yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: /* The cmp clears the condition bit. */ \ yann@1: - __asm__ ("cmp %0,%0 yann@1: - subx %5,%1 yann@1: - subx %3,%0" \ yann@1: + __asm__ ("cmp %0,%0\n" \ yann@1: + "subx %5,%1\n" \ yann@1: + "subx %3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \ yann@1: @@ -551,8 +551,8 @@ yann@1: yann@1: #if defined (__mc68000__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("add%.l %5,%1 yann@1: - addx%.l %3,%0" \ yann@1: + __asm__ ("add%.l %5,%1\n" \ yann@1: + "addx%.l %3,%0" \ yann@1: : "=d" ((USItype) (sh)), \ yann@1: "=&d" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -560,8 +560,8 @@ yann@1: "%1" ((USItype) (al)), \ yann@1: "g" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("sub%.l %5,%1 yann@1: - subx%.l %3,%0" \ yann@1: + __asm__ ("sub%.l %5,%1\n" \ yann@1: + "subx%.l %3,%0" \ yann@1: : "=d" ((USItype) (sh)), \ yann@1: "=&d" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \ yann@1: @@ -602,32 +602,32 @@ yann@1: #if !defined(__mcf5200__) yann@1: /* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX. */ yann@1: #define umul_ppmm(xh, xl, a, b) \ yann@1: - __asm__ ("| Inlined umul_ppmm yann@1: - move%.l %2,%/d0 yann@1: - move%.l %3,%/d1 yann@1: - move%.l %/d0,%/d2 yann@1: - swap %/d0 yann@1: - move%.l %/d1,%/d3 yann@1: - swap %/d1 yann@1: - move%.w %/d2,%/d4 yann@1: - mulu %/d3,%/d4 yann@1: - mulu %/d1,%/d2 yann@1: - mulu %/d0,%/d3 yann@1: - mulu %/d0,%/d1 yann@1: - move%.l %/d4,%/d0 yann@1: - eor%.w %/d0,%/d0 yann@1: - swap %/d0 yann@1: - add%.l %/d0,%/d2 yann@1: - add%.l %/d3,%/d2 yann@1: - jcc 1f yann@1: - add%.l %#65536,%/d1 yann@1: -1: swap %/d2 yann@1: - moveq %#0,%/d0 yann@1: - move%.w %/d2,%/d0 yann@1: - move%.w %/d4,%/d2 yann@1: - move%.l %/d2,%1 yann@1: - add%.l %/d1,%/d0 yann@1: - move%.l %/d0,%0" \ yann@1: + __asm__ ("| Inlined umul_ppmm\n" \ yann@1: + "move%.l %2,%/d0\n" \ yann@1: + "move%.l %3,%/d1\n" \ yann@1: + "move%.l %/d0,%/d2\n" \ yann@1: + "swap %/d0\n" \ yann@1: + "move%.l %/d1,%/d3\n" \ yann@1: + "swap %/d1\n" \ yann@1: + "move%.w %/d2,%/d4\n" \ yann@1: + "mulu %/d3,%/d4\n" \ yann@1: + "mulu %/d1,%/d2\n" \ yann@1: + "mulu %/d0,%/d3\n" \ yann@1: + "mulu %/d0,%/d1\n" \ yann@1: + "move%.l %/d4,%/d0\n" \ yann@1: + "eor%.w %/d0,%/d0\n" \ yann@1: + "swap %/d0\n" \ yann@1: + "add%.l %/d0,%/d2\n" \ yann@1: + "add%.l %/d3,%/d2\n" \ yann@1: + "jcc 1f\n" \ yann@1: + "add%.l %#65536,%/d1\n" \ yann@1: +"1: swap %/d2\n" \ yann@1: + "moveq %#0,%/d0\n" \ yann@1: + "move%.w %/d2,%/d0\n" \ yann@1: + "move%.w %/d4,%/d2\n" \ yann@1: + "move%.l %/d2,%1\n" \ yann@1: + "add%.l %/d1,%/d0\n" \ yann@1: + "move%.l %/d0,%0" \ yann@1: : "=g" ((USItype) (xh)), \ yann@1: "=g" ((USItype) (xl)) \ yann@1: : "g" ((USItype) (a)), \ yann@1: @@ -653,8 +653,8 @@ yann@1: yann@1: #if defined (__m88000__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("addu.co %1,%r4,%r5 yann@1: - addu.ci %0,%r2,%r3" \ yann@1: + __asm__ ("addu.co %1,%r4,%r5\n" \ yann@1: + "addu.ci %0,%r2,%r3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%rJ" ((USItype) (ah)), \ yann@1: @@ -662,8 +662,8 @@ yann@1: "%rJ" ((USItype) (al)), \ yann@1: "rJ" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subu.co %1,%r4,%r5 yann@1: - subu.ci %0,%r2,%r3" \ yann@1: + __asm__ ("subu.co %1,%r4,%r5\n" \ yann@1: + "subu.ci %0,%r2,%r3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "rJ" ((USItype) (ah)), \ yann@1: @@ -880,8 +880,8 @@ yann@1: yann@1: #if defined (__pyr__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("addw %5,%1 yann@1: - addwc %3,%0" \ yann@1: + __asm__ ("addw %5,%1\n" \ yann@1: + "addwc %3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -889,8 +889,8 @@ yann@1: "%1" ((USItype) (al)), \ yann@1: "g" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subw %5,%1 yann@1: - subwb %3,%0" \ yann@1: + __asm__ ("subw %5,%1\n" \ yann@1: + "subwb %3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \ yann@1: @@ -902,8 +902,8 @@ yann@1: ({union {UDItype __ll; \ yann@1: struct {USItype __h, __l;} __i; \ yann@1: } __xx; \ yann@1: - __asm__ ("movw %1,%R0 yann@1: - uemul %2,%0" \ yann@1: + __asm__ ("movw %1,%R0\n" \ yann@1: + "uemul %2,%0" \ yann@1: : "=&r" (__xx.__ll) \ yann@1: : "g" ((USItype) (u)), \ yann@1: "g" ((USItype) (v))); \ yann@1: @@ -912,8 +912,8 @@ yann@1: yann@1: #if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("a %1,%5 yann@1: - ae %0,%3" \ yann@1: + __asm__ ("a %1,%5\n" \ yann@1: + "ae %0,%3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -921,8 +921,8 @@ yann@1: "%1" ((USItype) (al)), \ yann@1: "r" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("s %1,%5 yann@1: - se %0,%3" \ yann@1: + __asm__ ("s %1,%5\n" \ yann@1: + "se %0,%3" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \ yann@1: @@ -933,26 +933,26 @@ yann@1: do { \ yann@1: USItype __m0 = (m0), __m1 = (m1); \ yann@1: __asm__ ( \ yann@1: - "s r2,r2 yann@1: - mts r10,%2 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - m r2,%3 yann@1: - cas %0,r2,r0 yann@1: - mfs r10,%1" \ yann@1: + "s r2,r2\n" yann@1: + "mts r10,%2\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "m r2,%3\n" \ yann@1: + "cas %0,r2,r0\n" \ yann@1: + "mfs r10,%1" \ yann@1: : "=r" ((USItype) (ph)), \ yann@1: "=r" ((USItype) (pl)) \ yann@1: : "%r" (__m0), \ yann@1: @@ -982,9 +982,9 @@ yann@1: #if defined (__sh2__) && W_TYPE_SIZE == 32 yann@1: #define umul_ppmm(w1, w0, u, v) \ yann@1: __asm__ ( \ yann@1: - "dmulu.l %2,%3 yann@1: - sts macl,%1 yann@1: - sts mach,%0" \ yann@1: + "dmulu.l %2,%3\n" \ yann@1: + "sts macl,%1\n" \ yann@1: + "sts mach,%0" \ yann@1: : "=r" ((USItype)(w1)), \ yann@1: "=r" ((USItype)(w0)) \ yann@1: : "r" ((USItype)(u)), \ yann@1: @@ -996,8 +996,8 @@ yann@1: #if defined (__sparc__) && !defined(__arch64__) \ yann@1: && !defined(__sparcv9) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("addcc %r4,%5,%1 yann@1: - addx %r2,%3,%0" \ yann@1: + __asm__ ("addcc %r4,%5,%1\n" \ yann@1: + "addx %r2,%3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "%rJ" ((USItype) (ah)), \ yann@1: @@ -1006,8 +1006,8 @@ yann@1: "rI" ((USItype) (bl)) \ yann@1: __CLOBBER_CC) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subcc %r4,%5,%1 yann@1: - subx %r2,%3,%0" \ yann@1: + __asm__ ("subcc %r4,%5,%1\n" \ yann@1: + "subx %r2,%3,%0" \ yann@1: : "=r" ((USItype) (sh)), \ yann@1: "=&r" ((USItype) (sl)) \ yann@1: : "rJ" ((USItype) (ah)), \ yann@1: @@ -1040,45 +1040,45 @@ yann@1: : "r" ((USItype) (u)), \ yann@1: "r" ((USItype) (v))) yann@1: #define udiv_qrnnd(q, r, n1, n0, d) \ yann@1: - __asm__ ("! Inlined udiv_qrnnd yann@1: - wr %%g0,%2,%%y ! Not a delayed write for sparclite yann@1: - tst %%g0 yann@1: - divscc %3,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%%g1 yann@1: - divscc %%g1,%4,%0 yann@1: - rd %%y,%1 yann@1: - bl,a 1f yann@1: - add %1,%4,%1 yann@1: -1: ! End of inline udiv_qrnnd" \ yann@1: + __asm__ ("! Inlined udiv_qrnnd\n" \ yann@1: + "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \ yann@1: + "tst %%g0\n" \ yann@1: + "divscc %3,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%%g1\n" \ yann@1: + "divscc %%g1,%4,%0\n" \ yann@1: + "rd %%y,%1\n" \ yann@1: + "bl,a 1f\n" \ yann@1: + "add %1,%4,%1\n" \ yann@1: +"1: ! End of inline udiv_qrnnd" \ yann@1: : "=r" ((USItype) (q)), \ yann@1: "=r" ((USItype) (r)) \ yann@1: : "r" ((USItype) (n1)), \ yann@1: @@ -1099,46 +1099,46 @@ yann@1: /* SPARC without integer multiplication and divide instructions. yann@1: (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */ yann@1: #define umul_ppmm(w1, w0, u, v) \ yann@1: - __asm__ ("! Inlined umul_ppmm yann@1: - wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr yann@1: - sra %3,31,%%o5 ! Don't move this insn yann@1: - and %2,%%o5,%%o5 ! Don't move this insn yann@1: - andcc %%g0,0,%%g1 ! Don't move this insn yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,%3,%%g1 yann@1: - mulscc %%g1,0,%%g1 yann@1: - add %%g1,%%o5,%0 yann@1: - rd %%y,%1" \ yann@1: + __asm__ ("! Inlined umul_ppmm\n" \ yann@1: + "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \ yann@1: + "sra %3,31,%%o5 ! Don't move this insn\n" \ yann@1: + "and %2,%%o5,%%o5 ! Don't move this insn\n" \ yann@1: + "andcc %%g0,0,%%g1 ! Don't move this insn\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,%3,%%g1\n" \ yann@1: + "mulscc %%g1,0,%%g1\n" \ yann@1: + "add %%g1,%%o5,%0\n" \ yann@1: + "rd %%y,%1" \ yann@1: : "=r" ((USItype) (w1)), \ yann@1: "=r" ((USItype) (w0)) \ yann@1: : "%rI" ((USItype) (u)), \ yann@1: @@ -1148,30 +1148,30 @@ yann@1: /* It's quite necessary to add this much assembler for the sparc. yann@1: The default udiv_qrnnd (in C) is more than 10 times slower! */ yann@1: #define udiv_qrnnd(q, r, n1, n0, d) \ yann@1: - __asm__ ("! Inlined udiv_qrnnd yann@1: - mov 32,%%g1 yann@1: - subcc %1,%2,%%g0 yann@1: -1: bcs 5f yann@1: - addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb yann@1: - sub %1,%2,%1 ! this kills msb of n yann@1: - addx %1,%1,%1 ! so this can't give carry yann@1: - subcc %%g1,1,%%g1 yann@1: -2: bne 1b yann@1: - subcc %1,%2,%%g0 yann@1: - bcs 3f yann@1: - addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb yann@1: - b 3f yann@1: - sub %1,%2,%1 ! this kills msb of n yann@1: -4: sub %1,%2,%1 yann@1: -5: addxcc %1,%1,%1 yann@1: - bcc 2b yann@1: - subcc %%g1,1,%%g1 yann@1: -! Got carry from n. Subtract next step to cancel this carry. yann@1: - bne 4b yann@1: - addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb yann@1: - sub %1,%2,%1 yann@1: -3: xnor %0,0,%0 yann@1: - ! End of inline udiv_qrnnd" \ yann@1: + __asm__ ("! Inlined udiv_qrnnd\n" \ yann@1: + "mov 32,%%g1\n" \ yann@1: + "subcc %1,%2,%%g0\n" \ yann@1: +"1: bcs 5f\n" \ yann@1: + "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ yann@1: + "sub %1,%2,%1 ! this kills msb of n\n" \ yann@1: + "addx %1,%1,%1 ! so this can't give carry\n" \ yann@1: + "subcc %%g1,1,%%g1\n" \ yann@1: +"2: bne 1b\n" \ yann@1: + "subcc %1,%2,%%g0\n" \ yann@1: + "bcs 3f\n" \ yann@1: + "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n" \ yann@1: + "b 3f\n" \ yann@1: + "sub %1,%2,%1 ! this kills msb of n\n" \ yann@1: +"4: sub %1,%2,%1\n" \ yann@1: +"5: addxcc %1,%1,%1\n" \ yann@1: + "bcc 2b\n" \ yann@1: + "subcc %%g1,1,%%g1\n" \ yann@1: +"! Got carry from n. Subtract next step to cancel this carry.\n" \ yann@1: + "bne 4b\n" \ yann@1: + "addcc %0,%0,%0 ! shift n1n0 and a 0-bit in lsb\n" \ yann@1: + "sub %1,%2,%1\n" \ yann@1: +"3: xnor %0,0,%0\n" \ yann@1: + "! End of inline udiv_qrnnd" \ yann@1: : "=&r" ((USItype) (q)), \ yann@1: "=&r" ((USItype) (r)) \ yann@1: : "r" ((USItype) (d)), \ yann@1: @@ -1185,11 +1185,11 @@ yann@1: #if ((defined (__sparc__) && defined (__arch64__)) \ yann@1: || defined (__sparcv9)) && W_TYPE_SIZE == 64 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("addcc %r4,%5,%1 yann@1: - add %r2,%3,%0 yann@1: - bcs,a,pn %%xcc, 1f yann@1: - add %0, 1, %0 yann@1: - 1:" \ yann@1: + __asm__ ("addcc %r4,%5,%1\n" \ yann@1: + "add %r2,%3,%0\n" \ yann@1: + "bcs,a,pn %%xcc, 1f\n" \ yann@1: + "add %0, 1, %0\n" \ yann@1: + "1:" \ yann@1: : "=r" ((UDItype)(sh)), \ yann@1: "=&r" ((UDItype)(sl)) \ yann@1: : "%rJ" ((UDItype)(ah)), \ yann@1: @@ -1199,11 +1199,11 @@ yann@1: __CLOBBER_CC) yann@1: yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subcc %r4,%5,%1 yann@1: - sub %r2,%3,%0 yann@1: - bcs,a,pn %%xcc, 1f yann@1: - sub %0, 1, %0 yann@1: - 1:" \ yann@1: + __asm__ ("subcc %r4,%5,%1\n" \ yann@1: + "sub %r2,%3,%0\n" \ yann@1: + "bcs,a,pn %%xcc, 1f\n" \ yann@1: + "sub %0, 1, %0\n" \ yann@1: + "1:" \ yann@1: : "=r" ((UDItype)(sh)), \ yann@1: "=&r" ((UDItype)(sl)) \ yann@1: : "rJ" ((UDItype)(ah)), \ yann@1: @@ -1216,27 +1216,27 @@ yann@1: do { \ yann@1: UDItype tmp1, tmp2, tmp3, tmp4; \ yann@1: __asm__ __volatile__ ( \ yann@1: - "srl %7,0,%3 yann@1: - mulx %3,%6,%1 yann@1: - srlx %6,32,%2 yann@1: - mulx %2,%3,%4 yann@1: - sllx %4,32,%5 yann@1: - srl %6,0,%3 yann@1: - sub %1,%5,%5 yann@1: - srlx %5,32,%5 yann@1: - addcc %4,%5,%4 yann@1: - srlx %7,32,%5 yann@1: - mulx %3,%5,%3 yann@1: - mulx %2,%5,%5 yann@1: - sethi %%hi(0x80000000),%2 yann@1: - addcc %4,%3,%4 yann@1: - srlx %4,32,%4 yann@1: - add %2,%2,%2 yann@1: - movcc %%xcc,%%g0,%2 yann@1: - addcc %5,%4,%5 yann@1: - sllx %3,32,%3 yann@1: - add %1,%3,%1 yann@1: - add %5,%2,%0" \ yann@1: + "srl %7,0,%3\n" \ yann@1: + "mulx %3,%6,%1\n" \ yann@1: + "srlx %6,32,%2\n" \ yann@1: + "mulx %2,%3,%4\n" \ yann@1: + "sllx %4,32,%5\n" \ yann@1: + "srl %6,0,%3\n" \ yann@1: + "sub %1,%5,%5\n" \ yann@1: + "srlx %5,32,%5\n" \ yann@1: + "addcc %4,%5,%4\n" \ yann@1: + "srlx %7,32,%5\n" \ yann@1: + "mulx %3,%5,%3\n" \ yann@1: + "mulx %2,%5,%5\n" \ yann@1: + "sethi %%hi(0x80000000),%2\n" \ yann@1: + "addcc %4,%3,%4\n" \ yann@1: + "srlx %4,32,%4\n" \ yann@1: + "add %2,%2,%2\n" \ yann@1: + "movcc %%xcc,%%g0,%2\n" \ yann@1: + "addcc %5,%4,%5\n" \ yann@1: + "sllx %3,32,%3\n" \ yann@1: + "add %1,%3,%1\n" \ yann@1: + "add %5,%2,%0" \ yann@1: : "=r" ((UDItype)(wh)), \ yann@1: "=&r" ((UDItype)(wl)), \ yann@1: "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4) \ yann@1: @@ -1250,8 +1250,8 @@ yann@1: yann@1: #if defined (__vax__) && W_TYPE_SIZE == 32 yann@1: #define add_ssaaaa(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("addl2 %5,%1 yann@1: - adwc %3,%0" \ yann@1: + __asm__ ("addl2 %5,%1\n" \ yann@1: + "adwc %3,%0" \ yann@1: : "=g" ((USItype) (sh)), \ yann@1: "=&g" ((USItype) (sl)) \ yann@1: : "%0" ((USItype) (ah)), \ yann@1: @@ -1259,8 +1259,8 @@ yann@1: "%1" ((USItype) (al)), \ yann@1: "g" ((USItype) (bl))) yann@1: #define sub_ddmmss(sh, sl, ah, al, bh, bl) \ yann@1: - __asm__ ("subl2 %5,%1 yann@1: - sbwc %3,%0" \ yann@1: + __asm__ ("subl2 %5,%1\n" \ yann@1: + "sbwc %3,%0" \ yann@1: : "=g" ((USItype) (sh)), \ yann@1: "=&g" ((USItype) (sl)) \ yann@1: : "0" ((USItype) (ah)), \