yann@96: Status: Unsuitable for upstream (at least, without a lot of arguing).
yann@96: 
yann@96: GCC does not specify the state of every last register in the CIE.  Since
yann@96: GCC's focus is on correctness of runtime unwinding, any registers which
yann@96: have to be unwound will be specified; but unmodified registers will not
yann@96: be explicitly marked.  (How about modified, call-clobbered registers?
yann@96: I'm not sure if they are marked as unavailable.)
yann@96: 
yann@96: GDB issues a noisy warning about this.  The warning is generally not useful,
yann@96: and we can get it extremely frequently (any time we load a new CIE).
yann@96: 
yann@96: This patch disables the warning.  Alternately we could set the complaints
yann@96: threshold to zero, or implement a default frame init-register method for
yann@96: every architecture.  But someday the compiler will support using different
yann@96: calling conventions for internal functions, so that's not much of a stopgap. 
yann@96: ARM has a complex algorithm for handling this, involving scanning all CIEs -
yann@96: benefit not completely clear outside of the ARM context of flexible register
yann@96: sets.
yann@96: 
yann@96: Index: gdb-6.3/gdb/dwarf2-frame.c
yann@96: ===================================================================
yann@96: --- gdb-6.3.orig/gdb/dwarf2-frame.c	2004-11-15 11:54:57.000000000 -0500
yann@96: +++ gdb-6.3/gdb/dwarf2-frame.c	2004-12-08 18:02:23.896409471 -0500
yann@96: @@ -705,9 +705,12 @@ dwarf2_frame_cache (struct frame_info *n
yann@96:  	   table.  We need a way of iterating through all the valid
yann@96:  	   DWARF2 register numbers.  */
yann@96:  	if (fs->regs.reg[column].how == DWARF2_FRAME_REG_UNSPECIFIED)
yann@96: -	  complaint (&symfile_complaints,
yann@96: -		     "Incomplete CFI data; unspecified registers at 0x%s",
yann@96: -		     paddr (fs->pc));
yann@96: +	  {
yann@96: +	    if (0)
yann@96: +	      complaint (&symfile_complaints,
yann@96: +			 "Incomplete CFI data; unspecified registers at 0x%s",
yann@96: +			 paddr (fs->pc));
yann@96: +	  }
yann@96:  	else
yann@96:  	  cache->reg[regnum] = fs->regs.reg[column];
yann@96:        }