yann@1: The 30_all_gcc34-arm-ldm-peephole.patch from Debian was conflicting 
yann@1: with the newer 36_all_pr16201-fix.patch, so i cut out the hunk from 
yann@1: it that was causing problems and grabbed an updated version from 
yann@1: upstream cvs.
yann@1: 
yann@1: Index: gcc/config/arm/arm.c
yann@1: ===================================================================
yann@1: RCS file: /cvsroot/gcc/gcc/gcc/config/arm/arm.c,v
yann@1: retrieving revision 1.432
yann@1: retrieving revision 1.433
yann@1: diff -u -r1.432 -r1.433
yann@1: --- gcc-3.4.4/gcc/config/arm/arm.c	29 Mar 2005 03:00:23 -0000	1.432
yann@1: +++ gcc-3.4.4/gcc/config/arm/arm.c	1 Apr 2005 11:02:22 -0000	1.433
yann@1: @@ -5139,6 +5139,10 @@
yann@1:  int
yann@1:  adjacent_mem_locations (rtx a, rtx b)
yann@1:  {
yann@1: +  /* We don't guarantee to preserve the order of these memory refs.  */
yann@1: +  if (volatile_refs_p (a) || volatile_refs_p (b))
yann@1: +    return 0;
yann@1: +
yann@1:    if ((GET_CODE (XEXP (a, 0)) == REG
yann@1:         || (GET_CODE (XEXP (a, 0)) == PLUS
yann@1:  	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
yann@1: @@ -5178,6 +5182,17 @@
yann@1:  	return 0;
yann@1:  
yann@1:        val_diff = val1 - val0;
yann@1: +
yann@1: +      if (arm_ld_sched)
yann@1: +	{
yann@1: +	  /* If the target has load delay slots, then there's no benefit
yann@1: +	     to using an ldm instruction unless the offset is zero and
yann@1: +	     we are optimizing for size.  */
yann@1: +	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
yann@1: +		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
yann@1: +		  && (val_diff == 4 || val_diff == -4));
yann@1: +	}
yann@1: +
yann@1:        return ((REGNO (reg0) == REGNO (reg1))
yann@1:  	      && (val_diff == 4 || val_diff == -4));
yann@1:      }