summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAntony Pavlov <antonynpavlov@gmail.com>2017-11-18 08:05:46 (GMT)
committerAntony Pavlov <antonynpavlov@gmail.com>2017-11-19 01:50:14 (GMT)
commit69c2ca97fbb1137d0b5717de47fd91a917811818 (patch)
tree93602f47d686fe01a2ff58756b5d50f02d908382
parent0b1595acf2cc60218f479fd310cce10d96df3094 (diff)
add RISC-V architecture support
Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
-rw-r--r--config/arch/riscv.in10
-rw-r--r--scripts/build/arch/riscv.sh5
2 files changed, 15 insertions, 0 deletions
diff --git a/config/arch/riscv.in b/config/arch/riscv.in
new file mode 100644
index 0000000..1323347
--- /dev/null
+++ b/config/arch/riscv.in
@@ -0,0 +1,10 @@
+# RISC-V specific config options
+
+## depends on EXPERIMENTAL
+##
+## select ARCH_SUPPORTS_32
+## select ARCH_DEFAULT_32
+## select GCC_REQUIRE_7_or_later
+
+## help The RISC-V architecture, as defined by:
+## help http://www.riscv.org/
diff --git a/scripts/build/arch/riscv.sh b/scripts/build/arch/riscv.sh
new file mode 100644
index 0000000..a0a5ba4
--- /dev/null
+++ b/scripts/build/arch/riscv.sh
@@ -0,0 +1,5 @@
+# Compute RISC-V-specific values
+
+CT_DoArchTupleValues() {
+ CT_TARGET_ARCH="riscv${CT_ARCH_BITNESS}"
+}