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authorAlexey Neyman <stilor@att.net>2018-09-22 06:28:49 (GMT)
committerGitHub <noreply@github.com>2018-09-22 06:28:49 (GMT)
commit9ab0c733cd72dddfa7ed491d87e47bb75a5fc7ca (patch)
tree13d13f99f760c8bfa31a7e854cb618b40bba0ff9
parentd5900debd397b8909d9cafeb9a1093fb7a5dc6e6 (diff)
parent05d74f9d63aaeaa8afebf77f3dce64aa2a7fdde6 (diff)
Merge pull request #1020 from sifive/dev/paulw/rv64-fixed
riscv: add rv64gc support
-rw-r--r--config/arch/riscv.in3
-rw-r--r--samples/riscv64-unknown-linux-gnu/crosstool.config12
-rw-r--r--samples/riscv64-unknown-linux-gnu/reported.by3
3 files changed, 18 insertions, 0 deletions
diff --git a/config/arch/riscv.in b/config/arch/riscv.in
index 4efde97..109556a 100644
--- a/config/arch/riscv.in
+++ b/config/arch/riscv.in
@@ -4,9 +4,12 @@
## depends on EXPERIMENTAL
##
## select ARCH_SUPPORTS_32
+## select ARCH_SUPPORTS_64
## select ARCH_DEFAULT_32
+## select ARCH_SUPPORTS_BOTH_MMU
## select ARCH_SUPPORTS_WITH_ABI
## select ARCH_SUPPORTS_WITH_ARCH
+## select ARCH_SUPPORTS_WITH_TUNE
## select GCC_REQUIRE_7_or_later
## help The RISC-V architecture, as defined by:
diff --git a/samples/riscv64-unknown-linux-gnu/crosstool.config b/samples/riscv64-unknown-linux-gnu/crosstool.config
new file mode 100644
index 0000000..66c288d
--- /dev/null
+++ b/samples/riscv64-unknown-linux-gnu/crosstool.config
@@ -0,0 +1,12 @@
+CT_EXPERIMENTAL=y
+CT_ARCH_RISCV=y
+# CT_DEMULTILIB is not set
+CT_ARCH_USE_MMU=y
+CT_ARCH_64=y
+CT_KERNEL_LINUX=y
+CT_DEBUG_GDB=y
+# CT_GDB_CROSS_PYTHON is not set
+# CT_GDB_GDBSERVER is not set
+CT_ZLIB_NEEDED=y
+CT_TARGET_VENDOR="unknown"
+CT_ARCH_ARCH="rv64gc"
diff --git a/samples/riscv64-unknown-linux-gnu/reported.by b/samples/riscv64-unknown-linux-gnu/reported.by
new file mode 100644
index 0000000..9456e59
--- /dev/null
+++ b/samples/riscv64-unknown-linux-gnu/reported.by
@@ -0,0 +1,3 @@
+reporter_name="Paul Walmsley <paul.walmsley@sifive.com>"
+reporter_url="https://www.sifive.com/"
+reporter_comment=""