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| author |   Alexey Neyman <stilor@att.net> | 2018-09-26 06:41:59 (GMT) |
|---|---|---|
| committer |   GitHub <noreply@github.com> | 2018-09-26 06:41:59 (GMT) |
| commit | ea1072c29ba37f29ca3f60871935aa5ca3fcb9b6 (patch) | |
| tree | 93ba237f3d82047ed21738a4915d7e2a13cb45c4 | |
| parent | 49520dbf6d55640974f89becae00fe142f5b9c21 (diff) | |
| parent | af8da8b181c43fe97de63c39e1d14e6c59a8950b (diff) | |
Merge pull request #1027 from sifive/dev/paulw/rv64-bare-metal
riscv64: samples: add rv64gc bare-metal sample configuration
| -rw-r--r-- | samples/riscv64-unknown-elf/crosstool.config | 7 | ||||
| -rw-r--r-- | samples/riscv64-unknown-elf/reported.by | 3 |
2 files changed, 10 insertions, 0 deletions
diff --git a/samples/riscv64-unknown-elf/crosstool.config b/samples/riscv64-unknown-elf/crosstool.config new file mode 100644 index 0000000..221ef20 --- /dev/null +++ b/samples/riscv64-unknown-elf/crosstool.config @@ -0,0 +1,7 @@ +CT_EXPERIMENTAL=y +CT_ARCH_RISCV=y +# CT_DEMULTILIB is not set +CT_ARCH_USE_MMU=y +CT_ARCH_64=y +CT_DEBUG_GDB=y +# CT_GDB_CROSS_PYTHON is not set diff --git a/samples/riscv64-unknown-elf/reported.by b/samples/riscv64-unknown-elf/reported.by new file mode 100644 index 0000000..9456e59 --- /dev/null +++ b/samples/riscv64-unknown-elf/reported.by @@ -0,0 +1,3 @@ +reporter_name="Paul Walmsley <paul.walmsley@sifive.com>" +reporter_url="https://www.sifive.com/" +reporter_comment="" |