gcc11: Fixes for ARC

See more details here:
1. https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/398
2. https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/427
3. https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/429

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

3 files changed, 285 insertions, 0 deletions

diff --git a/packages/gcc/11.2.0/0006-arc-Update-ZOL-pattern.patch b/packages/gcc/11.2.0/0006-arc-Update-ZOL-pattern.patch
new file mode 100644
index 0000000..361c9db
--- /dev/null
+++ b/packages/gcc/11.2.0/0006-arc-Update-ZOL-pattern.patch
@@ -0,0 +1,44 @@
+From 7efc628f79a1801b292623dfe5aa8c53a61a2121 Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@synopsys.com>
+Date: Tue, 14 Sep 2021 12:25:43 +0300
+Subject: [PATCH] arc: Update ZOL pattern.
+
+The ZOL pattern is missing modes which may lead to errors during
+var_tracking. Add them.
+
+gcc/
+	* config/arc/arc.md (doloop_end): Add missing mode.
+	(loop_end): Likewise.
+
+See more details here: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/398
+Will be a part of GCC 12, see: https://gcc.gnu.org/git/?p=gcc.git;a=commit;h=9bb20299ba1d1cc3bbd83a07a777fcc5a93cfeb0
+
+Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
+---
+ gcc/config/arc/arc.md |    8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -4990,8 +4990,8 @@
+ 			(const_int 1))
+ 		    (label_ref (match_operand 1 "" ""))
+ 		    (pc)))
+-	      (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
+-	      (unspec [(const_int 0)] UNSPEC_ARC_LP)
++	      (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
++	      (unspec:SI [(const_int 0)] UNSPEC_ARC_LP)
+ 	      (clobber (match_dup 2))])]
+   ""
+ {
+@@ -5020,8 +5020,8 @@
+ 			  (const_int 1))
+ 		      (label_ref (match_operand 1 "" ""))
+ 		      (pc)))
+-   (set (match_dup 0) (plus (match_dup 0) (const_int -1)))
+-   (unspec [(const_int 0)] UNSPEC_ARC_LP)
++   (set (match_dup 0) (plus:SI (match_dup 0) (const_int -1)))
++   (unspec:SI [(const_int 0)] UNSPEC_ARC_LP)
+    (clobber (match_scratch:SI 2 "=X,&r"))]
+   ""
+   "@
diff --git a/packages/gcc/11.2.0/0007-arc-Update-u-maddhisi4-patterns.patch b/packages/gcc/11.2.0/0007-arc-Update-u-maddhisi4-patterns.patch
new file mode 100644
index 0000000..8b0c34f
--- /dev/null
+++ b/packages/gcc/11.2.0/0007-arc-Update-u-maddhisi4-patterns.patch
@@ -0,0 +1,115 @@
+From b3873d67e4e8a1f16efbfa6ad7d73b9809bb2dd2 Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@synopsys.com>
+Date: Thu, 30 Sep 2021 14:08:39 +0300
+Subject: [PATCH] arc: Update (u)maddhisi4 patterns
+
+The (u)maddsihi4 patterns are using the ARC's VMAC2H(U)
+instruction with null destination, however, VMAC2H(U) doesn't
+rewrite the accumulator.  This patch solves the destination issue
+of VMAC2H by using the accumulator, and is using a
+define_insn_and_split to generate the extra move from the
+accumulator to the destination register.
+
+gcc/
+
+	* config/arc/arc.md (maddhisi4): Use a single move to accumulator.
+	(umaddhisi4): Likewise.
+	(machi): Convert it to an define_insn_and_split pattern.
+	(umachi): Likewise.
+
+See for more details: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/427
+
+Signed-off-by: Claudiu Zissulescu <claziss@synopsys.com>
+---
+ gcc/config/arc/arc.md |   57 +++++++++++++++++++++++++++++++++++---------------
+ 1 file changed, 40 insertions(+), 17 deletions(-)
+
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -6051,26 +6051,37 @@
+ (define_expand "maddhisi4"
+   [(match_operand:SI 0 "register_operand" "")
+    (match_operand:HI 1 "register_operand" "")
+-   (match_operand:HI 2 "extend_operand"   "")
++   (match_operand:HI 2 "register_operand" "")
+    (match_operand:SI 3 "register_operand" "")]
+   "TARGET_PLUS_MACD"
+   "{
+    rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+ 
+    emit_move_insn (acc_reg, operands[3]);
+-   emit_insn (gen_machi (operands[1], operands[2]));
+-   emit_move_insn (operands[0], acc_reg);
++   emit_insn (gen_machi (operands[0], operands[1], operands[2]));
+    DONE;
+   }")
+ 
+-(define_insn "machi"
+-  [(set (reg:SI ARCV2_ACC)
++(define_insn_and_split "machi"
++  [(set (match_operand:SI 0 "register_operand" "=Ral,r")
+ 	(plus:SI
+-	 (mult:SI (sign_extend:SI (match_operand:HI 0 "register_operand" "%r"))
+-		  (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))
+-	 (reg:SI ARCV2_ACC)))]
++	 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
++		  (sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
++	 (reg:SI ARCV2_ACC)))
++   (clobber (reg:DI ARCV2_ACC))]
+   "TARGET_PLUS_MACD"
+-  "vmac2h\\t0,%0,%1"
++  "@
++   vmac2h\\t%0,%1,%2
++   #"
++  "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
++  [(parallel
++    [(set (reg:SI ARCV2_ACC)
++	  (plus:SI (mult:SI (sign_extend:SI (match_dup 1))
++			    (sign_extend:SI (match_dup 2)))
++		   (reg:SI ARCV2_ACC)))
++     (clobber (reg:DI ARCV2_ACC))])
++   (set (match_dup 0) (reg:SI ARCV2_ACC))]
++  ""
+   [(set_attr "length" "4")
+    (set_attr "type" "multi")
+    (set_attr "predicable" "no")
+@@ -6087,19 +6098,31 @@
+    rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
+ 
+    emit_move_insn (acc_reg, operands[3]);
+-   emit_insn (gen_umachi (operands[1], operands[2]));
+-   emit_move_insn (operands[0], acc_reg);
++   emit_insn (gen_umachi (operands[0], operands[1], operands[2]));
+    DONE;
+   }")
+ 
+-(define_insn "umachi"
+-  [(set (reg:SI ARCV2_ACC)
++
++(define_insn_and_split "umachi"
++  [(set (match_operand:SI 0 "register_operand" "=Ral,r")
+ 	(plus:SI
+-	 (mult:SI (zero_extend:SI (match_operand:HI 0 "register_operand" "%r"))
+-		  (zero_extend:SI (match_operand:HI 1 "register_operand" "r")))
+-	 (reg:SI ARCV2_ACC)))]
++	 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
++		  (zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
++	 (reg:SI ARCV2_ACC)))
++   (clobber (reg:DI ARCV2_ACC))]
+   "TARGET_PLUS_MACD"
+-  "vmac2hu\\t0,%0,%1"
++  "@
++   vmac2hu\\t%0,%1,%2
++   #"
++  "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
++  [(parallel
++    [(set (reg:SI ARCV2_ACC)
++	  (plus:SI (mult:SI (zero_extend:SI (match_dup 1))
++			    (zero_extend:SI (match_dup 2)))
++		   (reg:SI ARCV2_ACC)))
++     (clobber (reg:DI ARCV2_ACC))])
++   (set (match_dup 0) (reg:SI ARCV2_ACC))]
++  ""
+   [(set_attr "length" "4")
+    (set_attr "type" "multi")
+    (set_attr "predicable" "no")
diff --git a/packages/gcc/11.2.0/0008-arc-Fix-maddhisi-patterns.patch b/packages/gcc/11.2.0/0008-arc-Fix-maddhisi-patterns.patch
new file mode 100644
index 0000000..e4233a3
--- /dev/null
+++ b/packages/gcc/11.2.0/0008-arc-Fix-maddhisi-patterns.patch
@@ -0,0 +1,126 @@
+From e73e3c3eaf2c3ea45083dda5dc4b7d29f6a03238 Mon Sep 17 00:00:00 2001
+From: Claudiu Zissulescu <claziss@synopsys.com>
+Date: Wed, 6 Oct 2021 09:47:50 +0300
+Subject: [PATCH] arc: Fix maddhisi patterns
+
+See for more details: https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/issues/429
+
+---
+ gcc/config/arc/arc.md                 |   43 +++++++---------------------------
+ gcc/testsuite/gcc.target/arc/tmac-4.c |   29 ++++++++++++++++++++++
+ 2 files changed, 39 insertions(+), 33 deletions(-)
+ create mode 100644 gcc/testsuite/gcc.target/arc/tmac-4.c
+
+--- a/gcc/config/arc/arc.md
++++ b/gcc/config/arc/arc.md
+@@ -6055,33 +6055,22 @@
+    (match_operand:SI 3 "register_operand" "")]
+   "TARGET_PLUS_MACD"
+   "{
+-   rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
++   rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
+ 
+    emit_move_insn (acc_reg, operands[3]);
+-   emit_insn (gen_machi (operands[0], operands[1], operands[2]));
++   emit_insn (gen_machi (operands[0], operands[1], operands[2], acc_reg));
+    DONE;
+   }")
+ 
+-(define_insn_and_split "machi"
++(define_insn "machi"
+   [(set (match_operand:SI 0 "register_operand" "=Ral,r")
+ 	(plus:SI
+ 	 (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
+ 		  (sign_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
+-	 (reg:SI ARCV2_ACC)))
++	 (match_operand:SI 3 "accl_operand" "")))
+    (clobber (reg:DI ARCV2_ACC))]
+   "TARGET_PLUS_MACD"
+-  "@
+-   vmac2h\\t%0,%1,%2
+-   #"
+-  "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
+-  [(parallel
+-    [(set (reg:SI ARCV2_ACC)
+-	  (plus:SI (mult:SI (sign_extend:SI (match_dup 1))
+-			    (sign_extend:SI (match_dup 2)))
+-		   (reg:SI ARCV2_ACC)))
+-     (clobber (reg:DI ARCV2_ACC))])
+-   (set (match_dup 0) (reg:SI ARCV2_ACC))]
+-  ""
++  "dmach\\t%0,%1,%2"
+   [(set_attr "length" "4")
+    (set_attr "type" "multi")
+    (set_attr "predicable" "no")
+@@ -6095,34 +6084,22 @@
+    (match_operand:SI 3 "register_operand" "")]
+   "TARGET_PLUS_MACD"
+   "{
+-   rtx acc_reg = gen_rtx_REG (SImode, ACC_REG_FIRST);
++   rtx acc_reg = gen_rtx_REG (SImode, ACCL_REGNO);
+ 
+    emit_move_insn (acc_reg, operands[3]);
+-   emit_insn (gen_umachi (operands[0], operands[1], operands[2]));
++   emit_insn (gen_umachi (operands[0], operands[1], operands[2], acc_reg));
+    DONE;
+   }")
+ 
+-
+-(define_insn_and_split "umachi"
++(define_insn "umachi"
+   [(set (match_operand:SI 0 "register_operand" "=Ral,r")
+ 	(plus:SI
+ 	 (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r,r"))
+ 		  (zero_extend:SI (match_operand:HI 2 "register_operand" "r,r")))
+-	 (reg:SI ARCV2_ACC)))
++	 (match_operand:SI 3 "accl_operand" "")))
+    (clobber (reg:DI ARCV2_ACC))]
+   "TARGET_PLUS_MACD"
+-  "@
+-   vmac2hu\\t%0,%1,%2
+-   #"
+-  "&& reload_completed && (REGNO (operands[0]) != ACCL_REGNO)"
+-  [(parallel
+-    [(set (reg:SI ARCV2_ACC)
+-	  (plus:SI (mult:SI (zero_extend:SI (match_dup 1))
+-			    (zero_extend:SI (match_dup 2)))
+-		   (reg:SI ARCV2_ACC)))
+-     (clobber (reg:DI ARCV2_ACC))])
+-   (set (match_dup 0) (reg:SI ARCV2_ACC))]
+-  ""
++  "dmachu\\t%0,%1,%2"
+   [(set_attr "length" "4")
+    (set_attr "type" "multi")
+    (set_attr "predicable" "no")
+--- /dev/null
++++ b/gcc/testsuite/gcc.target/arc/tmac-4.c
+@@ -0,0 +1,29 @@
++/* { dg-do compile } */
++/* { dg-skip-if "" { ! { clmcpu } } } */
++/* { dg-options "-O3 -mbig-endian -mcpu=hs38" } */
++
++struct a {};
++struct b {
++  int c;
++  int d;
++};
++
++struct {
++  struct a e;
++  struct b f[];
++} g;
++short h;
++
++extern void bar (int *);
++
++int foo(void)
++{
++  struct b *a;
++  for (;;)
++    {
++      a = &g.f[h];
++      bar(&a->d);
++    }
++}
++
++/* { dg-final { scan-assembler "dmach" } } */