gcc: Support only the latest branch releases of gcc

This change, as per #222, reduces the number of supported releases of
gcc to the latest branch releases.

I noticed while doing this work that gcc-4.5.4 was never added, so I
moved patches for gcc-4.5.3 to 4.5.4 and updated the
bfin-unknown-linux-uclibc example. Also, 120-siginfo.patch was fixed
upstream in the 4.5.4 release, so this patch is omitted.

I also bumped the avr sample to 4.9.3 from 4.9.2.

With the addition of gcc-5.x, the gcc release team now releases the
major.minor.0 versions, while updates to the branch are available in
svn/git. We'll address that when we get to issue #219. This change just
removes CC_GCC_5_1 and moves CC_GCC_5_2 to CC_GCC_5, and removes
CC_GCC_5_1_or_later and moves CC_GCC_5_2_or_later to CC_GCC_5_or_later.

This is the first of two part changes, as mentioned in #222.
This change is slated for release in 1.22.0. The next change will be
slated for 1.23.0, and will limit gcc versions to what is on
https://gcc.gnu.org under "Release Series and Status", which is
currently 4.9.3 and 5.2.0, although I will also support the previous
supported version. In this example that would be 4.8.5.

Last, but not least, this change also retires AVR32 support.

Signed-off-by: Bryan Hundven <bryanhundven@gmail.com>

1 files changed, 0 insertions, 32 deletions

diff --git a/patches/gcc/3.4.6/160-arm-ldm-peephole2.patch b/patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
deleted file mode 100644
index 395c516..0000000
--- a/patches/gcc/3.4.6/160-arm-ldm-peephole2.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-diff -durN gcc-3.4.6.orig/gcc/config/arm/arm.c gcc-3.4.6/gcc/config/arm/arm.c
---- gcc-3.4.6.orig/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
-+++ gcc-3.4.6/gcc/config/arm/arm.c	2007-08-15 22:57:51.000000000 +0200
-@@ -4572,6 +4572,10 @@
- int
- adjacent_mem_locations (rtx a, rtx b)
- {
-+  /* We don't guarantee to preserve the order of these memory refs.  */
-+  if (volatile_refs_p (a) || volatile_refs_p (b))
-+    return 0;
-+
-   if ((GET_CODE (XEXP (a, 0)) == REG
-        || (GET_CODE (XEXP (a, 0)) == PLUS
- 	   && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
-@@ -4611,6 +4615,17 @@
- 	return 0;
- 
-       val_diff = val1 - val0;
-+
-+      if (arm_ld_sched)
-+	{
-+	  /* If the target has load delay slots, then there's no benefit
-+	     to using an ldm instruction unless the offset is zero and
-+	     we are optimizing for size.  */
-+	  return (optimize_size && (REGNO (reg0) == REGNO (reg1))
-+		  && (val0 == 0 || val1 == 0 || val0 == 4 || val1 == 4)
-+		  && (val_diff == 4 || val_diff == -4));
-+	}
-+
-       return ((REGNO (reg0) == REGNO (reg1))
- 	      && (val_diff == 4 || val_diff == -4));
-     }