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authorYann E. MORIN" <yann.morin.1998@anciens.enib.fr>2007-09-23 17:08:09 (GMT)
committerYann E. MORIN" <yann.morin.1998@anciens.enib.fr>2007-09-23 17:08:09 (GMT)
commitb1e693e40281dc8c451e8892dfcdf55d78a4ade3 (patch)
treec276bc44f23b42895b459efbf2597f4bef378819 /patches/linux/2.6.11.3/120-linux-2.6.11-allow-gcc-4.0-asm-i386.patch
parent3ad6464ffe38eb15591b404e0749aa89f4074fd1 (diff)
Renamed all patches file names so that locales are now irrelevant to sort the files.
Removed the locale check as it is now irrelevant. Removed the experimental binutils 2.17.50.0.xx: 2.18 is here now.
Diffstat (limited to 'patches/linux/2.6.11.3/120-linux-2.6.11-allow-gcc-4.0-asm-i386.patch')
-rw-r--r--patches/linux/2.6.11.3/120-linux-2.6.11-allow-gcc-4.0-asm-i386.patch150
1 files changed, 150 insertions, 0 deletions
diff --git a/patches/linux/2.6.11.3/120-linux-2.6.11-allow-gcc-4.0-asm-i386.patch b/patches/linux/2.6.11.3/120-linux-2.6.11-allow-gcc-4.0-asm-i386.patch
new file mode 100644
index 0000000..1193a8c
--- /dev/null
+++ b/patches/linux/2.6.11.3/120-linux-2.6.11-allow-gcc-4.0-asm-i386.patch
@@ -0,0 +1,150 @@
+Fixes
+
+In file included from include/asm/thread_info.h:16,
+ from include/linux/thread_info.h:21,
+ from include/linux/spinlock.h:12,
+ from include/linux/capability.h:45,
+ from include/linux/sched.h:7,
+ from arch/i386/kernel/asm-offsets.c:7:
+include/asm/processor.h:87: error: array type has incomplete element type
+make[1]: *** [arch/i386/kernel/asm-offsets.asm] Error 1
+
+--- linux-2.6.11.3/include/asm-i386/processor.h.old Tue Mar 15 06:45:26 2005
++++ linux-2.6.11.3/include/asm-i386/processor.h Tue Mar 15 06:46:45 2005
+@@ -81,6 +81,64 @@
+ #define X86_VENDOR_UNKNOWN 0xff
+
+ /*
++ * Size of io_bitmap.
++ */
++#define IO_BITMAP_BITS 65536
++#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
++#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
++#define INVALID_IO_BITMAP_OFFSET 0x8000
++#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
++
++struct tss_struct {
++ unsigned short back_link,__blh;
++ unsigned long esp0;
++ unsigned short ss0,__ss0h;
++ unsigned long esp1;
++ unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
++ unsigned long esp2;
++ unsigned short ss2,__ss2h;
++ unsigned long __cr3;
++ unsigned long eip;
++ unsigned long eflags;
++ unsigned long eax,ecx,edx,ebx;
++ unsigned long esp;
++ unsigned long ebp;
++ unsigned long esi;
++ unsigned long edi;
++ unsigned short es, __esh;
++ unsigned short cs, __csh;
++ unsigned short ss, __ssh;
++ unsigned short ds, __dsh;
++ unsigned short fs, __fsh;
++ unsigned short gs, __gsh;
++ unsigned short ldt, __ldth;
++ unsigned short trace, io_bitmap_base;
++ /*
++ * The extra 1 is there because the CPU will access an
++ * additional byte beyond the end of the IO permission
++ * bitmap. The extra byte must be all 1 bits, and must
++ * be within the limit.
++ */
++ unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
++ /*
++ * Cache the current maximum and the last task that used the bitmap:
++ */
++ unsigned long io_bitmap_max;
++ struct thread_struct *io_bitmap_owner;
++ /*
++ * pads the TSS to be cacheline-aligned (size is 0x100)
++ */
++ unsigned long __cacheline_filler[35];
++ /*
++ * .. and then another 0x100 bytes for emergency kernel stack
++ */
++ unsigned long stack[64];
++} __attribute__((packed));
++
++#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
++#define ARCH_MIN_TASKALIGN 16
++
++/*
+ * capabilities of CPUs
+ */
+
+@@ -308,16 +366,6 @@
+
+ #define HAVE_ARCH_PICK_MMAP_LAYOUT
+
+-/*
+- * Size of io_bitmap.
+- */
+-#define IO_BITMAP_BITS 65536
+-#define IO_BITMAP_BYTES (IO_BITMAP_BITS/8)
+-#define IO_BITMAP_LONGS (IO_BITMAP_BYTES/sizeof(long))
+-#define IO_BITMAP_OFFSET offsetof(struct tss_struct,io_bitmap)
+-#define INVALID_IO_BITMAP_OFFSET 0x8000
+-#define INVALID_IO_BITMAP_OFFSET_LAZY 0x9000
+-
+ struct i387_fsave_struct {
+ long cwd;
+ long swd;
+@@ -371,54 +419,6 @@
+ } mm_segment_t;
+
+ struct thread_struct;
+-
+-struct tss_struct {
+- unsigned short back_link,__blh;
+- unsigned long esp0;
+- unsigned short ss0,__ss0h;
+- unsigned long esp1;
+- unsigned short ss1,__ss1h; /* ss1 is used to cache MSR_IA32_SYSENTER_CS */
+- unsigned long esp2;
+- unsigned short ss2,__ss2h;
+- unsigned long __cr3;
+- unsigned long eip;
+- unsigned long eflags;
+- unsigned long eax,ecx,edx,ebx;
+- unsigned long esp;
+- unsigned long ebp;
+- unsigned long esi;
+- unsigned long edi;
+- unsigned short es, __esh;
+- unsigned short cs, __csh;
+- unsigned short ss, __ssh;
+- unsigned short ds, __dsh;
+- unsigned short fs, __fsh;
+- unsigned short gs, __gsh;
+- unsigned short ldt, __ldth;
+- unsigned short trace, io_bitmap_base;
+- /*
+- * The extra 1 is there because the CPU will access an
+- * additional byte beyond the end of the IO permission
+- * bitmap. The extra byte must be all 1 bits, and must
+- * be within the limit.
+- */
+- unsigned long io_bitmap[IO_BITMAP_LONGS + 1];
+- /*
+- * Cache the current maximum and the last task that used the bitmap:
+- */
+- unsigned long io_bitmap_max;
+- struct thread_struct *io_bitmap_owner;
+- /*
+- * pads the TSS to be cacheline-aligned (size is 0x100)
+- */
+- unsigned long __cacheline_filler[35];
+- /*
+- * .. and then another 0x100 bytes for emergency kernel stack
+- */
+- unsigned long stack[64];
+-} __attribute__((packed));
+-
+-#define ARCH_MIN_TASKALIGN 16
+
+ struct thread_struct {
+ /* cached TLS descriptors. */