diff options
Diffstat (limited to 'packages/glibc/2.17/0035-glibc-ppc64le-13.patch')
| -rw-r--r-- | packages/glibc/2.17/0035-glibc-ppc64le-13.patch | 87 |
1 files changed, 45 insertions, 42 deletions
diff --git a/packages/glibc/2.17/0035-glibc-ppc64le-13.patch b/packages/glibc/2.17/0035-glibc-ppc64le-13.patch index 52830a1..345a19c 100644 --- a/packages/glibc/2.17/0035-glibc-ppc64le-13.patch +++ b/packages/glibc/2.17/0035-glibc-ppc64le-13.patch @@ -23,9 +23,25 @@ # * sysdeps/powerpc/fpu/fsetexcptflg.c (__fesetexceptflag): Adjust. # * sysdeps/powerpc/fpu/ftestexcept.c (fetestexcept): Adjust. # -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c 2014-05-27 22:31:43.000000000 -0500 +--- +# sysdeps/powerpc/fpu/e_sqrt.c | 2 +- +# sysdeps/powerpc/fpu/e_sqrtf.c | 2 +- +# sysdeps/powerpc/fpu/fclrexcpt.c | 4 ++-- +# sysdeps/powerpc/fpu/fedisblxcpt.c | 10 +++++----- +# sysdeps/powerpc/fpu/feenablxcpt.c | 10 +++++----- +# sysdeps/powerpc/fpu/fegetexcept.c | 10 +++++----- +# sysdeps/powerpc/fpu/feholdexcpt.c | 5 ++--- +# sysdeps/powerpc/fpu/fenv_libc.h | 2 +- +# sysdeps/powerpc/fpu/fesetenv.c | 4 ++-- +# sysdeps/powerpc/fpu/feupdateenv.c | 6 +++--- +# sysdeps/powerpc/fpu/fgetexcptflg.c | 2 +- +# sysdeps/powerpc/fpu/fraiseexcpt.c | 12 ++++++------ +# sysdeps/powerpc/fpu/fsetexcptflg.c | 8 ++++---- +# sysdeps/powerpc/fpu/ftestexcept.c | 2 +- +# 14 files changed, 39 insertions(+), 40 deletions(-) +# +--- a/sysdeps/powerpc/fpu/e_sqrt.c ++++ b/sysdeps/powerpc/fpu/e_sqrt.c @@ -145,7 +145,7 @@ feraiseexcept (FE_INVALID_SQRT); @@ -35,9 +51,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrt.c glibc-2.17-c758a686/s #endif feraiseexcept (FE_INVALID); x = a_nan.value; -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/e_sqrtf.c ++++ b/sysdeps/powerpc/fpu/e_sqrtf.c @@ -121,7 +121,7 @@ feraiseexcept (FE_INVALID_SQRT); @@ -47,9 +62,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/e_sqrtf.c glibc-2.17-c758a686/ #endif feraiseexcept (FE_INVALID); x = a_nan.value; -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fclrexcpt.c ++++ b/sysdeps/powerpc/fpu/fclrexcpt.c @@ -28,8 +28,8 @@ u.fenv = fegetenv_register (); @@ -61,9 +75,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fclrexcpt.c glibc-2.17-c758a68 /* Put the new state in effect. */ fesetenv_register (u.fenv); -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fedisblxcpt.c ++++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -32,15 +32,15 @@ fe.fenv = fegetenv_register (); @@ -85,9 +98,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fedisblxcpt.c glibc-2.17-c758a fesetenv_register (fe.fenv); new = __fegetexcept (); -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/feenablxcpt.c ++++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -32,15 +32,15 @@ fe.fenv = fegetenv_register (); @@ -109,9 +121,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feenablxcpt.c glibc-2.17-c758a fesetenv_register (fe.fenv); new = __fegetexcept (); -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fegetexcept.c ++++ b/sysdeps/powerpc/fpu/fegetexcept.c @@ -27,15 +27,15 @@ fe.fenv = fegetenv_register (); @@ -133,9 +144,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fegetexcept.c glibc-2.17-c758a result |= FE_INVALID; return result; -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c 2014-05-27 22:33:09.000000000 -0500 +--- a/sysdeps/powerpc/fpu/feholdexcpt.c ++++ b/sysdeps/powerpc/fpu/feholdexcpt.c @@ -30,13 +30,12 @@ /* Clear everything except for the rounding modes and non-IEEE arithmetic @@ -152,9 +162,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feholdexcpt.c glibc-2.17-c758a (void)__fe_mask_env (); /* Put the new state in effect. */ -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fenv_libc.h ++++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -69,7 +69,7 @@ typedef union { @@ -164,9 +173,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fenv_libc.h glibc-2.17-c758a68 } fenv_union_t; -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c 2014-05-27 22:35:18.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fesetenv.c ++++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -36,14 +36,14 @@ exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the hardware into "precise mode" and may cause the FPU to run slower on some @@ -184,9 +192,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fesetenv.c glibc-2.17-c758a686 (void)__fe_mask_env (); fesetenv_register (*envp); -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c 2014-05-27 22:34:23.000000000 -0500 +--- a/sysdeps/powerpc/fpu/feupdateenv.c ++++ b/sysdeps/powerpc/fpu/feupdateenv.c @@ -36,20 +36,20 @@ /* Restore rounding mode and exception enable from *envp and merge exceptions. Leave fraction rounded/inexact and FP result/CC bits @@ -211,9 +218,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/feupdateenv.c glibc-2.17-c758a (void)__fe_mask_env (); /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fgetexcptflg.c ++++ b/sysdeps/powerpc/fpu/fgetexcptflg.c @@ -28,7 +28,7 @@ u.fenv = fegetenv_register (); @@ -223,9 +229,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fgetexcptflg.c glibc-2.17-c758 /* Success. */ return 0; -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fraiseexcpt.c ++++ b/sysdeps/powerpc/fpu/fraiseexcpt.c @@ -34,11 +34,11 @@ u.fenv = fegetenv_register (); @@ -252,9 +257,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fraiseexcpt.c glibc-2.17-c758a set_fpscr_bit (FPSCR_VXSNAN); } -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/fsetexcptflg.c ++++ b/sysdeps/powerpc/fpu/fsetexcptflg.c @@ -32,10 +32,10 @@ flag = *flagp & excepts; @@ -270,9 +274,8 @@ diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/fsetexcptflg.c glibc-2.17-c758 /* Store the new status word (along with the rest of the environment). This may cause floating-point exceptions if the restored state -diff -urN glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c ---- glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c 2014-05-27 22:31:42.000000000 -0500 -+++ glibc-2.17-c758a686/sysdeps/powerpc/fpu/ftestexcept.c 2014-05-27 22:31:43.000000000 -0500 +--- a/sysdeps/powerpc/fpu/ftestexcept.c ++++ b/sysdeps/powerpc/fpu/ftestexcept.c @@ -28,6 +28,6 @@ /* The FE_INVALID bit is dealt with correctly by the hardware, so we can |