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authorAlexey Neyman <stilor@att.net>2017-11-20 05:44:22 (GMT)
committerGitHub <noreply@github.com>2017-11-20 05:44:22 (GMT)
commit8c581c25042301ee0ec4169e6fc3213d7f8cb35b (patch)
tree18c6d1e5284152da3707a7c458c71ed427966034 /config
parent0b1595acf2cc60218f479fd310cce10d96df3094 (diff)
parentcc342748ce231a860d46300363a789cfc330c002 (diff)
Merge pull request #868 from frantony/riscv
add RISC-V architecture support
Diffstat (limited to 'config')
-rw-r--r--config/arch/riscv.in10
1 files changed, 10 insertions, 0 deletions
diff --git a/config/arch/riscv.in b/config/arch/riscv.in
new file mode 100644
index 0000000..1323347
--- /dev/null
+++ b/config/arch/riscv.in
@@ -0,0 +1,10 @@
+# RISC-V specific config options
+
+## depends on EXPERIMENTAL
+##
+## select ARCH_SUPPORTS_32
+## select ARCH_DEFAULT_32
+## select GCC_REQUIRE_7_or_later
+
+## help The RISC-V architecture, as defined by:
+## help http://www.riscv.org/